2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/of_address.h>
43 #include <linux/of_irq.h>
44 #include <linux/of_platform.h>
46 #include <sound/core.h>
47 #include <sound/pcm.h>
48 #include <sound/pcm_params.h>
49 #include <sound/initval.h>
50 #include <sound/soc.h>
51 #include <sound/dmaengine_pcm.h>
57 #define read_ssi(addr) in_be32(addr)
58 #define write_ssi(val, addr) out_be32(addr, val)
59 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
61 #define read_ssi(addr) readl(addr)
62 #define write_ssi(val, addr) writel(val, addr)
64 * FIXME: Proper locking should be added at write_ssi_mask caller level
65 * to ensure this register read/modify/write sequence is race free.
67 static inline void write_ssi_mask(u32 __iomem
*addr
, u32 clear
, u32 set
)
69 u32 val
= readl(addr
);
70 val
= (val
& ~clear
) | set
;
76 * FSLSSI_I2S_RATES: sample rates supported by the I2S
78 * This driver currently only supports the SSI running in I2S slave mode,
79 * which means the codec determines the sample rate. Therefore, we tell
80 * ALSA that we support all rates and let the codec driver decide what rates
81 * are really supported.
83 #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
84 SNDRV_PCM_RATE_CONTINUOUS)
87 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
89 * This driver currently only supports the SSI running in I2S slave mode.
91 * The SSI has a limitation in that the samples must be in the same byte
92 * order as the host CPU. This is because when multiple bytes are written
93 * to the STX register, the bytes and bits must be written in the same
94 * order. The STX is a shift register, so all the bits need to be aligned
95 * (bit-endianness must match byte-endianness). Processors typically write
96 * the bits within a byte in the same order that the bytes of a word are
97 * written in. So if the host CPU is big-endian, then only big-endian
98 * samples will be written to STX properly.
101 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
102 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
103 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
105 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
106 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
107 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
110 /* SIER bitflag of interrupts to enable */
111 #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \
112 CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \
113 CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \
114 CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
115 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
118 * fsl_ssi_private: per-SSI private data
120 * @ssi: pointer to the SSI's registers
121 * @ssi_phys: physical address of the SSI registers
122 * @irq: IRQ of this SSI
123 * @playback: the number of playback streams opened
124 * @capture: the number of capture streams opened
125 * @cpu_dai: the CPU DAI for this device
126 * @dev_attr: the sysfs device attribute structure
127 * @stats: SSI statistics
128 * @name: name for this device
130 struct fsl_ssi_private
{
131 struct ccsr_ssi __iomem
*ssi
;
134 unsigned int fifo_depth
;
135 struct snd_soc_dai_driver cpu_dai_drv
;
136 struct device_attribute dev_attr
;
137 struct platform_device
*pdev
;
146 spinlock_t baudclk_lock
;
149 struct snd_dmaengine_dai_dma_data dma_params_tx
;
150 struct snd_dmaengine_dai_dma_data dma_params_rx
;
151 struct imx_dma_data filter_data_tx
;
152 struct imx_dma_data filter_data_rx
;
153 struct imx_pcm_fiq_params fiq_params
;
183 * fsl_ssi_isr: SSI interrupt handler
185 * Although it's possible to use the interrupt handler to send and receive
186 * data to/from the SSI, we use the DMA instead. Programming is more
187 * complicated, but the performance is much better.
189 * This interrupt handler is used only to gather statistics.
191 * @irq: IRQ of the SSI device
192 * @dev_id: pointer to the ssi_private structure for this SSI device
194 static irqreturn_t
fsl_ssi_isr(int irq
, void *dev_id
)
196 struct fsl_ssi_private
*ssi_private
= dev_id
;
197 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
198 irqreturn_t ret
= IRQ_NONE
;
202 /* We got an interrupt, so read the status register to see what we
203 were interrupted for. We mask it with the Interrupt Enable register
204 so that we only check for events that we're interested in.
206 sisr
= read_ssi(&ssi
->sisr
) & SIER_FLAGS
;
208 if (sisr
& CCSR_SSI_SISR_RFRC
) {
209 ssi_private
->stats
.rfrc
++;
210 sisr2
|= CCSR_SSI_SISR_RFRC
;
214 if (sisr
& CCSR_SSI_SISR_TFRC
) {
215 ssi_private
->stats
.tfrc
++;
216 sisr2
|= CCSR_SSI_SISR_TFRC
;
220 if (sisr
& CCSR_SSI_SISR_CMDAU
) {
221 ssi_private
->stats
.cmdau
++;
225 if (sisr
& CCSR_SSI_SISR_CMDDU
) {
226 ssi_private
->stats
.cmddu
++;
230 if (sisr
& CCSR_SSI_SISR_RXT
) {
231 ssi_private
->stats
.rxt
++;
235 if (sisr
& CCSR_SSI_SISR_RDR1
) {
236 ssi_private
->stats
.rdr1
++;
240 if (sisr
& CCSR_SSI_SISR_RDR0
) {
241 ssi_private
->stats
.rdr0
++;
245 if (sisr
& CCSR_SSI_SISR_TDE1
) {
246 ssi_private
->stats
.tde1
++;
250 if (sisr
& CCSR_SSI_SISR_TDE0
) {
251 ssi_private
->stats
.tde0
++;
255 if (sisr
& CCSR_SSI_SISR_ROE1
) {
256 ssi_private
->stats
.roe1
++;
257 sisr2
|= CCSR_SSI_SISR_ROE1
;
261 if (sisr
& CCSR_SSI_SISR_ROE0
) {
262 ssi_private
->stats
.roe0
++;
263 sisr2
|= CCSR_SSI_SISR_ROE0
;
267 if (sisr
& CCSR_SSI_SISR_TUE1
) {
268 ssi_private
->stats
.tue1
++;
269 sisr2
|= CCSR_SSI_SISR_TUE1
;
273 if (sisr
& CCSR_SSI_SISR_TUE0
) {
274 ssi_private
->stats
.tue0
++;
275 sisr2
|= CCSR_SSI_SISR_TUE0
;
279 if (sisr
& CCSR_SSI_SISR_TFS
) {
280 ssi_private
->stats
.tfs
++;
284 if (sisr
& CCSR_SSI_SISR_RFS
) {
285 ssi_private
->stats
.rfs
++;
289 if (sisr
& CCSR_SSI_SISR_TLS
) {
290 ssi_private
->stats
.tls
++;
294 if (sisr
& CCSR_SSI_SISR_RLS
) {
295 ssi_private
->stats
.rls
++;
299 if (sisr
& CCSR_SSI_SISR_RFF1
) {
300 ssi_private
->stats
.rff1
++;
304 if (sisr
& CCSR_SSI_SISR_RFF0
) {
305 ssi_private
->stats
.rff0
++;
309 if (sisr
& CCSR_SSI_SISR_TFE1
) {
310 ssi_private
->stats
.tfe1
++;
314 if (sisr
& CCSR_SSI_SISR_TFE0
) {
315 ssi_private
->stats
.tfe0
++;
319 /* Clear the bits that we set */
321 write_ssi(sisr2
, &ssi
->sisr
);
326 static void fsl_ssi_setup_ac97(struct fsl_ssi_private
*ssi_private
)
328 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
331 * Setup the clock control register
333 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
335 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
339 * Enable AC97 mode and startup the SSI
341 write_ssi(CCSR_SSI_SACNT_AC97EN
| CCSR_SSI_SACNT_FV
,
343 write_ssi(0xff, &ssi
->saccdis
);
344 write_ssi(0x300, &ssi
->saccen
);
347 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
348 * codec before a stream is started.
350 write_ssi_mask(&ssi
->scr
, 0, CCSR_SSI_SCR_SSIEN
|
351 CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
);
353 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi
->sor
);
356 static int fsl_ssi_setup(struct fsl_ssi_private
*ssi_private
)
358 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
360 int synchronous
= ssi_private
->cpu_dai_drv
.symmetric_rates
;
362 if (ssi_private
->imx_ac97
)
363 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_NORMAL
| CCSR_SSI_SCR_NET
;
365 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_SLAVE
;
368 * Section 16.5 of the MPC8610 reference manual says that the SSI needs
369 * to be disabled before updating the registers we set here.
371 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_SSIEN
, 0);
374 * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
375 * enable the transmit and receive FIFO.
377 * FIXME: Little-endian samples require a different shift dir
379 write_ssi_mask(&ssi
->scr
,
380 CCSR_SSI_SCR_I2S_MODE_MASK
| CCSR_SSI_SCR_SYN
,
381 CCSR_SSI_SCR_TFR_CLK_DIS
|
382 ssi_private
->i2s_mode
|
383 (synchronous
? CCSR_SSI_SCR_SYN
: 0));
385 write_ssi(CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TFEN0
|
386 CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TEFS
|
387 CCSR_SSI_STCR_TSCKP
, &ssi
->stcr
);
389 write_ssi(CCSR_SSI_SRCR_RXBIT0
| CCSR_SSI_SRCR_RFEN0
|
390 CCSR_SSI_SRCR_RFSI
| CCSR_SSI_SRCR_REFS
|
391 CCSR_SSI_SRCR_RSCKP
, &ssi
->srcr
);
393 * The DC and PM bits are only used if the SSI is the clock master.
397 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
398 * use FIFO 1. We program the transmit water to signal a DMA transfer
399 * if there are only two (or fewer) elements left in the FIFO. Two
400 * elements equals one frame (left channel, right channel). This value,
401 * however, depends on the depth of the transmit buffer.
403 * We set the watermark on the same level as the DMA burstsize. For
404 * fiq it is probably better to use the biggest possible watermark
407 if (ssi_private
->use_dma
)
408 wm
= ssi_private
->fifo_depth
- 2;
410 wm
= ssi_private
->fifo_depth
;
412 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm
) | CCSR_SSI_SFCSR_RFWM0(wm
) |
413 CCSR_SSI_SFCSR_TFWM1(wm
) | CCSR_SSI_SFCSR_RFWM1(wm
),
417 * For ac97 interrupts are enabled with the startup of the substream
418 * because it is also running without an active substream. Normally SSI
419 * is only enabled when there is a substream.
421 if (ssi_private
->imx_ac97
)
422 fsl_ssi_setup_ac97(ssi_private
);
429 * fsl_ssi_startup: create a new substream
431 * This is the first function called when a stream is opened.
433 * If this is the first stream open, then grab the IRQ and program most of
436 static int fsl_ssi_startup(struct snd_pcm_substream
*substream
,
437 struct snd_soc_dai
*dai
)
439 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
440 struct fsl_ssi_private
*ssi_private
=
441 snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
444 /* First, we only do fsl_ssi_setup() when SSI is going to be active.
445 * Second, fsl_ssi_setup was already called by ac97_init earlier if
446 * the driver is in ac97 mode.
448 if (!dai
->active
&& !ssi_private
->imx_ac97
) {
449 fsl_ssi_setup(ssi_private
);
450 spin_lock_irqsave(&ssi_private
->baudclk_lock
, flags
);
451 ssi_private
->baudclk_locked
= false;
452 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
459 * fsl_ssi_hw_params - program the sample size
461 * Most of the SSI registers have been programmed in the startup function,
462 * but the word length must be programmed here. Unfortunately, programming
463 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
464 * cause a problem with supporting simultaneous playback and capture. If
465 * the SSI is already playing a stream, then that stream may be temporarily
466 * stopped when you start capture.
468 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
471 static int fsl_ssi_hw_params(struct snd_pcm_substream
*substream
,
472 struct snd_pcm_hw_params
*hw_params
, struct snd_soc_dai
*cpu_dai
)
474 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
475 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
476 unsigned int channels
= params_channels(hw_params
);
477 unsigned int sample_size
=
478 snd_pcm_format_width(params_format(hw_params
));
479 u32 wl
= CCSR_SSI_SxCCR_WL(sample_size
);
480 int enabled
= read_ssi(&ssi
->scr
) & CCSR_SSI_SCR_SSIEN
;
483 * If we're in synchronous mode, and the SSI is already enabled,
484 * then STCCR is already set properly.
486 if (enabled
&& ssi_private
->cpu_dai_drv
.symmetric_rates
)
490 * FIXME: The documentation says that SxCCR[WL] should not be
491 * modified while the SSI is enabled. The only time this can
492 * happen is if we're trying to do simultaneous playback and
493 * capture in asynchronous mode. Unfortunately, I have been enable
494 * to get that to work at all on the P1022DS. Therefore, we don't
495 * bother to disable/enable the SSI when setting SxCCR[WL], because
496 * the SSI will stop anyway. Maybe one day, this will get fixed.
499 /* In synchronous mode, the SSI uses STCCR for capture */
500 if ((substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) ||
501 ssi_private
->cpu_dai_drv
.symmetric_rates
)
502 write_ssi_mask(&ssi
->stccr
, CCSR_SSI_SxCCR_WL_MASK
, wl
);
504 write_ssi_mask(&ssi
->srccr
, CCSR_SSI_SxCCR_WL_MASK
, wl
);
506 if (!ssi_private
->imx_ac97
)
507 write_ssi_mask(&ssi
->scr
,
508 CCSR_SSI_SCR_NET
| CCSR_SSI_SCR_I2S_MODE_MASK
,
509 channels
== 1 ? 0 : ssi_private
->i2s_mode
);
515 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
517 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai
*cpu_dai
, unsigned int fmt
)
519 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
520 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
521 u32 strcr
= 0, stcr
, srcr
, scr
, mask
;
523 scr
= read_ssi(&ssi
->scr
) & ~(CCSR_SSI_SCR_SYN
| CCSR_SSI_SCR_I2S_MODE_MASK
);
524 scr
|= CCSR_SSI_SCR_NET
;
526 mask
= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
|
527 CCSR_SSI_STCR_TSCKP
| CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TFSL
|
529 stcr
= read_ssi(&ssi
->stcr
) & ~mask
;
530 srcr
= read_ssi(&ssi
->srcr
) & ~mask
;
532 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
533 case SND_SOC_DAIFMT_I2S
:
534 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
535 case SND_SOC_DAIFMT_CBS_CFS
:
536 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_MASTER
;
538 case SND_SOC_DAIFMT_CBM_CFM
:
539 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_SLAVE
;
544 scr
|= ssi_private
->i2s_mode
;
546 /* Data on rising edge of bclk, frame low, 1clk before data */
547 strcr
|= CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TSCKP
|
548 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
550 case SND_SOC_DAIFMT_LEFT_J
:
551 /* Data on rising edge of bclk, frame high */
552 strcr
|= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TSCKP
;
554 case SND_SOC_DAIFMT_DSP_A
:
555 /* Data on rising edge of bclk, frame high, 1clk before data */
556 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
557 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
559 case SND_SOC_DAIFMT_DSP_B
:
560 /* Data on rising edge of bclk, frame high */
561 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
562 CCSR_SSI_STCR_TXBIT0
;
568 /* DAI clock inversion */
569 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
570 case SND_SOC_DAIFMT_NB_NF
:
571 /* Nothing to do for both normal cases */
573 case SND_SOC_DAIFMT_IB_NF
:
574 /* Invert bit clock */
575 strcr
^= CCSR_SSI_STCR_TSCKP
;
577 case SND_SOC_DAIFMT_NB_IF
:
578 /* Invert frame clock */
579 strcr
^= CCSR_SSI_STCR_TFSI
;
581 case SND_SOC_DAIFMT_IB_IF
:
582 /* Invert both clocks */
583 strcr
^= CCSR_SSI_STCR_TSCKP
;
584 strcr
^= CCSR_SSI_STCR_TFSI
;
590 /* DAI clock master masks */
591 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
592 case SND_SOC_DAIFMT_CBS_CFS
:
593 strcr
|= CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
;
594 scr
|= CCSR_SSI_SCR_SYS_CLK_EN
;
596 case SND_SOC_DAIFMT_CBM_CFM
:
597 scr
&= ~CCSR_SSI_SCR_SYS_CLK_EN
;
606 if (ssi_private
->cpu_dai_drv
.symmetric_rates
) {
607 /* Need to clear RXDIR when using SYNC mode */
608 srcr
&= ~CCSR_SSI_SRCR_RXDIR
;
609 scr
|= CCSR_SSI_SCR_SYN
;
612 write_ssi(stcr
, &ssi
->stcr
);
613 write_ssi(srcr
, &ssi
->srcr
);
614 write_ssi(scr
, &ssi
->scr
);
620 * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
622 * Note: This function can be only called when using SSI as DAI master
624 * Quick instruction for parameters:
625 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
626 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
628 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai
*cpu_dai
,
629 int clk_id
, unsigned int freq
, int dir
)
631 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
632 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
633 int synchronous
= ssi_private
->cpu_dai_drv
.symmetric_rates
, ret
;
634 u32 pm
= 999, div2
, psr
, stccr
, mask
, afreq
, factor
, i
;
635 unsigned long flags
, clkrate
, baudrate
, tmprate
;
636 u64 sub
, savesub
= 100000;
638 /* Don't apply it to any non-baudclk circumstance */
639 if (IS_ERR(ssi_private
->baudclk
))
642 /* It should be already enough to divide clock by setting pm alone */
646 factor
= (div2
+ 1) * (7 * psr
+ 1) * 2;
648 for (i
= 0; i
< 255; i
++) {
649 /* The bclk rate must be smaller than 1/5 sysclk rate */
650 if (factor
* (i
+ 1) < 5)
653 tmprate
= freq
* factor
* (i
+ 2);
654 clkrate
= clk_round_rate(ssi_private
->baudclk
, tmprate
);
656 do_div(clkrate
, factor
);
657 afreq
= (u32
)clkrate
/ (i
+ 1);
661 else if (freq
/ afreq
== 1)
663 else if (afreq
/ freq
== 1)
668 /* Calculate the fraction */
683 /* No proper pm found if it is still remaining the initial value */
685 dev_err(cpu_dai
->dev
, "failed to handle the required sysclk\n");
689 stccr
= CCSR_SSI_SxCCR_PM(pm
+ 1) | (div2
? CCSR_SSI_SxCCR_DIV2
: 0) |
690 (psr
? CCSR_SSI_SxCCR_PSR
: 0);
691 mask
= CCSR_SSI_SxCCR_PM_MASK
| CCSR_SSI_SxCCR_DIV2
| CCSR_SSI_SxCCR_PSR
;
693 if (dir
== SND_SOC_CLOCK_OUT
|| synchronous
)
694 write_ssi_mask(&ssi
->stccr
, mask
, stccr
);
696 write_ssi_mask(&ssi
->srccr
, mask
, stccr
);
698 spin_lock_irqsave(&ssi_private
->baudclk_lock
, flags
);
699 if (!ssi_private
->baudclk_locked
) {
700 ret
= clk_set_rate(ssi_private
->baudclk
, baudrate
);
702 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
703 dev_err(cpu_dai
->dev
, "failed to set baudclk rate\n");
706 ssi_private
->baudclk_locked
= true;
708 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
714 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
716 * Note: This function can be only called when using SSI as DAI master
718 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai
*cpu_dai
, u32 tx_mask
,
719 u32 rx_mask
, int slots
, int slot_width
)
721 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
722 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
725 /* The slot number should be >= 2 if using Network mode or I2S mode */
726 val
= read_ssi(&ssi
->scr
) & (CCSR_SSI_SCR_I2S_MODE_MASK
| CCSR_SSI_SCR_NET
);
727 if (val
&& slots
< 2) {
728 dev_err(cpu_dai
->dev
, "slot number should be >= 2 in I2S or NET\n");
732 write_ssi_mask(&ssi
->stccr
, CCSR_SSI_SxCCR_DC_MASK
,
733 CCSR_SSI_SxCCR_DC(slots
));
734 write_ssi_mask(&ssi
->srccr
, CCSR_SSI_SxCCR_DC_MASK
,
735 CCSR_SSI_SxCCR_DC(slots
));
737 /* The register SxMSKs needs SSI to provide essential clock due to
738 * hardware design. So we here temporarily enable SSI to set them.
740 val
= read_ssi(&ssi
->scr
) & CCSR_SSI_SCR_SSIEN
;
741 write_ssi_mask(&ssi
->scr
, 0, CCSR_SSI_SCR_SSIEN
);
743 write_ssi(tx_mask
, &ssi
->stmsk
);
744 write_ssi(rx_mask
, &ssi
->srmsk
);
746 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_SSIEN
, val
);
752 * fsl_ssi_trigger: start and stop the DMA transfer.
754 * This function is called by ALSA to start, stop, pause, and resume the DMA
757 * The DMA channel is in external master start and pause mode, which
758 * means the SSI completely controls the flow of data.
760 static int fsl_ssi_trigger(struct snd_pcm_substream
*substream
, int cmd
,
761 struct snd_soc_dai
*dai
)
763 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
764 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
765 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
766 unsigned int sier_bits
;
770 * Enable only the interrupts and DMA requests
771 * that are needed for the channel. As the fiq
772 * is polling for this bits, we have to ensure
773 * that this are aligned with the preallocated
777 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
778 if (ssi_private
->use_dma
)
779 sier_bits
= SIER_FLAGS
;
781 sier_bits
= CCSR_SSI_SIER_TIE
| CCSR_SSI_SIER_TFE0_EN
;
783 if (ssi_private
->use_dma
)
784 sier_bits
= SIER_FLAGS
;
786 sier_bits
= CCSR_SSI_SIER_RIE
| CCSR_SSI_SIER_RFF0_EN
;
790 case SNDRV_PCM_TRIGGER_START
:
791 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
792 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
793 write_ssi_mask(&ssi
->scr
, 0,
794 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_TE
);
796 write_ssi_mask(&ssi
->scr
, 0,
797 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_RE
);
800 case SNDRV_PCM_TRIGGER_STOP
:
801 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
802 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
803 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_TE
, 0);
805 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_RE
, 0);
807 if (!ssi_private
->imx_ac97
&& (read_ssi(&ssi
->scr
) &
808 (CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
)) == 0) {
809 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_SSIEN
, 0);
810 spin_lock_irqsave(&ssi_private
->baudclk_lock
, flags
);
811 ssi_private
->baudclk_locked
= false;
812 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
820 write_ssi(sier_bits
, &ssi
->sier
);
825 static int fsl_ssi_dai_probe(struct snd_soc_dai
*dai
)
827 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(dai
);
829 if (ssi_private
->ssi_on_imx
&& ssi_private
->use_dma
) {
830 dai
->playback_dma_data
= &ssi_private
->dma_params_tx
;
831 dai
->capture_dma_data
= &ssi_private
->dma_params_rx
;
837 static const struct snd_soc_dai_ops fsl_ssi_dai_ops
= {
838 .startup
= fsl_ssi_startup
,
839 .hw_params
= fsl_ssi_hw_params
,
840 .set_fmt
= fsl_ssi_set_dai_fmt
,
841 .set_sysclk
= fsl_ssi_set_dai_sysclk
,
842 .set_tdm_slot
= fsl_ssi_set_dai_tdm_slot
,
843 .trigger
= fsl_ssi_trigger
,
846 /* Template for the CPU dai driver structure */
847 static struct snd_soc_dai_driver fsl_ssi_dai_template
= {
848 .probe
= fsl_ssi_dai_probe
,
852 .rates
= FSLSSI_I2S_RATES
,
853 .formats
= FSLSSI_I2S_FORMATS
,
858 .rates
= FSLSSI_I2S_RATES
,
859 .formats
= FSLSSI_I2S_FORMATS
,
861 .ops
= &fsl_ssi_dai_ops
,
864 static const struct snd_soc_component_driver fsl_ssi_component
= {
869 * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit.
871 * This function is called by ALSA to start, stop, pause, and resume the
874 static int fsl_ssi_ac97_trigger(struct snd_pcm_substream
*substream
, int cmd
,
875 struct snd_soc_dai
*dai
)
877 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
878 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(
880 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
883 case SNDRV_PCM_TRIGGER_START
:
884 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
885 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
886 write_ssi_mask(&ssi
->sier
, 0, CCSR_SSI_SIER_TIE
|
887 CCSR_SSI_SIER_TFE0_EN
);
889 write_ssi_mask(&ssi
->sier
, 0, CCSR_SSI_SIER_RIE
|
890 CCSR_SSI_SIER_RFF0_EN
);
893 case SNDRV_PCM_TRIGGER_STOP
:
894 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
895 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
896 write_ssi_mask(&ssi
->sier
, CCSR_SSI_SIER_TIE
|
897 CCSR_SSI_SIER_TFE0_EN
, 0);
899 write_ssi_mask(&ssi
->sier
, CCSR_SSI_SIER_RIE
|
900 CCSR_SSI_SIER_RFF0_EN
, 0);
907 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
908 write_ssi(CCSR_SSI_SOR_TX_CLR
, &ssi
->sor
);
910 write_ssi(CCSR_SSI_SOR_RX_CLR
, &ssi
->sor
);
915 static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops
= {
916 .startup
= fsl_ssi_startup
,
917 .trigger
= fsl_ssi_ac97_trigger
,
920 static struct snd_soc_dai_driver fsl_ssi_ac97_dai
= {
923 .stream_name
= "AC97 Playback",
926 .rates
= SNDRV_PCM_RATE_8000_48000
,
927 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
930 .stream_name
= "AC97 Capture",
933 .rates
= SNDRV_PCM_RATE_48000
,
934 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
936 .ops
= &fsl_ssi_ac97_dai_ops
,
940 static struct fsl_ssi_private
*fsl_ac97_data
;
942 static void fsl_ssi_ac97_init(void)
944 fsl_ssi_setup(fsl_ac97_data
);
947 static void fsl_ssi_ac97_write(struct snd_ac97
*ac97
, unsigned short reg
,
950 struct ccsr_ssi
*ssi
= fsl_ac97_data
->ssi
;
959 write_ssi(lreg
, &ssi
->sacadd
);
962 write_ssi(lval
, &ssi
->sacdat
);
964 write_ssi_mask(&ssi
->sacnt
, CCSR_SSI_SACNT_RDWR_MASK
,
969 static unsigned short fsl_ssi_ac97_read(struct snd_ac97
*ac97
,
972 struct ccsr_ssi
*ssi
= fsl_ac97_data
->ssi
;
974 unsigned short val
= -1;
977 lreg
= (reg
& 0x7f) << 12;
978 write_ssi(lreg
, &ssi
->sacadd
);
979 write_ssi_mask(&ssi
->sacnt
, CCSR_SSI_SACNT_RDWR_MASK
,
984 val
= (read_ssi(&ssi
->sacdat
) >> 4) & 0xffff;
989 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops
= {
990 .read
= fsl_ssi_ac97_read
,
991 .write
= fsl_ssi_ac97_write
,
994 /* Show the statistics of a flag only if its interrupt is enabled. The
995 * compiler will optimze this code to a no-op if the interrupt is not
998 #define SIER_SHOW(flag, name) \
1000 if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \
1001 length += sprintf(buf + length, #name "=%u\n", \
1002 ssi_private->stats.name); \
1007 * fsl_sysfs_ssi_show: display SSI statistics
1009 * Display the statistics for the current SSI device. To avoid confusion,
1010 * we only show those counts that are enabled.
1012 static ssize_t
fsl_sysfs_ssi_show(struct device
*dev
,
1013 struct device_attribute
*attr
, char *buf
)
1015 struct fsl_ssi_private
*ssi_private
=
1016 container_of(attr
, struct fsl_ssi_private
, dev_attr
);
1019 SIER_SHOW(RFRC_EN
, rfrc
);
1020 SIER_SHOW(TFRC_EN
, tfrc
);
1021 SIER_SHOW(CMDAU_EN
, cmdau
);
1022 SIER_SHOW(CMDDU_EN
, cmddu
);
1023 SIER_SHOW(RXT_EN
, rxt
);
1024 SIER_SHOW(RDR1_EN
, rdr1
);
1025 SIER_SHOW(RDR0_EN
, rdr0
);
1026 SIER_SHOW(TDE1_EN
, tde1
);
1027 SIER_SHOW(TDE0_EN
, tde0
);
1028 SIER_SHOW(ROE1_EN
, roe1
);
1029 SIER_SHOW(ROE0_EN
, roe0
);
1030 SIER_SHOW(TUE1_EN
, tue1
);
1031 SIER_SHOW(TUE0_EN
, tue0
);
1032 SIER_SHOW(TFS_EN
, tfs
);
1033 SIER_SHOW(RFS_EN
, rfs
);
1034 SIER_SHOW(TLS_EN
, tls
);
1035 SIER_SHOW(RLS_EN
, rls
);
1036 SIER_SHOW(RFF1_EN
, rff1
);
1037 SIER_SHOW(RFF0_EN
, rff0
);
1038 SIER_SHOW(TFE1_EN
, tfe1
);
1039 SIER_SHOW(TFE0_EN
, tfe0
);
1045 * Make every character in a string lower-case
1047 static void make_lowercase(char *s
)
1053 if ((c
>= 'A') && (c
<= 'Z'))
1054 *p
= c
+ ('a' - 'A');
1059 static int fsl_ssi_probe(struct platform_device
*pdev
)
1061 struct fsl_ssi_private
*ssi_private
;
1063 struct device_attribute
*dev_attr
= NULL
;
1064 struct device_node
*np
= pdev
->dev
.of_node
;
1065 const char *p
, *sprop
;
1066 const uint32_t *iprop
;
1067 struct resource res
;
1072 /* SSIs that are not connected on the board should have a
1073 * status = "disabled"
1074 * property in their device tree nodes.
1076 if (!of_device_is_available(np
))
1079 /* We only support the SSI in "I2S Slave" mode */
1080 sprop
= of_get_property(np
, "fsl,mode", NULL
);
1082 dev_err(&pdev
->dev
, "fsl,mode property is necessary\n");
1085 if (!strcmp(sprop
, "ac97-slave")) {
1087 } else if (strcmp(sprop
, "i2s-slave")) {
1088 dev_notice(&pdev
->dev
, "mode %s is unsupported\n", sprop
);
1092 /* The DAI name is the last part of the full name of the node. */
1093 p
= strrchr(np
->full_name
, '/') + 1;
1094 ssi_private
= devm_kzalloc(&pdev
->dev
, sizeof(*ssi_private
) + strlen(p
),
1097 dev_err(&pdev
->dev
, "could not allocate DAI object\n");
1101 strcpy(ssi_private
->name
, p
);
1103 ssi_private
->use_dma
= !of_property_read_bool(np
,
1104 "fsl,fiq-stream-filter");
1107 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_ac97_dai
,
1108 sizeof(fsl_ssi_ac97_dai
));
1110 fsl_ac97_data
= ssi_private
;
1111 ssi_private
->imx_ac97
= true;
1113 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops
, pdev
);
1115 /* Initialize this copy of the CPU DAI driver structure */
1116 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_dai_template
,
1117 sizeof(fsl_ssi_dai_template
));
1119 ssi_private
->cpu_dai_drv
.name
= ssi_private
->name
;
1121 /* Get the addresses and IRQ */
1122 ret
= of_address_to_resource(np
, 0, &res
);
1124 dev_err(&pdev
->dev
, "could not determine device resources\n");
1127 ssi_private
->ssi
= of_iomap(np
, 0);
1128 if (!ssi_private
->ssi
) {
1129 dev_err(&pdev
->dev
, "could not map device resources\n");
1132 ssi_private
->ssi_phys
= res
.start
;
1134 ssi_private
->irq
= irq_of_parse_and_map(np
, 0);
1135 if (!ssi_private
->irq
) {
1136 dev_err(&pdev
->dev
, "no irq for node %s\n", np
->full_name
);
1140 /* Are the RX and the TX clocks locked? */
1141 if (!of_find_property(np
, "fsl,ssi-asynchronous", NULL
)) {
1142 ssi_private
->cpu_dai_drv
.symmetric_rates
= 1;
1143 ssi_private
->cpu_dai_drv
.symmetric_channels
= 1;
1144 ssi_private
->cpu_dai_drv
.symmetric_samplebits
= 1;
1147 /* Determine the FIFO depth. */
1148 iprop
= of_get_property(np
, "fsl,fifo-depth", NULL
);
1150 ssi_private
->fifo_depth
= be32_to_cpup(iprop
);
1152 /* Older 8610 DTs didn't have the fifo-depth property */
1153 ssi_private
->fifo_depth
= 8;
1155 ssi_private
->baudclk_locked
= false;
1156 spin_lock_init(&ssi_private
->baudclk_lock
);
1158 if (of_device_is_compatible(pdev
->dev
.of_node
, "fsl,imx21-ssi")) {
1160 ssi_private
->ssi_on_imx
= true;
1162 ssi_private
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1163 if (IS_ERR(ssi_private
->clk
)) {
1164 ret
= PTR_ERR(ssi_private
->clk
);
1165 dev_err(&pdev
->dev
, "could not get clock: %d\n", ret
);
1168 ret
= clk_prepare_enable(ssi_private
->clk
);
1170 dev_err(&pdev
->dev
, "clk_prepare_enable failed: %d\n",
1175 /* For those SLAVE implementations, we ingore non-baudclk cases
1176 * and, instead, abandon MASTER mode that needs baud clock.
1178 ssi_private
->baudclk
= devm_clk_get(&pdev
->dev
, "baud");
1179 if (IS_ERR(ssi_private
->baudclk
))
1180 dev_warn(&pdev
->dev
, "could not get baud clock: %ld\n",
1181 PTR_ERR(ssi_private
->baudclk
));
1183 clk_prepare_enable(ssi_private
->baudclk
);
1186 * We have burstsize be "fifo_depth - 2" to match the SSI
1187 * watermark setting in fsl_ssi_startup().
1189 ssi_private
->dma_params_tx
.maxburst
=
1190 ssi_private
->fifo_depth
- 2;
1191 ssi_private
->dma_params_rx
.maxburst
=
1192 ssi_private
->fifo_depth
- 2;
1193 ssi_private
->dma_params_tx
.addr
=
1194 ssi_private
->ssi_phys
+ offsetof(struct ccsr_ssi
, stx0
);
1195 ssi_private
->dma_params_rx
.addr
=
1196 ssi_private
->ssi_phys
+ offsetof(struct ccsr_ssi
, srx0
);
1197 ssi_private
->dma_params_tx
.filter_data
=
1198 &ssi_private
->filter_data_tx
;
1199 ssi_private
->dma_params_rx
.filter_data
=
1200 &ssi_private
->filter_data_rx
;
1201 if (!of_property_read_bool(pdev
->dev
.of_node
, "dmas") &&
1202 ssi_private
->use_dma
) {
1204 * FIXME: This is a temporary solution until all
1205 * necessary dma drivers support the generic dma
1208 ret
= of_property_read_u32_array(pdev
->dev
.of_node
,
1209 "fsl,ssi-dma-events", dma_events
, 2);
1210 if (ret
&& ssi_private
->use_dma
) {
1211 dev_err(&pdev
->dev
, "could not get dma events but fsl-ssi is configured to use DMA\n");
1216 shared
= of_device_is_compatible(of_get_parent(np
),
1219 imx_pcm_dma_params_init_data(&ssi_private
->filter_data_tx
,
1220 dma_events
[0], shared
? IMX_DMATYPE_SSI_SP
: IMX_DMATYPE_SSI
);
1221 imx_pcm_dma_params_init_data(&ssi_private
->filter_data_rx
,
1222 dma_events
[1], shared
? IMX_DMATYPE_SSI_SP
: IMX_DMATYPE_SSI
);
1223 } else if (ssi_private
->use_dma
) {
1224 /* The 'name' should not have any slashes in it. */
1225 ret
= devm_request_irq(&pdev
->dev
, ssi_private
->irq
,
1226 fsl_ssi_isr
, 0, ssi_private
->name
,
1228 ssi_private
->irq_stats
= true;
1230 dev_err(&pdev
->dev
, "could not claim irq %u\n",
1236 /* Initialize the the device_attribute structure */
1237 dev_attr
= &ssi_private
->dev_attr
;
1238 sysfs_attr_init(&dev_attr
->attr
);
1239 dev_attr
->attr
.name
= "statistics";
1240 dev_attr
->attr
.mode
= S_IRUGO
;
1241 dev_attr
->show
= fsl_sysfs_ssi_show
;
1243 ret
= device_create_file(&pdev
->dev
, dev_attr
);
1245 dev_err(&pdev
->dev
, "could not create sysfs %s file\n",
1246 ssi_private
->dev_attr
.attr
.name
);
1250 /* Register with ASoC */
1251 dev_set_drvdata(&pdev
->dev
, ssi_private
);
1253 ret
= snd_soc_register_component(&pdev
->dev
, &fsl_ssi_component
,
1254 &ssi_private
->cpu_dai_drv
, 1);
1256 dev_err(&pdev
->dev
, "failed to register DAI: %d\n", ret
);
1260 if (ssi_private
->ssi_on_imx
) {
1261 if (!ssi_private
->use_dma
) {
1264 * Some boards use an incompatible codec. To get it
1265 * working, we are using imx-fiq-pcm-audio, that
1266 * can handle those codecs. DMA is not possible in this
1270 ssi_private
->fiq_params
.irq
= ssi_private
->irq
;
1271 ssi_private
->fiq_params
.base
= ssi_private
->ssi
;
1272 ssi_private
->fiq_params
.dma_params_rx
=
1273 &ssi_private
->dma_params_rx
;
1274 ssi_private
->fiq_params
.dma_params_tx
=
1275 &ssi_private
->dma_params_tx
;
1277 ret
= imx_pcm_fiq_init(pdev
, &ssi_private
->fiq_params
);
1281 ret
= imx_pcm_dma_init(pdev
);
1288 * If codec-handle property is missing from SSI node, we assume
1289 * that the machine driver uses new binding which does not require
1290 * SSI driver to trigger machine driver's probe.
1292 if (!of_get_property(np
, "codec-handle", NULL
)) {
1293 ssi_private
->new_binding
= true;
1297 /* Trigger the machine driver's probe function. The platform driver
1298 * name of the machine driver is taken from /compatible property of the
1299 * device tree. We also pass the address of the CPU DAI driver
1302 sprop
= of_get_property(of_find_node_by_path("/"), "compatible", NULL
);
1303 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1304 p
= strrchr(sprop
, ',');
1307 snprintf(name
, sizeof(name
), "snd-soc-%s", sprop
);
1308 make_lowercase(name
);
1311 platform_device_register_data(&pdev
->dev
, name
, 0, NULL
, 0);
1312 if (IS_ERR(ssi_private
->pdev
)) {
1313 ret
= PTR_ERR(ssi_private
->pdev
);
1314 dev_err(&pdev
->dev
, "failed to register platform: %d\n", ret
);
1319 if (ssi_private
->imx_ac97
)
1320 fsl_ssi_ac97_init();
1325 if (ssi_private
->ssi_on_imx
&& !ssi_private
->use_dma
)
1326 imx_pcm_fiq_exit(pdev
);
1329 snd_soc_unregister_component(&pdev
->dev
);
1332 device_remove_file(&pdev
->dev
, dev_attr
);
1335 if (ssi_private
->ssi_on_imx
) {
1336 if (!IS_ERR(ssi_private
->baudclk
))
1337 clk_disable_unprepare(ssi_private
->baudclk
);
1338 clk_disable_unprepare(ssi_private
->clk
);
1342 if (ssi_private
->irq_stats
)
1343 irq_dispose_mapping(ssi_private
->irq
);
1348 static int fsl_ssi_remove(struct platform_device
*pdev
)
1350 struct fsl_ssi_private
*ssi_private
= dev_get_drvdata(&pdev
->dev
);
1352 if (!ssi_private
->new_binding
)
1353 platform_device_unregister(ssi_private
->pdev
);
1354 snd_soc_unregister_component(&pdev
->dev
);
1355 device_remove_file(&pdev
->dev
, &ssi_private
->dev_attr
);
1356 if (ssi_private
->ssi_on_imx
) {
1357 if (!IS_ERR(ssi_private
->baudclk
))
1358 clk_disable_unprepare(ssi_private
->baudclk
);
1359 clk_disable_unprepare(ssi_private
->clk
);
1361 if (ssi_private
->irq_stats
)
1362 irq_dispose_mapping(ssi_private
->irq
);
1367 static const struct of_device_id fsl_ssi_ids
[] = {
1368 { .compatible
= "fsl,mpc8610-ssi", },
1369 { .compatible
= "fsl,imx21-ssi", },
1372 MODULE_DEVICE_TABLE(of
, fsl_ssi_ids
);
1374 static struct platform_driver fsl_ssi_driver
= {
1376 .name
= "fsl-ssi-dai",
1377 .owner
= THIS_MODULE
,
1378 .of_match_table
= fsl_ssi_ids
,
1380 .probe
= fsl_ssi_probe
,
1381 .remove
= fsl_ssi_remove
,
1384 module_platform_driver(fsl_ssi_driver
);
1386 MODULE_ALIAS("platform:fsl-ssi-dai");
1387 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1388 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1389 MODULE_LICENSE("GPL v2");