drivers/net/wireless/wl12xx/wl12xx.h

   1 /*
   2  * This file is part of wl12xx
   3  *
   4  * Copyright (c) 1998-2007 Texas Instruments Incorporated
   5  * Copyright (C) 2008-2009 Nokia Corporation
   6  *
   7  * Contact: Kalle Valo <kalle.valo@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #ifndef __WL12XX_H__
  26 #define __WL12XX_H__
  27
  28 #include <linux/mutex.h>
  29 #include <linux/list.h>
  30 #include <linux/bitops.h>
  31 #include <net/mac80211.h>
  32
  33 #define DRIVER_NAME "wl12xx"
  34 #define DRIVER_PREFIX DRIVER_NAME ": "
  35
  36 enum {
  37         DEBUG_NONE      = 0,
  38         DEBUG_IRQ       = BIT(0),
  39         DEBUG_SPI       = BIT(1),
  40         DEBUG_BOOT      = BIT(2),
  41         DEBUG_MAILBOX   = BIT(3),
  42         DEBUG_NETLINK   = BIT(4),
  43         DEBUG_EVENT     = BIT(5),
  44         DEBUG_TX        = BIT(6),
  45         DEBUG_RX        = BIT(7),
  46         DEBUG_SCAN      = BIT(8),
  47         DEBUG_CRYPT     = BIT(9),
  48         DEBUG_PSM       = BIT(10),
  49         DEBUG_MAC80211  = BIT(11),
  50         DEBUG_CMD       = BIT(12),
  51         DEBUG_ACX       = BIT(13),
  52         DEBUG_ALL       = ~0,
  53 };
  54
  55 #define DEBUG_LEVEL (DEBUG_NONE)
  56
  57 #define DEBUG_DUMP_LIMIT 1024
  58
  59 #define wl12xx_error(fmt, arg...) \
  60         printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg)
  61
  62 #define wl12xx_warning(fmt, arg...) \
  63         printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg)
  64
  65 #define wl12xx_notice(fmt, arg...) \
  66         printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg)
  67
  68 #define wl12xx_info(fmt, arg...) \
  69         printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg)
  70
  71 #define wl12xx_debug(level, fmt, arg...) \
  72         do { \
  73                 if (level & DEBUG_LEVEL) \
  74                         printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \
  75         } while (0)
  76
  77 #define wl12xx_dump(level, prefix, buf, len)    \
  78         do { \
  79                 if (level & DEBUG_LEVEL) \
  80                         print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
  81                                        DUMP_PREFIX_OFFSET, 16, 1,       \
  82                                        buf,                             \
  83                                        min_t(size_t, len, DEBUG_DUMP_LIMIT), \
  84                                        0);                              \
  85         } while (0)
  86
  87 #define wl12xx_dump_ascii(level, prefix, buf, len)      \
  88         do { \
  89                 if (level & DEBUG_LEVEL) \
  90                         print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
  91                                        DUMP_PREFIX_OFFSET, 16, 1,       \
  92                                        buf,                             \
  93                                        min_t(size_t, len, DEBUG_DUMP_LIMIT), \
  94                                        true);                           \
  95         } while (0)
  96
  97 #define WL12XX_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN |   \
  98                                   CFG_BSSID_FILTER_EN)
  99
 100 #define WL12XX_DEFAULT_RX_FILTER (CFG_RX_PRSP_EN |  \
 101                                   CFG_RX_MGMT_EN |  \
 102                                   CFG_RX_DATA_EN |  \
 103                                   CFG_RX_CTL_EN |   \
 104                                   CFG_RX_BCN_EN |   \
 105                                   CFG_RX_AUTH_EN |  \
 106                                   CFG_RX_ASSOC_EN)
 107
 108 #define WL12XX_BUSY_WORD_LEN 8
 109
 110 struct boot_attr {
 111         u32 radio_type;
 112         u8 mac_clock;
 113         u8 arm_clock;
 114         int firmware_debug;
 115         u32 minor;
 116         u32 major;
 117         u32 bugfix;
 118 };
 119
 120 enum wl12xx_state {
 121         WL12XX_STATE_OFF,
 122         WL12XX_STATE_ON,
 123         WL12XX_STATE_PLT,
 124 };
 125
 126 enum wl12xx_partition_type {
 127         PART_DOWN,
 128         PART_WORK,
 129         PART_DRPW,
 130
 131         PART_TABLE_LEN
 132 };
 133
 134 struct wl12xx_partition {
 135         u32 size;
 136         u32 start;
 137 };
 138
 139 struct wl12xx_partition_set {
 140         struct wl12xx_partition mem;
 141         struct wl12xx_partition reg;
 142 };
 143
 144 struct wl12xx;
 145
 146 /* FIXME: I'm not sure about this structure name */
 147 struct wl12xx_chip {
 148         u32 id;
 149
 150         const char *fw_filename;
 151         const char *nvs_filename;
 152
 153         char fw_ver[21];
 154
 155         unsigned int power_on_sleep;
 156         int intr_cmd_complete;
 157         int intr_init_complete;
 158
 159         int (*op_upload_fw)(struct wl12xx *wl);
 160         int (*op_upload_nvs)(struct wl12xx *wl);
 161         int (*op_boot)(struct wl12xx *wl);
 162         void (*op_set_ecpu_ctrl)(struct wl12xx *wl, u32 flag);
 163         void (*op_target_enable_interrupts)(struct wl12xx *wl);
 164         int (*op_hw_init)(struct wl12xx *wl);
 165         int (*op_plt_init)(struct wl12xx *wl);
 166         void (*op_fw_version)(struct wl12xx *wl);
 167
 168         struct wl12xx_partition_set *p_table;
 169         enum wl12xx_acx_int_reg *acx_reg_table;
 170 };
 171
 172 struct wl12xx_stats {
 173         struct acx_statistics *fw_stats;
 174         unsigned long fw_stats_update;
 175
 176         unsigned int retry_count;
 177         unsigned int excessive_retries;
 178 };
 179
 180 struct wl12xx_debugfs {
 181         struct dentry *rootdir;
 182         struct dentry *fw_statistics;
 183
 184         struct dentry *tx_internal_desc_overflow;
 185
 186         struct dentry *rx_out_of_mem;
 187         struct dentry *rx_hdr_overflow;
 188         struct dentry *rx_hw_stuck;
 189         struct dentry *rx_dropped;
 190         struct dentry *rx_fcs_err;
 191         struct dentry *rx_xfr_hint_trig;
 192         struct dentry *rx_path_reset;
 193         struct dentry *rx_reset_counter;
 194
 195         struct dentry *dma_rx_requested;
 196         struct dentry *dma_rx_errors;
 197         struct dentry *dma_tx_requested;
 198         struct dentry *dma_tx_errors;
 199
 200         struct dentry *isr_cmd_cmplt;
 201         struct dentry *isr_fiqs;
 202         struct dentry *isr_rx_headers;
 203         struct dentry *isr_rx_mem_overflow;
 204         struct dentry *isr_rx_rdys;
 205         struct dentry *isr_irqs;
 206         struct dentry *isr_tx_procs;
 207         struct dentry *isr_decrypt_done;
 208         struct dentry *isr_dma0_done;
 209         struct dentry *isr_dma1_done;
 210         struct dentry *isr_tx_exch_complete;
 211         struct dentry *isr_commands;
 212         struct dentry *isr_rx_procs;
 213         struct dentry *isr_hw_pm_mode_changes;
 214         struct dentry *isr_host_acknowledges;
 215         struct dentry *isr_pci_pm;
 216         struct dentry *isr_wakeups;
 217         struct dentry *isr_low_rssi;
 218
 219         struct dentry *wep_addr_key_count;
 220         struct dentry *wep_default_key_count;
 221         /* skipping wep.reserved */
 222         struct dentry *wep_key_not_found;
 223         struct dentry *wep_decrypt_fail;
 224         struct dentry *wep_packets;
 225         struct dentry *wep_interrupt;
 226
 227         struct dentry *pwr_ps_enter;
 228         struct dentry *pwr_elp_enter;
 229         struct dentry *pwr_missing_bcns;
 230         struct dentry *pwr_wake_on_host;
 231         struct dentry *pwr_wake_on_timer_exp;
 232         struct dentry *pwr_tx_with_ps;
 233         struct dentry *pwr_tx_without_ps;
 234         struct dentry *pwr_rcvd_beacons;
 235         struct dentry *pwr_power_save_off;
 236         struct dentry *pwr_enable_ps;
 237         struct dentry *pwr_disable_ps;
 238         struct dentry *pwr_fix_tsf_ps;
 239         /* skipping cont_miss_bcns_spread for now */
 240         struct dentry *pwr_rcvd_awake_beacons;
 241
 242         struct dentry *mic_rx_pkts;
 243         struct dentry *mic_calc_failure;
 244
 245         struct dentry *aes_encrypt_fail;
 246         struct dentry *aes_decrypt_fail;
 247         struct dentry *aes_encrypt_packets;
 248         struct dentry *aes_decrypt_packets;
 249         struct dentry *aes_encrypt_interrupt;
 250         struct dentry *aes_decrypt_interrupt;
 251
 252         struct dentry *event_heart_beat;
 253         struct dentry *event_calibration;
 254         struct dentry *event_rx_mismatch;
 255         struct dentry *event_rx_mem_empty;
 256         struct dentry *event_rx_pool;
 257         struct dentry *event_oom_late;
 258         struct dentry *event_phy_transmit_error;
 259         struct dentry *event_tx_stuck;
 260
 261         struct dentry *ps_pspoll_timeouts;
 262         struct dentry *ps_upsd_timeouts;
 263         struct dentry *ps_upsd_max_sptime;
 264         struct dentry *ps_upsd_max_apturn;
 265         struct dentry *ps_pspoll_max_apturn;
 266         struct dentry *ps_pspoll_utilization;
 267         struct dentry *ps_upsd_utilization;
 268
 269         struct dentry *rxpipe_rx_prep_beacon_drop;
 270         struct dentry *rxpipe_descr_host_int_trig_rx_data;
 271         struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data;
 272         struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data;
 273         struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data;
 274
 275         struct dentry *tx_queue_len;
 276
 277         struct dentry *retry_count;
 278         struct dentry *excessive_retries;
 279 };
 280
 281 struct wl12xx {
 282         struct ieee80211_hw *hw;
 283         bool mac80211_registered;
 284
 285         struct spi_device *spi;
 286
 287         void (*set_power)(bool enable);
 288         int irq;
 289
 290         enum wl12xx_state state;
 291         struct mutex mutex;
 292
 293         int physical_mem_addr;
 294         int physical_reg_addr;
 295         int virtual_mem_addr;
 296         int virtual_reg_addr;
 297
 298         struct wl12xx_chip chip;
 299
 300         int cmd_box_addr;
 301         int event_box_addr;
 302         struct boot_attr boot_attr;
 303
 304         u8 *fw;
 305         size_t fw_len;
 306         u8 *nvs;
 307         size_t nvs_len;
 308
 309         u8 bssid[ETH_ALEN];
 310         u8 mac_addr[ETH_ALEN];
 311         u8 bss_type;
 312         u8 listen_int;
 313         int channel;
 314
 315         void *target_mem_map;
 316         struct acx_data_path_params_resp *data_path;
 317
 318         /* Number of TX packets transferred to the FW, modulo 16 */
 319         u32 data_in_count;
 320
 321         /* Frames scheduled for transmission, not handled yet */
 322         struct sk_buff_head tx_queue;
 323         bool tx_queue_stopped;
 324
 325         struct work_struct tx_work;
 326         struct work_struct filter_work;
 327
 328         /* Pending TX frames */
 329         struct sk_buff *tx_frames[16];
 330
 331         /*
 332          * Index pointing to the next TX complete entry
 333          * in the cyclic XT complete array we get from
 334          * the FW.
 335          */
 336         u32 next_tx_complete;
 337
 338         /* FW Rx counter */
 339         u32 rx_counter;
 340
 341         /* Rx frames handled */
 342         u32 rx_handled;
 343
 344         /* Current double buffer */
 345         u32 rx_current_buffer;
 346         u32 rx_last_id;
 347
 348         /* The target interrupt mask */
 349         u32 intr_mask;
 350         struct work_struct irq_work;
 351
 352         /* The mbox event mask */
 353         u32 event_mask;
 354
 355         /* Mailbox pointers */
 356         u32 mbox_ptr[2];
 357
 358         /* Are we currently scanning */
 359         bool scanning;
 360
 361         /* Our association ID */
 362         u16 aid;
 363
 364         /* Default key (for WEP) */
 365         u32 default_key;
 366
 367         unsigned int tx_mgmt_frm_rate;
 368         unsigned int tx_mgmt_frm_mod;
 369
 370         unsigned int rx_config;
 371         unsigned int rx_filter;
 372
 373         /* is firmware in elp mode */
 374         bool elp;
 375
 376         /* we can be in psm, but not in elp, we have to differentiate */
 377         bool psm;
 378
 379         /* PSM mode requested */
 380         bool psm_requested;
 381
 382         /* in dBm */
 383         int power_level;
 384
 385         struct wl12xx_stats stats;
 386         struct wl12xx_debugfs debugfs;
 387
 388         u32 buffer_32;
 389         u32 buffer_cmd;
 390         u8 buffer_busyword[WL12XX_BUSY_WORD_LEN];
 391         struct wl12xx_rx_descriptor *rx_descriptor;
 392 };
 393
 394 int wl12xx_plt_start(struct wl12xx *wl);
 395 int wl12xx_plt_stop(struct wl12xx *wl);
 396
 397 #define DEFAULT_HW_GEN_MODULATION_TYPE    CCK_LONG /* Long Preamble */
 398 #define DEFAULT_HW_GEN_TX_RATE          RATE_2MBPS
 399 #define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */
 400
 401 #define WL12XX_DEFAULT_POWER_LEVEL 20
 402
 403 #define WL12XX_TX_QUEUE_MAX_LENGTH 20
 404
 405 /* Different chips need different sleep times after power on.  WL1271 needs
 406  * 200ms, WL1251 needs only 10ms.  By default we use 200ms, but as soon as we
 407  * know the chip ID, we change the sleep value in the wl12xx chip structure,
 408  * so in subsequent power ons, we don't waste more time then needed.  */
 409 #define WL12XX_DEFAULT_POWER_ON_SLEEP 200
 410
 411 #define CHIP_ID_1251_PG10                  (0x7010101)
 412 #define CHIP_ID_1251_PG11                  (0x7020101)
 413 #define CHIP_ID_1251_PG12                  (0x7030101)
 414 #define CHIP_ID_1271_PG10                  (0x4030101)
 415 #define CHIP_ID_1271_PG20                  (0x4030111)
 416
 417 #endif