2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
7 * Copyright (C) 2015 John Crispin <john@phrozen.org>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
13 #include <asm/mipsregs.h>
14 #include <asm/smp-ops.h>
15 #include <asm/mips-cm.h>
16 #include <asm/mips-cpc.h>
17 #include <asm/mach-ralink/ralink_regs.h>
18 #include <asm/mach-ralink/mt7621.h>
24 #define SYSC_REG_SYSCFG 0x10
25 #define SYSC_REG_CPLL_CLKCFG0 0x2c
26 #define SYSC_REG_CUR_CLK_STS 0x44
27 #define CPU_CLK_SEL (BIT(30) | BIT(31))
29 #define MT7621_GPIO_MODE_UART1 1
30 #define MT7621_GPIO_MODE_I2C 2
31 #define MT7621_GPIO_MODE_UART3_MASK 0x3
32 #define MT7621_GPIO_MODE_UART3_SHIFT 3
33 #define MT7621_GPIO_MODE_UART3_GPIO 1
34 #define MT7621_GPIO_MODE_UART2_MASK 0x3
35 #define MT7621_GPIO_MODE_UART2_SHIFT 5
36 #define MT7621_GPIO_MODE_UART2_GPIO 1
37 #define MT7621_GPIO_MODE_JTAG 7
38 #define MT7621_GPIO_MODE_WDT_MASK 0x3
39 #define MT7621_GPIO_MODE_WDT_SHIFT 8
40 #define MT7621_GPIO_MODE_WDT_GPIO 1
41 #define MT7621_GPIO_MODE_PCIE_RST 0
42 #define MT7621_GPIO_MODE_PCIE_REF 2
43 #define MT7621_GPIO_MODE_PCIE_MASK 0x3
44 #define MT7621_GPIO_MODE_PCIE_SHIFT 10
45 #define MT7621_GPIO_MODE_PCIE_GPIO 1
46 #define MT7621_GPIO_MODE_MDIO_MASK 0x3
47 #define MT7621_GPIO_MODE_MDIO_SHIFT 12
48 #define MT7621_GPIO_MODE_MDIO_GPIO 1
49 #define MT7621_GPIO_MODE_RGMII1 14
50 #define MT7621_GPIO_MODE_RGMII2 15
51 #define MT7621_GPIO_MODE_SPI_MASK 0x3
52 #define MT7621_GPIO_MODE_SPI_SHIFT 16
53 #define MT7621_GPIO_MODE_SPI_GPIO 1
54 #define MT7621_GPIO_MODE_SDHCI_MASK 0x3
55 #define MT7621_GPIO_MODE_SDHCI_SHIFT 18
56 #define MT7621_GPIO_MODE_SDHCI_GPIO 1
58 static struct rt2880_pmx_func uart1_grp
[] = { FUNC("uart1", 0, 1, 2) };
59 static struct rt2880_pmx_func i2c_grp
[] = { FUNC("i2c", 0, 3, 2) };
60 static struct rt2880_pmx_func uart3_grp
[] = {
61 FUNC("uart3", 0, 5, 4),
63 FUNC("spdif3", 3, 5, 4),
65 static struct rt2880_pmx_func uart2_grp
[] = {
66 FUNC("uart2", 0, 9, 4),
68 FUNC("spdif2", 3, 9, 4),
70 static struct rt2880_pmx_func jtag_grp
[] = { FUNC("jtag", 0, 13, 5) };
71 static struct rt2880_pmx_func wdt_grp
[] = {
72 FUNC("wdt rst", 0, 18, 1),
73 FUNC("wdt refclk", 2, 18, 1),
75 static struct rt2880_pmx_func pcie_rst_grp
[] = {
76 FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST
, 19, 1),
77 FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF
, 19, 1)
79 static struct rt2880_pmx_func mdio_grp
[] = { FUNC("mdio", 0, 20, 2) };
80 static struct rt2880_pmx_func rgmii2_grp
[] = { FUNC("rgmii2", 0, 22, 12) };
81 static struct rt2880_pmx_func spi_grp
[] = {
82 FUNC("spi", 0, 34, 7),
83 FUNC("nand1", 2, 34, 7),
85 static struct rt2880_pmx_func sdhci_grp
[] = {
86 FUNC("sdhci", 0, 41, 8),
87 FUNC("nand2", 2, 41, 8),
89 static struct rt2880_pmx_func rgmii1_grp
[] = { FUNC("rgmii1", 0, 49, 12) };
91 static struct rt2880_pmx_group mt7621_pinmux_data
[] = {
92 GRP("uart1", uart1_grp
, 1, MT7621_GPIO_MODE_UART1
),
93 GRP("i2c", i2c_grp
, 1, MT7621_GPIO_MODE_I2C
),
94 GRP_G("uart3", uart3_grp
, MT7621_GPIO_MODE_UART3_MASK
,
95 MT7621_GPIO_MODE_UART3_GPIO
, MT7621_GPIO_MODE_UART3_SHIFT
),
96 GRP_G("uart2", uart2_grp
, MT7621_GPIO_MODE_UART2_MASK
,
97 MT7621_GPIO_MODE_UART2_GPIO
, MT7621_GPIO_MODE_UART2_SHIFT
),
98 GRP("jtag", jtag_grp
, 1, MT7621_GPIO_MODE_JTAG
),
99 GRP_G("wdt", wdt_grp
, MT7621_GPIO_MODE_WDT_MASK
,
100 MT7621_GPIO_MODE_WDT_GPIO
, MT7621_GPIO_MODE_WDT_SHIFT
),
101 GRP_G("pcie", pcie_rst_grp
, MT7621_GPIO_MODE_PCIE_MASK
,
102 MT7621_GPIO_MODE_PCIE_GPIO
, MT7621_GPIO_MODE_PCIE_SHIFT
),
103 GRP_G("mdio", mdio_grp
, MT7621_GPIO_MODE_MDIO_MASK
,
104 MT7621_GPIO_MODE_MDIO_GPIO
, MT7621_GPIO_MODE_MDIO_SHIFT
),
105 GRP("rgmii2", rgmii2_grp
, 1, MT7621_GPIO_MODE_RGMII2
),
106 GRP_G("spi", spi_grp
, MT7621_GPIO_MODE_SPI_MASK
,
107 MT7621_GPIO_MODE_SPI_GPIO
, MT7621_GPIO_MODE_SPI_SHIFT
),
108 GRP_G("sdhci", sdhci_grp
, MT7621_GPIO_MODE_SDHCI_MASK
,
109 MT7621_GPIO_MODE_SDHCI_GPIO
, MT7621_GPIO_MODE_SDHCI_SHIFT
),
110 GRP("rgmii1", rgmii1_grp
, 1, MT7621_GPIO_MODE_RGMII1
),
114 phys_addr_t
mips_cpc_default_phys_base(void)
116 panic("Cannot detect cpc address");
119 void __init
ralink_clk_init(void)
125 u8 clk_sel
= 0, xtal_mode
;
128 if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0
) & CPU_CLK_SEL
) != 0)
133 clk_sts
= rt_sysc_r32(SYSC_REG_CUR_CLK_STS
);
134 cpu_fdiv
= ((clk_sts
>> 8) & 0x1F);
135 cpu_ffrac
= (clk_sts
& 0x1F);
136 cpu_clk
= (500 * cpu_ffrac
/ cpu_fdiv
) * 1000 * 1000;
140 fbdiv
= ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
141 syscfg
= rt_sysc_r32(SYSC_REG_SYSCFG
);
142 xtal_mode
= (syscfg
>> 6) & 0x7;
143 if (xtal_mode
>= 6) {
145 cpu_clk
= 25 * fbdiv
* 1000 * 1000;
146 } else if (xtal_mode
>= 3) {
148 cpu_clk
= 40 * fbdiv
* 1000 * 1000;
151 cpu_clk
= 20 * fbdiv
* 1000 * 1000;
157 void __init
ralink_of_remap(void)
159 rt_sysc_membase
= plat_of_remap_node("mtk,mt7621-sysc");
160 rt_memc_membase
= plat_of_remap_node("mtk,mt7621-memc");
162 if (!rt_sysc_membase
|| !rt_memc_membase
)
163 panic("Failed to remap core resources");
166 void prom_soc_init(struct ralink_soc_info
*soc_info
)
168 void __iomem
*sysc
= (void __iomem
*) KSEG1ADDR(MT7621_SYSC_BASE
);
169 unsigned char *name
= NULL
;
174 n0
= __raw_readl(sysc
+ SYSC_REG_CHIP_NAME0
);
175 n1
= __raw_readl(sysc
+ SYSC_REG_CHIP_NAME1
);
177 if (n0
== MT7621_CHIP_NAME0
&& n1
== MT7621_CHIP_NAME1
) {
179 soc_info
->compatible
= "mtk,mt7621-soc";
181 panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0
, n1
);
183 ralink_soc
= MT762X_SOC_MT7621AT
;
184 rev
= __raw_readl(sysc
+ SYSC_REG_CHIP_REV
);
186 snprintf(soc_info
->sys_type
, RAMIPS_SYS_TYPE_LEN
,
187 "MediaTek %s ver:%u eco:%u",
189 (rev
>> CHIP_REV_VER_SHIFT
) & CHIP_REV_VER_MASK
,
190 (rev
& CHIP_REV_ECO_MASK
));
192 soc_info
->mem_size_min
= MT7621_DDR2_SIZE_MIN
;
193 soc_info
->mem_size_max
= MT7621_DDR2_SIZE_MAX
;
194 soc_info
->mem_base
= MT7621_DRAM_BASE
;
196 rt2880_pinmux_data
= mt7621_pinmux_data
;
198 /* Early detection of CMP support */
202 if (mips_cm_numiocu()) {
204 * mips_cm_probe() wipes out bootloader
205 * config for CM regions and we have to configure them
206 * again. This SoC cannot talk to pamlbus devices
207 * witout proper iocu region set up.
209 * FIXME: it would be better to do this with values
210 * from DT, but we need this very early because
211 * without this we cannot talk to pretty much anything
214 write_gcr_reg0_base(MT7621_PALMBUS_BASE
);
215 write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE
|
216 CM_GCR_REGn_MASK_CMTGT_IOCU0
);
219 if (!register_cps_smp_ops())
221 if (!register_cmp_smp_ops())
223 if (!register_vsmp_smp_ops())