drivers/net/wireless/rtlwifi/wifi.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL_WIFI_H__
  31 #define __RTL_WIFI_H__
  32
  33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  34
  35 #include <linux/sched.h>
  36 #include <linux/firmware.h>
  37 #include <linux/etherdevice.h>
  38 #include <linux/vmalloc.h>
  39 #include <linux/usb.h>
  40 #include <net/mac80211.h>
  41 #include <linux/completion.h>
  42 #include "debug.h"
  43
  44 #define RF_CHANGE_BY_INIT                       0
  45 #define RF_CHANGE_BY_IPS                        BIT(28)
  46 #define RF_CHANGE_BY_PS                         BIT(29)
  47 #define RF_CHANGE_BY_HW                         BIT(30)
  48 #define RF_CHANGE_BY_SW                         BIT(31)
  49
  50 #define IQK_ADDA_REG_NUM                        16
  51 #define IQK_MAC_REG_NUM                         4
  52
  53 #define MAX_KEY_LEN                             61
  54 #define KEY_BUF_SIZE                            5
  55
  56 /* QoS related. */
  57 /*aci: 0x00     Best Effort*/
  58 /*aci: 0x01     Background*/
  59 /*aci: 0x10     Video*/
  60 /*aci: 0x11     Voice*/
  61 /*Max: define total number.*/
  62 #define AC0_BE                                  0
  63 #define AC1_BK                                  1
  64 #define AC2_VI                                  2
  65 #define AC3_VO                                  3
  66 #define AC_MAX                                  4
  67 #define QOS_QUEUE_NUM                           4
  68 #define RTL_MAC80211_NUM_QUEUE                  5
  69 #define REALTEK_USB_VENQT_MAX_BUF_SIZE          254
  70 #define RTL_USB_MAX_RX_COUNT                    100
  71 #define QBSS_LOAD_SIZE                          5
  72 #define MAX_WMMELE_LENGTH                       64
  73
  74 #define TOTAL_CAM_ENTRY                         32
  75
  76 /*slot time for 11g. */
  77 #define RTL_SLOT_TIME_9                         9
  78 #define RTL_SLOT_TIME_20                        20
  79
  80 /*related with tcp/ip. */
  81 /*if_ehther.h*/
  82 #define ETH_P_PAE               0x888E  /*Port Access Entity (IEEE 802.1X) */
  83 #define ETH_P_IP                0x0800  /*Internet Protocol packet */
  84 #define ETH_P_ARP               0x0806  /*Address Resolution packet */
  85 #define SNAP_SIZE               6
  86 #define PROTOC_TYPE_SIZE        2
  87
  88 /*related with 802.11 frame*/
  89 #define MAC80211_3ADDR_LEN                      24
  90 #define MAC80211_4ADDR_LEN                      30
  91
  92 #define CHANNEL_MAX_NUMBER      (14 + 24 + 21)  /* 14 is the max channel no */
  93 #define CHANNEL_GROUP_MAX       (3 + 9) /*  ch1~3, 4~9, 10~14 = three groups */
  94 #define MAX_PG_GROUP                    13
  95 #define CHANNEL_GROUP_MAX_2G            3
  96 #define CHANNEL_GROUP_IDX_5GL           3
  97 #define CHANNEL_GROUP_IDX_5GM           6
  98 #define CHANNEL_GROUP_IDX_5GH           9
  99 #define CHANNEL_GROUP_MAX_5G            9
 100 #define CHANNEL_MAX_NUMBER_2G           14
 101 #define AVG_THERMAL_NUM                 8
 102 #define MAX_TID_COUNT                   9
 103
 104 /* for early mode */
 105 #define FCS_LEN                         4
 106 #define EM_HDR_LEN                      8
 107
 108 enum intf_type {
 109         INTF_PCI = 0,
 110         INTF_USB = 1,
 111 };
 112
 113 enum radio_path {
 114         RF90_PATH_A = 0,
 115         RF90_PATH_B = 1,
 116         RF90_PATH_C = 2,
 117         RF90_PATH_D = 3,
 118 };
 119
 120 enum rt_eeprom_type {
 121         EEPROM_93C46,
 122         EEPROM_93C56,
 123         EEPROM_BOOT_EFUSE,
 124 };
 125
 126 enum ttl_status {
 127         RTL_STATUS_INTERFACE_START = 0,
 128 };
 129
 130 enum hardware_type {
 131         HARDWARE_TYPE_RTL8192E,
 132         HARDWARE_TYPE_RTL8192U,
 133         HARDWARE_TYPE_RTL8192SE,
 134         HARDWARE_TYPE_RTL8192SU,
 135         HARDWARE_TYPE_RTL8192CE,
 136         HARDWARE_TYPE_RTL8192CU,
 137         HARDWARE_TYPE_RTL8192DE,
 138         HARDWARE_TYPE_RTL8192DU,
 139         HARDWARE_TYPE_RTL8723AE,
 140         HARDWARE_TYPE_RTL8723U,
 141
 142         /* keep it last */
 143         HARDWARE_TYPE_NUM
 144 };
 145
 146 #define IS_HARDWARE_TYPE_8192SU(rtlhal)                 \
 147         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
 148 #define IS_HARDWARE_TYPE_8192SE(rtlhal)                 \
 149         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
 150 #define IS_HARDWARE_TYPE_8192CE(rtlhal)                 \
 151         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
 152 #define IS_HARDWARE_TYPE_8192CU(rtlhal)                 \
 153         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
 154 #define IS_HARDWARE_TYPE_8192DE(rtlhal)                 \
 155         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
 156 #define IS_HARDWARE_TYPE_8192DU(rtlhal)                 \
 157         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
 158 #define IS_HARDWARE_TYPE_8723E(rtlhal)                  \
 159         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
 160 #define IS_HARDWARE_TYPE_8723U(rtlhal)                  \
 161         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
 162 #define IS_HARDWARE_TYPE_8192S(rtlhal)                  \
 163 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
 164 #define IS_HARDWARE_TYPE_8192C(rtlhal)                  \
 165 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
 166 #define IS_HARDWARE_TYPE_8192D(rtlhal)                  \
 167 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
 168 #define IS_HARDWARE_TYPE_8723(rtlhal)                   \
 169 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
 170 #define IS_HARDWARE_TYPE_8723U(rtlhal)                  \
 171         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
 172
 173 #define RX_HAL_IS_CCK_RATE(_pdesc)\
 174         (_pdesc->rxmcs == DESC92_RATE1M ||              \
 175          _pdesc->rxmcs == DESC92_RATE2M ||              \
 176          _pdesc->rxmcs == DESC92_RATE5_5M ||            \
 177          _pdesc->rxmcs == DESC92_RATE11M)
 178
 179 enum scan_operation_backup_opt {
 180         SCAN_OPT_BACKUP = 0,
 181         SCAN_OPT_RESTORE,
 182         SCAN_OPT_MAX
 183 };
 184
 185 /*RF state.*/
 186 enum rf_pwrstate {
 187         ERFON,
 188         ERFSLEEP,
 189         ERFOFF
 190 };
 191
 192 struct bb_reg_def {
 193         u32 rfintfs;
 194         u32 rfintfi;
 195         u32 rfintfo;
 196         u32 rfintfe;
 197         u32 rf3wire_offset;
 198         u32 rflssi_select;
 199         u32 rftxgain_stage;
 200         u32 rfhssi_para1;
 201         u32 rfhssi_para2;
 202         u32 rfsw_ctrl;
 203         u32 rfagc_control1;
 204         u32 rfagc_control2;
 205         u32 rfrxiq_imbal;
 206         u32 rfrx_afe;
 207         u32 rftxiq_imbal;
 208         u32 rftx_afe;
 209         u32 rf_rb;              /* rflssi_readback */
 210         u32 rf_rbpi;            /* rflssi_readbackpi */
 211 };
 212
 213 enum io_type {
 214         IO_CMD_PAUSE_DM_BY_SCAN = 0,
 215         IO_CMD_RESUME_DM_BY_SCAN = 1,
 216 };
 217
 218 enum hw_variables {
 219         HW_VAR_ETHER_ADDR,
 220         HW_VAR_MULTICAST_REG,
 221         HW_VAR_BASIC_RATE,
 222         HW_VAR_BSSID,
 223         HW_VAR_MEDIA_STATUS,
 224         HW_VAR_SECURITY_CONF,
 225         HW_VAR_BEACON_INTERVAL,
 226         HW_VAR_ATIM_WINDOW,
 227         HW_VAR_LISTEN_INTERVAL,
 228         HW_VAR_CS_COUNTER,
 229         HW_VAR_DEFAULTKEY0,
 230         HW_VAR_DEFAULTKEY1,
 231         HW_VAR_DEFAULTKEY2,
 232         HW_VAR_DEFAULTKEY3,
 233         HW_VAR_SIFS,
 234         HW_VAR_DIFS,
 235         HW_VAR_EIFS,
 236         HW_VAR_SLOT_TIME,
 237         HW_VAR_ACK_PREAMBLE,
 238         HW_VAR_CW_CONFIG,
 239         HW_VAR_CW_VALUES,
 240         HW_VAR_RATE_FALLBACK_CONTROL,
 241         HW_VAR_CONTENTION_WINDOW,
 242         HW_VAR_RETRY_COUNT,
 243         HW_VAR_TR_SWITCH,
 244         HW_VAR_COMMAND,
 245         HW_VAR_WPA_CONFIG,
 246         HW_VAR_AMPDU_MIN_SPACE,
 247         HW_VAR_SHORTGI_DENSITY,
 248         HW_VAR_AMPDU_FACTOR,
 249         HW_VAR_MCS_RATE_AVAILABLE,
 250         HW_VAR_AC_PARAM,
 251         HW_VAR_ACM_CTRL,
 252         HW_VAR_DIS_Req_Qsize,
 253         HW_VAR_CCX_CHNL_LOAD,
 254         HW_VAR_CCX_NOISE_HISTOGRAM,
 255         HW_VAR_CCX_CLM_NHM,
 256         HW_VAR_TxOPLimit,
 257         HW_VAR_TURBO_MODE,
 258         HW_VAR_RF_STATE,
 259         HW_VAR_RF_OFF_BY_HW,
 260         HW_VAR_BUS_SPEED,
 261         HW_VAR_SET_DEV_POWER,
 262
 263         HW_VAR_RCR,
 264         HW_VAR_RATR_0,
 265         HW_VAR_RRSR,
 266         HW_VAR_CPU_RST,
 267         HW_VAR_CHECK_BSSID,
 268         HW_VAR_LBK_MODE,
 269         HW_VAR_AES_11N_FIX,
 270         HW_VAR_USB_RX_AGGR,
 271         HW_VAR_USER_CONTROL_TURBO_MODE,
 272         HW_VAR_RETRY_LIMIT,
 273         HW_VAR_INIT_TX_RATE,
 274         HW_VAR_TX_RATE_REG,
 275         HW_VAR_EFUSE_USAGE,
 276         HW_VAR_EFUSE_BYTES,
 277         HW_VAR_AUTOLOAD_STATUS,
 278         HW_VAR_RF_2R_DISABLE,
 279         HW_VAR_SET_RPWM,
 280         HW_VAR_H2C_FW_PWRMODE,
 281         HW_VAR_H2C_FW_JOINBSSRPT,
 282         HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
 283         HW_VAR_FW_PSMODE_STATUS,
 284         HW_VAR_RESUME_CLK_ON,
 285         HW_VAR_FW_LPS_ACTION,
 286         HW_VAR_1X1_RECV_COMBINE,
 287         HW_VAR_STOP_SEND_BEACON,
 288         HW_VAR_TSF_TIMER,
 289         HW_VAR_IO_CMD,
 290
 291         HW_VAR_RF_RECOVERY,
 292         HW_VAR_H2C_FW_UPDATE_GTK,
 293         HW_VAR_WF_MASK,
 294         HW_VAR_WF_CRC,
 295         HW_VAR_WF_IS_MAC_ADDR,
 296         HW_VAR_H2C_FW_OFFLOAD,
 297         HW_VAR_RESET_WFCRC,
 298
 299         HW_VAR_HANDLE_FW_C2H,
 300         HW_VAR_DL_FW_RSVD_PAGE,
 301         HW_VAR_AID,
 302         HW_VAR_HW_SEQ_ENABLE,
 303         HW_VAR_CORRECT_TSF,
 304         HW_VAR_BCN_VALID,
 305         HW_VAR_FWLPS_RF_ON,
 306         HW_VAR_DUAL_TSF_RST,
 307         HW_VAR_SWITCH_EPHY_WoWLAN,
 308         HW_VAR_INT_MIGRATION,
 309         HW_VAR_INT_AC,
 310         HW_VAR_RF_TIMING,
 311
 312         HAL_DEF_WOWLAN,
 313         HW_VAR_MRC,
 314
 315         HW_VAR_MGT_FILTER,
 316         HW_VAR_CTRL_FILTER,
 317         HW_VAR_DATA_FILTER,
 318 };
 319
 320 enum _RT_MEDIA_STATUS {
 321         RT_MEDIA_DISCONNECT = 0,
 322         RT_MEDIA_CONNECT = 1
 323 };
 324
 325 enum rt_oem_id {
 326         RT_CID_DEFAULT = 0,
 327         RT_CID_8187_ALPHA0 = 1,
 328         RT_CID_8187_SERCOMM_PS = 2,
 329         RT_CID_8187_HW_LED = 3,
 330         RT_CID_8187_NETGEAR = 4,
 331         RT_CID_WHQL = 5,
 332         RT_CID_819x_CAMEO = 6,
 333         RT_CID_819x_RUNTOP = 7,
 334         RT_CID_819x_Senao = 8,
 335         RT_CID_TOSHIBA = 9,
 336         RT_CID_819x_Netcore = 10,
 337         RT_CID_Nettronix = 11,
 338         RT_CID_DLINK = 12,
 339         RT_CID_PRONET = 13,
 340         RT_CID_COREGA = 14,
 341         RT_CID_819x_ALPHA = 15,
 342         RT_CID_819x_Sitecom = 16,
 343         RT_CID_CCX = 17,
 344         RT_CID_819x_Lenovo = 18,
 345         RT_CID_819x_QMI = 19,
 346         RT_CID_819x_Edimax_Belkin = 20,
 347         RT_CID_819x_Sercomm_Belkin = 21,
 348         RT_CID_819x_CAMEO1 = 22,
 349         RT_CID_819x_MSI = 23,
 350         RT_CID_819x_Acer = 24,
 351         RT_CID_819x_HP = 27,
 352         RT_CID_819x_CLEVO = 28,
 353         RT_CID_819x_Arcadyan_Belkin = 29,
 354         RT_CID_819x_SAMSUNG = 30,
 355         RT_CID_819x_WNC_COREGA = 31,
 356         RT_CID_819x_Foxcoon = 32,
 357         RT_CID_819x_DELL = 33,
 358         RT_CID_819x_PRONETS = 34,
 359         RT_CID_819x_Edimax_ASUS = 35,
 360         RT_CID_NETGEAR = 36,
 361         RT_CID_PLANEX = 37,
 362         RT_CID_CC_C = 38,
 363 };
 364
 365 enum hw_descs {
 366         HW_DESC_OWN,
 367         HW_DESC_RXOWN,
 368         HW_DESC_TX_NEXTDESC_ADDR,
 369         HW_DESC_TXBUFF_ADDR,
 370         HW_DESC_RXBUFF_ADDR,
 371         HW_DESC_RXPKT_LEN,
 372         HW_DESC_RXERO,
 373 };
 374
 375 enum prime_sc {
 376         PRIME_CHNL_OFFSET_DONT_CARE = 0,
 377         PRIME_CHNL_OFFSET_LOWER = 1,
 378         PRIME_CHNL_OFFSET_UPPER = 2,
 379 };
 380
 381 enum rf_type {
 382         RF_1T1R = 0,
 383         RF_1T2R = 1,
 384         RF_2T2R = 2,
 385         RF_2T2R_GREEN = 3,
 386 };
 387
 388 enum ht_channel_width {
 389         HT_CHANNEL_WIDTH_20 = 0,
 390         HT_CHANNEL_WIDTH_20_40 = 1,
 391 };
 392
 393 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
 394 Cipher Suites Encryption Algorithms */
 395 enum rt_enc_alg {
 396         NO_ENCRYPTION = 0,
 397         WEP40_ENCRYPTION = 1,
 398         TKIP_ENCRYPTION = 2,
 399         RSERVED_ENCRYPTION = 3,
 400         AESCCMP_ENCRYPTION = 4,
 401         WEP104_ENCRYPTION = 5,
 402         AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
 403 };
 404
 405 enum rtl_hal_state {
 406         _HAL_STATE_STOP = 0,
 407         _HAL_STATE_START = 1,
 408 };
 409
 410 enum rtl_desc92_rate {
 411         DESC92_RATE1M = 0x00,
 412         DESC92_RATE2M = 0x01,
 413         DESC92_RATE5_5M = 0x02,
 414         DESC92_RATE11M = 0x03,
 415
 416         DESC92_RATE6M = 0x04,
 417         DESC92_RATE9M = 0x05,
 418         DESC92_RATE12M = 0x06,
 419         DESC92_RATE18M = 0x07,
 420         DESC92_RATE24M = 0x08,
 421         DESC92_RATE36M = 0x09,
 422         DESC92_RATE48M = 0x0a,
 423         DESC92_RATE54M = 0x0b,
 424
 425         DESC92_RATEMCS0 = 0x0c,
 426         DESC92_RATEMCS1 = 0x0d,
 427         DESC92_RATEMCS2 = 0x0e,
 428         DESC92_RATEMCS3 = 0x0f,
 429         DESC92_RATEMCS4 = 0x10,
 430         DESC92_RATEMCS5 = 0x11,
 431         DESC92_RATEMCS6 = 0x12,
 432         DESC92_RATEMCS7 = 0x13,
 433         DESC92_RATEMCS8 = 0x14,
 434         DESC92_RATEMCS9 = 0x15,
 435         DESC92_RATEMCS10 = 0x16,
 436         DESC92_RATEMCS11 = 0x17,
 437         DESC92_RATEMCS12 = 0x18,
 438         DESC92_RATEMCS13 = 0x19,
 439         DESC92_RATEMCS14 = 0x1a,
 440         DESC92_RATEMCS15 = 0x1b,
 441         DESC92_RATEMCS15_SG = 0x1c,
 442         DESC92_RATEMCS32 = 0x20,
 443 };
 444
 445 enum rtl_var_map {
 446         /*reg map */
 447         SYS_ISO_CTRL = 0,
 448         SYS_FUNC_EN,
 449         SYS_CLK,
 450         MAC_RCR_AM,
 451         MAC_RCR_AB,
 452         MAC_RCR_ACRC32,
 453         MAC_RCR_ACF,
 454         MAC_RCR_AAP,
 455
 456         /*efuse map */
 457         EFUSE_TEST,
 458         EFUSE_CTRL,
 459         EFUSE_CLK,
 460         EFUSE_CLK_CTRL,
 461         EFUSE_PWC_EV12V,
 462         EFUSE_FEN_ELDR,
 463         EFUSE_LOADER_CLK_EN,
 464         EFUSE_ANA8M,
 465         EFUSE_HWSET_MAX_SIZE,
 466         EFUSE_MAX_SECTION_MAP,
 467         EFUSE_REAL_CONTENT_SIZE,
 468         EFUSE_OOB_PROTECT_BYTES_LEN,
 469         EFUSE_ACCESS,
 470
 471         /*CAM map */
 472         RWCAM,
 473         WCAMI,
 474         RCAMO,
 475         CAMDBG,
 476         SECR,
 477         SEC_CAM_NONE,
 478         SEC_CAM_WEP40,
 479         SEC_CAM_TKIP,
 480         SEC_CAM_AES,
 481         SEC_CAM_WEP104,
 482
 483         /*IMR map */
 484         RTL_IMR_BCNDMAINT6,     /*Beacon DMA Interrupt 6 */
 485         RTL_IMR_BCNDMAINT5,     /*Beacon DMA Interrupt 5 */
 486         RTL_IMR_BCNDMAINT4,     /*Beacon DMA Interrupt 4 */
 487         RTL_IMR_BCNDMAINT3,     /*Beacon DMA Interrupt 3 */
 488         RTL_IMR_BCNDMAINT2,     /*Beacon DMA Interrupt 2 */
 489         RTL_IMR_BCNDMAINT1,     /*Beacon DMA Interrupt 1 */
 490         RTL_IMR_BCNDOK8,        /*Beacon Queue DMA OK Interrup 8 */
 491         RTL_IMR_BCNDOK7,        /*Beacon Queue DMA OK Interrup 7 */
 492         RTL_IMR_BCNDOK6,        /*Beacon Queue DMA OK Interrup 6 */
 493         RTL_IMR_BCNDOK5,        /*Beacon Queue DMA OK Interrup 5 */
 494         RTL_IMR_BCNDOK4,        /*Beacon Queue DMA OK Interrup 4 */
 495         RTL_IMR_BCNDOK3,        /*Beacon Queue DMA OK Interrup 3 */
 496         RTL_IMR_BCNDOK2,        /*Beacon Queue DMA OK Interrup 2 */
 497         RTL_IMR_BCNDOK1,        /*Beacon Queue DMA OK Interrup 1 */
 498         RTL_IMR_TIMEOUT2,       /*Timeout interrupt 2 */
 499         RTL_IMR_TIMEOUT1,       /*Timeout interrupt 1 */
 500         RTL_IMR_TXFOVW,         /*Transmit FIFO Overflow */
 501         RTL_IMR_PSTIMEOUT,      /*Power save time out interrupt */
 502         RTL_IMR_BcnInt,         /*Beacon DMA Interrupt 0 */
 503         RTL_IMR_RXFOVW,         /*Receive FIFO Overflow */
 504         RTL_IMR_RDU,            /*Receive Descriptor Unavailable */
 505         RTL_IMR_ATIMEND,        /*For 92C,ATIM Window End Interrupt */
 506         RTL_IMR_BDOK,           /*Beacon Queue DMA OK Interrup */
 507         RTL_IMR_HIGHDOK,        /*High Queue DMA OK Interrupt */
 508         RTL_IMR_COMDOK,         /*Command Queue DMA OK Interrupt*/
 509         RTL_IMR_TBDOK,          /*Transmit Beacon OK interrup */
 510         RTL_IMR_MGNTDOK,        /*Management Queue DMA OK Interrupt */
 511         RTL_IMR_TBDER,          /*For 92C,Transmit Beacon Error Interrupt */
 512         RTL_IMR_BKDOK,          /*AC_BK DMA OK Interrupt */
 513         RTL_IMR_BEDOK,          /*AC_BE DMA OK Interrupt */
 514         RTL_IMR_VIDOK,          /*AC_VI DMA OK Interrupt */
 515         RTL_IMR_VODOK,          /*AC_VO DMA Interrupt */
 516         RTL_IMR_ROK,            /*Receive DMA OK Interrupt */
 517         RTL_IBSS_INT_MASKS,     /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
 518                                  * RTL_IMR_TBDER) */
 519         RTL_IMR_C2HCMD,         /*fw interrupt*/
 520
 521         /*CCK Rates, TxHT = 0 */
 522         RTL_RC_CCK_RATE1M,
 523         RTL_RC_CCK_RATE2M,
 524         RTL_RC_CCK_RATE5_5M,
 525         RTL_RC_CCK_RATE11M,
 526
 527         /*OFDM Rates, TxHT = 0 */
 528         RTL_RC_OFDM_RATE6M,
 529         RTL_RC_OFDM_RATE9M,
 530         RTL_RC_OFDM_RATE12M,
 531         RTL_RC_OFDM_RATE18M,
 532         RTL_RC_OFDM_RATE24M,
 533         RTL_RC_OFDM_RATE36M,
 534         RTL_RC_OFDM_RATE48M,
 535         RTL_RC_OFDM_RATE54M,
 536
 537         RTL_RC_HT_RATEMCS7,
 538         RTL_RC_HT_RATEMCS15,
 539
 540         /*keep it last */
 541         RTL_VAR_MAP_MAX,
 542 };
 543
 544 /*Firmware PS mode for control LPS.*/
 545 enum _fw_ps_mode {
 546         FW_PS_ACTIVE_MODE = 0,
 547         FW_PS_MIN_MODE = 1,
 548         FW_PS_MAX_MODE = 2,
 549         FW_PS_DTIM_MODE = 3,
 550         FW_PS_VOIP_MODE = 4,
 551         FW_PS_UAPSD_WMM_MODE = 5,
 552         FW_PS_UAPSD_MODE = 6,
 553         FW_PS_IBSS_MODE = 7,
 554         FW_PS_WWLAN_MODE = 8,
 555         FW_PS_PM_Radio_Off = 9,
 556         FW_PS_PM_Card_Disable = 10,
 557 };
 558
 559 enum rt_psmode {
 560         EACTIVE,                /*Active/Continuous access. */
 561         EMAXPS,                 /*Max power save mode. */
 562         EFASTPS,                /*Fast power save mode. */
 563         EAUTOPS,                /*Auto power save mode. */
 564 };
 565
 566 /*LED related.*/
 567 enum led_ctl_mode {
 568         LED_CTL_POWER_ON = 1,
 569         LED_CTL_LINK = 2,
 570         LED_CTL_NO_LINK = 3,
 571         LED_CTL_TX = 4,
 572         LED_CTL_RX = 5,
 573         LED_CTL_SITE_SURVEY = 6,
 574         LED_CTL_POWER_OFF = 7,
 575         LED_CTL_START_TO_LINK = 8,
 576         LED_CTL_START_WPS = 9,
 577         LED_CTL_STOP_WPS = 10,
 578 };
 579
 580 enum rtl_led_pin {
 581         LED_PIN_GPIO0,
 582         LED_PIN_LED0,
 583         LED_PIN_LED1,
 584         LED_PIN_LED2
 585 };
 586
 587 /*QoS related.*/
 588 /*acm implementation method.*/
 589 enum acm_method {
 590         eAcmWay0_SwAndHw = 0,
 591         eAcmWay1_HW = 1,
 592         eAcmWay2_SW = 2,
 593 };
 594
 595 enum macphy_mode {
 596         SINGLEMAC_SINGLEPHY = 0,
 597         DUALMAC_DUALPHY,
 598         DUALMAC_SINGLEPHY,
 599 };
 600
 601 enum band_type {
 602         BAND_ON_2_4G = 0,
 603         BAND_ON_5G,
 604         BAND_ON_BOTH,
 605         BANDMAX
 606 };
 607
 608 /*aci/aifsn Field.
 609 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
 610 union aci_aifsn {
 611         u8 char_data;
 612
 613         struct {
 614                 u8 aifsn:4;
 615                 u8 acm:1;
 616                 u8 aci:2;
 617                 u8 reserved:1;
 618         } f;                    /* Field */
 619 };
 620
 621 /*mlme related.*/
 622 enum wireless_mode {
 623         WIRELESS_MODE_UNKNOWN = 0x00,
 624         WIRELESS_MODE_A = 0x01,
 625         WIRELESS_MODE_B = 0x02,
 626         WIRELESS_MODE_G = 0x04,
 627         WIRELESS_MODE_AUTO = 0x08,
 628         WIRELESS_MODE_N_24G = 0x10,
 629         WIRELESS_MODE_N_5G = 0x20
 630 };
 631
 632 #define IS_WIRELESS_MODE_A(wirelessmode)        \
 633         (wirelessmode == WIRELESS_MODE_A)
 634 #define IS_WIRELESS_MODE_B(wirelessmode)        \
 635         (wirelessmode == WIRELESS_MODE_B)
 636 #define IS_WIRELESS_MODE_G(wirelessmode)        \
 637         (wirelessmode == WIRELESS_MODE_G)
 638 #define IS_WIRELESS_MODE_N_24G(wirelessmode)    \
 639         (wirelessmode == WIRELESS_MODE_N_24G)
 640 #define IS_WIRELESS_MODE_N_5G(wirelessmode)     \
 641         (wirelessmode == WIRELESS_MODE_N_5G)
 642
 643 enum ratr_table_mode {
 644         RATR_INX_WIRELESS_NGB = 0,
 645         RATR_INX_WIRELESS_NG = 1,
 646         RATR_INX_WIRELESS_NB = 2,
 647         RATR_INX_WIRELESS_N = 3,
 648         RATR_INX_WIRELESS_GB = 4,
 649         RATR_INX_WIRELESS_G = 5,
 650         RATR_INX_WIRELESS_B = 6,
 651         RATR_INX_WIRELESS_MC = 7,
 652         RATR_INX_WIRELESS_A = 8,
 653 };
 654
 655 enum rtl_link_state {
 656         MAC80211_NOLINK = 0,
 657         MAC80211_LINKING = 1,
 658         MAC80211_LINKED = 2,
 659         MAC80211_LINKED_SCANNING = 3,
 660 };
 661
 662 enum act_category {
 663         ACT_CAT_QOS = 1,
 664         ACT_CAT_DLS = 2,
 665         ACT_CAT_BA = 3,
 666         ACT_CAT_HT = 7,
 667         ACT_CAT_WMM = 17,
 668 };
 669
 670 enum ba_action {
 671         ACT_ADDBAREQ = 0,
 672         ACT_ADDBARSP = 1,
 673         ACT_DELBA = 2,
 674 };
 675
 676 enum rt_polarity_ctl {
 677         RT_POLARITY_LOW_ACT = 0,
 678         RT_POLARITY_HIGH_ACT = 1,
 679 };
 680
 681 struct octet_string {
 682         u8 *octet;
 683         u16 length;
 684 };
 685
 686 struct rtl_hdr_3addr {
 687         __le16 frame_ctl;
 688         __le16 duration_id;
 689         u8 addr1[ETH_ALEN];
 690         u8 addr2[ETH_ALEN];
 691         u8 addr3[ETH_ALEN];
 692         __le16 seq_ctl;
 693         u8 payload[0];
 694 } __packed;
 695
 696 struct rtl_info_element {
 697         u8 id;
 698         u8 len;
 699         u8 data[0];
 700 } __packed;
 701
 702 struct rtl_probe_rsp {
 703         struct rtl_hdr_3addr header;
 704         u32 time_stamp[2];
 705         __le16 beacon_interval;
 706         __le16 capability;
 707         /*SSID, supported rates, FH params, DS params,
 708            CF params, IBSS params, TIM (if beacon), RSN */
 709         struct rtl_info_element info_element[0];
 710 } __packed;
 711
 712 /*LED related.*/
 713 /*ledpin Identify how to implement this SW led.*/
 714 struct rtl_led {
 715         void *hw;
 716         enum rtl_led_pin ledpin;
 717         bool ledon;
 718 };
 719
 720 struct rtl_led_ctl {
 721         bool led_opendrain;
 722         struct rtl_led sw_led0;
 723         struct rtl_led sw_led1;
 724 };
 725
 726 struct rtl_qos_parameters {
 727         __le16 cw_min;
 728         __le16 cw_max;
 729         u8 aifs;
 730         u8 flag;
 731         __le16 tx_op;
 732 } __packed;
 733
 734 struct rt_smooth_data {
 735         u32 elements[100];      /*array to store values */
 736         u32 index;              /*index to current array to store */
 737         u32 total_num;          /*num of valid elements */
 738         u32 total_val;          /*sum of valid elements */
 739 };
 740
 741 struct false_alarm_statistics {
 742         u32 cnt_parity_fail;
 743         u32 cnt_rate_illegal;
 744         u32 cnt_crc8_fail;
 745         u32 cnt_mcs_fail;
 746         u32 cnt_fast_fsync_fail;
 747         u32 cnt_sb_search_fail;
 748         u32 cnt_ofdm_fail;
 749         u32 cnt_cck_fail;
 750         u32 cnt_all;
 751         u32 cnt_ofdm_cca;
 752         u32 cnt_cck_cca;
 753         u32 cnt_cca_all;
 754         u32 cnt_bw_usc;
 755         u32 cnt_bw_lsc;
 756 };
 757
 758 struct init_gain {
 759         u8 xaagccore1;
 760         u8 xbagccore1;
 761         u8 xcagccore1;
 762         u8 xdagccore1;
 763         u8 cca;
 764
 765 };
 766
 767 struct wireless_stats {
 768         unsigned long txbytesunicast;
 769         unsigned long txbytesmulticast;
 770         unsigned long txbytesbroadcast;
 771         unsigned long rxbytesunicast;
 772
 773         long rx_snr_db[4];
 774         /*Correct smoothed ss in Dbm, only used
 775            in driver to report real power now. */
 776         long recv_signal_power;
 777         long signal_quality;
 778         long last_sigstrength_inpercent;
 779
 780         u32 rssi_calculate_cnt;
 781
 782         /*Transformed, in dbm. Beautified signal
 783            strength for UI, not correct. */
 784         long signal_strength;
 785
 786         u8 rx_rssi_percentage[4];
 787         u8 rx_evm_percentage[2];
 788
 789         struct rt_smooth_data ui_rssi;
 790         struct rt_smooth_data ui_link_quality;
 791 };
 792
 793 struct rate_adaptive {
 794         u8 rate_adaptive_disabled;
 795         u8 ratr_state;
 796         u16 reserve;
 797
 798         u32 high_rssi_thresh_for_ra;
 799         u32 high2low_rssi_thresh_for_ra;
 800         u8 low2high_rssi_thresh_for_ra40m;
 801         u32 low_rssi_thresh_for_ra40M;
 802         u8 low2high_rssi_thresh_for_ra20m;
 803         u32 low_rssi_thresh_for_ra20M;
 804         u32 upper_rssi_threshold_ratr;
 805         u32 middleupper_rssi_threshold_ratr;
 806         u32 middle_rssi_threshold_ratr;
 807         u32 middlelow_rssi_threshold_ratr;
 808         u32 low_rssi_threshold_ratr;
 809         u32 ultralow_rssi_threshold_ratr;
 810         u32 low_rssi_threshold_ratr_40m;
 811         u32 low_rssi_threshold_ratr_20m;
 812         u8 ping_rssi_enable;
 813         u32 ping_rssi_ratr;
 814         u32 ping_rssi_thresh_for_ra;
 815         u32 last_ratr;
 816         u8 pre_ratr_state;
 817 };
 818
 819 struct regd_pair_mapping {
 820         u16 reg_dmnenum;
 821         u16 reg_5ghz_ctl;
 822         u16 reg_2ghz_ctl;
 823 };
 824
 825 struct rtl_regulatory {
 826         char alpha2[2];
 827         u16 country_code;
 828         u16 max_power_level;
 829         u32 tp_scale;
 830         u16 current_rd;
 831         u16 current_rd_ext;
 832         int16_t power_limit;
 833         struct regd_pair_mapping *regpair;
 834 };
 835
 836 struct rtl_rfkill {
 837         bool rfkill_state;      /*0 is off, 1 is on */
 838 };
 839
 840 /*for P2P PS**/
 841 #define P2P_MAX_NOA_NUM         2
 842
 843 enum p2p_role {
 844         P2P_ROLE_DISABLE = 0,
 845         P2P_ROLE_DEVICE = 1,
 846         P2P_ROLE_CLIENT = 2,
 847         P2P_ROLE_GO = 3
 848 };
 849
 850 enum p2p_ps_state {
 851         P2P_PS_DISABLE = 0,
 852         P2P_PS_ENABLE = 1,
 853         P2P_PS_SCAN = 2,
 854         P2P_PS_SCAN_DONE = 3,
 855         P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
 856 };
 857
 858 enum p2p_ps_mode {
 859         P2P_PS_NONE = 0,
 860         P2P_PS_CTWINDOW = 1,
 861         P2P_PS_NOA       = 2,
 862         P2P_PS_MIX = 3, /* CTWindow and NoA */
 863 };
 864
 865 struct rtl_p2p_ps_info {
 866         enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
 867         enum p2p_ps_state p2p_ps_state; /*  indicate p2p ps state */
 868         u8 noa_index; /*  Identifies instance of Notice of Absence timing. */
 869         /*  Client traffic window. A period of time in TU after TBTT. */
 870         u8 ctwindow;
 871         u8 opp_ps; /*  opportunistic power save. */
 872         u8 noa_num; /*  number of NoA descriptor in P2P IE. */
 873         /*  Count for owner, Type of client. */
 874         u8 noa_count_type[P2P_MAX_NOA_NUM];
 875         /*  Max duration for owner, preferred or min acceptable duration
 876          * for client.
 877          */
 878         u32 noa_duration[P2P_MAX_NOA_NUM];
 879         /*  Length of interval for owner, preferred or max acceptable intervali
 880          * of client.
 881          */
 882         u32 noa_interval[P2P_MAX_NOA_NUM];
 883         /*  schedule in terms of the lower 4 bytes of the TSF timer. */
 884         u32 noa_start_time[P2P_MAX_NOA_NUM];
 885 };
 886
 887 struct p2p_ps_offload_t {
 888         u8 offload_en:1;
 889         u8 role:1; /* 1: Owner, 0: Client */
 890         u8 ctwindow_en:1;
 891         u8 noa0_en:1;
 892         u8 noa1_en:1;
 893         u8 allstasleep:1;
 894         u8 discovery:1;
 895         u8 reserved:1;
 896 };
 897
 898 #define IQK_MATRIX_REG_NUM      8
 899 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
 900
 901 struct iqk_matrix_regs {
 902         bool iqk_done;
 903         long value[1][IQK_MATRIX_REG_NUM];
 904 };
 905
 906 struct phy_parameters {
 907         u16 length;
 908         u32 *pdata;
 909 };
 910
 911 enum hw_param_tab_index {
 912         PHY_REG_2T,
 913         PHY_REG_1T,
 914         PHY_REG_PG,
 915         RADIOA_2T,
 916         RADIOB_2T,
 917         RADIOA_1T,
 918         RADIOB_1T,
 919         MAC_REG,
 920         AGCTAB_2T,
 921         AGCTAB_1T,
 922         MAX_TAB
 923 };
 924
 925 struct rtl_phy {
 926         struct bb_reg_def phyreg_def[4];        /*Radio A/B/C/D */
 927         struct init_gain initgain_backup;
 928         enum io_type current_io_type;
 929
 930         u8 rf_mode;
 931         u8 rf_type;
 932         u8 current_chan_bw;
 933         u8 set_bwmode_inprogress;
 934         u8 sw_chnl_inprogress;
 935         u8 sw_chnl_stage;
 936         u8 sw_chnl_step;
 937         u8 current_channel;
 938         u8 h2c_box_num;
 939         u8 set_io_inprogress;
 940         u8 lck_inprogress;
 941
 942         /* record for power tracking */
 943         s32 reg_e94;
 944         s32 reg_e9c;
 945         s32 reg_ea4;
 946         s32 reg_eac;
 947         s32 reg_eb4;
 948         s32 reg_ebc;
 949         s32 reg_ec4;
 950         s32 reg_ecc;
 951         u8 rfpienable;
 952         u8 reserve_0;
 953         u16 reserve_1;
 954         u32 reg_c04, reg_c08, reg_874;
 955         u32 adda_backup[16];
 956         u32 iqk_mac_backup[IQK_MAC_REG_NUM];
 957         u32 iqk_bb_backup[10];
 958         bool iqk_initialized;
 959
 960         /* Dual mac */
 961         bool need_iqk;
 962         struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
 963
 964         bool rfpi_enable;
 965
 966         u8 pwrgroup_cnt;
 967         u8 cck_high_power;
 968         /* MAX_PG_GROUP groups of pwr diff by rates */
 969         u32 mcs_offset[MAX_PG_GROUP][16];
 970         u8 default_initialgain[4];
 971
 972         /* the current Tx power level */
 973         u8 cur_cck_txpwridx;
 974         u8 cur_ofdm24g_txpwridx;
 975         u8 cur_bw20_txpwridx;
 976         u8 cur_bw40_txpwridx;
 977
 978         u32 rfreg_chnlval[2];
 979         bool apk_done;
 980         u32 reg_rf3c[2];        /* pathA / pathB  */
 981
 982         /* bfsync */
 983         u8 framesync;
 984         u32 framesync_c34;
 985
 986         u8 num_total_rfpath;
 987         struct phy_parameters hwparam_tables[MAX_TAB];
 988         u16 rf_pathmap;
 989
 990         enum rt_polarity_ctl polarity_ctl;
 991 };
 992
 993 #define MAX_TID_COUNT                           9
 994 #define RTL_AGG_STOP                            0
 995 #define RTL_AGG_PROGRESS                        1
 996 #define RTL_AGG_START                           2
 997 #define RTL_AGG_OPERATIONAL                     3
 998 #define RTL_AGG_OFF                             0
 999 #define RTL_AGG_ON                              1
1000 #define RTL_RX_AGG_START                        1
1001 #define RTL_RX_AGG_STOP                         0
1002 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA         2
1003 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA         3
1004
1005 struct rtl_ht_agg {
1006         u16 txq_id;
1007         u16 wait_for_ba;
1008         u16 start_idx;
1009         u64 bitmap;
1010         u32 rate_n_flags;
1011         u8 agg_state;
1012         u8 rx_agg_state;
1013 };
1014
1015 struct rssi_sta {
1016         long undec_sm_pwdb;
1017 };
1018
1019 struct rtl_tid_data {
1020         u16 seq_number;
1021         struct rtl_ht_agg agg;
1022 };
1023
1024 struct rtl_sta_info {
1025         struct list_head list;
1026         u8 ratr_index;
1027         u8 wireless_mode;
1028         u8 mimo_ps;
1029         u8 mac_addr[ETH_ALEN];
1030         struct rtl_tid_data tids[MAX_TID_COUNT];
1031
1032         /* just used for ap adhoc or mesh*/
1033         struct rssi_sta rssi_stat;
1034 } __packed;
1035
1036 struct rtl_priv;
1037 struct rtl_io {
1038         struct device *dev;
1039         struct mutex bb_mutex;
1040
1041         /*PCI MEM map */
1042         unsigned long pci_mem_end;      /*shared mem end        */
1043         unsigned long pci_mem_start;    /*shared mem start */
1044
1045         /*PCI IO map */
1046         unsigned long pci_base_addr;    /*device I/O address */
1047
1048         void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1049         void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1050         void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1051         void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1052                              u16 len);
1053
1054         u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1055         u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1056         u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1057
1058 };
1059
1060 struct rtl_mac {
1061         u8 mac_addr[ETH_ALEN];
1062         u8 mac80211_registered;
1063         u8 beacon_enabled;
1064
1065         u32 tx_ss_num;
1066         u32 rx_ss_num;
1067
1068         struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1069         struct ieee80211_hw *hw;
1070         struct ieee80211_vif *vif;
1071         enum nl80211_iftype opmode;
1072
1073         /*Probe Beacon management */
1074         struct rtl_tid_data tids[MAX_TID_COUNT];
1075         enum rtl_link_state link_state;
1076
1077         int n_channels;
1078         int n_bitrates;
1079
1080         bool offchan_delay;
1081         u8 p2p; /*using p2p role*/
1082         bool p2p_in_use;
1083
1084         /*filters */
1085         u32 rx_conf;
1086         u16 rx_mgt_filter;
1087         u16 rx_ctrl_filter;
1088         u16 rx_data_filter;
1089
1090         bool act_scanning;
1091         u8 cnt_after_linked;
1092         bool skip_scan;
1093
1094         /* early mode */
1095         /* skb wait queue */
1096         struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1097
1098         /*RDG*/
1099         bool rdg_en;
1100
1101         /*AP*/
1102         u8 bssid[6];
1103         u32 vendor;
1104         u8 mcs[16];     /* 16 bytes mcs for HT rates. */
1105         u32 basic_rates; /* b/g rates */
1106         u8 ht_enable;
1107         u8 sgi_40;
1108         u8 sgi_20;
1109         u8 bw_40;
1110         u8 mode;                /* wireless mode */
1111         u8 slot_time;
1112         u8 short_preamble;
1113         u8 use_cts_protect;
1114         u8 cur_40_prime_sc;
1115         u8 cur_40_prime_sc_bk;
1116         u64 tsf;
1117         u8 retry_short;
1118         u8 retry_long;
1119         u16 assoc_id;
1120         bool hiddenssid;
1121
1122         /*IBSS*/
1123         int beacon_interval;
1124
1125         /*AMPDU*/
1126         u8 min_space_cfg;       /*For Min spacing configurations */
1127         u8 max_mss_density;
1128         u8 current_ampdu_factor;
1129         u8 current_ampdu_density;
1130
1131         /*QOS & EDCA */
1132         struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1133         struct rtl_qos_parameters ac[AC_MAX];
1134
1135         /* counters */
1136         u64 last_txok_cnt;
1137         u64 last_rxok_cnt;
1138         u32 last_bt_edca_ul;
1139         u32 last_bt_edca_dl;
1140 };
1141
1142 struct btdm_8723 {
1143         bool all_off;
1144         bool agc_table_en;
1145         bool adc_back_off_on;
1146         bool b2_ant_hid_en;
1147         bool low_penalty_rate_adaptive;
1148         bool rf_rx_lpf_shrink;
1149         bool reject_aggre_pkt;
1150         bool tra_tdma_on;
1151         u8 tra_tdma_nav;
1152         u8 tra_tdma_ant;
1153         bool tdma_on;
1154         u8 tdma_ant;
1155         u8 tdma_nav;
1156         u8 tdma_dac_swing;
1157         u8 fw_dac_swing_lvl;
1158         bool ps_tdma_on;
1159         u8 ps_tdma_byte[5];
1160         bool pta_on;
1161         u32 val_0x6c0;
1162         u32 val_0x6c8;
1163         u32 val_0x6cc;
1164         bool sw_dac_swing_on;
1165         u32 sw_dac_swing_lvl;
1166         u32 wlan_act_hi;
1167         u32 wlan_act_lo;
1168         u32 bt_retry_index;
1169         bool dec_bt_pwr;
1170         bool ignore_wlan_act;
1171 };
1172
1173 struct bt_coexist_8723 {
1174         u32 high_priority_tx;
1175         u32 high_priority_rx;
1176         u32 low_priority_tx;
1177         u32 low_priority_rx;
1178         u8 c2h_bt_info;
1179         bool c2h_bt_info_req_sent;
1180         bool c2h_bt_inquiry_page;
1181         u32 bt_inq_page_start_time;
1182         u8 bt_retry_cnt;
1183         u8 c2h_bt_info_original;
1184         u8 bt_inquiry_page_cnt;
1185         struct btdm_8723 btdm;
1186 };
1187
1188 struct rtl_hal {
1189         struct ieee80211_hw *hw;
1190         bool driver_is_goingto_unload;
1191         bool up_first_time;
1192         bool first_init;
1193         bool being_init_adapter;
1194         bool bbrf_ready;
1195         bool mac_func_enable;
1196         struct bt_coexist_8723 hal_coex_8723;
1197
1198         enum intf_type interface;
1199         u16 hw_type;            /*92c or 92d or 92s and so on */
1200         u8 ic_class;
1201         u8 oem_id;
1202         u32 version;            /*version of chip */
1203         u8 state;               /*stop 0, start 1 */
1204         u8 board_type;
1205
1206         /*firmware */
1207         u32 fwsize;
1208         u8 *pfirmware;
1209         u16 fw_version;
1210         u16 fw_subversion;
1211         bool h2c_setinprogress;
1212         u8 last_hmeboxnum;
1213         bool fw_ready;
1214         /*Reserve page start offset except beacon in TxQ. */
1215         u8 fw_rsvdpage_startoffset;
1216         u8 h2c_txcmd_seq;
1217
1218         /* FW Cmd IO related */
1219         u16 fwcmd_iomap;
1220         u32 fwcmd_ioparam;
1221         bool set_fwcmd_inprogress;
1222         u8 current_fwcmd_io;
1223
1224         bool fw_clk_change_in_progress;
1225         bool allow_sw_to_change_hwclc;
1226         u8 fw_ps_state;
1227         struct p2p_ps_offload_t p2p_ps_offload;
1228         /**/
1229         bool driver_going2unload;
1230
1231         /*AMPDU init min space*/
1232         u8 minspace_cfg;        /*For Min spacing configurations */
1233
1234         /* Dual mac */
1235         enum macphy_mode macphymode;
1236         enum band_type current_bandtype;        /* 0:2.4G, 1:5G */
1237         enum band_type current_bandtypebackup;
1238         enum band_type bandset;
1239         /* dual MAC 0--Mac0 1--Mac1 */
1240         u32 interfaceindex;
1241         /* just for DualMac S3S4 */
1242         u8 macphyctl_reg;
1243         bool earlymode_enable;
1244         u8 max_earlymode_num;
1245         /* Dual mac*/
1246         bool during_mac0init_radiob;
1247         bool during_mac1init_radioa;
1248         bool reloadtxpowerindex;
1249         /* True if IMR or IQK  have done
1250         for 2.4G in scan progress */
1251         bool load_imrandiqk_setting_for2g;
1252
1253         bool disable_amsdu_8k;
1254         bool master_of_dmsp;
1255         bool slave_of_dmsp;
1256 };
1257
1258 struct rtl_security {
1259         /*default 0 */
1260         bool use_sw_sec;
1261
1262         bool being_setkey;
1263         bool use_defaultkey;
1264         /*Encryption Algorithm for Unicast Packet */
1265         enum rt_enc_alg pairwise_enc_algorithm;
1266         /*Encryption Algorithm for Brocast/Multicast */
1267         enum rt_enc_alg group_enc_algorithm;
1268         /*Cam Entry Bitmap */
1269         u32 hwsec_cam_bitmap;
1270         u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1271         /*local Key buffer, indx 0 is for
1272            pairwise key 1-4 is for agoup key. */
1273         u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1274         u8 key_len[KEY_BUF_SIZE];
1275
1276         /*The pointer of Pairwise Key,
1277            it always points to KeyBuf[4] */
1278         u8 *pairwise_key;
1279 };
1280
1281 struct rtl_dm {
1282         /*PHY status for Dynamic Management */
1283         long entry_min_undec_sm_pwdb;
1284         long undec_sm_pwdb;     /*out dm */
1285         long entry_max_undec_sm_pwdb;
1286         bool dm_initialgain_enable;
1287         bool dynamic_txpower_enable;
1288         bool current_turbo_edca;
1289         bool is_any_nonbepkts;  /*out dm */
1290         bool is_cur_rdlstate;
1291         bool txpower_trackinginit;
1292         bool disable_framebursting;
1293         bool cck_inch14;
1294         bool txpower_tracking;
1295         bool useramask;
1296         bool rfpath_rxenable[4];
1297         bool inform_fw_driverctrldm;
1298         bool current_mrc_switch;
1299         u8 txpowercount;
1300
1301         u8 thermalvalue_rxgain;
1302         u8 thermalvalue_iqk;
1303         u8 thermalvalue_lck;
1304         u8 thermalvalue;
1305         u8 last_dtp_lvl;
1306         u8 thermalvalue_avg[AVG_THERMAL_NUM];
1307         u8 thermalvalue_avg_index;
1308         bool done_txpower;
1309         u8 dynamic_txhighpower_lvl;     /*Tx high power level */
1310         u8 dm_flag;             /*Indicate each dynamic mechanism's status. */
1311         u8 dm_type;
1312         u8 txpower_track_control;
1313         bool interrupt_migration;
1314         bool disable_tx_int;
1315         char ofdm_index[2];
1316         char cck_index;
1317
1318         /* DMSP */
1319         bool supp_phymode_switch;
1320 };
1321
1322 #define EFUSE_MAX_LOGICAL_SIZE                  256
1323
1324 struct rtl_efuse {
1325         bool autoLoad_ok;
1326         bool bootfromefuse;
1327         u16 max_physical_size;
1328
1329         u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1330         u16 efuse_usedbytes;
1331         u8 efuse_usedpercentage;
1332 #ifdef EFUSE_REPG_WORKAROUND
1333         bool efuse_re_pg_sec1flag;
1334         u8 efuse_re_pg_data[8];
1335 #endif
1336
1337         u8 autoload_failflag;
1338         u8 autoload_status;
1339
1340         short epromtype;
1341         u16 eeprom_vid;
1342         u16 eeprom_did;
1343         u16 eeprom_svid;
1344         u16 eeprom_smid;
1345         u8 eeprom_oemid;
1346         u16 eeprom_channelplan;
1347         u8 eeprom_version;
1348         u8 board_type;
1349         u8 external_pa;
1350
1351         u8 dev_addr[6];
1352
1353         bool txpwr_fromeprom;
1354         u8 eeprom_crystalcap;
1355         u8 eeprom_tssi[2];
1356         u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1357         u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1358         u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1359         u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1360         u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1361         u8 eprom_chnl_txpwr_ht40_2sdf[2][CHANNEL_GROUP_MAX];
1362         u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1363         u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER];   /*For HT 40MHZ pwr */
1364         u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER];   /*For HT 40MHZ pwr */
1365
1366         u8 internal_pa_5g[2];   /* pathA / pathB */
1367         u8 eeprom_c9;
1368         u8 eeprom_cc;
1369
1370         /*For power group */
1371         u8 eeprom_pwrgroup[2][3];
1372         u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1373         u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1374
1375         char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1376         /*For HT<->legacy pwr diff*/
1377         u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1378         u8 txpwr_safetyflag;                    /* Band edge enable flag */
1379         u16 eeprom_txpowerdiff;
1380         u8 legacy_httxpowerdiff;        /* Legacy to HT rate power diff */
1381         u8 antenna_txpwdiff[3];
1382
1383         u8 eeprom_regulatory;
1384         u8 eeprom_thermalmeter;
1385         u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1386         u16 tssi_13dbm;
1387         u8 crystalcap;          /* CrystalCap. */
1388         u8 delta_iqk;
1389         u8 delta_lck;
1390
1391         u8 legacy_ht_txpowerdiff;       /*Legacy to HT rate power diff */
1392         bool apk_thermalmeterignore;
1393
1394         bool b1x1_recvcombine;
1395         bool b1ss_support;
1396
1397         /*channel plan */
1398         u8 channel_plan;
1399 };
1400
1401 struct rtl_ps_ctl {
1402         bool pwrdomain_protect;
1403         bool in_powersavemode;
1404         bool rfchange_inprogress;
1405         bool swrf_processing;
1406         bool hwradiooff;
1407
1408         /*
1409          * just for PCIE ASPM
1410          * If it supports ASPM, Offset[560h] = 0x40,
1411          * otherwise Offset[560h] = 0x00.
1412          * */
1413         bool support_aspm;
1414
1415         bool support_backdoor;
1416
1417         /*for LPS */
1418         enum rt_psmode dot11_psmode;    /*Power save mode configured. */
1419         bool swctrl_lps;
1420         bool leisure_ps;
1421         bool fwctrl_lps;
1422         u8 fwctrl_psmode;
1423         /*For Fw control LPS mode */
1424         u8 reg_fwctrl_lps;
1425         /*Record Fw PS mode status. */
1426         bool fw_current_inpsmode;
1427         u8 reg_max_lps_awakeintvl;
1428         bool report_linked;
1429         bool low_power_enable;/*for 32k*/
1430
1431         /*for IPS */
1432         bool inactiveps;
1433
1434         u32 rfoff_reason;
1435
1436         /*RF OFF Level */
1437         u32 cur_ps_level;
1438         u32 reg_rfps_level;
1439
1440         /*just for PCIE ASPM */
1441         u8 const_amdpci_aspm;
1442         bool pwrdown_mode;
1443
1444         enum rf_pwrstate inactive_pwrstate;
1445         enum rf_pwrstate rfpwr_state;   /*cur power state */
1446
1447         /* for SW LPS*/
1448         bool sw_ps_enabled;
1449         bool state;
1450         bool state_inap;
1451         bool multi_buffered;
1452         u16 nullfunc_seq;
1453         unsigned int dtim_counter;
1454         unsigned int sleep_ms;
1455         unsigned long last_sleep_jiffies;
1456         unsigned long last_awake_jiffies;
1457         unsigned long last_delaylps_stamp_jiffies;
1458         unsigned long last_dtim;
1459         unsigned long last_beacon;
1460         unsigned long last_action;
1461         unsigned long last_slept;
1462
1463         /*For P2P PS */
1464         struct rtl_p2p_ps_info p2p_ps_info;
1465         u8 pwr_mode;
1466         u8 smart_ps;
1467 };
1468
1469 struct rtl_stats {
1470         u8 psaddr[ETH_ALEN];
1471         u32 mac_time[2];
1472         s8 rssi;
1473         u8 signal;
1474         u8 noise;
1475         u16 rate;               /*in 100 kbps */
1476         u8 received_channel;
1477         u8 control;
1478         u8 mask;
1479         u8 freq;
1480         u16 len;
1481         u64 tsf;
1482         u32 beacon_time;
1483         u8 nic_type;
1484         u16 length;
1485         u8 signalquality;       /*in 0-100 index. */
1486         /*
1487          * Real power in dBm for this packet,
1488          * no beautification and aggregation.
1489          * */
1490         s32 recvsignalpower;
1491         s8 rxpower;             /*in dBm Translate from PWdB */
1492         u8 signalstrength;      /*in 0-100 index. */
1493         u16 hwerror:1;
1494         u16 crc:1;
1495         u16 icv:1;
1496         u16 shortpreamble:1;
1497         u16 antenna:1;
1498         u16 decrypted:1;
1499         u16 wakeup:1;
1500         u32 timestamp_low;
1501         u32 timestamp_high;
1502
1503         u8 rx_drvinfo_size;
1504         u8 rx_bufshift;
1505         bool isampdu;
1506         bool isfirst_ampdu;
1507         bool rx_is40Mhzpacket;
1508         u32 rx_pwdb_all;
1509         u8 rx_mimo_signalstrength[4];   /*in 0~100 index */
1510         s8 rx_mimo_sig_qual[2];
1511         bool packet_matchbssid;
1512         bool is_cck;
1513         bool is_ht;
1514         bool packet_toself;
1515         bool packet_beacon;     /*for rssi */
1516         char cck_adc_pwdb[4];   /*for rx path selection */
1517 };
1518
1519 struct rt_link_detect {
1520         /* count for roaming */
1521         u32 bcn_rx_inperiod;
1522         u32 roam_times;
1523
1524         u32 num_tx_in4period[4];
1525         u32 num_rx_in4period[4];
1526
1527         u32 num_tx_inperiod;
1528         u32 num_rx_inperiod;
1529
1530         bool busytraffic;
1531         bool tx_busy_traffic;
1532         bool rx_busy_traffic;
1533         bool higher_busytraffic;
1534         bool higher_busyrxtraffic;
1535
1536         u32 tidtx_in4period[MAX_TID_COUNT][4];
1537         u32 tidtx_inperiod[MAX_TID_COUNT];
1538         bool higher_busytxtraffic[MAX_TID_COUNT];
1539 };
1540
1541 struct rtl_tcb_desc {
1542         u8 packet_bw:1;
1543         u8 multicast:1;
1544         u8 broadcast:1;
1545
1546         u8 rts_stbc:1;
1547         u8 rts_enable:1;
1548         u8 cts_enable:1;
1549         u8 rts_use_shortpreamble:1;
1550         u8 rts_use_shortgi:1;
1551         u8 rts_sc:1;
1552         u8 rts_bw:1;
1553         u8 rts_rate;
1554
1555         u8 use_shortgi:1;
1556         u8 use_shortpreamble:1;
1557         u8 use_driver_rate:1;
1558         u8 disable_ratefallback:1;
1559
1560         u8 ratr_index;
1561         u8 mac_id;
1562         u8 hw_rate;
1563
1564         u8 last_inipkt:1;
1565         u8 cmd_or_init:1;
1566         u8 queue_index;
1567
1568         /* early mode */
1569         u8 empkt_num;
1570         /* The max value by HW */
1571         u32 empkt_len[5];
1572 };
1573
1574 struct rtl_hal_ops {
1575         int (*init_sw_vars) (struct ieee80211_hw *hw);
1576         void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1577         void (*read_chip_version)(struct ieee80211_hw *hw);
1578         void (*read_eeprom_info) (struct ieee80211_hw *hw);
1579         void (*interrupt_recognized) (struct ieee80211_hw *hw,
1580                                       u32 *p_inta, u32 *p_intb);
1581         int (*hw_init) (struct ieee80211_hw *hw);
1582         void (*hw_disable) (struct ieee80211_hw *hw);
1583         void (*hw_suspend) (struct ieee80211_hw *hw);
1584         void (*hw_resume) (struct ieee80211_hw *hw);
1585         void (*enable_interrupt) (struct ieee80211_hw *hw);
1586         void (*disable_interrupt) (struct ieee80211_hw *hw);
1587         int (*set_network_type) (struct ieee80211_hw *hw,
1588                                  enum nl80211_iftype type);
1589         void (*set_chk_bssid)(struct ieee80211_hw *hw,
1590                                 bool check_bssid);
1591         void (*set_bw_mode) (struct ieee80211_hw *hw,
1592                              enum nl80211_channel_type ch_type);
1593          u8(*switch_channel) (struct ieee80211_hw *hw);
1594         void (*set_qos) (struct ieee80211_hw *hw, int aci);
1595         void (*set_bcn_reg) (struct ieee80211_hw *hw);
1596         void (*set_bcn_intv) (struct ieee80211_hw *hw);
1597         void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1598                                        u32 add_msr, u32 rm_msr);
1599         void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1600         void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1601         void (*update_rate_tbl) (struct ieee80211_hw *hw,
1602                               struct ieee80211_sta *sta, u8 rssi_level);
1603         void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1604         void (*fill_tx_desc) (struct ieee80211_hw *hw,
1605                               struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1606                               struct ieee80211_tx_info *info,
1607                               struct ieee80211_sta *sta,
1608                               struct sk_buff *skb, u8 hw_queue,
1609                               struct rtl_tcb_desc *ptcb_desc);
1610         void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1611                                   u32 buffer_len, bool bIsPsPoll);
1612         void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1613                                  bool firstseg, bool lastseg,
1614                                  struct sk_buff *skb);
1615         bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1616         bool (*query_rx_desc) (struct ieee80211_hw *hw,
1617                                struct rtl_stats *stats,
1618                                struct ieee80211_rx_status *rx_status,
1619                                u8 *pdesc, struct sk_buff *skb);
1620         void (*set_channel_access) (struct ieee80211_hw *hw);
1621         bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1622         void (*dm_watchdog) (struct ieee80211_hw *hw);
1623         void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1624         bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1625                                     enum rf_pwrstate rfpwr_state);
1626         void (*led_control) (struct ieee80211_hw *hw,
1627                              enum led_ctl_mode ledaction);
1628         void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1629         u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1630         void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1631         void (*enable_hw_sec) (struct ieee80211_hw *hw);
1632         void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1633                          u8 *macaddr, bool is_group, u8 enc_algo,
1634                          bool is_wepkey, bool clear_all);
1635         void (*init_sw_leds) (struct ieee80211_hw *hw);
1636         void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1637         u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1638         void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1639                            u32 data);
1640         u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1641                           u32 regaddr, u32 bitmask);
1642         void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1643                            u32 regaddr, u32 bitmask, u32 data);
1644         void (*allow_all_destaddr)(struct ieee80211_hw *hw,
1645                 bool allow_all_da, bool write_into_reg);
1646         void (*linked_set_reg) (struct ieee80211_hw *hw);
1647         void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
1648         void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
1649         void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
1650         bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1651         void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1652                                             u8 *powerlevel);
1653         void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1654                                              u8 *ppowerlevel, u8 channel);
1655         bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1656                                            u8 configtype);
1657         bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1658                                              u8 configtype);
1659         void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1660         void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1661         void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1662         void (*c2h_command_handle) (struct ieee80211_hw *hw);
1663         void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
1664                                              bool mstate);
1665         void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
1666 };
1667
1668 struct rtl_intf_ops {
1669         /*com */
1670         void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1671         int (*adapter_start) (struct ieee80211_hw *hw);
1672         void (*adapter_stop) (struct ieee80211_hw *hw);
1673         bool (*check_buddy_priv)(struct ieee80211_hw *hw,
1674                                  struct rtl_priv **buddy_priv);
1675
1676         int (*adapter_tx) (struct ieee80211_hw *hw,
1677                            struct ieee80211_sta *sta,
1678                            struct sk_buff *skb,
1679                            struct rtl_tcb_desc *ptcb_desc);
1680         void (*flush)(struct ieee80211_hw *hw, bool drop);
1681         int (*reset_trx_ring) (struct ieee80211_hw *hw);
1682         bool (*waitq_insert) (struct ieee80211_hw *hw,
1683                               struct ieee80211_sta *sta,
1684                               struct sk_buff *skb);
1685
1686         /*pci */
1687         void (*disable_aspm) (struct ieee80211_hw *hw);
1688         void (*enable_aspm) (struct ieee80211_hw *hw);
1689
1690         /*usb */
1691 };
1692
1693 struct rtl_mod_params {
1694         /* default: 0 = using hardware encryption */
1695         bool sw_crypto;
1696
1697         /* default: 0 = DBG_EMERG (0)*/
1698         int debug;
1699
1700         /* default: 1 = using no linked power save */
1701         bool inactiveps;
1702
1703         /* default: 1 = using linked sw power save */
1704         bool swctrl_lps;
1705
1706         /* default: 1 = using linked fw power save */
1707         bool fwctrl_lps;
1708 };
1709
1710 struct rtl_hal_usbint_cfg {
1711         /* data - rx */
1712         u32 in_ep_num;
1713         u32 rx_urb_num;
1714         u32 rx_max_size;
1715
1716         /* op - rx */
1717         void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1718         void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1719                                      struct sk_buff_head *);
1720
1721         /* tx */
1722         void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1723         int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1724                                struct sk_buff *);
1725         struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1726                                                 struct sk_buff_head *);
1727
1728         /* endpoint mapping */
1729         int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1730         u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1731 };
1732
1733 struct rtl_hal_cfg {
1734         u8 bar_id;
1735         bool write_readback;
1736         char *name;
1737         char *fw_name;
1738         struct rtl_hal_ops *ops;
1739         struct rtl_mod_params *mod_params;
1740         struct rtl_hal_usbint_cfg *usb_interface_cfg;
1741
1742         /*this map used for some registers or vars
1743            defined int HAL but used in MAIN */
1744         u32 maps[RTL_VAR_MAP_MAX];
1745
1746 };
1747
1748 struct rtl_locks {
1749         /* mutex */
1750         struct mutex conf_mutex;
1751         struct mutex ps_mutex;
1752
1753         /*spin lock */
1754         spinlock_t ips_lock;
1755         spinlock_t irq_th_lock;
1756         spinlock_t irq_pci_lock;
1757         spinlock_t tx_lock;
1758         spinlock_t h2c_lock;
1759         spinlock_t rf_ps_lock;
1760         spinlock_t rf_lock;
1761         spinlock_t lps_lock;
1762         spinlock_t waitq_lock;
1763         spinlock_t entry_list_lock;
1764         spinlock_t usb_lock;
1765
1766         /*FW clock change */
1767         spinlock_t fw_ps_lock;
1768
1769         /*Dual mac*/
1770         spinlock_t cck_and_rw_pagea_lock;
1771
1772         /*Easy concurrent*/
1773         spinlock_t check_sendpkt_lock;
1774 };
1775
1776 struct rtl_works {
1777         struct ieee80211_hw *hw;
1778
1779         /*timer */
1780         struct timer_list watchdog_timer;
1781         struct timer_list dualmac_easyconcurrent_retrytimer;
1782         struct timer_list fw_clockoff_timer;
1783         struct timer_list fast_antenna_training_timer;
1784
1785         /*task */
1786         struct tasklet_struct irq_tasklet;
1787         struct tasklet_struct irq_prepare_bcn_tasklet;
1788
1789         /*work queue */
1790         struct workqueue_struct *rtl_wq;
1791         struct delayed_work watchdog_wq;
1792         struct delayed_work ips_nic_off_wq;
1793
1794         /* For SW LPS */
1795         struct delayed_work ps_work;
1796         struct delayed_work ps_rfon_wq;
1797         struct delayed_work fwevt_wq;
1798
1799         struct work_struct lps_leave_work;
1800 };
1801
1802 struct rtl_debug {
1803         u32 dbgp_type[DBGP_TYPE_MAX];
1804         int global_debuglevel;
1805         u64 global_debugcomponents;
1806
1807         /* add for proc debug */
1808         struct proc_dir_entry *proc_dir;
1809         char proc_name[20];
1810 };
1811
1812 #define MIMO_PS_STATIC                  0
1813 #define MIMO_PS_DYNAMIC                 1
1814 #define MIMO_PS_NOLIMIT                 3
1815
1816 struct rtl_dualmac_easy_concurrent_ctl {
1817         enum band_type currentbandtype_backfordmdp;
1818         bool close_bbandrf_for_dmsp;
1819         bool change_to_dmdp;
1820         bool change_to_dmsp;
1821         bool switch_in_process;
1822 };
1823
1824 struct rtl_dmsp_ctl {
1825         bool activescan_for_slaveofdmsp;
1826         bool scan_for_anothermac_fordmsp;
1827         bool scan_for_itself_fordmsp;
1828         bool writedig_for_anothermacofdmsp;
1829         u32 curdigvalue_for_anothermacofdmsp;
1830         bool changecckpdstate_for_anothermacofdmsp;
1831         u8 curcckpdstate_for_anothermacofdmsp;
1832         bool changetxhighpowerlvl_for_anothermacofdmsp;
1833         u8 curtxhighlvl_for_anothermacofdmsp;
1834         long rssivalmin_for_anothermacofdmsp;
1835 };
1836
1837 struct ps_t {
1838         u8 pre_ccastate;
1839         u8 cur_ccasate;
1840         u8 pre_rfstate;
1841         u8 cur_rfstate;
1842         long rssi_val_min;
1843 };
1844
1845 struct dig_t {
1846         u32 rssi_lowthresh;
1847         u32 rssi_highthresh;
1848         u32 fa_lowthresh;
1849         u32 fa_highthresh;
1850         long last_min_undec_pwdb_for_dm;
1851         long rssi_highpower_lowthresh;
1852         long rssi_highpower_highthresh;
1853         u32 recover_cnt;
1854         u32 pre_igvalue;
1855         u32 cur_igvalue;
1856         long rssi_val;
1857         u8 dig_enable_flag;
1858         u8 dig_ext_port_stage;
1859         u8 dig_algorithm;
1860         u8 dig_twoport_algorithm;
1861         u8 dig_dbgmode;
1862         u8 dig_slgorithm_switch;
1863         u8 cursta_cstate;
1864         u8 presta_cstate;
1865         u8 curmultista_cstate;
1866         char back_val;
1867         char back_range_max;
1868         char back_range_min;
1869         u8 rx_gain_range_max;
1870         u8 rx_gain_range_min;
1871         u8 min_undec_pwdb_for_dm;
1872         u8 rssi_val_min;
1873         u8 pre_cck_pd_state;
1874         u8 cur_cck_pd_state;
1875         u8 pre_cck_fa_state;
1876         u8 cur_cck_fa_state;
1877         u8 pre_ccastate;
1878         u8 cur_ccasate;
1879         u8 large_fa_hit;
1880         u8 forbidden_igi;
1881         u8 dig_state;
1882         u8 dig_highpwrstate;
1883         u8 cur_sta_cstate;
1884         u8 pre_sta_cstate;
1885         u8 cur_ap_cstate;
1886         u8 pre_ap_cstate;
1887         u8 cur_pd_thstate;
1888         u8 pre_pd_thstate;
1889         u8 cur_cs_ratiostate;
1890         u8 pre_cs_ratiostate;
1891         u8 backoff_enable_flag;
1892         char backoffval_range_max;
1893         char backoffval_range_min;
1894 };
1895
1896 struct rtl_global_var {
1897         /* from this list we can get
1898          * other adapter's rtl_priv */
1899         struct list_head glb_priv_list;
1900         spinlock_t glb_list_lock;
1901 };
1902
1903 struct rtl_priv {
1904         struct ieee80211_hw *hw;
1905         struct completion firmware_loading_complete;
1906         struct list_head list;
1907         struct rtl_priv *buddy_priv;
1908         struct rtl_global_var *glb_var;
1909         struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
1910         struct rtl_dmsp_ctl dmsp_ctl;
1911         struct rtl_locks locks;
1912         struct rtl_works works;
1913         struct rtl_mac mac80211;
1914         struct rtl_hal rtlhal;
1915         struct rtl_regulatory regd;
1916         struct rtl_rfkill rfkill;
1917         struct rtl_io io;
1918         struct rtl_phy phy;
1919         struct rtl_dm dm;
1920         struct rtl_security sec;
1921         struct rtl_efuse efuse;
1922
1923         struct rtl_ps_ctl psc;
1924         struct rate_adaptive ra;
1925         struct wireless_stats stats;
1926         struct rt_link_detect link_info;
1927         struct false_alarm_statistics falsealm_cnt;
1928
1929         struct rtl_rate_priv *rate_priv;
1930
1931         /* sta entry list for ap adhoc or mesh */
1932         struct list_head entry_list;
1933
1934         struct rtl_debug dbg;
1935         int max_fw_size;
1936
1937         /*
1938          *hal_cfg : for diff cards
1939          *intf_ops : for diff interrface usb/pcie
1940          */
1941         struct rtl_hal_cfg *cfg;
1942         struct rtl_intf_ops *intf_ops;
1943
1944         /*this var will be set by set_bit,
1945            and was used to indicate status of
1946            interface or hardware */
1947         unsigned long status;
1948
1949         /* tables for dm */
1950         struct dig_t dm_digtable;
1951         struct ps_t dm_pstable;
1952
1953         /* section shared by individual drivers */
1954         union {
1955                 struct {        /* data buffer pointer for USB reads */
1956                         __le32 *usb_data;
1957                         int usb_data_index;
1958                         bool initialized;
1959                 };
1960                 struct {        /* section for 8723ae */
1961                         bool reg_init;  /* true if regs saved */
1962                         u32 reg_874;
1963                         u32 reg_c70;
1964                         u32 reg_85c;
1965                         u32 reg_a74;
1966                         bool bt_operation_on;
1967                 };
1968         };
1969
1970         /*This must be the last item so
1971            that it points to the data allocated
1972            beyond  this structure like:
1973            rtl_pci_priv or rtl_usb_priv */
1974         u8 priv[0];
1975 };
1976
1977 #define rtl_priv(hw)            (((struct rtl_priv *)(hw)->priv))
1978 #define rtl_mac(rtlpriv)        (&((rtlpriv)->mac80211))
1979 #define rtl_hal(rtlpriv)        (&((rtlpriv)->rtlhal))
1980 #define rtl_efuse(rtlpriv)      (&((rtlpriv)->efuse))
1981 #define rtl_psc(rtlpriv)        (&((rtlpriv)->psc))
1982
1983
1984 /***************************************
1985     Bluetooth Co-existence Related
1986 ****************************************/
1987
1988 enum bt_ant_num {
1989         ANT_X2 = 0,
1990         ANT_X1 = 1,
1991 };
1992
1993 enum bt_co_type {
1994         BT_2WIRE = 0,
1995         BT_ISSC_3WIRE = 1,
1996         BT_ACCEL = 2,
1997         BT_CSR_BC4 = 3,
1998         BT_CSR_BC8 = 4,
1999         BT_RTL8756 = 5,
2000         BT_RTL8723A = 6,
2001 };
2002
2003 enum bt_cur_state {
2004         BT_OFF = 0,
2005         BT_ON = 1,
2006 };
2007
2008 enum bt_service_type {
2009         BT_SCO = 0,
2010         BT_A2DP = 1,
2011         BT_HID = 2,
2012         BT_HID_IDLE = 3,
2013         BT_SCAN = 4,
2014         BT_IDLE = 5,
2015         BT_OTHER_ACTION = 6,
2016         BT_BUSY = 7,
2017         BT_OTHERBUSY = 8,
2018         BT_PAN = 9,
2019 };
2020
2021 enum bt_radio_shared {
2022         BT_RADIO_SHARED = 0,
2023         BT_RADIO_INDIVIDUAL = 1,
2024 };
2025
2026 struct bt_coexist_info {
2027
2028         /* EEPROM BT info. */
2029         u8 eeprom_bt_coexist;
2030         u8 eeprom_bt_type;
2031         u8 eeprom_bt_ant_num;
2032         u8 eeprom_bt_ant_isol;
2033         u8 eeprom_bt_radio_shared;
2034
2035         u8 bt_coexistence;
2036         u8 bt_ant_num;
2037         u8 bt_coexist_type;
2038         u8 bt_state;
2039         u8 bt_cur_state;        /* 0:on, 1:off */
2040         u8 bt_ant_isolation;    /* 0:good, 1:bad */
2041         u8 bt_pape_ctrl;        /* 0:SW, 1:SW/HW dynamic */
2042         u8 bt_service;
2043         u8 bt_radio_shared_type;
2044         u8 bt_rfreg_origin_1e;
2045         u8 bt_rfreg_origin_1f;
2046         u8 bt_rssi_state;
2047         u32 ratio_tx;
2048         u32 ratio_pri;
2049         u32 bt_edca_ul;
2050         u32 bt_edca_dl;
2051
2052         bool init_set;
2053         bool bt_busy_traffic;
2054         bool bt_traffic_mode_set;
2055         bool bt_non_traffic_mode_set;
2056
2057         bool fw_coexist_all_off;
2058         bool sw_coexist_all_off;
2059         bool hw_coexist_all_off;
2060         u32 cstate;
2061         u32 previous_state;
2062         u32 cstate_h;
2063         u32 previous_state_h;
2064
2065         u8 bt_pre_rssi_state;
2066         u8 bt_pre_rssi_state1;
2067
2068         u8 reg_bt_iso;
2069         u8 reg_bt_sco;
2070         bool balance_on;
2071         u8 bt_active_zero_cnt;
2072         bool cur_bt_disabled;
2073         bool pre_bt_disabled;
2074
2075         u8 bt_profile_case;
2076         u8 bt_profile_action;
2077         bool bt_busy;
2078         bool hold_for_bt_operation;
2079         u8 lps_counter;
2080 };
2081
2082
2083 /****************************************
2084         mem access macro define start
2085         Call endian free function when
2086         1. Read/write packet content.
2087         2. Before write integer to IO.
2088         3. After read integer from IO.
2089 ****************************************/
2090 /* Convert little data endian to host ordering */
2091 #define EF1BYTE(_val)           \
2092         ((u8)(_val))
2093 #define EF2BYTE(_val)           \
2094         (le16_to_cpu(_val))
2095 #define EF4BYTE(_val)           \
2096         (le32_to_cpu(_val))
2097
2098 /* Read data from memory */
2099 #define READEF1BYTE(_ptr)       \
2100         EF1BYTE(*((u8 *)(_ptr)))
2101 /* Read le16 data from memory and convert to host ordering */
2102 #define READEF2BYTE(_ptr)       \
2103         EF2BYTE(*(_ptr))
2104 #define READEF4BYTE(_ptr)       \
2105         EF4BYTE(*(_ptr))
2106
2107 /* Write data to memory */
2108 #define WRITEEF1BYTE(_ptr, _val)        \
2109         (*((u8 *)(_ptr))) = EF1BYTE(_val)
2110 /* Write le16 data to memory in host ordering */
2111 #define WRITEEF2BYTE(_ptr, _val)        \
2112         (*((u16 *)(_ptr))) = EF2BYTE(_val)
2113 #define WRITEEF4BYTE(_ptr, _val)        \
2114         (*((u32 *)(_ptr))) = EF2BYTE(_val)
2115
2116 /* Create a bit mask
2117  * Examples:
2118  * BIT_LEN_MASK_32(0) => 0x00000000
2119  * BIT_LEN_MASK_32(1) => 0x00000001
2120  * BIT_LEN_MASK_32(2) => 0x00000003
2121  * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2122  */
2123 #define BIT_LEN_MASK_32(__bitlen)        \
2124         (0xFFFFFFFF >> (32 - (__bitlen)))
2125 #define BIT_LEN_MASK_16(__bitlen)        \
2126         (0xFFFF >> (16 - (__bitlen)))
2127 #define BIT_LEN_MASK_8(__bitlen) \
2128         (0xFF >> (8 - (__bitlen)))
2129
2130 /* Create an offset bit mask
2131  * Examples:
2132  * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2133  * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2134  */
2135 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2136         (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2137 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2138         (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2139 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2140         (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2141
2142 /*Description:
2143  * Return 4-byte value in host byte ordering from
2144  * 4-byte pointer in little-endian system.
2145  */
2146 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2147         (EF4BYTE(*((__le32 *)(__pstart))))
2148 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2149         (EF2BYTE(*((__le16 *)(__pstart))))
2150 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2151         (EF1BYTE(*((u8 *)(__pstart))))
2152
2153 /*Description:
2154 Translate subfield (continuous bits in little-endian) of 4-byte
2155 value to host byte ordering.*/
2156 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2157         ( \
2158                 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset))  & \
2159                 BIT_LEN_MASK_32(__bitlen) \
2160         )
2161 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2162         ( \
2163                 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2164                 BIT_LEN_MASK_16(__bitlen) \
2165         )
2166 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2167         ( \
2168                 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2169                 BIT_LEN_MASK_8(__bitlen) \
2170         )
2171
2172 /* Description:
2173  * Mask subfield (continuous bits in little-endian) of 4-byte value
2174  * and return the result in 4-byte value in host byte ordering.
2175  */
2176 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2177         ( \
2178                 LE_P4BYTE_TO_HOST_4BYTE(__pstart)  & \
2179                 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2180         )
2181 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2182         ( \
2183                 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2184                 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2185         )
2186 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2187         ( \
2188                 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2189                 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2190         )
2191
2192 /* Description:
2193  * Set subfield of little-endian 4-byte value to specified value.
2194  */
2195 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2196         *((u32 *)(__pstart)) = \
2197         ( \
2198                 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2199                 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2200         );
2201 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2202         *((u16 *)(__pstart)) = \
2203         ( \
2204                 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2205                 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2206         );
2207 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2208         *((u8 *)(__pstart)) = EF1BYTE \
2209         ( \
2210                 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2211                 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2212         );
2213
2214 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2215         (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2216
2217 /****************************************
2218         mem access macro define end
2219 ****************************************/
2220
2221 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2222
2223 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2224 #define RTL_WATCH_DOG_TIME      2000
2225 #define MSECS(t)                msecs_to_jiffies(t)
2226 #define WLAN_FC_GET_VERS(fc)    (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2227 #define WLAN_FC_GET_TYPE(fc)    (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2228 #define WLAN_FC_GET_STYPE(fc)   (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2229 #define WLAN_FC_MORE_DATA(fc)   (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2230
2231 #define RT_RF_OFF_LEVL_ASPM             BIT(0)  /*PCI ASPM */
2232 #define RT_RF_OFF_LEVL_CLK_REQ          BIT(1)  /*PCI clock request */
2233 #define RT_RF_OFF_LEVL_PCI_D3           BIT(2)  /*PCI D3 mode */
2234 /*NIC halt, re-initialize hw parameters*/
2235 #define RT_RF_OFF_LEVL_HALT_NIC         BIT(3)
2236 #define RT_RF_OFF_LEVL_FREE_FW          BIT(4)  /*FW free, re-download the FW */
2237 #define RT_RF_OFF_LEVL_FW_32K           BIT(5)  /*FW in 32k */
2238 /*Always enable ASPM and Clock Req in initialization.*/
2239 #define RT_RF_PS_LEVEL_ALWAYS_ASPM      BIT(6)
2240 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2241 #define RT_PS_LEVEL_ASPM                BIT(7)
2242 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2243 #define RT_RF_LPS_DISALBE_2R            BIT(30)
2244 #define RT_RF_LPS_LEVEL_ASPM            BIT(31) /*LPS with ASPM */
2245 #define RT_IN_PS_LEVEL(ppsc, _ps_flg)           \
2246         ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2247 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg)        \
2248         (ppsc->cur_ps_level &= (~(_ps_flg)))
2249 #define RT_SET_PS_LEVEL(ppsc, _ps_flg)          \
2250         (ppsc->cur_ps_level |= _ps_flg)
2251
2252 #define container_of_dwork_rtl(x, y, z) \
2253         container_of(container_of(x, struct delayed_work, work), y, z)
2254
2255 #define FILL_OCTET_STRING(_os, _octet, _len)    \
2256                 (_os).octet = (u8 *)(_octet);           \
2257                 (_os).length = (_len);
2258
2259 #define CP_MACADDR(des, src)    \
2260         ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2261         (des)[2] = (src)[2], (des)[3] = (src)[3],\
2262         (des)[4] = (src)[4], (des)[5] = (src)[5])
2263
2264 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2265 {
2266         return rtlpriv->io.read8_sync(rtlpriv, addr);
2267 }
2268
2269 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2270 {
2271         return rtlpriv->io.read16_sync(rtlpriv, addr);
2272 }
2273
2274 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2275 {
2276         return rtlpriv->io.read32_sync(rtlpriv, addr);
2277 }
2278
2279 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2280 {
2281         rtlpriv->io.write8_async(rtlpriv, addr, val8);
2282
2283         if (rtlpriv->cfg->write_readback)
2284                 rtlpriv->io.read8_sync(rtlpriv, addr);
2285 }
2286
2287 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2288 {
2289         rtlpriv->io.write16_async(rtlpriv, addr, val16);
2290
2291         if (rtlpriv->cfg->write_readback)
2292                 rtlpriv->io.read16_sync(rtlpriv, addr);
2293 }
2294
2295 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2296                                    u32 addr, u32 val32)
2297 {
2298         rtlpriv->io.write32_async(rtlpriv, addr, val32);
2299
2300         if (rtlpriv->cfg->write_readback)
2301                 rtlpriv->io.read32_sync(rtlpriv, addr);
2302 }
2303
2304 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2305                                 u32 regaddr, u32 bitmask)
2306 {
2307         struct rtl_priv *rtlpriv = hw->priv;
2308
2309         return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2310 }
2311
2312 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2313                                  u32 bitmask, u32 data)
2314 {
2315         struct rtl_priv *rtlpriv = hw->priv;
2316
2317         rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2318 }
2319
2320 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2321                                 enum radio_path rfpath, u32 regaddr,
2322                                 u32 bitmask)
2323 {
2324         struct rtl_priv *rtlpriv = hw->priv;
2325
2326         return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2327 }
2328
2329 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2330                                  enum radio_path rfpath, u32 regaddr,
2331                                  u32 bitmask, u32 data)
2332 {
2333         struct rtl_priv *rtlpriv = hw->priv;
2334
2335         rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2336 }
2337
2338 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2339 {
2340         return (_HAL_STATE_STOP == rtlhal->state);
2341 }
2342
2343 static inline void set_hal_start(struct rtl_hal *rtlhal)
2344 {
2345         rtlhal->state = _HAL_STATE_START;
2346 }
2347
2348 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2349 {
2350         rtlhal->state = _HAL_STATE_STOP;
2351 }
2352
2353 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2354 {
2355         return rtlphy->rf_type;
2356 }
2357
2358 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2359 {
2360         return (struct ieee80211_hdr *)(skb->data);
2361 }
2362
2363 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2364 {
2365         return rtl_get_hdr(skb)->frame_control;
2366 }
2367
2368 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2369 {
2370         return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2371 }
2372
2373 static inline u16 rtl_get_tid(struct sk_buff *skb)
2374 {
2375         return rtl_get_tid_h(rtl_get_hdr(skb));
2376 }
2377
2378 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2379                                             struct ieee80211_vif *vif,
2380                                             const u8 *bssid)
2381 {
2382         return ieee80211_find_sta(vif, bssid);
2383 }
2384
2385 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
2386                 u8 *mac_addr)
2387 {
2388         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2389         return ieee80211_find_sta(mac->vif, mac_addr);
2390 }
2391
2392 #endif