1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/ipv6.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <scsi/fc/fc_fcoe.h>
45 #include "ixgbe_common.h"
47 char ixgbe_driver_name
[] = "ixgbe";
48 static const char ixgbe_driver_string
[] =
49 "Intel(R) 10 Gigabit PCI Express Network Driver";
51 #define DRV_VERSION "2.0.16-k2"
52 const char ixgbe_driver_version
[] = DRV_VERSION
;
53 static char ixgbe_copyright
[] = "Copyright (c) 1999-2009 Intel Corporation.";
55 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
56 [board_82598
] = &ixgbe_82598_info
,
57 [board_82599
] = &ixgbe_82599_info
,
60 /* ixgbe_pci_tbl - PCI Device ID Table
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
68 static struct pci_device_id ixgbe_pci_tbl
[] = {
69 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
71 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
73 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
75 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
77 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
79 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
96 /* required last entry */
99 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
101 #ifdef CONFIG_IXGBE_DCA
102 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
104 static struct notifier_block dca_notifier
= {
105 .notifier_call
= ixgbe_notify_dca
,
111 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
112 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
113 MODULE_LICENSE("GPL");
114 MODULE_VERSION(DRV_VERSION
);
116 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
118 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
122 /* Let firmware take over control of h/w */
123 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
124 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
125 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
128 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
132 /* Let firmware know the driver has taken over */
133 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
134 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
135 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
139 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
140 * @adapter: pointer to adapter struct
141 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
142 * @queue: queue to map the corresponding interrupt to
143 * @msix_vector: the vector to map to the corresponding queue
146 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
147 u8 queue
, u8 msix_vector
)
150 struct ixgbe_hw
*hw
= &adapter
->hw
;
151 switch (hw
->mac
.type
) {
152 case ixgbe_mac_82598EB
:
153 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
156 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
157 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
158 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
159 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
160 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
162 case ixgbe_mac_82599EB
:
163 if (direction
== -1) {
165 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
166 index
= ((queue
& 1) * 8);
167 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
168 ivar
&= ~(0xFF << index
);
169 ivar
|= (msix_vector
<< index
);
170 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
173 /* tx or rx causes */
174 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
175 index
= ((16 * (queue
& 1)) + (8 * direction
));
176 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
177 ivar
&= ~(0xFF << index
);
178 ivar
|= (msix_vector
<< index
);
179 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
187 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter
*adapter
,
188 struct ixgbe_tx_buffer
191 tx_buffer_info
->dma
= 0;
192 if (tx_buffer_info
->skb
) {
193 skb_dma_unmap(&adapter
->pdev
->dev
, tx_buffer_info
->skb
,
195 dev_kfree_skb_any(tx_buffer_info
->skb
);
196 tx_buffer_info
->skb
= NULL
;
198 tx_buffer_info
->time_stamp
= 0;
199 /* tx_buffer_info must be completely set up in the transmit path */
202 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter
*adapter
,
203 struct ixgbe_ring
*tx_ring
,
206 struct ixgbe_hw
*hw
= &adapter
->hw
;
208 /* Detect a transmit hang in hardware, this serializes the
209 * check with the clearing of time_stamp and movement of eop */
210 adapter
->detect_tx_hung
= false;
211 if (tx_ring
->tx_buffer_info
[eop
].time_stamp
&&
212 time_after(jiffies
, tx_ring
->tx_buffer_info
[eop
].time_stamp
+ HZ
) &&
213 !(IXGBE_READ_REG(&adapter
->hw
, IXGBE_TFCS
) & IXGBE_TFCS_TXOFF
)) {
214 /* detected Tx unit hang */
215 union ixgbe_adv_tx_desc
*tx_desc
;
216 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
217 DPRINTK(DRV
, ERR
, "Detected Tx Unit Hang\n"
219 " TDH, TDT <%x>, <%x>\n"
220 " next_to_use <%x>\n"
221 " next_to_clean <%x>\n"
222 "tx_buffer_info[next_to_clean]\n"
223 " time_stamp <%lx>\n"
225 tx_ring
->queue_index
,
226 IXGBE_READ_REG(hw
, tx_ring
->head
),
227 IXGBE_READ_REG(hw
, tx_ring
->tail
),
228 tx_ring
->next_to_use
, eop
,
229 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
236 #define IXGBE_MAX_TXD_PWR 14
237 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
239 /* Tx Descriptors needed, worst case */
240 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
241 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
242 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
243 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
245 static void ixgbe_tx_timeout(struct net_device
*netdev
);
248 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
249 * @adapter: board private structure
250 * @tx_ring: tx ring to clean
252 * returns true if transmit work is done
254 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter
*adapter
,
255 struct ixgbe_ring
*tx_ring
)
257 struct net_device
*netdev
= adapter
->netdev
;
258 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
259 struct ixgbe_tx_buffer
*tx_buffer_info
;
260 unsigned int i
, eop
, count
= 0;
261 unsigned int total_bytes
= 0, total_packets
= 0;
263 i
= tx_ring
->next_to_clean
;
264 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
265 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
267 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
268 (count
< tx_ring
->work_limit
)) {
269 bool cleaned
= false;
270 for ( ; !cleaned
; count
++) {
272 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
273 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
274 cleaned
= (i
== eop
);
275 skb
= tx_buffer_info
->skb
;
277 if (cleaned
&& skb
) {
278 unsigned int segs
, bytecount
;
280 /* gso_segs is currently only valid for tcp */
281 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
282 /* multiply data chunks by size of headers */
283 bytecount
= ((segs
- 1) * skb_headlen(skb
)) +
285 total_packets
+= segs
;
286 total_bytes
+= bytecount
;
289 ixgbe_unmap_and_free_tx_resource(adapter
,
292 tx_desc
->wb
.status
= 0;
295 if (i
== tx_ring
->count
)
299 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
300 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
303 tx_ring
->next_to_clean
= i
;
305 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
306 if (unlikely(count
&& netif_carrier_ok(netdev
) &&
307 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
308 /* Make sure that anybody stopping the queue after this
309 * sees the new next_to_clean.
312 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
313 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
314 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
315 ++adapter
->restart_queue
;
319 if (adapter
->detect_tx_hung
) {
320 if (ixgbe_check_tx_hang(adapter
, tx_ring
, i
)) {
321 /* schedule immediate reset if we believe we hung */
323 "tx hang %d detected, resetting adapter\n",
324 adapter
->tx_timeout_count
+ 1);
325 ixgbe_tx_timeout(adapter
->netdev
);
329 /* re-arm the interrupt */
330 if (count
>= tx_ring
->work_limit
) {
331 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
332 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
,
334 else if (tx_ring
->v_idx
& 0xFFFFFFFF)
335 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0),
338 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1),
339 (tx_ring
->v_idx
>> 32));
343 tx_ring
->total_bytes
+= total_bytes
;
344 tx_ring
->total_packets
+= total_packets
;
345 tx_ring
->stats
.packets
+= total_packets
;
346 tx_ring
->stats
.bytes
+= total_bytes
;
347 adapter
->net_stats
.tx_bytes
+= total_bytes
;
348 adapter
->net_stats
.tx_packets
+= total_packets
;
349 return (count
< tx_ring
->work_limit
);
352 #ifdef CONFIG_IXGBE_DCA
353 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
354 struct ixgbe_ring
*rx_ring
)
358 int q
= rx_ring
- adapter
->rx_ring
;
360 if (rx_ring
->cpu
!= cpu
) {
361 rxctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
));
362 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
363 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
364 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
365 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
366 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
367 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
368 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
370 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
371 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
372 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
373 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
374 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
375 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
), rxctrl
);
381 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
382 struct ixgbe_ring
*tx_ring
)
386 int q
= tx_ring
- adapter
->tx_ring
;
388 if (tx_ring
->cpu
!= cpu
) {
389 txctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_TXCTRL(q
));
390 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
391 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
392 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
393 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
394 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
395 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
396 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
398 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
399 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_TXCTRL(q
), txctrl
);
405 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
409 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
412 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
413 adapter
->tx_ring
[i
].cpu
= -1;
414 ixgbe_update_tx_dca(adapter
, &adapter
->tx_ring
[i
]);
416 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
417 adapter
->rx_ring
[i
].cpu
= -1;
418 ixgbe_update_rx_dca(adapter
, &adapter
->rx_ring
[i
]);
422 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
424 struct net_device
*netdev
= dev_get_drvdata(dev
);
425 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
426 unsigned long event
= *(unsigned long *)data
;
429 case DCA_PROVIDER_ADD
:
430 /* if we're already enabled, don't do it again */
431 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
433 /* Always use CB2 mode, difference is masked
434 * in the CB driver. */
435 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
436 if (dca_add_requester(dev
) == 0) {
437 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
438 ixgbe_setup_dca(adapter
);
441 /* Fall Through since DCA is disabled. */
442 case DCA_PROVIDER_REMOVE
:
443 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
444 dca_remove_requester(dev
);
445 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
446 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
454 #endif /* CONFIG_IXGBE_DCA */
456 * ixgbe_receive_skb - Send a completed packet up the stack
457 * @adapter: board private structure
458 * @skb: packet to send up
459 * @status: hardware indication of status of receive
460 * @rx_ring: rx descriptor ring (for a specific queue) to setup
461 * @rx_desc: rx descriptor
463 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
464 struct sk_buff
*skb
, u8 status
,
465 struct ixgbe_ring
*ring
,
466 union ixgbe_adv_rx_desc
*rx_desc
)
468 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
469 struct napi_struct
*napi
= &q_vector
->napi
;
470 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
471 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
473 skb_record_rx_queue(skb
, ring
->queue_index
);
474 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
)) {
475 if (adapter
->vlgrp
&& is_vlan
&& (tag
!= 0))
476 vlan_gro_receive(napi
, adapter
->vlgrp
, tag
, skb
);
478 napi_gro_receive(napi
, skb
);
480 if (adapter
->vlgrp
&& is_vlan
&& (tag
!= 0))
481 vlan_hwaccel_rx(skb
, adapter
->vlgrp
, tag
);
488 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
489 * @adapter: address of board private structure
490 * @status_err: hardware indication of status of receive
491 * @skb: skb currently being received and modified
493 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
494 u32 status_err
, struct sk_buff
*skb
)
496 skb
->ip_summed
= CHECKSUM_NONE
;
498 /* Rx csum disabled */
499 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
502 /* if IP and error */
503 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
504 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
505 adapter
->hw_csum_rx_error
++;
509 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
512 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
513 adapter
->hw_csum_rx_error
++;
517 /* It must be a TCP or UDP packet with a valid checksum */
518 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
519 adapter
->hw_csum_rx_good
++;
522 static inline void ixgbe_release_rx_desc(struct ixgbe_hw
*hw
,
523 struct ixgbe_ring
*rx_ring
, u32 val
)
526 * Force memory writes to complete before letting h/w
527 * know there are new descriptors to fetch. (Only
528 * applicable for weak-ordered memory model archs,
532 IXGBE_WRITE_REG(hw
, IXGBE_RDT(rx_ring
->reg_idx
), val
);
536 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
537 * @adapter: address of board private structure
539 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter
*adapter
,
540 struct ixgbe_ring
*rx_ring
,
543 struct pci_dev
*pdev
= adapter
->pdev
;
544 union ixgbe_adv_rx_desc
*rx_desc
;
545 struct ixgbe_rx_buffer
*bi
;
547 unsigned int bufsz
= rx_ring
->rx_buf_len
+ NET_IP_ALIGN
;
549 i
= rx_ring
->next_to_use
;
550 bi
= &rx_ring
->rx_buffer_info
[i
];
552 while (cleaned_count
--) {
553 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
556 (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)) {
558 bi
->page
= alloc_page(GFP_ATOMIC
);
560 adapter
->alloc_rx_page_failed
++;
565 /* use a half page if we're re-using */
566 bi
->page_offset
^= (PAGE_SIZE
/ 2);
569 bi
->page_dma
= pci_map_page(pdev
, bi
->page
,
577 skb
= netdev_alloc_skb(adapter
->netdev
, bufsz
);
580 adapter
->alloc_rx_buff_failed
++;
585 * Make buffer alignment 2 beyond a 16 byte boundary
586 * this will result in a 16 byte aligned IP header after
587 * the 14 byte MAC header is removed
589 skb_reserve(skb
, NET_IP_ALIGN
);
592 bi
->dma
= pci_map_single(pdev
, skb
->data
, bufsz
,
595 /* Refresh the desc even if buffer_addrs didn't change because
596 * each write-back erases this info. */
597 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
598 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
599 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
601 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
605 if (i
== rx_ring
->count
)
607 bi
= &rx_ring
->rx_buffer_info
[i
];
611 if (rx_ring
->next_to_use
!= i
) {
612 rx_ring
->next_to_use
= i
;
614 i
= (rx_ring
->count
- 1);
616 ixgbe_release_rx_desc(&adapter
->hw
, rx_ring
, i
);
620 static inline u16
ixgbe_get_hdr_info(union ixgbe_adv_rx_desc
*rx_desc
)
622 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
;
625 static inline u16
ixgbe_get_pkt_info(union ixgbe_adv_rx_desc
*rx_desc
)
627 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
630 static inline u32
ixgbe_get_rsc_count(union ixgbe_adv_rx_desc
*rx_desc
)
632 return (le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
633 IXGBE_RXDADV_RSCCNT_MASK
) >>
634 IXGBE_RXDADV_RSCCNT_SHIFT
;
638 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
639 * @skb: pointer to the last skb in the rsc queue
641 * This function changes a queue full of hw rsc buffers into a completed
642 * packet. It uses the ->prev pointers to find the first packet and then
643 * turns it into the frag list owner.
645 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
)
647 unsigned int frag_list_size
= 0;
650 struct sk_buff
*prev
= skb
->prev
;
651 frag_list_size
+= skb
->len
;
656 skb_shinfo(skb
)->frag_list
= skb
->next
;
658 skb
->len
+= frag_list_size
;
659 skb
->data_len
+= frag_list_size
;
660 skb
->truesize
+= frag_list_size
;
664 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
665 struct ixgbe_ring
*rx_ring
,
666 int *work_done
, int work_to_do
)
668 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
669 struct pci_dev
*pdev
= adapter
->pdev
;
670 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
671 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
673 unsigned int i
, rsc_count
= 0;
676 bool cleaned
= false;
677 int cleaned_count
= 0;
678 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
680 i
= rx_ring
->next_to_clean
;
681 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
682 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
683 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
685 while (staterr
& IXGBE_RXD_STAT_DD
) {
687 if (*work_done
>= work_to_do
)
691 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
692 hdr_info
= le16_to_cpu(ixgbe_get_hdr_info(rx_desc
));
693 len
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
694 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
695 if (hdr_info
& IXGBE_RXDADV_SPH
)
696 adapter
->rx_hdr_split
++;
697 if (len
> IXGBE_RX_HDR_SIZE
)
698 len
= IXGBE_RX_HDR_SIZE
;
699 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
701 len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
705 skb
= rx_buffer_info
->skb
;
706 prefetch(skb
->data
- NET_IP_ALIGN
);
707 rx_buffer_info
->skb
= NULL
;
709 if (len
&& !skb_shinfo(skb
)->nr_frags
) {
710 pci_unmap_single(pdev
, rx_buffer_info
->dma
,
717 pci_unmap_page(pdev
, rx_buffer_info
->page_dma
,
718 PAGE_SIZE
/ 2, PCI_DMA_FROMDEVICE
);
719 rx_buffer_info
->page_dma
= 0;
720 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
721 rx_buffer_info
->page
,
722 rx_buffer_info
->page_offset
,
725 if ((rx_ring
->rx_buf_len
> (PAGE_SIZE
/ 2)) ||
726 (page_count(rx_buffer_info
->page
) != 1))
727 rx_buffer_info
->page
= NULL
;
729 get_page(rx_buffer_info
->page
);
731 skb
->len
+= upper_len
;
732 skb
->data_len
+= upper_len
;
733 skb
->truesize
+= upper_len
;
737 if (i
== rx_ring
->count
)
740 next_rxd
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
744 if (adapter
->flags
& IXGBE_FLAG_RSC_CAPABLE
)
745 rsc_count
= ixgbe_get_rsc_count(rx_desc
);
748 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
749 IXGBE_RXDADV_NEXTP_SHIFT
;
750 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
751 rx_ring
->rsc_count
+= (rsc_count
- 1);
753 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
756 if (staterr
& IXGBE_RXD_STAT_EOP
) {
758 skb
= ixgbe_transform_rsc_queue(skb
);
759 rx_ring
->stats
.packets
++;
760 rx_ring
->stats
.bytes
+= skb
->len
;
762 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
763 rx_buffer_info
->skb
= next_buffer
->skb
;
764 rx_buffer_info
->dma
= next_buffer
->dma
;
765 next_buffer
->skb
= skb
;
766 next_buffer
->dma
= 0;
768 skb
->next
= next_buffer
->skb
;
769 skb
->next
->prev
= skb
;
771 adapter
->non_eop_descs
++;
775 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
776 dev_kfree_skb_irq(skb
);
780 ixgbe_rx_checksum(adapter
, staterr
, skb
);
782 /* probably a little skewed due to removing CRC */
783 total_rx_bytes
+= skb
->len
;
786 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
788 /* if ddp, not passing to ULD unless for FCP_RSP or error */
789 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
790 if (!ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
))
792 #endif /* IXGBE_FCOE */
793 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
796 rx_desc
->wb
.upper
.status_error
= 0;
798 /* return some buffers to hardware, one at a time is too slow */
799 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
800 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
804 /* use prefetched values */
806 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
808 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
811 rx_ring
->next_to_clean
= i
;
812 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
815 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
817 rx_ring
->total_packets
+= total_rx_packets
;
818 rx_ring
->total_bytes
+= total_rx_bytes
;
819 adapter
->net_stats
.rx_bytes
+= total_rx_bytes
;
820 adapter
->net_stats
.rx_packets
+= total_rx_packets
;
825 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
827 * ixgbe_configure_msix - Configure MSI-X hardware
828 * @adapter: board private structure
830 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
833 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
835 struct ixgbe_q_vector
*q_vector
;
836 int i
, j
, q_vectors
, v_idx
, r_idx
;
839 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
842 * Populate the IVAR table and set the ITR values to the
843 * corresponding register.
845 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
846 q_vector
= adapter
->q_vector
[v_idx
];
847 /* XXX for_each_bit(...) */
848 r_idx
= find_first_bit(q_vector
->rxr_idx
,
849 adapter
->num_rx_queues
);
851 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
852 j
= adapter
->rx_ring
[r_idx
].reg_idx
;
853 ixgbe_set_ivar(adapter
, 0, j
, v_idx
);
854 r_idx
= find_next_bit(q_vector
->rxr_idx
,
855 adapter
->num_rx_queues
,
858 r_idx
= find_first_bit(q_vector
->txr_idx
,
859 adapter
->num_tx_queues
);
861 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
862 j
= adapter
->tx_ring
[r_idx
].reg_idx
;
863 ixgbe_set_ivar(adapter
, 1, j
, v_idx
);
864 r_idx
= find_next_bit(q_vector
->txr_idx
,
865 adapter
->num_tx_queues
,
869 /* if this is a tx only vector halve the interrupt rate */
870 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
871 q_vector
->eitr
= (adapter
->eitr_param
>> 1);
872 else if (q_vector
->rxr_count
)
874 q_vector
->eitr
= adapter
->eitr_param
;
877 * since this is initial set up don't need to call
878 * ixgbe_write_eitr helper
880 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
),
881 EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
));
884 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
885 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
887 else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
888 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
889 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
891 /* set up to autoclear timer, and the vectors */
892 mask
= IXGBE_EIMS_ENABLE_MASK
;
893 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
894 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
901 latency_invalid
= 255
905 * ixgbe_update_itr - update the dynamic ITR value based on statistics
906 * @adapter: pointer to adapter
907 * @eitr: eitr setting (ints per sec) to give last timeslice
908 * @itr_setting: current throttle rate in ints/second
909 * @packets: the number of packets during this measurement interval
910 * @bytes: the number of bytes during this measurement interval
912 * Stores a new ITR value based on packets and byte
913 * counts during the last interrupt. The advantage of per interrupt
914 * computation is faster updates and more accurate ITR for the current
915 * traffic pattern. Constants in this function were computed
916 * based on theoretical maximum wire speed and thresholds were set based
917 * on testing data as well as attempting to minimize response time
918 * while increasing bulk throughput.
919 * this functionality is controlled by the InterruptThrottleRate module
920 * parameter (see ixgbe_param.c)
922 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
923 u32 eitr
, u8 itr_setting
,
924 int packets
, int bytes
)
926 unsigned int retval
= itr_setting
;
931 goto update_itr_done
;
934 /* simple throttlerate management
935 * 0-20MB/s lowest (100000 ints/s)
936 * 20-100MB/s low (20000 ints/s)
937 * 100-1249MB/s bulk (8000 ints/s)
939 /* what was last interrupt timeslice? */
940 timepassed_us
= 1000000/eitr
;
941 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
943 switch (itr_setting
) {
945 if (bytes_perint
> adapter
->eitr_low
)
946 retval
= low_latency
;
949 if (bytes_perint
> adapter
->eitr_high
)
950 retval
= bulk_latency
;
951 else if (bytes_perint
<= adapter
->eitr_low
)
952 retval
= lowest_latency
;
955 if (bytes_perint
<= adapter
->eitr_high
)
956 retval
= low_latency
;
965 * ixgbe_write_eitr - write EITR register in hardware specific way
966 * @adapter: pointer to adapter struct
967 * @v_idx: vector index into q_vector array
968 * @itr_reg: new value to be written in *register* format, not ints/s
970 * This function is made to be called by ethtool and by the driver
971 * when it needs to update EITR registers at runtime. Hardware
972 * specific quirks/differences are taken care of here.
974 void ixgbe_write_eitr(struct ixgbe_adapter
*adapter
, int v_idx
, u32 itr_reg
)
976 struct ixgbe_hw
*hw
= &adapter
->hw
;
977 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
978 /* must write high and low 16 bits to reset counter */
979 itr_reg
|= (itr_reg
<< 16);
980 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
982 * set the WDIS bit to not clear the timer bits and cause an
983 * immediate assertion of the interrupt
985 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
987 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
990 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
992 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
994 u8 current_itr
, ret_itr
;
995 int i
, r_idx
, v_idx
= q_vector
->v_idx
;
996 struct ixgbe_ring
*rx_ring
, *tx_ring
;
998 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
999 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1000 tx_ring
= &(adapter
->tx_ring
[r_idx
]);
1001 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1003 tx_ring
->total_packets
,
1004 tx_ring
->total_bytes
);
1005 /* if the result for this queue would decrease interrupt
1006 * rate for this vector then use that result */
1007 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1008 q_vector
->tx_itr
- 1 : ret_itr
);
1009 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1013 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1014 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1015 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1016 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1018 rx_ring
->total_packets
,
1019 rx_ring
->total_bytes
);
1020 /* if the result for this queue would decrease interrupt
1021 * rate for this vector then use that result */
1022 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1023 q_vector
->rx_itr
- 1 : ret_itr
);
1024 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1028 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1030 switch (current_itr
) {
1031 /* counts and packets in update_itr are dependent on these numbers */
1032 case lowest_latency
:
1036 new_itr
= 20000; /* aka hwitr = ~200 */
1044 if (new_itr
!= q_vector
->eitr
) {
1047 /* save the algorithm value here, not the smoothed one */
1048 q_vector
->eitr
= new_itr
;
1049 /* do an exponential smoothing */
1050 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1051 itr_reg
= EITR_INTS_PER_SEC_TO_REG(new_itr
);
1052 ixgbe_write_eitr(adapter
, v_idx
, itr_reg
);
1058 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1060 struct ixgbe_hw
*hw
= &adapter
->hw
;
1062 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1063 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1064 DPRINTK(PROBE
, CRIT
, "Fan has stopped, replace the adapter\n");
1065 /* write to clear the interrupt */
1066 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1070 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1072 struct ixgbe_hw
*hw
= &adapter
->hw
;
1074 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1075 /* Clear the interrupt */
1076 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1077 schedule_work(&adapter
->multispeed_fiber_task
);
1078 } else if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1079 /* Clear the interrupt */
1080 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1081 schedule_work(&adapter
->sfp_config_module_task
);
1083 /* Interrupt isn't for us... */
1088 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1090 struct ixgbe_hw
*hw
= &adapter
->hw
;
1093 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1094 adapter
->link_check_timeout
= jiffies
;
1095 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1096 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1097 schedule_work(&adapter
->watchdog_task
);
1101 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1103 struct net_device
*netdev
= data
;
1104 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1105 struct ixgbe_hw
*hw
= &adapter
->hw
;
1109 * Workaround for Silicon errata. Use clear-by-write instead
1110 * of clear-by-read. Reading with EICS will return the
1111 * interrupt causes without clearing, which later be done
1112 * with the write to EICR.
1114 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1115 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1117 if (eicr
& IXGBE_EICR_LSC
)
1118 ixgbe_check_lsc(adapter
);
1120 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1121 ixgbe_check_fan_failure(adapter
, eicr
);
1123 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
1124 ixgbe_check_sfp_event(adapter
, eicr
);
1125 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1126 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1131 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1133 struct ixgbe_q_vector
*q_vector
= data
;
1134 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1135 struct ixgbe_ring
*tx_ring
;
1138 if (!q_vector
->txr_count
)
1141 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1142 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1143 tx_ring
= &(adapter
->tx_ring
[r_idx
]);
1144 #ifdef CONFIG_IXGBE_DCA
1145 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1146 ixgbe_update_tx_dca(adapter
, tx_ring
);
1148 tx_ring
->total_bytes
= 0;
1149 tx_ring
->total_packets
= 0;
1150 ixgbe_clean_tx_irq(adapter
, tx_ring
);
1151 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1159 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1161 * @data: pointer to our q_vector struct for this interrupt vector
1163 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
1165 struct ixgbe_q_vector
*q_vector
= data
;
1166 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1167 struct ixgbe_ring
*rx_ring
;
1171 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1172 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1173 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1174 rx_ring
->total_bytes
= 0;
1175 rx_ring
->total_packets
= 0;
1176 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1180 if (!q_vector
->rxr_count
)
1183 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1184 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1185 /* disable interrupts on this vector only */
1186 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
1187 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, rx_ring
->v_idx
);
1188 else if (rx_ring
->v_idx
& 0xFFFFFFFF)
1189 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), rx_ring
->v_idx
);
1191 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1),
1192 (rx_ring
->v_idx
>> 32));
1193 napi_schedule(&q_vector
->napi
);
1198 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
1200 ixgbe_msix_clean_rx(irq
, data
);
1201 ixgbe_msix_clean_tx(irq
, data
);
1206 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1211 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1212 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1213 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1215 mask
= (qmask
& 0xFFFFFFFF);
1216 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(0), mask
);
1217 mask
= (qmask
>> 32);
1218 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(1), mask
);
1220 /* skip the flush */
1224 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1225 * @napi: napi struct with our devices info in it
1226 * @budget: amount of work driver is allowed to do this pass, in packets
1228 * This function is optimized for cleaning one queue only on a single
1231 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
1233 struct ixgbe_q_vector
*q_vector
=
1234 container_of(napi
, struct ixgbe_q_vector
, napi
);
1235 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1236 struct ixgbe_ring
*rx_ring
= NULL
;
1240 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1241 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1242 #ifdef CONFIG_IXGBE_DCA
1243 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1244 ixgbe_update_rx_dca(adapter
, rx_ring
);
1247 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1249 /* If all Rx work done, exit the polling mode */
1250 if (work_done
< budget
) {
1251 napi_complete(napi
);
1252 if (adapter
->itr_setting
& 1)
1253 ixgbe_set_itr_msix(q_vector
);
1254 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1255 ixgbe_irq_enable_queues(adapter
, rx_ring
->v_idx
);
1262 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1263 * @napi: napi struct with our devices info in it
1264 * @budget: amount of work driver is allowed to do this pass, in packets
1266 * This function will clean more than one rx queue associated with a
1269 static int ixgbe_clean_rxonly_many(struct napi_struct
*napi
, int budget
)
1271 struct ixgbe_q_vector
*q_vector
=
1272 container_of(napi
, struct ixgbe_q_vector
, napi
);
1273 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1274 struct ixgbe_ring
*rx_ring
= NULL
;
1275 int work_done
= 0, i
;
1277 u64 enable_mask
= 0;
1279 /* attempt to distribute budget to each queue fairly, but don't allow
1280 * the budget to go below 1 because we'll exit polling */
1281 budget
/= (q_vector
->rxr_count
?: 1);
1282 budget
= max(budget
, 1);
1283 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1284 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1285 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1286 #ifdef CONFIG_IXGBE_DCA
1287 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1288 ixgbe_update_rx_dca(adapter
, rx_ring
);
1290 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1291 enable_mask
|= rx_ring
->v_idx
;
1292 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1296 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1297 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1298 /* If all Rx work done, exit the polling mode */
1299 if (work_done
< budget
) {
1300 napi_complete(napi
);
1301 if (adapter
->itr_setting
& 1)
1302 ixgbe_set_itr_msix(q_vector
);
1303 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1304 ixgbe_irq_enable_queues(adapter
, enable_mask
);
1310 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
1313 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1315 set_bit(r_idx
, q_vector
->rxr_idx
);
1316 q_vector
->rxr_count
++;
1317 a
->rx_ring
[r_idx
].v_idx
= (u64
)1 << v_idx
;
1320 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
1323 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1325 set_bit(t_idx
, q_vector
->txr_idx
);
1326 q_vector
->txr_count
++;
1327 a
->tx_ring
[t_idx
].v_idx
= (u64
)1 << v_idx
;
1331 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1332 * @adapter: board private structure to initialize
1333 * @vectors: allotted vector count for descriptor rings
1335 * This function maps descriptor rings to the queue-specific vectors
1336 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1337 * one vector per ring/queue, but on a constrained vector budget, we
1338 * group the rings as "efficiently" as possible. You would add new
1339 * mapping configurations in here.
1341 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
,
1345 int rxr_idx
= 0, txr_idx
= 0;
1346 int rxr_remaining
= adapter
->num_rx_queues
;
1347 int txr_remaining
= adapter
->num_tx_queues
;
1352 /* No mapping required if MSI-X is disabled. */
1353 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
1357 * The ideal configuration...
1358 * We have enough vectors to map one per queue.
1360 if (vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
1361 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
1362 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
1364 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
1365 map_vector_to_txq(adapter
, v_start
, txr_idx
);
1371 * If we don't have enough vectors for a 1-to-1
1372 * mapping, we'll have to group them so there are
1373 * multiple queues per vector.
1375 /* Re-adjusting *qpv takes care of the remainder. */
1376 for (i
= v_start
; i
< vectors
; i
++) {
1377 rqpv
= DIV_ROUND_UP(rxr_remaining
, vectors
- i
);
1378 for (j
= 0; j
< rqpv
; j
++) {
1379 map_vector_to_rxq(adapter
, i
, rxr_idx
);
1384 for (i
= v_start
; i
< vectors
; i
++) {
1385 tqpv
= DIV_ROUND_UP(txr_remaining
, vectors
- i
);
1386 for (j
= 0; j
< tqpv
; j
++) {
1387 map_vector_to_txq(adapter
, i
, txr_idx
);
1398 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1399 * @adapter: board private structure
1401 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1402 * interrupts from the kernel.
1404 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
1406 struct net_device
*netdev
= adapter
->netdev
;
1407 irqreturn_t (*handler
)(int, void *);
1408 int i
, vector
, q_vectors
, err
;
1411 /* Decrement for Other and TCP Timer vectors */
1412 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1414 /* Map the Tx/Rx rings to the vectors we were allotted. */
1415 err
= ixgbe_map_rings_to_vectors(adapter
, q_vectors
);
1419 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1420 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1421 &ixgbe_msix_clean_many)
1422 for (vector
= 0; vector
< q_vectors
; vector
++) {
1423 handler
= SET_HANDLER(adapter
->q_vector
[vector
]);
1425 if(handler
== &ixgbe_msix_clean_rx
) {
1426 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1427 netdev
->name
, "rx", ri
++);
1429 else if(handler
== &ixgbe_msix_clean_tx
) {
1430 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1431 netdev
->name
, "tx", ti
++);
1434 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1435 netdev
->name
, "TxRx", vector
);
1437 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1438 handler
, 0, adapter
->name
[vector
],
1439 adapter
->q_vector
[vector
]);
1442 "request_irq failed for MSIX interrupt "
1443 "Error: %d\n", err
);
1444 goto free_queue_irqs
;
1448 sprintf(adapter
->name
[vector
], "%s:lsc", netdev
->name
);
1449 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1450 &ixgbe_msix_lsc
, 0, adapter
->name
[vector
], netdev
);
1453 "request_irq for msix_lsc failed: %d\n", err
);
1454 goto free_queue_irqs
;
1460 for (i
= vector
- 1; i
>= 0; i
--)
1461 free_irq(adapter
->msix_entries
[--vector
].vector
,
1462 adapter
->q_vector
[i
]);
1463 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
1464 pci_disable_msix(adapter
->pdev
);
1465 kfree(adapter
->msix_entries
);
1466 adapter
->msix_entries
= NULL
;
1471 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
1473 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1475 u32 new_itr
= q_vector
->eitr
;
1476 struct ixgbe_ring
*rx_ring
= &adapter
->rx_ring
[0];
1477 struct ixgbe_ring
*tx_ring
= &adapter
->tx_ring
[0];
1479 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1481 tx_ring
->total_packets
,
1482 tx_ring
->total_bytes
);
1483 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1485 rx_ring
->total_packets
,
1486 rx_ring
->total_bytes
);
1488 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1490 switch (current_itr
) {
1491 /* counts and packets in update_itr are dependent on these numbers */
1492 case lowest_latency
:
1496 new_itr
= 20000; /* aka hwitr = ~200 */
1505 if (new_itr
!= q_vector
->eitr
) {
1508 /* save the algorithm value here, not the smoothed one */
1509 q_vector
->eitr
= new_itr
;
1510 /* do an exponential smoothing */
1511 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1512 itr_reg
= EITR_INTS_PER_SEC_TO_REG(new_itr
);
1513 ixgbe_write_eitr(adapter
, 0, itr_reg
);
1520 * ixgbe_irq_enable - Enable default interrupt generation settings
1521 * @adapter: board private structure
1523 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
)
1527 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
1528 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
1529 mask
|= IXGBE_EIMS_GPI_SDP1
;
1530 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1531 mask
|= IXGBE_EIMS_ECC
;
1532 mask
|= IXGBE_EIMS_GPI_SDP1
;
1533 mask
|= IXGBE_EIMS_GPI_SDP2
;
1536 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1537 ixgbe_irq_enable_queues(adapter
, ~0);
1538 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1542 * ixgbe_intr - legacy mode Interrupt Handler
1543 * @irq: interrupt number
1544 * @data: pointer to a network interface device structure
1546 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
1548 struct net_device
*netdev
= data
;
1549 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1550 struct ixgbe_hw
*hw
= &adapter
->hw
;
1551 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1555 * Workaround for silicon errata. Mask the interrupts
1556 * before the read of EICR.
1558 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
1560 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1561 * therefore no explict interrupt disable is necessary */
1562 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
1564 /* shared interrupt alert!
1565 * make sure interrupts are enabled because the read will
1566 * have disabled interrupts due to EIAM */
1567 ixgbe_irq_enable(adapter
);
1568 return IRQ_NONE
; /* Not our interrupt */
1571 if (eicr
& IXGBE_EICR_LSC
)
1572 ixgbe_check_lsc(adapter
);
1574 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
1575 ixgbe_check_sfp_event(adapter
, eicr
);
1577 ixgbe_check_fan_failure(adapter
, eicr
);
1579 if (napi_schedule_prep(&(q_vector
->napi
))) {
1580 adapter
->tx_ring
[0].total_packets
= 0;
1581 adapter
->tx_ring
[0].total_bytes
= 0;
1582 adapter
->rx_ring
[0].total_packets
= 0;
1583 adapter
->rx_ring
[0].total_bytes
= 0;
1584 /* would disable interrupts here but EIAM disabled it */
1585 __napi_schedule(&(q_vector
->napi
));
1591 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
1593 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1595 for (i
= 0; i
< q_vectors
; i
++) {
1596 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
1597 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
1598 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
1599 q_vector
->rxr_count
= 0;
1600 q_vector
->txr_count
= 0;
1605 * ixgbe_request_irq - initialize interrupts
1606 * @adapter: board private structure
1608 * Attempts to configure interrupts using the best available
1609 * capabilities of the hardware and kernel.
1611 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
1613 struct net_device
*netdev
= adapter
->netdev
;
1616 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1617 err
= ixgbe_request_msix_irqs(adapter
);
1618 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
1619 err
= request_irq(adapter
->pdev
->irq
, &ixgbe_intr
, 0,
1620 netdev
->name
, netdev
);
1622 err
= request_irq(adapter
->pdev
->irq
, &ixgbe_intr
, IRQF_SHARED
,
1623 netdev
->name
, netdev
);
1627 DPRINTK(PROBE
, ERR
, "request_irq failed, Error %d\n", err
);
1632 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
1634 struct net_device
*netdev
= adapter
->netdev
;
1636 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1639 q_vectors
= adapter
->num_msix_vectors
;
1642 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
1645 for (; i
>= 0; i
--) {
1646 free_irq(adapter
->msix_entries
[i
].vector
,
1647 adapter
->q_vector
[i
]);
1650 ixgbe_reset_q_vectors(adapter
);
1652 free_irq(adapter
->pdev
->irq
, netdev
);
1657 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1658 * @adapter: board private structure
1660 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
1662 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1663 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
1665 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
1666 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
1667 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
1669 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1670 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1672 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
1673 synchronize_irq(adapter
->msix_entries
[i
].vector
);
1675 synchronize_irq(adapter
->pdev
->irq
);
1680 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1683 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
1685 struct ixgbe_hw
*hw
= &adapter
->hw
;
1687 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
1688 EITR_INTS_PER_SEC_TO_REG(adapter
->eitr_param
));
1690 ixgbe_set_ivar(adapter
, 0, 0, 0);
1691 ixgbe_set_ivar(adapter
, 1, 0, 0);
1693 map_vector_to_rxq(adapter
, 0, 0);
1694 map_vector_to_txq(adapter
, 0, 0);
1696 DPRINTK(HW
, INFO
, "Legacy interrupt IVAR setup done\n");
1700 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1701 * @adapter: board private structure
1703 * Configure the Tx unit of the MAC after a reset.
1705 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
1708 struct ixgbe_hw
*hw
= &adapter
->hw
;
1709 u32 i
, j
, tdlen
, txctrl
;
1711 /* Setup the HW Tx Head and Tail descriptor pointers */
1712 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1713 struct ixgbe_ring
*ring
= &adapter
->tx_ring
[i
];
1716 tdlen
= ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
1717 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(j
),
1718 (tdba
& DMA_BIT_MASK(32)));
1719 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(j
), (tdba
>> 32));
1720 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(j
), tdlen
);
1721 IXGBE_WRITE_REG(hw
, IXGBE_TDH(j
), 0);
1722 IXGBE_WRITE_REG(hw
, IXGBE_TDT(j
), 0);
1723 adapter
->tx_ring
[i
].head
= IXGBE_TDH(j
);
1724 adapter
->tx_ring
[i
].tail
= IXGBE_TDT(j
);
1725 /* Disable Tx Head Writeback RO bit, since this hoses
1726 * bookkeeping if things aren't delivered in order.
1728 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(j
));
1729 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
1730 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(j
), txctrl
);
1732 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1733 /* We enable 8 traffic classes, DCB only */
1734 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
1735 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, (IXGBE_MTQC_RT_ENA
|
1736 IXGBE_MTQC_8TC_8TQ
));
1740 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1742 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
, int index
)
1744 struct ixgbe_ring
*rx_ring
;
1749 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1750 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
1751 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
1753 queue0
= index
>> 4;
1754 else if (dcb_i
== 4)
1755 queue0
= index
>> 5;
1757 dev_err(&adapter
->pdev
->dev
, "Invalid DCB "
1760 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1761 struct ixgbe_ring_feature
*f
;
1763 rx_ring
= &adapter
->rx_ring
[queue0
];
1764 f
= &adapter
->ring_feature
[RING_F_FCOE
];
1765 if ((queue0
== 0) && (index
> rx_ring
->reg_idx
))
1766 queue0
= f
->mask
+ index
-
1767 rx_ring
->reg_idx
- 1;
1769 #endif /* IXGBE_FCOE */
1774 mask
= (unsigned long) adapter
->ring_feature
[RING_F_RSS
].mask
;
1775 queue0
= index
& mask
;
1776 index
= index
& mask
;
1779 rx_ring
= &adapter
->rx_ring
[queue0
];
1781 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(index
));
1783 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
1784 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
1786 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
1787 IXGBE_SRRCTL_BSIZEHDR_MASK
;
1789 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
1790 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1791 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
1793 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
1795 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
1797 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
1798 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
1799 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
1802 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(index
), srrctl
);
1806 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1807 * @adapter: board private structure
1809 * Configure the Rx unit of the MAC after a reset.
1811 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
1814 struct ixgbe_hw
*hw
= &adapter
->hw
;
1815 struct net_device
*netdev
= adapter
->netdev
;
1816 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
1818 u32 rdlen
, rxctrl
, rxcsum
;
1819 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1820 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1821 0x6A3E67EA, 0x14364D17, 0x3BED200D};
1823 u32 reta
= 0, mrqc
= 0;
1828 /* Decide whether to use packet split mode or not */
1829 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
1832 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
1833 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
1834 #endif /* IXGBE_FCOE */
1836 /* Set the RX buffer length according to the mode */
1837 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
1838 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
1839 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1840 /* PSRTYPE must be initialized in 82599 */
1841 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
1842 IXGBE_PSRTYPE_UDPHDR
|
1843 IXGBE_PSRTYPE_IPV4HDR
|
1844 IXGBE_PSRTYPE_IPV6HDR
|
1845 IXGBE_PSRTYPE_L2HDR
;
1846 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(0), psrtype
);
1849 if (!(adapter
->flags
& IXGBE_FLAG_RSC_ENABLED
) &&
1850 (netdev
->mtu
<= ETH_DATA_LEN
))
1851 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
1853 rx_buf_len
= ALIGN(max_frame
, 1024);
1856 fctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_FCTRL
);
1857 fctrl
|= IXGBE_FCTRL_BAM
;
1858 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
1859 fctrl
|= IXGBE_FCTRL_PMCF
;
1860 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_FCTRL
, fctrl
);
1862 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
1863 if (adapter
->netdev
->mtu
<= ETH_DATA_LEN
)
1864 hlreg0
&= ~IXGBE_HLREG0_JUMBOEN
;
1866 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
1868 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
1869 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
1871 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
1873 rdlen
= adapter
->rx_ring
[0].count
* sizeof(union ixgbe_adv_rx_desc
);
1874 /* disable receives while setting up the descriptors */
1875 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
1876 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
1878 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1879 * the Base and Length of the Rx Descriptor Ring */
1880 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
1881 rdba
= adapter
->rx_ring
[i
].dma
;
1882 j
= adapter
->rx_ring
[i
].reg_idx
;
1883 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(j
), (rdba
& DMA_BIT_MASK(32)));
1884 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(j
), (rdba
>> 32));
1885 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(j
), rdlen
);
1886 IXGBE_WRITE_REG(hw
, IXGBE_RDH(j
), 0);
1887 IXGBE_WRITE_REG(hw
, IXGBE_RDT(j
), 0);
1888 adapter
->rx_ring
[i
].head
= IXGBE_RDH(j
);
1889 adapter
->rx_ring
[i
].tail
= IXGBE_RDT(j
);
1890 adapter
->rx_ring
[i
].rx_buf_len
= rx_buf_len
;
1893 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1894 struct ixgbe_ring_feature
*f
;
1895 f
= &adapter
->ring_feature
[RING_F_FCOE
];
1896 if ((rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
) &&
1897 (i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
))
1898 adapter
->rx_ring
[i
].rx_buf_len
=
1899 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
1902 #endif /* IXGBE_FCOE */
1903 ixgbe_configure_srrctl(adapter
, j
);
1906 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
1908 * For VMDq support of different descriptor types or
1909 * buffer sizes through the use of multiple SRRCTL
1910 * registers, RDRXCTL.MVMEN must be set to 1
1912 * also, the manual doesn't mention it clearly but DCA hints
1913 * will only use queue 0's tags unless this bit is set. Side
1914 * effects of setting this bit are only that SRRCTL must be
1915 * fully programmed [0..15]
1917 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
1918 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
1919 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
1922 /* Program MRQC for the distribution of queues */
1923 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1924 int mask
= adapter
->flags
& (
1925 IXGBE_FLAG_RSS_ENABLED
1926 | IXGBE_FLAG_DCB_ENABLED
1930 case (IXGBE_FLAG_RSS_ENABLED
):
1931 mrqc
= IXGBE_MRQC_RSSEN
;
1933 case (IXGBE_FLAG_DCB_ENABLED
):
1934 mrqc
= IXGBE_MRQC_RT8TCEN
;
1940 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
1941 /* Fill out redirection table */
1942 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
1943 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
1945 /* reta = 4-byte sliding window of
1946 * 0x00..(indices-1)(indices-1)00..etc. */
1947 reta
= (reta
<< 8) | (j
* 0x11);
1949 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
1952 /* Fill out hash function seeds */
1953 for (i
= 0; i
< 10; i
++)
1954 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
1956 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1957 mrqc
|= IXGBE_MRQC_RSSEN
;
1958 /* Perform hash on these packet types */
1959 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
1960 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1961 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1962 | IXGBE_MRQC_RSS_FIELD_IPV6
1963 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1964 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
;
1966 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
1968 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
1970 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
||
1971 adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
) {
1972 /* Disable indicating checksum in descriptor, enables
1974 rxcsum
|= IXGBE_RXCSUM_PCSD
;
1976 if (!(rxcsum
& IXGBE_RXCSUM_PCSD
)) {
1977 /* Enable IPv4 payload checksum for UDP fragments
1978 * if PCSD is not set */
1979 rxcsum
|= IXGBE_RXCSUM_IPPCSE
;
1982 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
1984 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1985 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
1986 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
1987 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
1988 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
1991 if (adapter
->flags
& IXGBE_FLAG_RSC_ENABLED
) {
1992 /* Enable 82599 HW-RSC */
1993 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
1994 j
= adapter
->rx_ring
[i
].reg_idx
;
1995 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(j
));
1996 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
1998 * if packet split is enabled we can only support up
1999 * to max frags + 1 descriptors.
2001 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
2002 #if (MAX_SKB_FRAGS < 3)
2003 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2004 #elif (MAX_SKB_FRAGS < 7)
2005 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2006 #elif (MAX_SKB_FRAGS < 15)
2007 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2009 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2012 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2013 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(j
), rscctrl
);
2015 /* Disable RSC for ACK packets */
2016 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
2017 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
2021 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
2023 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2024 struct ixgbe_hw
*hw
= &adapter
->hw
;
2026 /* add VID to filter table */
2027 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, 0, true);
2030 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
2032 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2033 struct ixgbe_hw
*hw
= &adapter
->hw
;
2035 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2036 ixgbe_irq_disable(adapter
);
2038 vlan_group_set_device(adapter
->vlgrp
, vid
, NULL
);
2040 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2041 ixgbe_irq_enable(adapter
);
2043 /* remove VID from filter table */
2044 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, 0, false);
2047 static void ixgbe_vlan_rx_register(struct net_device
*netdev
,
2048 struct vlan_group
*grp
)
2050 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2054 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2055 ixgbe_irq_disable(adapter
);
2056 adapter
->vlgrp
= grp
;
2059 * For a DCB driver, always enable VLAN tag stripping so we can
2060 * still receive traffic from a DCB-enabled host even if we're
2063 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_VLNCTRL
);
2064 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2065 ctrl
|= IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
;
2066 ctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2067 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_VLNCTRL
, ctrl
);
2068 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
2069 ctrl
|= IXGBE_VLNCTRL_VFE
;
2070 /* enable VLAN tag insert/strip */
2071 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_VLNCTRL
);
2072 ctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2073 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_VLNCTRL
, ctrl
);
2074 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2075 j
= adapter
->rx_ring
[i
].reg_idx
;
2076 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_RXDCTL(j
));
2077 ctrl
|= IXGBE_RXDCTL_VME
;
2078 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_RXDCTL(j
), ctrl
);
2081 ixgbe_vlan_rx_add_vid(netdev
, 0);
2083 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2084 ixgbe_irq_enable(adapter
);
2087 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
2089 ixgbe_vlan_rx_register(adapter
->netdev
, adapter
->vlgrp
);
2091 if (adapter
->vlgrp
) {
2093 for (vid
= 0; vid
< VLAN_GROUP_ARRAY_LEN
; vid
++) {
2094 if (!vlan_group_get_device(adapter
->vlgrp
, vid
))
2096 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
2101 static u8
*ixgbe_addr_list_itr(struct ixgbe_hw
*hw
, u8
**mc_addr_ptr
, u32
*vmdq
)
2103 struct dev_mc_list
*mc_ptr
;
2104 u8
*addr
= *mc_addr_ptr
;
2107 mc_ptr
= container_of(addr
, struct dev_mc_list
, dmi_addr
[0]);
2109 *mc_addr_ptr
= mc_ptr
->next
->dmi_addr
;
2111 *mc_addr_ptr
= NULL
;
2117 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2118 * @netdev: network interface device structure
2120 * The set_rx_method entry point is called whenever the unicast/multicast
2121 * address list or the network interface flags are updated. This routine is
2122 * responsible for configuring the hardware for proper unicast, multicast and
2125 static void ixgbe_set_rx_mode(struct net_device
*netdev
)
2127 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2128 struct ixgbe_hw
*hw
= &adapter
->hw
;
2130 u8
*addr_list
= NULL
;
2133 /* Check for Promiscuous and All Multicast modes */
2135 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
2136 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2138 if (netdev
->flags
& IFF_PROMISC
) {
2139 hw
->addr_ctrl
.user_set_promisc
= 1;
2140 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2141 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
2143 if (netdev
->flags
& IFF_ALLMULTI
) {
2144 fctrl
|= IXGBE_FCTRL_MPE
;
2145 fctrl
&= ~IXGBE_FCTRL_UPE
;
2147 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2149 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2150 hw
->addr_ctrl
.user_set_promisc
= 0;
2153 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
2154 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2156 /* reprogram secondary unicast list */
2157 addr_count
= netdev
->uc_count
;
2159 addr_list
= netdev
->uc_list
->dmi_addr
;
2160 hw
->mac
.ops
.update_uc_addr_list(hw
, addr_list
, addr_count
,
2161 ixgbe_addr_list_itr
);
2163 /* reprogram multicast list */
2164 addr_count
= netdev
->mc_count
;
2166 addr_list
= netdev
->mc_list
->dmi_addr
;
2167 hw
->mac
.ops
.update_mc_addr_list(hw
, addr_list
, addr_count
,
2168 ixgbe_addr_list_itr
);
2171 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
2174 struct ixgbe_q_vector
*q_vector
;
2175 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2177 /* legacy and MSI only use one vector */
2178 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2181 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2182 struct napi_struct
*napi
;
2183 q_vector
= adapter
->q_vector
[q_idx
];
2184 if (!q_vector
->rxr_count
)
2186 napi
= &q_vector
->napi
;
2187 if ((adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) &&
2188 (q_vector
->rxr_count
> 1))
2189 napi
->poll
= &ixgbe_clean_rxonly_many
;
2195 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
2198 struct ixgbe_q_vector
*q_vector
;
2199 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2201 /* legacy and MSI only use one vector */
2202 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2205 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2206 q_vector
= adapter
->q_vector
[q_idx
];
2207 if (!q_vector
->rxr_count
)
2209 napi_disable(&q_vector
->napi
);
2213 #ifdef CONFIG_IXGBE_DCB
2215 * ixgbe_configure_dcb - Configure DCB hardware
2216 * @adapter: ixgbe adapter struct
2218 * This is called by the driver on open to configure the DCB hardware.
2219 * This is also called by the gennetlink interface when reconfiguring
2222 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
2224 struct ixgbe_hw
*hw
= &adapter
->hw
;
2225 u32 txdctl
, vlnctrl
;
2228 ixgbe_dcb_check_config(&adapter
->dcb_cfg
);
2229 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_TX_CONFIG
);
2230 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_RX_CONFIG
);
2232 /* reconfigure the hardware */
2233 ixgbe_dcb_hw_config(&adapter
->hw
, &adapter
->dcb_cfg
);
2235 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2236 j
= adapter
->tx_ring
[i
].reg_idx
;
2237 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2238 /* PThresh workaround for Tx hang with DFP enabled. */
2240 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2242 /* Enable VLAN tag insert/strip */
2243 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2244 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2245 vlnctrl
|= IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
;
2246 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2247 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2248 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2249 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2250 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2251 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2252 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2253 j
= adapter
->rx_ring
[i
].reg_idx
;
2254 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2255 vlnctrl
|= IXGBE_RXDCTL_VME
;
2256 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2259 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
2263 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
2265 struct net_device
*netdev
= adapter
->netdev
;
2268 ixgbe_set_rx_mode(netdev
);
2270 ixgbe_restore_vlan(adapter
);
2271 #ifdef CONFIG_IXGBE_DCB
2272 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2273 netif_set_gso_max_size(netdev
, 32768);
2274 ixgbe_configure_dcb(adapter
);
2276 netif_set_gso_max_size(netdev
, 65536);
2279 netif_set_gso_max_size(netdev
, 65536);
2283 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
2284 ixgbe_configure_fcoe(adapter
);
2286 #endif /* IXGBE_FCOE */
2287 ixgbe_configure_tx(adapter
);
2288 ixgbe_configure_rx(adapter
);
2289 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2290 ixgbe_alloc_rx_buffers(adapter
, &adapter
->rx_ring
[i
],
2291 (adapter
->rx_ring
[i
].count
- 1));
2294 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
2296 switch (hw
->phy
.type
) {
2297 case ixgbe_phy_sfp_avago
:
2298 case ixgbe_phy_sfp_ftl
:
2299 case ixgbe_phy_sfp_intel
:
2300 case ixgbe_phy_sfp_unknown
:
2301 case ixgbe_phy_tw_tyco
:
2302 case ixgbe_phy_tw_unknown
:
2310 * ixgbe_sfp_link_config - set up SFP+ link
2311 * @adapter: pointer to private adapter struct
2313 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
2315 struct ixgbe_hw
*hw
= &adapter
->hw
;
2317 if (hw
->phy
.multispeed_fiber
) {
2319 * In multispeed fiber setups, the device may not have
2320 * had a physical connection when the driver loaded.
2321 * If that's the case, the initial link configuration
2322 * couldn't get the MAC into 10G or 1G mode, so we'll
2323 * never have a link status change interrupt fire.
2324 * We need to try and force an autonegotiation
2325 * session, then bring up link.
2327 hw
->mac
.ops
.setup_sfp(hw
);
2328 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
2329 schedule_work(&adapter
->multispeed_fiber_task
);
2332 * Direct Attach Cu and non-multispeed fiber modules
2333 * still need to be configured properly prior to
2336 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
2337 schedule_work(&adapter
->sfp_config_module_task
);
2342 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2343 * @hw: pointer to private hardware struct
2345 * Returns 0 on success, negative on failure
2347 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
2350 bool link_up
= false;
2351 u32 ret
= IXGBE_ERR_LINK_SETUP
;
2353 if (hw
->mac
.ops
.check_link
)
2354 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
2359 if (hw
->mac
.ops
.get_link_capabilities
)
2360 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
,
2365 if (hw
->mac
.ops
.setup_link_speed
)
2366 ret
= hw
->mac
.ops
.setup_link_speed(hw
, autoneg
, true, link_up
);
2371 #define IXGBE_MAX_RX_DESC_POLL 10
2372 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
2375 int j
= adapter
->rx_ring
[rxr
].reg_idx
;
2378 for (k
= 0; k
< IXGBE_MAX_RX_DESC_POLL
; k
++) {
2379 if (IXGBE_READ_REG(&adapter
->hw
,
2380 IXGBE_RXDCTL(j
)) & IXGBE_RXDCTL_ENABLE
)
2385 if (k
>= IXGBE_MAX_RX_DESC_POLL
) {
2386 DPRINTK(DRV
, ERR
, "RXDCTL.ENABLE on Rx queue %d "
2387 "not set within the polling period\n", rxr
);
2389 ixgbe_release_rx_desc(&adapter
->hw
, &adapter
->rx_ring
[rxr
],
2390 (adapter
->rx_ring
[rxr
].count
- 1));
2393 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
2395 struct net_device
*netdev
= adapter
->netdev
;
2396 struct ixgbe_hw
*hw
= &adapter
->hw
;
2398 int num_rx_rings
= adapter
->num_rx_queues
;
2400 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2401 u32 txdctl
, rxdctl
, mhadd
;
2405 ixgbe_get_hw_control(adapter
);
2407 if ((adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) ||
2408 (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
)) {
2409 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2410 gpie
= (IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_EIAME
|
2411 IXGBE_GPIE_PBA_SUPPORT
| IXGBE_GPIE_OCD
);
2416 /* XXX: to interrupt immediately for EICS writes, enable this */
2417 /* gpie |= IXGBE_GPIE_EIMEN; */
2418 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2421 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
2422 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2423 * specifically only auto mask tx and rx interrupts */
2424 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
2427 /* Enable fan failure interrupt if media type is copper */
2428 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
2429 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2430 gpie
|= IXGBE_SDP1_GPIEN
;
2431 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2434 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2435 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2436 gpie
|= IXGBE_SDP1_GPIEN
;
2437 gpie
|= IXGBE_SDP2_GPIEN
;
2438 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2442 /* adjust max frame to be able to do baby jumbo for FCoE */
2443 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
2444 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
2445 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2447 #endif /* IXGBE_FCOE */
2448 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
2449 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
2450 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
2451 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
2453 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
2456 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2457 j
= adapter
->tx_ring
[i
].reg_idx
;
2458 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2459 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2460 txdctl
|= (8 << 16);
2461 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2464 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2465 /* DMATXCTL.EN must be set after all Tx queue config is done */
2466 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2467 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2468 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2470 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2471 j
= adapter
->tx_ring
[i
].reg_idx
;
2472 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2473 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2474 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2477 for (i
= 0; i
< num_rx_rings
; i
++) {
2478 j
= adapter
->rx_ring
[i
].reg_idx
;
2479 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2480 /* enable PTHRESH=32 descriptors (half the internal cache)
2481 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2482 * this also removes a pesky rx_no_buffer_count increment */
2484 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
2485 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), rxdctl
);
2486 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2487 ixgbe_rx_desc_queue_enable(adapter
, i
);
2489 /* enable all receives */
2490 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2491 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2492 rxdctl
|= (IXGBE_RXCTRL_DMBYPS
| IXGBE_RXCTRL_RXEN
);
2494 rxdctl
|= IXGBE_RXCTRL_RXEN
;
2495 hw
->mac
.ops
.enable_rx_dma(hw
, rxdctl
);
2497 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
2498 ixgbe_configure_msix(adapter
);
2500 ixgbe_configure_msi_and_legacy(adapter
);
2502 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
2503 ixgbe_napi_enable_all(adapter
);
2505 /* clear any pending interrupts, may auto mask */
2506 IXGBE_READ_REG(hw
, IXGBE_EICR
);
2508 ixgbe_irq_enable(adapter
);
2511 * If this adapter has a fan, check to see if we had a failure
2512 * before we enabled the interrupt.
2514 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
2515 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
2516 if (esdp
& IXGBE_ESDP_SDP1
)
2518 "Fan has stopped, replace the adapter\n");
2522 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2523 * arrived before interrupts were enabled. We need to kick off
2524 * the SFP+ module setup first, then try to bring up link.
2525 * If we're not hot-pluggable SFP+, we just need to configure link
2528 err
= hw
->phy
.ops
.identify(hw
);
2529 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
2530 DPRINTK(PROBE
, ERR
, "PHY not supported on this NIC %d\n", err
);
2531 ixgbe_down(adapter
);
2535 if (ixgbe_is_sfp(hw
)) {
2536 ixgbe_sfp_link_config(adapter
);
2538 err
= ixgbe_non_sfp_link_config(hw
);
2540 DPRINTK(PROBE
, ERR
, "link_config FAILED %d\n", err
);
2543 /* enable transmits */
2544 netif_tx_start_all_queues(netdev
);
2546 /* bring the link up in the watchdog, this could race with our first
2547 * link up interrupt but shouldn't be a problem */
2548 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
2549 adapter
->link_check_timeout
= jiffies
;
2550 mod_timer(&adapter
->watchdog_timer
, jiffies
);
2554 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
2556 WARN_ON(in_interrupt());
2557 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
2559 ixgbe_down(adapter
);
2561 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
2564 int ixgbe_up(struct ixgbe_adapter
*adapter
)
2566 /* hardware has been reset, we need to reload some things */
2567 ixgbe_configure(adapter
);
2569 return ixgbe_up_complete(adapter
);
2572 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
2574 struct ixgbe_hw
*hw
= &adapter
->hw
;
2575 if (hw
->mac
.ops
.init_hw(hw
))
2576 dev_err(&adapter
->pdev
->dev
, "Hardware Error\n");
2578 /* reprogram the RAR[0] in case user changed it. */
2579 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
2584 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2585 * @adapter: board private structure
2586 * @rx_ring: ring to free buffers from
2588 static void ixgbe_clean_rx_ring(struct ixgbe_adapter
*adapter
,
2589 struct ixgbe_ring
*rx_ring
)
2591 struct pci_dev
*pdev
= adapter
->pdev
;
2595 /* Free all the Rx ring sk_buffs */
2597 for (i
= 0; i
< rx_ring
->count
; i
++) {
2598 struct ixgbe_rx_buffer
*rx_buffer_info
;
2600 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
2601 if (rx_buffer_info
->dma
) {
2602 pci_unmap_single(pdev
, rx_buffer_info
->dma
,
2603 rx_ring
->rx_buf_len
,
2604 PCI_DMA_FROMDEVICE
);
2605 rx_buffer_info
->dma
= 0;
2607 if (rx_buffer_info
->skb
) {
2608 struct sk_buff
*skb
= rx_buffer_info
->skb
;
2609 rx_buffer_info
->skb
= NULL
;
2611 struct sk_buff
*this = skb
;
2613 dev_kfree_skb(this);
2616 if (!rx_buffer_info
->page
)
2618 pci_unmap_page(pdev
, rx_buffer_info
->page_dma
, PAGE_SIZE
/ 2,
2619 PCI_DMA_FROMDEVICE
);
2620 rx_buffer_info
->page_dma
= 0;
2621 put_page(rx_buffer_info
->page
);
2622 rx_buffer_info
->page
= NULL
;
2623 rx_buffer_info
->page_offset
= 0;
2626 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
2627 memset(rx_ring
->rx_buffer_info
, 0, size
);
2629 /* Zero out the descriptor ring */
2630 memset(rx_ring
->desc
, 0, rx_ring
->size
);
2632 rx_ring
->next_to_clean
= 0;
2633 rx_ring
->next_to_use
= 0;
2636 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->head
);
2638 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
2642 * ixgbe_clean_tx_ring - Free Tx Buffers
2643 * @adapter: board private structure
2644 * @tx_ring: ring to be cleaned
2646 static void ixgbe_clean_tx_ring(struct ixgbe_adapter
*adapter
,
2647 struct ixgbe_ring
*tx_ring
)
2649 struct ixgbe_tx_buffer
*tx_buffer_info
;
2653 /* Free all the Tx ring sk_buffs */
2655 for (i
= 0; i
< tx_ring
->count
; i
++) {
2656 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
2657 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
2660 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
2661 memset(tx_ring
->tx_buffer_info
, 0, size
);
2663 /* Zero out the descriptor ring */
2664 memset(tx_ring
->desc
, 0, tx_ring
->size
);
2666 tx_ring
->next_to_use
= 0;
2667 tx_ring
->next_to_clean
= 0;
2670 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->head
);
2672 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
2676 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2677 * @adapter: board private structure
2679 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
2683 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2684 ixgbe_clean_rx_ring(adapter
, &adapter
->rx_ring
[i
]);
2688 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2689 * @adapter: board private structure
2691 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
2695 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2696 ixgbe_clean_tx_ring(adapter
, &adapter
->tx_ring
[i
]);
2699 void ixgbe_down(struct ixgbe_adapter
*adapter
)
2701 struct net_device
*netdev
= adapter
->netdev
;
2702 struct ixgbe_hw
*hw
= &adapter
->hw
;
2707 /* signal that we are down to the interrupt handler */
2708 set_bit(__IXGBE_DOWN
, &adapter
->state
);
2710 /* disable receives */
2711 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2712 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
2714 netif_tx_disable(netdev
);
2716 IXGBE_WRITE_FLUSH(hw
);
2719 netif_tx_stop_all_queues(netdev
);
2721 ixgbe_irq_disable(adapter
);
2723 ixgbe_napi_disable_all(adapter
);
2725 del_timer_sync(&adapter
->watchdog_timer
);
2726 cancel_work_sync(&adapter
->watchdog_task
);
2728 /* disable transmits in the hardware now that interrupts are off */
2729 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2730 j
= adapter
->tx_ring
[i
].reg_idx
;
2731 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2732 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
),
2733 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
2735 /* Disable the Tx DMA engine on 82599 */
2736 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2737 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
2738 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
2739 ~IXGBE_DMATXCTL_TE
));
2741 netif_carrier_off(netdev
);
2743 #ifdef CONFIG_IXGBE_DCA
2744 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
2745 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
2746 dca_remove_requester(&adapter
->pdev
->dev
);
2750 if (!pci_channel_offline(adapter
->pdev
))
2751 ixgbe_reset(adapter
);
2752 ixgbe_clean_all_tx_rings(adapter
);
2753 ixgbe_clean_all_rx_rings(adapter
);
2755 #ifdef CONFIG_IXGBE_DCA
2756 /* since we reset the hardware DCA settings were cleared */
2757 if (dca_add_requester(&adapter
->pdev
->dev
) == 0) {
2758 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
2759 /* always use CB2 mode, difference is masked
2760 * in the CB driver */
2761 IXGBE_WRITE_REG(hw
, IXGBE_DCA_CTRL
, 2);
2762 ixgbe_setup_dca(adapter
);
2768 * ixgbe_poll - NAPI Rx polling callback
2769 * @napi: structure for representing this polling device
2770 * @budget: how many packets driver is allowed to clean
2772 * This function is used for legacy and MSI, NAPI mode
2774 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
2776 struct ixgbe_q_vector
*q_vector
=
2777 container_of(napi
, struct ixgbe_q_vector
, napi
);
2778 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2779 int tx_clean_complete
, work_done
= 0;
2781 #ifdef CONFIG_IXGBE_DCA
2782 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
2783 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
);
2784 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
);
2788 tx_clean_complete
= ixgbe_clean_tx_irq(adapter
, adapter
->tx_ring
);
2789 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
, &work_done
, budget
);
2791 if (!tx_clean_complete
)
2794 /* If budget not fully consumed, exit the polling mode */
2795 if (work_done
< budget
) {
2796 napi_complete(napi
);
2797 if (adapter
->itr_setting
& 1)
2798 ixgbe_set_itr(adapter
);
2799 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2800 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
2806 * ixgbe_tx_timeout - Respond to a Tx Hang
2807 * @netdev: network interface device structure
2809 static void ixgbe_tx_timeout(struct net_device
*netdev
)
2811 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2813 /* Do the reset outside of interrupt context */
2814 schedule_work(&adapter
->reset_task
);
2817 static void ixgbe_reset_task(struct work_struct
*work
)
2819 struct ixgbe_adapter
*adapter
;
2820 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
2822 /* If we're already down or resetting, just bail */
2823 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
2824 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
2827 adapter
->tx_timeout_count
++;
2829 ixgbe_reinit_locked(adapter
);
2832 #ifdef CONFIG_IXGBE_DCB
2833 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
2837 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2838 adapter
->ring_feature
[RING_F_DCB
].mask
= 0x7 << 3;
2839 adapter
->num_rx_queues
=
2840 adapter
->ring_feature
[RING_F_DCB
].indices
;
2841 adapter
->num_tx_queues
=
2842 adapter
->ring_feature
[RING_F_DCB
].indices
;
2853 * ixgbe_set_rss_queues: Allocate queues for RSS
2854 * @adapter: board private structure to initialize
2856 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2857 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2860 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
2864 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
2865 adapter
->ring_feature
[RING_F_RSS
].mask
= 0xF;
2866 adapter
->num_rx_queues
=
2867 adapter
->ring_feature
[RING_F_RSS
].indices
;
2868 adapter
->num_tx_queues
=
2869 adapter
->ring_feature
[RING_F_RSS
].indices
;
2880 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
2881 * @adapter: board private structure to initialize
2883 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
2884 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
2885 * rx queues out of the max number of rx queues, instead, it is used as the
2886 * index of the first rx queue used by FCoE.
2889 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
2892 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
2894 f
->indices
= min((int)num_online_cpus(), f
->indices
);
2895 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
2896 #ifdef CONFIG_IXGBE_DCB
2897 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2898 DPRINTK(PROBE
, INFO
, "FCOE enabled with DCB \n");
2899 ixgbe_set_dcb_queues(adapter
);
2902 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
2903 DPRINTK(PROBE
, INFO
, "FCOE enabled with RSS \n");
2904 ixgbe_set_rss_queues(adapter
);
2906 /* adding FCoE rx rings to the end */
2907 f
->mask
= adapter
->num_rx_queues
;
2908 adapter
->num_rx_queues
+= f
->indices
;
2909 if (adapter
->num_tx_queues
== 0)
2910 adapter
->num_tx_queues
= f
->indices
;
2918 #endif /* IXGBE_FCOE */
2920 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2921 * @adapter: board private structure to initialize
2923 * This is the top level queue allocation routine. The order here is very
2924 * important, starting with the "most" number of features turned on at once,
2925 * and ending with the smallest set of features. This way large combinations
2926 * can be allocated if they're turned on, and smaller combinations are the
2927 * fallthrough conditions.
2930 static void ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
2933 if (ixgbe_set_fcoe_queues(adapter
))
2936 #endif /* IXGBE_FCOE */
2937 #ifdef CONFIG_IXGBE_DCB
2938 if (ixgbe_set_dcb_queues(adapter
))
2942 if (ixgbe_set_rss_queues(adapter
))
2945 /* fallback to base case */
2946 adapter
->num_rx_queues
= 1;
2947 adapter
->num_tx_queues
= 1;
2950 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2951 adapter
->netdev
->real_num_tx_queues
= adapter
->num_tx_queues
;
2954 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
2957 int err
, vector_threshold
;
2959 /* We'll want at least 3 (vector_threshold):
2962 * 3) Other (Link Status Change, etc.)
2963 * 4) TCP Timer (optional)
2965 vector_threshold
= MIN_MSIX_COUNT
;
2967 /* The more we get, the more we will assign to Tx/Rx Cleanup
2968 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2969 * Right now, we simply care about how many we'll get; we'll
2970 * set them up later while requesting irq's.
2972 while (vectors
>= vector_threshold
) {
2973 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
2975 if (!err
) /* Success in acquiring all requested vectors. */
2978 vectors
= 0; /* Nasty failure, quit now */
2979 else /* err == number of vectors we should try again with */
2983 if (vectors
< vector_threshold
) {
2984 /* Can't allocate enough MSI-X interrupts? Oh well.
2985 * This just means we'll go with either a single MSI
2986 * vector or fall back to legacy interrupts.
2988 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI-X interrupts\n");
2989 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2990 kfree(adapter
->msix_entries
);
2991 adapter
->msix_entries
= NULL
;
2993 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
2995 * Adjust for only the vectors we'll use, which is minimum
2996 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2997 * vectors we were allocated.
2999 adapter
->num_msix_vectors
= min(vectors
,
3000 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
3005 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3006 * @adapter: board private structure to initialize
3008 * Cache the descriptor ring offsets for RSS to the assigned rings.
3011 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
3016 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3017 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3018 adapter
->rx_ring
[i
].reg_idx
= i
;
3019 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3020 adapter
->tx_ring
[i
].reg_idx
= i
;
3029 #ifdef CONFIG_IXGBE_DCB
3031 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3032 * @adapter: board private structure to initialize
3034 * Cache the descriptor ring offsets for DCB to the assigned rings.
3037 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
3041 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
3043 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3044 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
3045 /* the number of queues is assumed to be symmetric */
3046 for (i
= 0; i
< dcb_i
; i
++) {
3047 adapter
->rx_ring
[i
].reg_idx
= i
<< 3;
3048 adapter
->tx_ring
[i
].reg_idx
= i
<< 2;
3051 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
3054 * Tx TC0 starts at: descriptor queue 0
3055 * Tx TC1 starts at: descriptor queue 32
3056 * Tx TC2 starts at: descriptor queue 64
3057 * Tx TC3 starts at: descriptor queue 80
3058 * Tx TC4 starts at: descriptor queue 96
3059 * Tx TC5 starts at: descriptor queue 104
3060 * Tx TC6 starts at: descriptor queue 112
3061 * Tx TC7 starts at: descriptor queue 120
3063 * Rx TC0-TC7 are offset by 16 queues each
3065 for (i
= 0; i
< 3; i
++) {
3066 adapter
->tx_ring
[i
].reg_idx
= i
<< 5;
3067 adapter
->rx_ring
[i
].reg_idx
= i
<< 4;
3069 for ( ; i
< 5; i
++) {
3070 adapter
->tx_ring
[i
].reg_idx
=
3072 adapter
->rx_ring
[i
].reg_idx
= i
<< 4;
3074 for ( ; i
< dcb_i
; i
++) {
3075 adapter
->tx_ring
[i
].reg_idx
=
3077 adapter
->rx_ring
[i
].reg_idx
= i
<< 4;
3081 } else if (dcb_i
== 4) {
3083 * Tx TC0 starts at: descriptor queue 0
3084 * Tx TC1 starts at: descriptor queue 64
3085 * Tx TC2 starts at: descriptor queue 96
3086 * Tx TC3 starts at: descriptor queue 112
3088 * Rx TC0-TC3 are offset by 32 queues each
3090 adapter
->tx_ring
[0].reg_idx
= 0;
3091 adapter
->tx_ring
[1].reg_idx
= 64;
3092 adapter
->tx_ring
[2].reg_idx
= 96;
3093 adapter
->tx_ring
[3].reg_idx
= 112;
3094 for (i
= 0 ; i
< dcb_i
; i
++)
3095 adapter
->rx_ring
[i
].reg_idx
= i
<< 5;
3114 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3115 * @adapter: board private structure to initialize
3117 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3120 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
3124 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3126 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3127 #ifdef CONFIG_IXGBE_DCB
3128 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3129 ixgbe_cache_ring_dcb(adapter
);
3130 fcoe_i
= adapter
->rx_ring
[0].reg_idx
+ 1;
3132 #endif /* CONFIG_IXGBE_DCB */
3133 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3134 ixgbe_cache_ring_rss(adapter
);
3137 for (i
= 0; i
< f
->indices
; i
++, fcoe_i
++)
3138 adapter
->rx_ring
[f
->mask
+ i
].reg_idx
= fcoe_i
;
3144 #endif /* IXGBE_FCOE */
3146 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3147 * @adapter: board private structure to initialize
3149 * Once we know the feature-set enabled for the device, we'll cache
3150 * the register offset the descriptor ring is assigned to.
3152 * Note, the order the various feature calls is important. It must start with
3153 * the "most" features enabled at the same time, then trickle down to the
3154 * least amount of features turned on at once.
3156 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
3158 /* start with default case */
3159 adapter
->rx_ring
[0].reg_idx
= 0;
3160 adapter
->tx_ring
[0].reg_idx
= 0;
3163 if (ixgbe_cache_ring_fcoe(adapter
))
3166 #endif /* IXGBE_FCOE */
3167 #ifdef CONFIG_IXGBE_DCB
3168 if (ixgbe_cache_ring_dcb(adapter
))
3172 if (ixgbe_cache_ring_rss(adapter
))
3177 * ixgbe_alloc_queues - Allocate memory for all rings
3178 * @adapter: board private structure to initialize
3180 * We allocate one ring per queue at run-time since we don't know the
3181 * number of queues at compile-time. The polling_netdev array is
3182 * intended for Multiqueue, but should work fine with a single queue.
3184 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
3188 adapter
->tx_ring
= kcalloc(adapter
->num_tx_queues
,
3189 sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3190 if (!adapter
->tx_ring
)
3191 goto err_tx_ring_allocation
;
3193 adapter
->rx_ring
= kcalloc(adapter
->num_rx_queues
,
3194 sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3195 if (!adapter
->rx_ring
)
3196 goto err_rx_ring_allocation
;
3198 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3199 adapter
->tx_ring
[i
].count
= adapter
->tx_ring_count
;
3200 adapter
->tx_ring
[i
].queue_index
= i
;
3203 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3204 adapter
->rx_ring
[i
].count
= adapter
->rx_ring_count
;
3205 adapter
->rx_ring
[i
].queue_index
= i
;
3208 ixgbe_cache_ring_register(adapter
);
3212 err_rx_ring_allocation
:
3213 kfree(adapter
->tx_ring
);
3214 err_tx_ring_allocation
:
3219 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3220 * @adapter: board private structure to initialize
3222 * Attempt to configure the interrupts using the best available
3223 * capabilities of the hardware and the kernel.
3225 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
3227 struct ixgbe_hw
*hw
= &adapter
->hw
;
3229 int vector
, v_budget
;
3232 * It's easy to be greedy for MSI-X vectors, but it really
3233 * doesn't do us much good if we have a lot more vectors
3234 * than CPU's. So let's be conservative and only ask for
3235 * (roughly) twice the number of vectors as there are CPU's.
3237 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
3238 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS
;
3241 * At the same time, hardware can only support a maximum of
3242 * hw.mac->max_msix_vectors vectors. With features
3243 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3244 * descriptor queues supported by our device. Thus, we cap it off in
3245 * those rare cases where the cpu count also exceeds our vector limit.
3247 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
3249 /* A failure in MSI-X entry allocation isn't fatal, but it does
3250 * mean we disable MSI-X capabilities of the adapter. */
3251 adapter
->msix_entries
= kcalloc(v_budget
,
3252 sizeof(struct msix_entry
), GFP_KERNEL
);
3253 if (adapter
->msix_entries
) {
3254 for (vector
= 0; vector
< v_budget
; vector
++)
3255 adapter
->msix_entries
[vector
].entry
= vector
;
3257 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
3259 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3263 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
3264 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
3265 ixgbe_set_num_queues(adapter
);
3267 err
= pci_enable_msi(adapter
->pdev
);
3269 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
3271 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI interrupt, "
3272 "falling back to legacy. Error: %d\n", err
);
3282 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3283 * @adapter: board private structure to initialize
3285 * We allocate one q_vector per queue interrupt. If allocation fails we
3288 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
3290 int q_idx
, num_q_vectors
;
3291 struct ixgbe_q_vector
*q_vector
;
3293 int (*poll
)(struct napi_struct
*, int);
3295 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3296 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3297 napi_vectors
= adapter
->num_rx_queues
;
3298 poll
= &ixgbe_clean_rxonly
;
3305 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
3306 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
), GFP_KERNEL
);
3309 q_vector
->adapter
= adapter
;
3310 q_vector
->v_idx
= q_idx
;
3311 q_vector
->eitr
= adapter
->eitr_param
;
3312 if (q_idx
< napi_vectors
)
3313 netif_napi_add(adapter
->netdev
, &q_vector
->napi
,
3315 adapter
->q_vector
[q_idx
] = q_vector
;
3323 q_vector
= adapter
->q_vector
[q_idx
];
3324 netif_napi_del(&q_vector
->napi
);
3326 adapter
->q_vector
[q_idx
] = NULL
;
3332 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3333 * @adapter: board private structure to initialize
3335 * This function frees the memory allocated to the q_vectors. In addition if
3336 * NAPI is enabled it will delete any references to the NAPI struct prior
3337 * to freeing the q_vector.
3339 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
3341 int q_idx
, num_q_vectors
;
3344 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3345 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3346 napi_vectors
= adapter
->num_rx_queues
;
3352 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
3353 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
3355 adapter
->q_vector
[q_idx
] = NULL
;
3356 if (q_idx
< napi_vectors
)
3357 netif_napi_del(&q_vector
->napi
);
3362 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
3364 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3365 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
3366 pci_disable_msix(adapter
->pdev
);
3367 kfree(adapter
->msix_entries
);
3368 adapter
->msix_entries
= NULL
;
3369 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
3370 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
3371 pci_disable_msi(adapter
->pdev
);
3377 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3378 * @adapter: board private structure to initialize
3380 * We determine which interrupt scheme to use based on...
3381 * - Kernel support (MSI, MSI-X)
3382 * - which can be user-defined (via MODULE_PARAM)
3383 * - Hardware queue count (num_*_queues)
3384 * - defined by miscellaneous hardware support/features (RSS, etc.)
3386 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
3390 /* Number of supported queues */
3391 ixgbe_set_num_queues(adapter
);
3393 err
= ixgbe_set_interrupt_capability(adapter
);
3395 DPRINTK(PROBE
, ERR
, "Unable to setup interrupt capabilities\n");
3396 goto err_set_interrupt
;
3399 err
= ixgbe_alloc_q_vectors(adapter
);
3401 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queue "
3403 goto err_alloc_q_vectors
;
3406 err
= ixgbe_alloc_queues(adapter
);
3408 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queues\n");
3409 goto err_alloc_queues
;
3412 DPRINTK(DRV
, INFO
, "Multiqueue %s: Rx Queue count = %u, "
3413 "Tx Queue count = %u\n",
3414 (adapter
->num_rx_queues
> 1) ? "Enabled" :
3415 "Disabled", adapter
->num_rx_queues
, adapter
->num_tx_queues
);
3417 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3422 ixgbe_free_q_vectors(adapter
);
3423 err_alloc_q_vectors
:
3424 ixgbe_reset_interrupt_capability(adapter
);
3430 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3431 * @adapter: board private structure to clear interrupt scheme on
3433 * We go through and clear interrupt specific resources and reset the structure
3434 * to pre-load conditions
3436 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
3438 kfree(adapter
->tx_ring
);
3439 kfree(adapter
->rx_ring
);
3440 adapter
->tx_ring
= NULL
;
3441 adapter
->rx_ring
= NULL
;
3443 ixgbe_free_q_vectors(adapter
);
3444 ixgbe_reset_interrupt_capability(adapter
);
3448 * ixgbe_sfp_timer - worker thread to find a missing module
3449 * @data: pointer to our adapter struct
3451 static void ixgbe_sfp_timer(unsigned long data
)
3453 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
3456 * Do the sfp_timer outside of interrupt context due to the
3457 * delays that sfp+ detection requires
3459 schedule_work(&adapter
->sfp_task
);
3463 * ixgbe_sfp_task - worker thread to find a missing module
3464 * @work: pointer to work_struct containing our data
3466 static void ixgbe_sfp_task(struct work_struct
*work
)
3468 struct ixgbe_adapter
*adapter
= container_of(work
,
3469 struct ixgbe_adapter
,
3471 struct ixgbe_hw
*hw
= &adapter
->hw
;
3473 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
3474 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
3475 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
3478 ret
= hw
->phy
.ops
.reset(hw
);
3479 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
3480 DPRINTK(PROBE
, ERR
, "failed to initialize because an "
3481 "unsupported SFP+ module type was detected.\n"
3482 "Reload the driver after installing a "
3483 "supported module.\n");
3484 unregister_netdev(adapter
->netdev
);
3486 DPRINTK(PROBE
, INFO
, "detected SFP+: %d\n",
3489 /* don't need this routine any more */
3490 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3494 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
3495 mod_timer(&adapter
->sfp_timer
,
3496 round_jiffies(jiffies
+ (2 * HZ
)));
3500 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3501 * @adapter: board private structure to initialize
3503 * ixgbe_sw_init initializes the Adapter private data structure.
3504 * Fields are initialized based on PCI device information and
3505 * OS network device settings (MTU size).
3507 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
3509 struct ixgbe_hw
*hw
= &adapter
->hw
;
3510 struct pci_dev
*pdev
= adapter
->pdev
;
3512 #ifdef CONFIG_IXGBE_DCB
3514 struct tc_configuration
*tc
;
3517 /* PCI config space info */
3519 hw
->vendor_id
= pdev
->vendor
;
3520 hw
->device_id
= pdev
->device
;
3521 hw
->revision_id
= pdev
->revision
;
3522 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
3523 hw
->subsystem_device_id
= pdev
->subsystem_device
;
3525 /* Set capability flags */
3526 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
3527 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
3528 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
3529 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
3530 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
3531 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
3532 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
3533 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
3534 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3535 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
3536 adapter
->flags
|= IXGBE_FLAG_RSC_CAPABLE
;
3537 adapter
->flags
|= IXGBE_FLAG_RSC_ENABLED
;
3539 adapter
->flags
|= IXGBE_FLAG_FCOE_ENABLED
;
3540 adapter
->ring_feature
[RING_F_FCOE
].indices
= IXGBE_FCRETA_SIZE
;
3541 #endif /* IXGBE_FCOE */
3544 #ifdef CONFIG_IXGBE_DCB
3545 /* Configure DCB traffic classes */
3546 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
3547 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
3548 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
3549 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
3550 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
3551 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
3552 tc
->dcb_pfc
= pfc_disabled
;
3554 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
3555 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
3556 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
3557 adapter
->dcb_cfg
.pfc_mode_enable
= false;
3558 adapter
->dcb_cfg
.round_robin_enable
= false;
3559 adapter
->dcb_set_bitmap
= 0x00;
3560 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
3561 adapter
->ring_feature
[RING_F_DCB
].indices
);
3565 /* default flow control settings */
3566 hw
->fc
.requested_mode
= ixgbe_fc_full
;
3567 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
3569 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
3571 hw
->fc
.high_water
= IXGBE_DEFAULT_FCRTH
;
3572 hw
->fc
.low_water
= IXGBE_DEFAULT_FCRTL
;
3573 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
3574 hw
->fc
.send_xon
= true;
3575 hw
->fc
.disable_fc_autoneg
= false;
3577 /* enable itr by default in dynamic mode */
3578 adapter
->itr_setting
= 1;
3579 adapter
->eitr_param
= 20000;
3581 /* set defaults for eitr in MegaBytes */
3582 adapter
->eitr_low
= 10;
3583 adapter
->eitr_high
= 20;
3585 /* set default ring sizes */
3586 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
3587 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
3589 /* initialize eeprom parameters */
3590 if (ixgbe_init_eeprom_params_generic(hw
)) {
3591 dev_err(&pdev
->dev
, "EEPROM initialization failed\n");
3595 /* enable rx csum by default */
3596 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
3598 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3604 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3605 * @adapter: board private structure
3606 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3608 * Return 0 on success, negative on failure
3610 int ixgbe_setup_tx_resources(struct ixgbe_adapter
*adapter
,
3611 struct ixgbe_ring
*tx_ring
)
3613 struct pci_dev
*pdev
= adapter
->pdev
;
3616 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3617 tx_ring
->tx_buffer_info
= vmalloc(size
);
3618 if (!tx_ring
->tx_buffer_info
)
3620 memset(tx_ring
->tx_buffer_info
, 0, size
);
3622 /* round up to nearest 4K */
3623 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
3624 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
3626 tx_ring
->desc
= pci_alloc_consistent(pdev
, tx_ring
->size
,
3631 tx_ring
->next_to_use
= 0;
3632 tx_ring
->next_to_clean
= 0;
3633 tx_ring
->work_limit
= tx_ring
->count
;
3637 vfree(tx_ring
->tx_buffer_info
);
3638 tx_ring
->tx_buffer_info
= NULL
;
3639 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for the transmit "
3640 "descriptor ring\n");
3645 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3646 * @adapter: board private structure
3648 * If this function returns with an error, then it's possible one or
3649 * more of the rings is populated (while the rest are not). It is the
3650 * callers duty to clean those orphaned rings.
3652 * Return 0 on success, negative on failure
3654 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
3658 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3659 err
= ixgbe_setup_tx_resources(adapter
, &adapter
->tx_ring
[i
]);
3662 DPRINTK(PROBE
, ERR
, "Allocation for Tx Queue %u failed\n", i
);
3670 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3671 * @adapter: board private structure
3672 * @rx_ring: rx descriptor ring (for a specific queue) to setup
3674 * Returns 0 on success, negative on failure
3676 int ixgbe_setup_rx_resources(struct ixgbe_adapter
*adapter
,
3677 struct ixgbe_ring
*rx_ring
)
3679 struct pci_dev
*pdev
= adapter
->pdev
;
3682 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3683 rx_ring
->rx_buffer_info
= vmalloc(size
);
3684 if (!rx_ring
->rx_buffer_info
) {
3686 "vmalloc allocation failed for the rx desc ring\n");
3689 memset(rx_ring
->rx_buffer_info
, 0, size
);
3691 /* Round up to nearest 4K */
3692 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
3693 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
3695 rx_ring
->desc
= pci_alloc_consistent(pdev
, rx_ring
->size
, &rx_ring
->dma
);
3697 if (!rx_ring
->desc
) {
3699 "Memory allocation failed for the rx desc ring\n");
3700 vfree(rx_ring
->rx_buffer_info
);
3704 rx_ring
->next_to_clean
= 0;
3705 rx_ring
->next_to_use
= 0;
3714 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3715 * @adapter: board private structure
3717 * If this function returns with an error, then it's possible one or
3718 * more of the rings is populated (while the rest are not). It is the
3719 * callers duty to clean those orphaned rings.
3721 * Return 0 on success, negative on failure
3724 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
3728 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3729 err
= ixgbe_setup_rx_resources(adapter
, &adapter
->rx_ring
[i
]);
3732 DPRINTK(PROBE
, ERR
, "Allocation for Rx Queue %u failed\n", i
);
3740 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3741 * @adapter: board private structure
3742 * @tx_ring: Tx descriptor ring for a specific queue
3744 * Free all transmit software resources
3746 void ixgbe_free_tx_resources(struct ixgbe_adapter
*adapter
,
3747 struct ixgbe_ring
*tx_ring
)
3749 struct pci_dev
*pdev
= adapter
->pdev
;
3751 ixgbe_clean_tx_ring(adapter
, tx_ring
);
3753 vfree(tx_ring
->tx_buffer_info
);
3754 tx_ring
->tx_buffer_info
= NULL
;
3756 pci_free_consistent(pdev
, tx_ring
->size
, tx_ring
->desc
, tx_ring
->dma
);
3758 tx_ring
->desc
= NULL
;
3762 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3763 * @adapter: board private structure
3765 * Free all transmit software resources
3767 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
3771 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3772 if (adapter
->tx_ring
[i
].desc
)
3773 ixgbe_free_tx_resources(adapter
, &adapter
->tx_ring
[i
]);
3777 * ixgbe_free_rx_resources - Free Rx Resources
3778 * @adapter: board private structure
3779 * @rx_ring: ring to clean the resources from
3781 * Free all receive software resources
3783 void ixgbe_free_rx_resources(struct ixgbe_adapter
*adapter
,
3784 struct ixgbe_ring
*rx_ring
)
3786 struct pci_dev
*pdev
= adapter
->pdev
;
3788 ixgbe_clean_rx_ring(adapter
, rx_ring
);
3790 vfree(rx_ring
->rx_buffer_info
);
3791 rx_ring
->rx_buffer_info
= NULL
;
3793 pci_free_consistent(pdev
, rx_ring
->size
, rx_ring
->desc
, rx_ring
->dma
);
3795 rx_ring
->desc
= NULL
;
3799 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3800 * @adapter: board private structure
3802 * Free all receive software resources
3804 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
3808 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3809 if (adapter
->rx_ring
[i
].desc
)
3810 ixgbe_free_rx_resources(adapter
, &adapter
->rx_ring
[i
]);
3814 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3815 * @netdev: network interface device structure
3816 * @new_mtu: new value for maximum frame size
3818 * Returns 0 on success, negative on failure
3820 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
3822 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3823 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3825 /* MTU < 68 is an error and causes problems on some kernels */
3826 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
3829 DPRINTK(PROBE
, INFO
, "changing MTU from %d to %d\n",
3830 netdev
->mtu
, new_mtu
);
3831 /* must set new MTU before calling down or up */
3832 netdev
->mtu
= new_mtu
;
3834 if (netif_running(netdev
))
3835 ixgbe_reinit_locked(adapter
);
3841 * ixgbe_open - Called when a network interface is made active
3842 * @netdev: network interface device structure
3844 * Returns 0 on success, negative value on failure
3846 * The open entry point is called when a network interface is made
3847 * active by the system (IFF_UP). At this point all resources needed
3848 * for transmit and receive operations are allocated, the interrupt
3849 * handler is registered with the OS, the watchdog timer is started,
3850 * and the stack is notified that the interface is ready.
3852 static int ixgbe_open(struct net_device
*netdev
)
3854 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3857 /* disallow open during test */
3858 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
3861 netif_carrier_off(netdev
);
3863 /* allocate transmit descriptors */
3864 err
= ixgbe_setup_all_tx_resources(adapter
);
3868 /* allocate receive descriptors */
3869 err
= ixgbe_setup_all_rx_resources(adapter
);
3873 ixgbe_configure(adapter
);
3875 err
= ixgbe_request_irq(adapter
);
3879 err
= ixgbe_up_complete(adapter
);
3883 netif_tx_start_all_queues(netdev
);
3888 ixgbe_release_hw_control(adapter
);
3889 ixgbe_free_irq(adapter
);
3892 ixgbe_free_all_rx_resources(adapter
);
3894 ixgbe_free_all_tx_resources(adapter
);
3895 ixgbe_reset(adapter
);
3901 * ixgbe_close - Disables a network interface
3902 * @netdev: network interface device structure
3904 * Returns 0, this is not allowed to fail
3906 * The close entry point is called when an interface is de-activated
3907 * by the OS. The hardware is still under the drivers control, but
3908 * needs to be disabled. A global MAC reset is issued to stop the
3909 * hardware, and all transmit and receive resources are freed.
3911 static int ixgbe_close(struct net_device
*netdev
)
3913 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3915 ixgbe_down(adapter
);
3916 ixgbe_free_irq(adapter
);
3918 ixgbe_free_all_tx_resources(adapter
);
3919 ixgbe_free_all_rx_resources(adapter
);
3921 ixgbe_release_hw_control(adapter
);
3927 static int ixgbe_resume(struct pci_dev
*pdev
)
3929 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3930 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3933 pci_set_power_state(pdev
, PCI_D0
);
3934 pci_restore_state(pdev
);
3936 err
= pci_enable_device_mem(pdev
);
3938 printk(KERN_ERR
"ixgbe: Cannot enable PCI device from "
3942 pci_set_master(pdev
);
3944 pci_wake_from_d3(pdev
, false);
3946 err
= ixgbe_init_interrupt_scheme(adapter
);
3948 printk(KERN_ERR
"ixgbe: Cannot initialize interrupts for "
3953 ixgbe_reset(adapter
);
3955 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
3957 if (netif_running(netdev
)) {
3958 err
= ixgbe_open(adapter
->netdev
);
3963 netif_device_attach(netdev
);
3967 #endif /* CONFIG_PM */
3969 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
3971 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3972 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3973 struct ixgbe_hw
*hw
= &adapter
->hw
;
3975 u32 wufc
= adapter
->wol
;
3980 netif_device_detach(netdev
);
3982 if (netif_running(netdev
)) {
3983 ixgbe_down(adapter
);
3984 ixgbe_free_irq(adapter
);
3985 ixgbe_free_all_tx_resources(adapter
);
3986 ixgbe_free_all_rx_resources(adapter
);
3988 ixgbe_clear_interrupt_scheme(adapter
);
3991 retval
= pci_save_state(pdev
);
3997 ixgbe_set_rx_mode(netdev
);
3999 /* turn on all-multi mode if wake on multicast is enabled */
4000 if (wufc
& IXGBE_WUFC_MC
) {
4001 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
4002 fctrl
|= IXGBE_FCTRL_MPE
;
4003 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
4006 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
4007 ctrl
|= IXGBE_CTRL_GIO_DIS
;
4008 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
4010 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
4012 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
4013 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
4016 if (wufc
&& hw
->mac
.type
== ixgbe_mac_82599EB
)
4017 pci_wake_from_d3(pdev
, true);
4019 pci_wake_from_d3(pdev
, false);
4021 *enable_wake
= !!wufc
;
4023 ixgbe_release_hw_control(adapter
);
4025 pci_disable_device(pdev
);
4031 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4036 retval
= __ixgbe_shutdown(pdev
, &wake
);
4041 pci_prepare_to_sleep(pdev
);
4043 pci_wake_from_d3(pdev
, false);
4044 pci_set_power_state(pdev
, PCI_D3hot
);
4049 #endif /* CONFIG_PM */
4051 static void ixgbe_shutdown(struct pci_dev
*pdev
)
4055 __ixgbe_shutdown(pdev
, &wake
);
4057 if (system_state
== SYSTEM_POWER_OFF
) {
4058 pci_wake_from_d3(pdev
, wake
);
4059 pci_set_power_state(pdev
, PCI_D3hot
);
4064 * ixgbe_update_stats - Update the board statistics counters.
4065 * @adapter: board private structure
4067 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
4069 struct ixgbe_hw
*hw
= &adapter
->hw
;
4071 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
4073 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4075 for (i
= 0; i
< 16; i
++)
4076 adapter
->hw_rx_no_dma_resources
+=
4077 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4078 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4079 rsc_count
+= adapter
->rx_ring
[i
].rsc_count
;
4080 adapter
->rsc_count
= rsc_count
;
4083 adapter
->stats
.crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
4084 for (i
= 0; i
< 8; i
++) {
4085 /* for packet buffers not used, the register should read 0 */
4086 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
4088 adapter
->stats
.mpc
[i
] += mpc
;
4089 total_mpc
+= adapter
->stats
.mpc
[i
];
4090 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4091 adapter
->stats
.rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
4092 adapter
->stats
.qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
4093 adapter
->stats
.qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
4094 adapter
->stats
.qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
4095 adapter
->stats
.qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
4096 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4097 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4098 IXGBE_PXONRXCNT(i
));
4099 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4100 IXGBE_PXOFFRXCNT(i
));
4101 adapter
->stats
.qprdc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4103 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4105 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4108 adapter
->stats
.pxontxc
[i
] += IXGBE_READ_REG(hw
,
4110 adapter
->stats
.pxofftxc
[i
] += IXGBE_READ_REG(hw
,
4113 adapter
->stats
.gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
4114 /* work around hardware counting issue */
4115 adapter
->stats
.gprc
-= missed_rx
;
4117 /* 82598 hardware only has a 32 bit counter in the high register */
4118 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4119 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
4120 IXGBE_READ_REG(hw
, IXGBE_GORCH
); /* to clear */
4121 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
4122 IXGBE_READ_REG(hw
, IXGBE_GOTCH
); /* to clear */
4123 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
4124 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
4125 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
4126 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
4128 adapter
->stats
.fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
4129 adapter
->stats
.fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
4130 adapter
->stats
.fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
4131 adapter
->stats
.fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
4132 adapter
->stats
.fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
4133 adapter
->stats
.fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
4134 #endif /* IXGBE_FCOE */
4136 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
4137 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
4138 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
4139 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
4140 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
4142 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
4143 adapter
->stats
.bprc
+= bprc
;
4144 adapter
->stats
.mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
4145 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4146 adapter
->stats
.mprc
-= bprc
;
4147 adapter
->stats
.roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
4148 adapter
->stats
.prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
4149 adapter
->stats
.prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
4150 adapter
->stats
.prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
4151 adapter
->stats
.prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
4152 adapter
->stats
.prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
4153 adapter
->stats
.prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
4154 adapter
->stats
.rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
4155 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
4156 adapter
->stats
.lxontxc
+= lxon
;
4157 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
4158 adapter
->stats
.lxofftxc
+= lxoff
;
4159 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4160 adapter
->stats
.gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
4161 adapter
->stats
.mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
4163 * 82598 errata - tx of flow control packets is included in tx counters
4165 xon_off_tot
= lxon
+ lxoff
;
4166 adapter
->stats
.gptc
-= xon_off_tot
;
4167 adapter
->stats
.mptc
-= xon_off_tot
;
4168 adapter
->stats
.gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
4169 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4170 adapter
->stats
.rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
4171 adapter
->stats
.rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
4172 adapter
->stats
.tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
4173 adapter
->stats
.ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
4174 adapter
->stats
.ptc64
-= xon_off_tot
;
4175 adapter
->stats
.ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
4176 adapter
->stats
.ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
4177 adapter
->stats
.ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
4178 adapter
->stats
.ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
4179 adapter
->stats
.ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
4180 adapter
->stats
.bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
4182 /* Fill out the OS statistics structure */
4183 adapter
->net_stats
.multicast
= adapter
->stats
.mprc
;
4186 adapter
->net_stats
.rx_errors
= adapter
->stats
.crcerrs
+
4187 adapter
->stats
.rlec
;
4188 adapter
->net_stats
.rx_dropped
= 0;
4189 adapter
->net_stats
.rx_length_errors
= adapter
->stats
.rlec
;
4190 adapter
->net_stats
.rx_crc_errors
= adapter
->stats
.crcerrs
;
4191 adapter
->net_stats
.rx_missed_errors
= total_mpc
;
4195 * ixgbe_watchdog - Timer Call-back
4196 * @data: pointer to adapter cast into an unsigned long
4198 static void ixgbe_watchdog(unsigned long data
)
4200 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4201 struct ixgbe_hw
*hw
= &adapter
->hw
;
4203 /* Do the watchdog outside of interrupt context due to the lovely
4204 * delays that some of the newer hardware requires */
4205 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
4209 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++)
4210 eics
|= ((u64
)1 << i
);
4212 /* Cause software interrupt to ensure rx rings are cleaned */
4213 switch (hw
->mac
.type
) {
4214 case ixgbe_mac_82598EB
:
4215 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4216 IXGBE_WRITE_REG(hw
, IXGBE_EICS
, (u32
)eics
);
4219 * for legacy and MSI interrupts don't set any
4220 * bits that are enabled for EIAM, because this
4221 * operation would set *both* EIMS and EICS for
4224 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
4225 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
4228 case ixgbe_mac_82599EB
:
4229 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4230 IXGBE_WRITE_REG(hw
, IXGBE_EICS_EX(0),
4231 (u32
)(eics
& 0xFFFFFFFF));
4232 IXGBE_WRITE_REG(hw
, IXGBE_EICS_EX(1),
4236 * for legacy and MSI interrupts don't set any
4237 * bits that are enabled for EIAM, because this
4238 * operation would set *both* EIMS and EICS for
4241 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
4242 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
4248 /* Reset the timer */
4249 mod_timer(&adapter
->watchdog_timer
,
4250 round_jiffies(jiffies
+ 2 * HZ
));
4253 schedule_work(&adapter
->watchdog_task
);
4257 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4258 * @work: pointer to work_struct containing our data
4260 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
4262 struct ixgbe_adapter
*adapter
= container_of(work
,
4263 struct ixgbe_adapter
,
4264 multispeed_fiber_task
);
4265 struct ixgbe_hw
*hw
= &adapter
->hw
;
4268 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
4269 if (hw
->mac
.ops
.get_link_capabilities
)
4270 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
,
4272 if (hw
->mac
.ops
.setup_link_speed
)
4273 hw
->mac
.ops
.setup_link_speed(hw
, autoneg
, true, true);
4274 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
4275 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
4279 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4280 * @work: pointer to work_struct containing our data
4282 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
4284 struct ixgbe_adapter
*adapter
= container_of(work
,
4285 struct ixgbe_adapter
,
4286 sfp_config_module_task
);
4287 struct ixgbe_hw
*hw
= &adapter
->hw
;
4290 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
4291 err
= hw
->phy
.ops
.identify_sfp(hw
);
4292 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4293 DPRINTK(PROBE
, ERR
, "PHY not supported on this NIC %d\n", err
);
4294 ixgbe_down(adapter
);
4297 hw
->mac
.ops
.setup_sfp(hw
);
4299 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
4300 /* This will also work for DA Twinax connections */
4301 schedule_work(&adapter
->multispeed_fiber_task
);
4302 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
4306 * ixgbe_watchdog_task - worker thread to bring link up
4307 * @work: pointer to work_struct containing our data
4309 static void ixgbe_watchdog_task(struct work_struct
*work
)
4311 struct ixgbe_adapter
*adapter
= container_of(work
,
4312 struct ixgbe_adapter
,
4314 struct net_device
*netdev
= adapter
->netdev
;
4315 struct ixgbe_hw
*hw
= &adapter
->hw
;
4316 u32 link_speed
= adapter
->link_speed
;
4317 bool link_up
= adapter
->link_up
;
4319 struct ixgbe_ring
*tx_ring
;
4320 int some_tx_pending
= 0;
4322 adapter
->flags
|= IXGBE_FLAG_IN_WATCHDOG_TASK
;
4324 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
4325 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
4328 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4329 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
4330 hw
->mac
.ops
.setup_fc(hw
, i
);
4332 hw
->mac
.ops
.setup_fc(hw
, 0);
4335 hw
->mac
.ops
.setup_fc(hw
, 0);
4340 time_after(jiffies
, (adapter
->link_check_timeout
+
4341 IXGBE_TRY_LINK_TIMEOUT
))) {
4342 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
4343 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
4345 adapter
->link_up
= link_up
;
4346 adapter
->link_speed
= link_speed
;
4350 if (!netif_carrier_ok(netdev
)) {
4351 bool flow_rx
, flow_tx
;
4353 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4354 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
4355 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
4356 flow_rx
= (mflcn
& IXGBE_MFLCN_RFCE
);
4357 flow_tx
= (fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
4359 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
4360 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
4361 flow_rx
= (frctl
& IXGBE_FCTRL_RFCE
);
4362 flow_tx
= (rmcs
& IXGBE_RMCS_TFCE_802_3X
);
4365 printk(KERN_INFO
"ixgbe: %s NIC Link is Up %s, "
4366 "Flow Control: %s\n",
4368 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
4370 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
4371 "1 Gbps" : "unknown speed")),
4372 ((flow_rx
&& flow_tx
) ? "RX/TX" :
4374 (flow_tx
? "TX" : "None"))));
4376 netif_carrier_on(netdev
);
4378 /* Force detection of hung controller */
4379 adapter
->detect_tx_hung
= true;
4382 adapter
->link_up
= false;
4383 adapter
->link_speed
= 0;
4384 if (netif_carrier_ok(netdev
)) {
4385 printk(KERN_INFO
"ixgbe: %s NIC Link is Down\n",
4387 netif_carrier_off(netdev
);
4391 if (!netif_carrier_ok(netdev
)) {
4392 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4393 tx_ring
= &adapter
->tx_ring
[i
];
4394 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
4395 some_tx_pending
= 1;
4400 if (some_tx_pending
) {
4401 /* We've lost link, so the controller stops DMA,
4402 * but we've got queued Tx work that's never going
4403 * to get done, so reset controller to flush Tx.
4404 * (Do the reset outside of interrupt context).
4406 schedule_work(&adapter
->reset_task
);
4410 ixgbe_update_stats(adapter
);
4411 adapter
->flags
&= ~IXGBE_FLAG_IN_WATCHDOG_TASK
;
4414 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
4415 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
4416 u32 tx_flags
, u8
*hdr_len
)
4418 struct ixgbe_adv_tx_context_desc
*context_desc
;
4421 struct ixgbe_tx_buffer
*tx_buffer_info
;
4422 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
4423 u32 mss_l4len_idx
, l4len
;
4425 if (skb_is_gso(skb
)) {
4426 if (skb_header_cloned(skb
)) {
4427 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
4431 l4len
= tcp_hdrlen(skb
);
4434 if (skb
->protocol
== htons(ETH_P_IP
)) {
4435 struct iphdr
*iph
= ip_hdr(skb
);
4438 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
4442 adapter
->hw_tso_ctxt
++;
4443 } else if (skb_shinfo(skb
)->gso_type
== SKB_GSO_TCPV6
) {
4444 ipv6_hdr(skb
)->payload_len
= 0;
4445 tcp_hdr(skb
)->check
=
4446 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
4447 &ipv6_hdr(skb
)->daddr
,
4449 adapter
->hw_tso6_ctxt
++;
4452 i
= tx_ring
->next_to_use
;
4454 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4455 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
4457 /* VLAN MACLEN IPLEN */
4458 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
4460 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
4461 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
4462 IXGBE_ADVTXD_MACLEN_SHIFT
);
4463 *hdr_len
+= skb_network_offset(skb
);
4465 (skb_transport_header(skb
) - skb_network_header(skb
));
4467 (skb_transport_header(skb
) - skb_network_header(skb
));
4468 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
4469 context_desc
->seqnum_seed
= 0;
4471 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4472 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
4473 IXGBE_ADVTXD_DTYP_CTXT
);
4475 if (skb
->protocol
== htons(ETH_P_IP
))
4476 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
4477 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
4478 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
4482 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
4483 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
4484 /* use index 1 for TSO */
4485 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
4486 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
4488 tx_buffer_info
->time_stamp
= jiffies
;
4489 tx_buffer_info
->next_to_watch
= i
;
4492 if (i
== tx_ring
->count
)
4494 tx_ring
->next_to_use
= i
;
4501 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
4502 struct ixgbe_ring
*tx_ring
,
4503 struct sk_buff
*skb
, u32 tx_flags
)
4505 struct ixgbe_adv_tx_context_desc
*context_desc
;
4507 struct ixgbe_tx_buffer
*tx_buffer_info
;
4508 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
4510 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
4511 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
4512 i
= tx_ring
->next_to_use
;
4513 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4514 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
4516 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
4518 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
4519 vlan_macip_lens
|= (skb_network_offset(skb
) <<
4520 IXGBE_ADVTXD_MACLEN_SHIFT
);
4521 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
4522 vlan_macip_lens
|= (skb_transport_header(skb
) -
4523 skb_network_header(skb
));
4525 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
4526 context_desc
->seqnum_seed
= 0;
4528 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
4529 IXGBE_ADVTXD_DTYP_CTXT
);
4531 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4532 switch (skb
->protocol
) {
4533 case cpu_to_be16(ETH_P_IP
):
4534 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
4535 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
4537 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
4538 else if (ip_hdr(skb
)->protocol
== IPPROTO_SCTP
)
4540 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
4542 case cpu_to_be16(ETH_P_IPV6
):
4543 /* XXX what about other V6 headers?? */
4544 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
4546 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
4547 else if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_SCTP
)
4549 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
4552 if (unlikely(net_ratelimit())) {
4553 DPRINTK(PROBE
, WARNING
,
4554 "partial checksum but proto=%x!\n",
4561 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
4562 /* use index zero for tx checksum offload */
4563 context_desc
->mss_l4len_idx
= 0;
4565 tx_buffer_info
->time_stamp
= jiffies
;
4566 tx_buffer_info
->next_to_watch
= i
;
4568 adapter
->hw_csum_tx_good
++;
4570 if (i
== tx_ring
->count
)
4572 tx_ring
->next_to_use
= i
;
4580 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
4581 struct ixgbe_ring
*tx_ring
,
4582 struct sk_buff
*skb
, u32 tx_flags
,
4585 struct ixgbe_tx_buffer
*tx_buffer_info
;
4587 unsigned int total
= skb
->len
;
4588 unsigned int offset
= 0, size
, count
= 0, i
;
4589 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
4593 i
= tx_ring
->next_to_use
;
4595 if (skb_dma_map(&adapter
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
4596 dev_err(&adapter
->pdev
->dev
, "TX DMA map failed\n");
4600 map
= skb_shinfo(skb
)->dma_maps
;
4602 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
4603 /* excluding fcoe_crc_eof for FCoE */
4604 total
-= sizeof(struct fcoe_crc_eof
);
4606 len
= min(skb_headlen(skb
), total
);
4608 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4609 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
4611 tx_buffer_info
->length
= size
;
4612 tx_buffer_info
->dma
= map
[0] + offset
;
4613 tx_buffer_info
->time_stamp
= jiffies
;
4614 tx_buffer_info
->next_to_watch
= i
;
4623 if (i
== tx_ring
->count
)
4628 for (f
= 0; f
< nr_frags
; f
++) {
4629 struct skb_frag_struct
*frag
;
4631 frag
= &skb_shinfo(skb
)->frags
[f
];
4632 len
= min((unsigned int)frag
->size
, total
);
4637 if (i
== tx_ring
->count
)
4640 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4641 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
4643 tx_buffer_info
->length
= size
;
4644 tx_buffer_info
->dma
= map
[f
+ 1] + offset
;
4645 tx_buffer_info
->time_stamp
= jiffies
;
4646 tx_buffer_info
->next_to_watch
= i
;
4657 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
4658 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
4663 static void ixgbe_tx_queue(struct ixgbe_adapter
*adapter
,
4664 struct ixgbe_ring
*tx_ring
,
4665 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
4667 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
4668 struct ixgbe_tx_buffer
*tx_buffer_info
;
4669 u32 olinfo_status
= 0, cmd_type_len
= 0;
4671 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
4673 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
4675 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
4677 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
4678 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
4680 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
4681 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
4683 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
4684 IXGBE_ADVTXD_POPTS_SHIFT
;
4686 /* use index 1 context for tso */
4687 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
4688 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
4689 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
4690 IXGBE_ADVTXD_POPTS_SHIFT
;
4692 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
4693 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
4694 IXGBE_ADVTXD_POPTS_SHIFT
;
4696 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
4697 olinfo_status
|= IXGBE_ADVTXD_CC
;
4698 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
4699 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
4700 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
4703 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
4705 i
= tx_ring
->next_to_use
;
4707 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4708 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
4709 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
4710 tx_desc
->read
.cmd_type_len
=
4711 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
4712 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
4714 if (i
== tx_ring
->count
)
4718 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
4721 * Force memory writes to complete before letting h/w
4722 * know there are new descriptors to fetch. (Only
4723 * applicable for weak-ordered memory model archs,
4728 tx_ring
->next_to_use
= i
;
4729 writel(i
, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
4732 static int __ixgbe_maybe_stop_tx(struct net_device
*netdev
,
4733 struct ixgbe_ring
*tx_ring
, int size
)
4735 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4737 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
4738 /* Herbert's original patch had:
4739 * smp_mb__after_netif_stop_queue();
4740 * but since that doesn't exist yet, just open code it. */
4743 /* We need to check again in a case another CPU has just
4744 * made room available. */
4745 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
4748 /* A reprieve! - use start_queue because it doesn't call schedule */
4749 netif_start_subqueue(netdev
, tx_ring
->queue_index
);
4750 ++adapter
->restart_queue
;
4754 static int ixgbe_maybe_stop_tx(struct net_device
*netdev
,
4755 struct ixgbe_ring
*tx_ring
, int size
)
4757 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
4759 return __ixgbe_maybe_stop_tx(netdev
, tx_ring
, size
);
4762 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
4764 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
4766 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
4767 return 0; /* All traffic should default to class 0 */
4769 return skb_tx_hash(dev
, skb
);
4772 static int ixgbe_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
4774 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4775 struct ixgbe_ring
*tx_ring
;
4777 unsigned int tx_flags
= 0;
4783 r_idx
= skb
->queue_mapping
;
4784 tx_ring
= &adapter
->tx_ring
[r_idx
];
4786 if (adapter
->vlgrp
&& vlan_tx_tag_present(skb
)) {
4787 tx_flags
|= vlan_tx_tag_get(skb
);
4788 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4789 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
4790 tx_flags
|= (skb
->queue_mapping
<< 13);
4792 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
4793 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
4794 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4795 tx_flags
|= (skb
->queue_mapping
<< 13);
4796 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
4797 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
4800 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
4801 (skb
->protocol
== htons(ETH_P_FCOE
)))
4802 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
4804 /* four things can cause us to need a context descriptor */
4805 if (skb_is_gso(skb
) ||
4806 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
4807 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
4808 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
4811 count
+= TXD_USE_COUNT(skb_headlen(skb
));
4812 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
4813 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
4815 if (ixgbe_maybe_stop_tx(netdev
, tx_ring
, count
)) {
4817 return NETDEV_TX_BUSY
;
4820 first
= tx_ring
->next_to_use
;
4821 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
4823 /* setup tx offload for FCoE */
4824 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
4826 dev_kfree_skb_any(skb
);
4827 return NETDEV_TX_OK
;
4830 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
4831 #endif /* IXGBE_FCOE */
4833 if (skb
->protocol
== htons(ETH_P_IP
))
4834 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
4835 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
4837 dev_kfree_skb_any(skb
);
4838 return NETDEV_TX_OK
;
4842 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
4843 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
) &&
4844 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
4845 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
4848 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
);
4850 ixgbe_tx_queue(adapter
, tx_ring
, tx_flags
, count
, skb
->len
,
4852 netdev
->trans_start
= jiffies
;
4853 ixgbe_maybe_stop_tx(netdev
, tx_ring
, DESC_NEEDED
);
4856 dev_kfree_skb_any(skb
);
4857 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
4858 tx_ring
->next_to_use
= first
;
4861 return NETDEV_TX_OK
;
4865 * ixgbe_get_stats - Get System Network Statistics
4866 * @netdev: network interface device structure
4868 * Returns the address of the device statistics structure.
4869 * The statistics are actually updated from the timer callback.
4871 static struct net_device_stats
*ixgbe_get_stats(struct net_device
*netdev
)
4873 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4875 /* only return the current stats */
4876 return &adapter
->net_stats
;
4880 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4881 * @netdev: network interface device structure
4882 * @p: pointer to an address structure
4884 * Returns 0 on success, negative on failure
4886 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
4888 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4889 struct ixgbe_hw
*hw
= &adapter
->hw
;
4890 struct sockaddr
*addr
= p
;
4892 if (!is_valid_ether_addr(addr
->sa_data
))
4893 return -EADDRNOTAVAIL
;
4895 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
4896 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
4898 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
4904 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
4906 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4907 struct ixgbe_hw
*hw
= &adapter
->hw
;
4911 if (prtad
!= hw
->phy
.mdio
.prtad
)
4913 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
4919 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
4920 u16 addr
, u16 value
)
4922 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4923 struct ixgbe_hw
*hw
= &adapter
->hw
;
4925 if (prtad
!= hw
->phy
.mdio
.prtad
)
4927 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
4930 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
4932 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4934 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
4938 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
4939 * netdev->dev_addr_list
4940 * @netdev: network interface device structure
4942 * Returns non-zero on failure
4944 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
4947 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
4948 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
4950 if (is_valid_ether_addr(mac
->san_addr
)) {
4952 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
4959 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
4960 * netdev->dev_addr_list
4961 * @netdev: network interface device structure
4963 * Returns non-zero on failure
4965 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
4968 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
4969 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
4971 if (is_valid_ether_addr(mac
->san_addr
)) {
4973 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
4979 #ifdef CONFIG_NET_POLL_CONTROLLER
4981 * Polling 'interrupt' - used by things like netconsole to send skbs
4982 * without having to re-enable interrupts. It's not called while
4983 * the interrupt routine is executing.
4985 static void ixgbe_netpoll(struct net_device
*netdev
)
4987 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4989 disable_irq(adapter
->pdev
->irq
);
4990 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
4991 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
4992 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
4993 enable_irq(adapter
->pdev
->irq
);
4997 static const struct net_device_ops ixgbe_netdev_ops
= {
4998 .ndo_open
= ixgbe_open
,
4999 .ndo_stop
= ixgbe_close
,
5000 .ndo_start_xmit
= ixgbe_xmit_frame
,
5001 .ndo_select_queue
= ixgbe_select_queue
,
5002 .ndo_get_stats
= ixgbe_get_stats
,
5003 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
5004 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
5005 .ndo_validate_addr
= eth_validate_addr
,
5006 .ndo_set_mac_address
= ixgbe_set_mac
,
5007 .ndo_change_mtu
= ixgbe_change_mtu
,
5008 .ndo_tx_timeout
= ixgbe_tx_timeout
,
5009 .ndo_vlan_rx_register
= ixgbe_vlan_rx_register
,
5010 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
5011 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
5012 .ndo_do_ioctl
= ixgbe_ioctl
,
5013 #ifdef CONFIG_NET_POLL_CONTROLLER
5014 .ndo_poll_controller
= ixgbe_netpoll
,
5017 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
5018 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
5019 #endif /* IXGBE_FCOE */
5023 * ixgbe_probe - Device Initialization Routine
5024 * @pdev: PCI device information struct
5025 * @ent: entry in ixgbe_pci_tbl
5027 * Returns 0 on success, negative on failure
5029 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5030 * The OS initialization, configuring of the adapter private structure,
5031 * and a hardware reset occur.
5033 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
5034 const struct pci_device_id
*ent
)
5036 struct net_device
*netdev
;
5037 struct ixgbe_adapter
*adapter
= NULL
;
5038 struct ixgbe_hw
*hw
;
5039 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
5040 static int cards_found
;
5041 int i
, err
, pci_using_dac
;
5047 err
= pci_enable_device_mem(pdev
);
5051 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) &&
5052 !pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64))) {
5055 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
5057 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
5059 dev_err(&pdev
->dev
, "No usable DMA "
5060 "configuration, aborting\n");
5067 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
5068 IORESOURCE_MEM
), ixgbe_driver_name
);
5071 "pci_request_selected_regions failed 0x%x\n", err
);
5075 err
= pci_enable_pcie_error_reporting(pdev
);
5077 dev_err(&pdev
->dev
, "pci_enable_pcie_error_reporting failed "
5079 /* non-fatal, continue */
5082 pci_set_master(pdev
);
5083 pci_save_state(pdev
);
5085 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), MAX_TX_QUEUES
);
5088 goto err_alloc_etherdev
;
5091 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
5093 pci_set_drvdata(pdev
, netdev
);
5094 adapter
= netdev_priv(netdev
);
5096 adapter
->netdev
= netdev
;
5097 adapter
->pdev
= pdev
;
5100 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
5102 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
5103 pci_resource_len(pdev
, 0));
5109 for (i
= 1; i
<= 5; i
++) {
5110 if (pci_resource_len(pdev
, i
) == 0)
5114 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
5115 ixgbe_set_ethtool_ops(netdev
);
5116 netdev
->watchdog_timeo
= 5 * HZ
;
5117 strcpy(netdev
->name
, pci_name(pdev
));
5119 adapter
->bd_number
= cards_found
;
5122 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
5123 hw
->mac
.type
= ii
->mac
;
5126 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
5127 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
5128 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5129 if (!(eec
& (1 << 8)))
5130 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
5133 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
5134 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
5135 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5136 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
5137 hw
->phy
.mdio
.mmds
= 0;
5138 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
5139 hw
->phy
.mdio
.dev
= netdev
;
5140 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
5141 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
5143 /* set up this timer and work struct before calling get_invariants
5144 * which might start the timer
5146 init_timer(&adapter
->sfp_timer
);
5147 adapter
->sfp_timer
.function
= &ixgbe_sfp_timer
;
5148 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
5150 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
5152 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5153 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
5155 /* a new SFP+ module arrival, called from GPI SDP2 context */
5156 INIT_WORK(&adapter
->sfp_config_module_task
,
5157 ixgbe_sfp_config_module_task
);
5159 err
= ii
->get_invariants(hw
);
5160 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
) {
5161 /* start a kernel thread to watch for a module to arrive */
5162 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
5163 mod_timer(&adapter
->sfp_timer
,
5164 round_jiffies(jiffies
+ (2 * HZ
)));
5166 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5167 DPRINTK(PROBE
, ERR
, "failed to load because an "
5168 "unsupported SFP+ module type was detected.\n");
5174 /* setup the private structure */
5175 err
= ixgbe_sw_init(adapter
);
5180 * If there is a fan on this device and it has failed log the
5183 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
5184 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
5185 if (esdp
& IXGBE_ESDP_SDP1
)
5186 DPRINTK(PROBE
, CRIT
,
5187 "Fan has stopped, replace the adapter\n");
5190 /* reset_hw fills in the perm_addr as well */
5191 err
= hw
->mac
.ops
.reset_hw(hw
);
5192 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5193 dev_err(&adapter
->pdev
->dev
, "failed to load because an "
5194 "unsupported SFP+ module type was detected.\n");
5197 dev_err(&adapter
->pdev
->dev
, "HW Init failed: %d\n", err
);
5201 netdev
->features
= NETIF_F_SG
|
5203 NETIF_F_HW_VLAN_TX
|
5204 NETIF_F_HW_VLAN_RX
|
5205 NETIF_F_HW_VLAN_FILTER
;
5207 netdev
->features
|= NETIF_F_IPV6_CSUM
;
5208 netdev
->features
|= NETIF_F_TSO
;
5209 netdev
->features
|= NETIF_F_TSO6
;
5210 netdev
->features
|= NETIF_F_GRO
;
5212 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
5213 netdev
->features
|= NETIF_F_SCTP_CSUM
;
5215 netdev
->vlan_features
|= NETIF_F_TSO
;
5216 netdev
->vlan_features
|= NETIF_F_TSO6
;
5217 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
5218 netdev
->vlan_features
|= NETIF_F_SG
;
5220 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
5221 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
5223 #ifdef CONFIG_IXGBE_DCB
5224 netdev
->dcbnl_ops
= &dcbnl_ops
;
5228 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
5229 if (hw
->mac
.ops
.get_device_caps
) {
5230 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
5231 if (!(device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)) {
5232 netdev
->features
|= NETIF_F_FCOE_CRC
;
5233 netdev
->features
|= NETIF_F_FSO
;
5234 netdev
->fcoe_ddp_xid
= IXGBE_FCOE_DDP_MAX
- 1;
5236 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
5240 #endif /* IXGBE_FCOE */
5242 netdev
->features
|= NETIF_F_HIGHDMA
;
5244 if (adapter
->flags
& IXGBE_FLAG_RSC_ENABLED
)
5245 netdev
->features
|= NETIF_F_LRO
;
5247 /* make sure the EEPROM is good */
5248 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
5249 dev_err(&pdev
->dev
, "The EEPROM Checksum Is Not Valid\n");
5254 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
5255 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
5257 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
5258 dev_err(&pdev
->dev
, "invalid MAC address\n");
5263 init_timer(&adapter
->watchdog_timer
);
5264 adapter
->watchdog_timer
.function
= &ixgbe_watchdog
;
5265 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
5267 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
5268 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
5270 err
= ixgbe_init_interrupt_scheme(adapter
);
5274 switch (pdev
->device
) {
5275 case IXGBE_DEV_ID_82599_KX4
:
5276 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
5277 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
5283 device_init_wakeup(&adapter
->pdev
->dev
, true);
5284 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
5286 /* pick up the PCI bus settings for reporting later */
5287 hw
->mac
.ops
.get_bus_info(hw
);
5289 /* print bus type/speed/width info */
5290 dev_info(&pdev
->dev
, "(PCI Express:%s:%s) %pM\n",
5291 ((hw
->bus
.speed
== ixgbe_bus_speed_5000
) ? "5.0Gb/s":
5292 (hw
->bus
.speed
== ixgbe_bus_speed_2500
) ? "2.5Gb/s":"Unknown"),
5293 ((hw
->bus
.width
== ixgbe_bus_width_pcie_x8
) ? "Width x8" :
5294 (hw
->bus
.width
== ixgbe_bus_width_pcie_x4
) ? "Width x4" :
5295 (hw
->bus
.width
== ixgbe_bus_width_pcie_x1
) ? "Width x1" :
5298 ixgbe_read_pba_num_generic(hw
, &part_num
);
5299 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
5300 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5301 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
5302 (part_num
>> 8), (part_num
& 0xff));
5304 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5305 hw
->mac
.type
, hw
->phy
.type
,
5306 (part_num
>> 8), (part_num
& 0xff));
5308 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
5309 dev_warn(&pdev
->dev
, "PCI-Express bandwidth available for "
5310 "this card is not sufficient for optimal "
5312 dev_warn(&pdev
->dev
, "For optimal performance a x8 "
5313 "PCI-Express slot is required.\n");
5316 /* save off EEPROM version number */
5317 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
5319 /* reset the hardware with the new settings */
5320 hw
->mac
.ops
.start_hw(hw
);
5322 strcpy(netdev
->name
, "eth%d");
5323 err
= register_netdev(netdev
);
5327 /* carrier off reporting is important to ethtool even BEFORE open */
5328 netif_carrier_off(netdev
);
5330 #ifdef CONFIG_IXGBE_DCA
5331 if (dca_add_requester(&pdev
->dev
) == 0) {
5332 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
5333 /* always use CB2 mode, difference is masked
5334 * in the CB driver */
5335 IXGBE_WRITE_REG(hw
, IXGBE_DCA_CTRL
, 2);
5336 ixgbe_setup_dca(adapter
);
5339 /* add san mac addr to netdev */
5340 ixgbe_add_sanmac_netdev(netdev
);
5342 dev_info(&pdev
->dev
, "Intel(R) 10 Gigabit Network Connection\n");
5347 ixgbe_release_hw_control(adapter
);
5349 ixgbe_clear_interrupt_scheme(adapter
);
5352 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
5353 del_timer_sync(&adapter
->sfp_timer
);
5354 cancel_work_sync(&adapter
->sfp_task
);
5355 cancel_work_sync(&adapter
->multispeed_fiber_task
);
5356 cancel_work_sync(&adapter
->sfp_config_module_task
);
5357 iounmap(hw
->hw_addr
);
5359 free_netdev(netdev
);
5361 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
5365 pci_disable_device(pdev
);
5370 * ixgbe_remove - Device Removal Routine
5371 * @pdev: PCI device information struct
5373 * ixgbe_remove is called by the PCI subsystem to alert the driver
5374 * that it should release a PCI device. The could be caused by a
5375 * Hot-Plug event, or because the driver is going to be removed from
5378 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
5380 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5381 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5384 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5385 /* clear the module not found bit to make sure the worker won't
5388 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
5389 del_timer_sync(&adapter
->watchdog_timer
);
5391 del_timer_sync(&adapter
->sfp_timer
);
5392 cancel_work_sync(&adapter
->watchdog_task
);
5393 cancel_work_sync(&adapter
->sfp_task
);
5394 cancel_work_sync(&adapter
->multispeed_fiber_task
);
5395 cancel_work_sync(&adapter
->sfp_config_module_task
);
5396 flush_scheduled_work();
5398 #ifdef CONFIG_IXGBE_DCA
5399 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
5400 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
5401 dca_remove_requester(&pdev
->dev
);
5402 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
5407 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
5408 ixgbe_cleanup_fcoe(adapter
);
5410 #endif /* IXGBE_FCOE */
5412 /* remove the added san mac */
5413 ixgbe_del_sanmac_netdev(netdev
);
5415 if (netdev
->reg_state
== NETREG_REGISTERED
)
5416 unregister_netdev(netdev
);
5418 ixgbe_clear_interrupt_scheme(adapter
);
5420 ixgbe_release_hw_control(adapter
);
5422 iounmap(adapter
->hw
.hw_addr
);
5423 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
5426 DPRINTK(PROBE
, INFO
, "complete\n");
5428 free_netdev(netdev
);
5430 err
= pci_disable_pcie_error_reporting(pdev
);
5433 "pci_disable_pcie_error_reporting failed 0x%x\n", err
);
5435 pci_disable_device(pdev
);
5439 * ixgbe_io_error_detected - called when PCI error is detected
5440 * @pdev: Pointer to PCI device
5441 * @state: The current pci connection state
5443 * This function is called after a PCI bus error affecting
5444 * this device has been detected.
5446 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
5447 pci_channel_state_t state
)
5449 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5450 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5452 netif_device_detach(netdev
);
5454 if (state
== pci_channel_io_perm_failure
)
5455 return PCI_ERS_RESULT_DISCONNECT
;
5457 if (netif_running(netdev
))
5458 ixgbe_down(adapter
);
5459 pci_disable_device(pdev
);
5461 /* Request a slot reset. */
5462 return PCI_ERS_RESULT_NEED_RESET
;
5466 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5467 * @pdev: Pointer to PCI device
5469 * Restart the card from scratch, as if from a cold-boot.
5471 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
5473 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5474 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5475 pci_ers_result_t result
;
5478 if (pci_enable_device_mem(pdev
)) {
5480 "Cannot re-enable PCI device after reset.\n");
5481 result
= PCI_ERS_RESULT_DISCONNECT
;
5483 pci_set_master(pdev
);
5484 pci_restore_state(pdev
);
5486 pci_wake_from_d3(pdev
, false);
5488 ixgbe_reset(adapter
);
5489 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5490 result
= PCI_ERS_RESULT_RECOVERED
;
5493 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
5496 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err
);
5497 /* non-fatal, continue */
5504 * ixgbe_io_resume - called when traffic can start flowing again.
5505 * @pdev: Pointer to PCI device
5507 * This callback is called when the error recovery driver tells us that
5508 * its OK to resume normal operation.
5510 static void ixgbe_io_resume(struct pci_dev
*pdev
)
5512 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5513 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5515 if (netif_running(netdev
)) {
5516 if (ixgbe_up(adapter
)) {
5517 DPRINTK(PROBE
, INFO
, "ixgbe_up failed after reset\n");
5522 netif_device_attach(netdev
);
5525 static struct pci_error_handlers ixgbe_err_handler
= {
5526 .error_detected
= ixgbe_io_error_detected
,
5527 .slot_reset
= ixgbe_io_slot_reset
,
5528 .resume
= ixgbe_io_resume
,
5531 static struct pci_driver ixgbe_driver
= {
5532 .name
= ixgbe_driver_name
,
5533 .id_table
= ixgbe_pci_tbl
,
5534 .probe
= ixgbe_probe
,
5535 .remove
= __devexit_p(ixgbe_remove
),
5537 .suspend
= ixgbe_suspend
,
5538 .resume
= ixgbe_resume
,
5540 .shutdown
= ixgbe_shutdown
,
5541 .err_handler
= &ixgbe_err_handler
5545 * ixgbe_init_module - Driver Registration Routine
5547 * ixgbe_init_module is the first routine called when the driver is
5548 * loaded. All it does is register with the PCI subsystem.
5550 static int __init
ixgbe_init_module(void)
5553 printk(KERN_INFO
"%s: %s - version %s\n", ixgbe_driver_name
,
5554 ixgbe_driver_string
, ixgbe_driver_version
);
5556 printk(KERN_INFO
"%s: %s\n", ixgbe_driver_name
, ixgbe_copyright
);
5558 #ifdef CONFIG_IXGBE_DCA
5559 dca_register_notify(&dca_notifier
);
5562 ret
= pci_register_driver(&ixgbe_driver
);
5566 module_init(ixgbe_init_module
);
5569 * ixgbe_exit_module - Driver Exit Cleanup Routine
5571 * ixgbe_exit_module is called just before the driver is removed
5574 static void __exit
ixgbe_exit_module(void)
5576 #ifdef CONFIG_IXGBE_DCA
5577 dca_unregister_notify(&dca_notifier
);
5579 pci_unregister_driver(&ixgbe_driver
);
5582 #ifdef CONFIG_IXGBE_DCA
5583 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
5588 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
5589 __ixgbe_notify_dca
);
5591 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
5594 #endif /* CONFIG_IXGBE_DCA */
5597 * ixgbe_get_hw_dev_name - return device name string
5598 * used by hardware layer to print debugging information
5600 char *ixgbe_get_hw_dev_name(struct ixgbe_hw
*hw
)
5602 struct ixgbe_adapter
*adapter
= hw
->back
;
5603 return adapter
->netdev
->name
;
5607 module_exit(ixgbe_exit_module
);