2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/irqdomain.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
40 #include <linux/slab.h>
41 #include <linux/bootmem.h>
42 #include <linux/dmar.h>
43 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
55 #include <asm/msidef.h>
56 #include <asm/hypertransport.h>
57 #include <asm/setup.h>
58 #include <asm/irq_remapping.h>
60 #include <asm/hw_irq.h>
64 #define __apicdebuginit(type) static type __init
66 #define for_each_ioapic(idx) \
67 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
68 #define for_each_ioapic_reverse(idx) \
69 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
70 #define for_each_pin(idx, pin) \
71 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
72 #define for_each_ioapic_pin(idx, pin) \
73 for_each_ioapic((idx)) \
74 for_each_pin((idx), (pin))
76 #define for_each_irq_pin(entry, head) \
77 for (entry = head; entry; entry = entry->next)
80 * Is the SiS APIC rmw bug present ?
81 * -1 = don't know, 0 = no, 1 = yes
83 int sis_apic_bug
= -1;
85 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
86 static DEFINE_RAW_SPINLOCK(vector_lock
);
87 static DEFINE_MUTEX(ioapic_mutex
);
88 static unsigned int ioapic_dynirq_base
;
89 static int ioapic_initialized
;
99 static struct ioapic
{
101 * # of IRQ routing registers
105 * Saved state during suspend/resume, or while enabling intr-remap.
107 struct IO_APIC_route_entry
*saved_registers
;
108 /* I/O APIC config */
109 struct mpc_ioapic mp_config
;
110 /* IO APIC gsi routing info */
111 struct mp_ioapic_gsi gsi_config
;
112 struct ioapic_domain_cfg irqdomain_cfg
;
113 struct irq_domain
*irqdomain
;
114 struct mp_pin_info
*pin_info
;
115 struct resource
*iomem_res
;
116 } ioapics
[MAX_IO_APICS
];
118 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
120 int mpc_ioapic_id(int ioapic_idx
)
122 return ioapics
[ioapic_idx
].mp_config
.apicid
;
125 unsigned int mpc_ioapic_addr(int ioapic_idx
)
127 return ioapics
[ioapic_idx
].mp_config
.apicaddr
;
130 struct mp_ioapic_gsi
*mp_ioapic_gsi_routing(int ioapic_idx
)
132 return &ioapics
[ioapic_idx
].gsi_config
;
135 static inline int mp_ioapic_pin_count(int ioapic
)
137 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
139 return gsi_cfg
->gsi_end
- gsi_cfg
->gsi_base
+ 1;
142 u32
mp_pin_to_gsi(int ioapic
, int pin
)
144 return mp_ioapic_gsi_routing(ioapic
)->gsi_base
+ pin
;
148 * Initialize all legacy IRQs and all pins on the first IOAPIC
149 * if we have legacy interrupt controller. Kernel boot option "pirq="
150 * may rely on non-legacy pins on the first IOAPIC.
152 static inline int mp_init_irq_at_boot(int ioapic
, int irq
)
154 if (!nr_legacy_irqs())
157 return ioapic
== 0 || (irq
>= 0 && irq
< nr_legacy_irqs());
160 static inline struct mp_pin_info
*mp_pin_info(int ioapic_idx
, int pin
)
162 return ioapics
[ioapic_idx
].pin_info
+ pin
;
165 static inline struct irq_domain
*mp_ioapic_irqdomain(int ioapic
)
167 return ioapics
[ioapic
].irqdomain
;
172 /* The one past the highest gsi number used */
175 /* MP IRQ source entries */
176 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
178 /* # of MP IRQ source entries */
182 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
185 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
187 int skip_ioapic_setup
;
190 * disable_ioapic_support() - disables ioapic support at runtime
192 void disable_ioapic_support(void)
196 noioapicreroute
= -1;
198 skip_ioapic_setup
= 1;
201 static int __init
parse_noapic(char *str
)
203 /* disable IO-APIC */
204 disable_ioapic_support();
207 early_param("noapic", parse_noapic
);
209 static struct irq_cfg
*alloc_irq_and_cfg_at(unsigned int at
, int node
);
211 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
212 void mp_save_irq(struct mpc_intsrc
*m
)
216 apic_printk(APIC_VERBOSE
, "Int: type %d, pol %d, trig %d, bus %02x,"
217 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
218 m
->irqtype
, m
->irqflag
& 3, (m
->irqflag
>> 2) & 3, m
->srcbus
,
219 m
->srcbusirq
, m
->dstapic
, m
->dstirq
);
221 for (i
= 0; i
< mp_irq_entries
; i
++) {
222 if (!memcmp(&mp_irqs
[i
], m
, sizeof(*m
)))
226 memcpy(&mp_irqs
[mp_irq_entries
], m
, sizeof(*m
));
227 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
228 panic("Max # of irq sources exceeded!!\n");
231 struct irq_pin_list
{
233 struct irq_pin_list
*next
;
236 static struct irq_pin_list
*alloc_irq_pin_list(int node
)
238 return kzalloc_node(sizeof(struct irq_pin_list
), GFP_KERNEL
, node
);
241 static void alloc_ioapic_saved_registers(int idx
)
245 if (ioapics
[idx
].saved_registers
)
248 size
= sizeof(struct IO_APIC_route_entry
) * ioapics
[idx
].nr_registers
;
249 ioapics
[idx
].saved_registers
= kzalloc(size
, GFP_KERNEL
);
250 if (!ioapics
[idx
].saved_registers
)
251 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx
);
254 static void free_ioapic_saved_registers(int idx
)
256 kfree(ioapics
[idx
].saved_registers
);
257 ioapics
[idx
].saved_registers
= NULL
;
260 int __init
arch_early_irq_init(void)
263 int i
, node
= cpu_to_node(0);
265 if (!nr_legacy_irqs())
269 alloc_ioapic_saved_registers(i
);
272 * For legacy IRQ's, start with assigning irq0 to irq15 to
273 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
275 for (i
= 0; i
< nr_legacy_irqs(); i
++) {
276 cfg
= alloc_irq_and_cfg_at(i
, node
);
277 cfg
->vector
= IRQ0_VECTOR
+ i
;
278 cpumask_setall(cfg
->domain
);
284 static inline struct irq_cfg
*irq_cfg(unsigned int irq
)
286 return irq_get_chip_data(irq
);
289 static struct irq_cfg
*alloc_irq_cfg(unsigned int irq
, int node
)
293 cfg
= kzalloc_node(sizeof(*cfg
), GFP_KERNEL
, node
);
296 if (!zalloc_cpumask_var_node(&cfg
->domain
, GFP_KERNEL
, node
))
298 if (!zalloc_cpumask_var_node(&cfg
->old_domain
, GFP_KERNEL
, node
))
302 free_cpumask_var(cfg
->domain
);
308 static void free_irq_cfg(unsigned int at
, struct irq_cfg
*cfg
)
312 irq_set_chip_data(at
, NULL
);
313 free_cpumask_var(cfg
->domain
);
314 free_cpumask_var(cfg
->old_domain
);
318 static struct irq_cfg
*alloc_irq_and_cfg_at(unsigned int at
, int node
)
320 int res
= irq_alloc_desc_at(at
, node
);
331 cfg
= alloc_irq_cfg(at
, node
);
333 irq_set_chip_data(at
, cfg
);
341 unsigned int unused
[3];
343 unsigned int unused2
[11];
347 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
349 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
350 + (mpc_ioapic_addr(idx
) & ~PAGE_MASK
);
353 void io_apic_eoi(unsigned int apic
, unsigned int vector
)
355 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
356 writel(vector
, &io_apic
->eoi
);
359 unsigned int native_io_apic_read(unsigned int apic
, unsigned int reg
)
361 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
362 writel(reg
, &io_apic
->index
);
363 return readl(&io_apic
->data
);
366 void native_io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
368 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
370 writel(reg
, &io_apic
->index
);
371 writel(value
, &io_apic
->data
);
375 * Re-write a value: to be used for read-modify-write
376 * cycles where the read already set up the index register.
378 * Older SiS APIC requires we rewrite the index register
380 void native_io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
382 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
385 writel(reg
, &io_apic
->index
);
386 writel(value
, &io_apic
->data
);
390 struct { u32 w1
, w2
; };
391 struct IO_APIC_route_entry entry
;
394 static struct IO_APIC_route_entry
__ioapic_read_entry(int apic
, int pin
)
396 union entry_union eu
;
398 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
399 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
404 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
406 union entry_union eu
;
409 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
410 eu
.entry
= __ioapic_read_entry(apic
, pin
);
411 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
417 * When we write a new IO APIC routing entry, we need to write the high
418 * word first! If the mask bit in the low word is clear, we will enable
419 * the interrupt, and we need to make sure the entry is fully populated
420 * before that happens.
422 static void __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
424 union entry_union eu
= {{0, 0}};
427 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
428 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
431 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
435 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
436 __ioapic_write_entry(apic
, pin
, e
);
437 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
441 * When we mask an IO APIC routing entry, we need to write the low
442 * word first, in order to set the mask bit before we change the
445 static void ioapic_mask_entry(int apic
, int pin
)
448 union entry_union eu
= { .entry
.mask
= 1 };
450 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
451 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
452 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
453 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
457 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
458 * shared ISA-space IRQs, so we have to support them. We are super
459 * fast in the common case, and fast for shared ISA-space IRQs.
461 static int __add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
463 struct irq_pin_list
**last
, *entry
;
465 /* don't allow duplicates */
466 last
= &cfg
->irq_2_pin
;
467 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
468 if (entry
->apic
== apic
&& entry
->pin
== pin
)
473 entry
= alloc_irq_pin_list(node
);
475 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
486 static void __remove_pin_from_irq(struct irq_cfg
*cfg
, int apic
, int pin
)
488 struct irq_pin_list
**last
, *entry
;
490 last
= &cfg
->irq_2_pin
;
491 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
492 if (entry
->apic
== apic
&& entry
->pin
== pin
) {
501 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
503 if (__add_pin_to_irq_node(cfg
, node
, apic
, pin
))
504 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
508 * Reroute an IRQ to a different pin.
510 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
511 int oldapic
, int oldpin
,
512 int newapic
, int newpin
)
514 struct irq_pin_list
*entry
;
516 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
517 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
518 entry
->apic
= newapic
;
520 /* every one is different, right? */
525 /* old apic/pin didn't exist, so just add new ones */
526 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
529 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
530 int mask_and
, int mask_or
,
531 void (*final
)(struct irq_pin_list
*entry
))
533 unsigned int reg
, pin
;
536 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
539 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
544 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
545 int mask_and
, int mask_or
,
546 void (*final
)(struct irq_pin_list
*entry
))
548 struct irq_pin_list
*entry
;
550 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
551 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
554 static void io_apic_sync(struct irq_pin_list
*entry
)
557 * Synchronize the IO-APIC and the CPU by doing
558 * a dummy read from the IO-APIC
560 struct io_apic __iomem
*io_apic
;
562 io_apic
= io_apic_base(entry
->apic
);
563 readl(&io_apic
->data
);
566 static void mask_ioapic(struct irq_cfg
*cfg
)
570 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
571 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
572 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
575 static void mask_ioapic_irq(struct irq_data
*data
)
577 mask_ioapic(data
->chip_data
);
580 static void __unmask_ioapic(struct irq_cfg
*cfg
)
582 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
585 static void unmask_ioapic(struct irq_cfg
*cfg
)
589 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
590 __unmask_ioapic(cfg
);
591 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
594 static void unmask_ioapic_irq(struct irq_data
*data
)
596 unmask_ioapic(data
->chip_data
);
600 * IO-APIC versions below 0x20 don't support EOI register.
601 * For the record, here is the information about various versions:
603 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
604 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
607 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
608 * version as 0x2. This is an error with documentation and these ICH chips
609 * use io-apic's of version 0x20.
611 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
612 * Otherwise, we simulate the EOI message manually by changing the trigger
613 * mode to edge and then back to level, with RTE being masked during this.
615 void native_eoi_ioapic_pin(int apic
, int pin
, int vector
)
617 if (mpc_ioapic_ver(apic
) >= 0x20) {
618 io_apic_eoi(apic
, vector
);
620 struct IO_APIC_route_entry entry
, entry1
;
622 entry
= entry1
= __ioapic_read_entry(apic
, pin
);
625 * Mask the entry and change the trigger mode to edge.
628 entry1
.trigger
= IOAPIC_EDGE
;
630 __ioapic_write_entry(apic
, pin
, entry1
);
633 * Restore the previous level triggered entry.
635 __ioapic_write_entry(apic
, pin
, entry
);
639 void eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
641 struct irq_pin_list
*entry
;
644 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
645 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
646 x86_io_apic_ops
.eoi_ioapic_pin(entry
->apic
, entry
->pin
,
648 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
651 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
653 struct IO_APIC_route_entry entry
;
655 /* Check delivery_mode to be sure we're not clearing an SMI pin */
656 entry
= ioapic_read_entry(apic
, pin
);
657 if (entry
.delivery_mode
== dest_SMI
)
661 * Make sure the entry is masked and re-read the contents to check
662 * if it is a level triggered pin and if the remote-IRR is set.
666 ioapic_write_entry(apic
, pin
, entry
);
667 entry
= ioapic_read_entry(apic
, pin
);
674 * Make sure the trigger mode is set to level. Explicit EOI
675 * doesn't clear the remote-IRR if the trigger mode is not
678 if (!entry
.trigger
) {
679 entry
.trigger
= IOAPIC_LEVEL
;
680 ioapic_write_entry(apic
, pin
, entry
);
683 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
684 x86_io_apic_ops
.eoi_ioapic_pin(apic
, pin
, entry
.vector
);
685 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
689 * Clear the rest of the bits in the IO-APIC RTE except for the mask
692 ioapic_mask_entry(apic
, pin
);
693 entry
= ioapic_read_entry(apic
, pin
);
695 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
696 mpc_ioapic_id(apic
), pin
);
699 static void clear_IO_APIC (void)
703 for_each_ioapic_pin(apic
, pin
)
704 clear_IO_APIC_pin(apic
, pin
);
709 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
710 * specific CPU-side IRQs.
714 static int pirq_entries
[MAX_PIRQS
] = {
715 [0 ... MAX_PIRQS
- 1] = -1
718 static int __init
ioapic_pirq_setup(char *str
)
721 int ints
[MAX_PIRQS
+1];
723 get_options(str
, ARRAY_SIZE(ints
), ints
);
725 apic_printk(APIC_VERBOSE
, KERN_INFO
726 "PIRQ redirection, working around broken MP-BIOS.\n");
728 if (ints
[0] < MAX_PIRQS
)
731 for (i
= 0; i
< max
; i
++) {
732 apic_printk(APIC_VERBOSE
, KERN_DEBUG
733 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
735 * PIRQs are mapped upside down, usually.
737 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
742 __setup("pirq=", ioapic_pirq_setup
);
743 #endif /* CONFIG_X86_32 */
746 * Saves all the IO-APIC RTE's
748 int save_ioapic_entries(void)
753 for_each_ioapic(apic
) {
754 if (!ioapics
[apic
].saved_registers
) {
759 for_each_pin(apic
, pin
)
760 ioapics
[apic
].saved_registers
[pin
] =
761 ioapic_read_entry(apic
, pin
);
768 * Mask all IO APIC entries.
770 void mask_ioapic_entries(void)
774 for_each_ioapic(apic
) {
775 if (!ioapics
[apic
].saved_registers
)
778 for_each_pin(apic
, pin
) {
779 struct IO_APIC_route_entry entry
;
781 entry
= ioapics
[apic
].saved_registers
[pin
];
784 ioapic_write_entry(apic
, pin
, entry
);
791 * Restore IO APIC entries which was saved in the ioapic structure.
793 int restore_ioapic_entries(void)
797 for_each_ioapic(apic
) {
798 if (!ioapics
[apic
].saved_registers
)
801 for_each_pin(apic
, pin
)
802 ioapic_write_entry(apic
, pin
,
803 ioapics
[apic
].saved_registers
[pin
]);
809 * Find the IRQ entry number of a certain pin.
811 static int find_irq_entry(int ioapic_idx
, int pin
, int type
)
815 for (i
= 0; i
< mp_irq_entries
; i
++)
816 if (mp_irqs
[i
].irqtype
== type
&&
817 (mp_irqs
[i
].dstapic
== mpc_ioapic_id(ioapic_idx
) ||
818 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
819 mp_irqs
[i
].dstirq
== pin
)
826 * Find the pin to which IRQ[irq] (ISA) is connected
828 static int __init
find_isa_irq_pin(int irq
, int type
)
832 for (i
= 0; i
< mp_irq_entries
; i
++) {
833 int lbus
= mp_irqs
[i
].srcbus
;
835 if (test_bit(lbus
, mp_bus_not_pci
) &&
836 (mp_irqs
[i
].irqtype
== type
) &&
837 (mp_irqs
[i
].srcbusirq
== irq
))
839 return mp_irqs
[i
].dstirq
;
844 static int __init
find_isa_irq_apic(int irq
, int type
)
848 for (i
= 0; i
< mp_irq_entries
; i
++) {
849 int lbus
= mp_irqs
[i
].srcbus
;
851 if (test_bit(lbus
, mp_bus_not_pci
) &&
852 (mp_irqs
[i
].irqtype
== type
) &&
853 (mp_irqs
[i
].srcbusirq
== irq
))
857 if (i
< mp_irq_entries
) {
860 for_each_ioapic(ioapic_idx
)
861 if (mpc_ioapic_id(ioapic_idx
) == mp_irqs
[i
].dstapic
)
870 * EISA Edge/Level control register, ELCR
872 static int EISA_ELCR(unsigned int irq
)
874 if (irq
< nr_legacy_irqs()) {
875 unsigned int port
= 0x4d0 + (irq
>> 3);
876 return (inb(port
) >> (irq
& 7)) & 1;
878 apic_printk(APIC_VERBOSE
, KERN_INFO
879 "Broken MPtable reports ISA irq %d\n", irq
);
885 /* ISA interrupts are always polarity zero edge triggered,
886 * when listed as conforming in the MP table. */
888 #define default_ISA_trigger(idx) (0)
889 #define default_ISA_polarity(idx) (0)
891 /* EISA interrupts are always polarity zero and can be edge or level
892 * trigger depending on the ELCR value. If an interrupt is listed as
893 * EISA conforming in the MP table, that means its trigger type must
894 * be read in from the ELCR */
896 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
897 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
899 /* PCI interrupts are always polarity one level triggered,
900 * when listed as conforming in the MP table. */
902 #define default_PCI_trigger(idx) (1)
903 #define default_PCI_polarity(idx) (1)
905 static int irq_polarity(int idx
)
907 int bus
= mp_irqs
[idx
].srcbus
;
911 * Determine IRQ line polarity (high active or low active):
913 switch (mp_irqs
[idx
].irqflag
& 3)
915 case 0: /* conforms, ie. bus-type dependent polarity */
916 if (test_bit(bus
, mp_bus_not_pci
))
917 polarity
= default_ISA_polarity(idx
);
919 polarity
= default_PCI_polarity(idx
);
921 case 1: /* high active */
926 case 2: /* reserved */
928 pr_warn("broken BIOS!!\n");
932 case 3: /* low active */
937 default: /* invalid */
939 pr_warn("broken BIOS!!\n");
947 static int irq_trigger(int idx
)
949 int bus
= mp_irqs
[idx
].srcbus
;
953 * Determine IRQ trigger mode (edge or level sensitive):
955 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
957 case 0: /* conforms, ie. bus-type dependent */
958 if (test_bit(bus
, mp_bus_not_pci
))
959 trigger
= default_ISA_trigger(idx
);
961 trigger
= default_PCI_trigger(idx
);
963 switch (mp_bus_id_to_type
[bus
]) {
964 case MP_BUS_ISA
: /* ISA pin */
966 /* set before the switch */
969 case MP_BUS_EISA
: /* EISA pin */
971 trigger
= default_EISA_trigger(idx
);
974 case MP_BUS_PCI
: /* PCI pin */
976 /* set before the switch */
981 pr_warn("broken BIOS!!\n");
993 case 2: /* reserved */
995 pr_warn("broken BIOS!!\n");
1004 default: /* invalid */
1006 pr_warn("broken BIOS!!\n");
1014 static int alloc_irq_from_domain(struct irq_domain
*domain
, u32 gsi
, int pin
)
1017 int ioapic
= (int)(long)domain
->host_data
;
1018 int type
= ioapics
[ioapic
].irqdomain_cfg
.type
;
1021 case IOAPIC_DOMAIN_LEGACY
:
1023 * Dynamically allocate IRQ number for non-ISA IRQs in the first 16
1024 * GSIs on some weird platforms.
1026 if (gsi
< nr_legacy_irqs())
1027 irq
= irq_create_mapping(domain
, pin
);
1028 else if (irq_create_strict_mappings(domain
, gsi
, pin
, 1) == 0)
1031 case IOAPIC_DOMAIN_STRICT
:
1032 if (irq_create_strict_mappings(domain
, gsi
, pin
, 1) == 0)
1035 case IOAPIC_DOMAIN_DYNAMIC
:
1036 irq
= irq_create_mapping(domain
, pin
);
1039 WARN(1, "ioapic: unknown irqdomain type %d\n", type
);
1043 return irq
> 0 ? irq
: -1;
1046 static int mp_map_pin_to_irq(u32 gsi
, int idx
, int ioapic
, int pin
,
1050 struct irq_domain
*domain
= mp_ioapic_irqdomain(ioapic
);
1051 struct mp_pin_info
*info
= mp_pin_info(ioapic
, pin
);
1056 mutex_lock(&ioapic_mutex
);
1059 * Don't use irqdomain to manage ISA IRQs because there may be
1060 * multiple IOAPIC pins sharing the same ISA IRQ number and
1061 * irqdomain only supports 1:1 mapping between IOAPIC pin and
1062 * IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are used
1063 * for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
1064 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are
1065 * available, and some BIOSes may use MP Interrupt Source records
1066 * to override IRQ numbers for PIRQs instead of reprogramming
1067 * the interrupt routing logic. Thus there may be multiple pins
1068 * sharing the same legacy IRQ number when ACPI is disabled.
1070 if (idx
>= 0 && test_bit(mp_irqs
[idx
].srcbus
, mp_bus_not_pci
)) {
1071 irq
= mp_irqs
[idx
].srcbusirq
;
1072 if (flags
& IOAPIC_MAP_ALLOC
) {
1073 if (info
->count
== 0 &&
1074 mp_irqdomain_map(domain
, irq
, pin
) != 0)
1077 /* special handling for timer IRQ0 */
1082 irq
= irq_find_mapping(domain
, pin
);
1083 if (irq
<= 0 && (flags
& IOAPIC_MAP_ALLOC
))
1084 irq
= alloc_irq_from_domain(domain
, gsi
, pin
);
1087 if (flags
& IOAPIC_MAP_ALLOC
) {
1088 /* special handling for legacy IRQs */
1089 if (irq
< nr_legacy_irqs() && info
->count
== 1 &&
1090 mp_irqdomain_map(domain
, irq
, pin
) != 0)
1095 else if (info
->count
== 0)
1099 mutex_unlock(&ioapic_mutex
);
1101 return irq
> 0 ? irq
: -1;
1104 static int pin_2_irq(int idx
, int ioapic
, int pin
, unsigned int flags
)
1106 u32 gsi
= mp_pin_to_gsi(ioapic
, pin
);
1109 * Debugging check, we are in big trouble if this message pops up!
1111 if (mp_irqs
[idx
].dstirq
!= pin
)
1112 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1114 #ifdef CONFIG_X86_32
1116 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1118 if ((pin
>= 16) && (pin
<= 23)) {
1119 if (pirq_entries
[pin
-16] != -1) {
1120 if (!pirq_entries
[pin
-16]) {
1121 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1122 "disabling PIRQ%d\n", pin
-16);
1124 int irq
= pirq_entries
[pin
-16];
1125 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1126 "using PIRQ%d -> IRQ %d\n",
1134 return mp_map_pin_to_irq(gsi
, idx
, ioapic
, pin
, flags
);
1137 int mp_map_gsi_to_irq(u32 gsi
, unsigned int flags
)
1139 int ioapic
, pin
, idx
;
1141 ioapic
= mp_find_ioapic(gsi
);
1145 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
1146 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
1147 if ((flags
& IOAPIC_MAP_CHECK
) && idx
< 0)
1150 return mp_map_pin_to_irq(gsi
, idx
, ioapic
, pin
, flags
);
1153 void mp_unmap_irq(int irq
)
1155 struct irq_data
*data
= irq_get_irq_data(irq
);
1156 struct mp_pin_info
*info
;
1159 if (!data
|| !data
->domain
)
1162 ioapic
= (int)(long)data
->domain
->host_data
;
1163 pin
= (int)data
->hwirq
;
1164 info
= mp_pin_info(ioapic
, pin
);
1166 mutex_lock(&ioapic_mutex
);
1167 if (--info
->count
== 0) {
1169 if (irq
< nr_legacy_irqs() &&
1170 ioapics
[ioapic
].irqdomain_cfg
.type
== IOAPIC_DOMAIN_LEGACY
)
1171 mp_irqdomain_unmap(data
->domain
, irq
);
1173 irq_dispose_mapping(irq
);
1175 mutex_unlock(&ioapic_mutex
);
1179 * Find a specific PCI IRQ entry.
1180 * Not an __init, possibly needed by modules
1182 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
1184 int irq
, i
, best_ioapic
= -1, best_idx
= -1;
1186 apic_printk(APIC_DEBUG
,
1187 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1189 if (test_bit(bus
, mp_bus_not_pci
)) {
1190 apic_printk(APIC_VERBOSE
,
1191 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1195 for (i
= 0; i
< mp_irq_entries
; i
++) {
1196 int lbus
= mp_irqs
[i
].srcbus
;
1197 int ioapic_idx
, found
= 0;
1199 if (bus
!= lbus
|| mp_irqs
[i
].irqtype
!= mp_INT
||
1200 slot
!= ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))
1203 for_each_ioapic(ioapic_idx
)
1204 if (mpc_ioapic_id(ioapic_idx
) == mp_irqs
[i
].dstapic
||
1205 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) {
1213 irq
= pin_2_irq(i
, ioapic_idx
, mp_irqs
[i
].dstirq
, 0);
1214 if (irq
> 0 && !IO_APIC_IRQ(irq
))
1217 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1219 best_ioapic
= ioapic_idx
;
1224 * Use the first all-but-pin matching entry as a
1225 * best-guess fuzzy result for broken mptables.
1229 best_ioapic
= ioapic_idx
;
1236 return pin_2_irq(best_idx
, best_ioapic
, mp_irqs
[best_idx
].dstirq
,
1239 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1241 void lock_vector_lock(void)
1243 /* Used to the online set of cpus does not change
1244 * during assign_irq_vector.
1246 raw_spin_lock(&vector_lock
);
1249 void unlock_vector_lock(void)
1251 raw_spin_unlock(&vector_lock
);
1255 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1258 * NOTE! The local APIC isn't very good at handling
1259 * multiple interrupts at the same interrupt level.
1260 * As the interrupt level is determined by taking the
1261 * vector number and shifting that right by 4, we
1262 * want to spread these out a bit so that they don't
1263 * all fall in the same interrupt level.
1265 * Also, we've got to be careful not to trash gate
1266 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1268 static int current_vector
= FIRST_EXTERNAL_VECTOR
+ VECTOR_OFFSET_START
;
1269 static int current_offset
= VECTOR_OFFSET_START
% 16;
1271 cpumask_var_t tmp_mask
;
1273 if (cfg
->move_in_progress
)
1276 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1279 /* Only try and allocate irqs on cpus that are present */
1281 cpumask_clear(cfg
->old_domain
);
1282 cpu
= cpumask_first_and(mask
, cpu_online_mask
);
1283 while (cpu
< nr_cpu_ids
) {
1284 int new_cpu
, vector
, offset
;
1286 apic
->vector_allocation_domain(cpu
, tmp_mask
, mask
);
1288 if (cpumask_subset(tmp_mask
, cfg
->domain
)) {
1290 if (cpumask_equal(tmp_mask
, cfg
->domain
))
1293 * New cpumask using the vector is a proper subset of
1294 * the current in use mask. So cleanup the vector
1295 * allocation for the members that are not used anymore.
1297 cpumask_andnot(cfg
->old_domain
, cfg
->domain
, tmp_mask
);
1298 cfg
->move_in_progress
=
1299 cpumask_intersects(cfg
->old_domain
, cpu_online_mask
);
1300 cpumask_and(cfg
->domain
, cfg
->domain
, tmp_mask
);
1304 vector
= current_vector
;
1305 offset
= current_offset
;
1308 if (vector
>= first_system_vector
) {
1309 offset
= (offset
+ 1) % 16;
1310 vector
= FIRST_EXTERNAL_VECTOR
+ offset
;
1313 if (unlikely(current_vector
== vector
)) {
1314 cpumask_or(cfg
->old_domain
, cfg
->old_domain
, tmp_mask
);
1315 cpumask_andnot(tmp_mask
, mask
, cfg
->old_domain
);
1316 cpu
= cpumask_first_and(tmp_mask
, cpu_online_mask
);
1320 if (test_bit(vector
, used_vectors
))
1323 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
) {
1324 if (per_cpu(vector_irq
, new_cpu
)[vector
] > VECTOR_UNDEFINED
)
1328 current_vector
= vector
;
1329 current_offset
= offset
;
1331 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1332 cfg
->move_in_progress
=
1333 cpumask_intersects(cfg
->old_domain
, cpu_online_mask
);
1335 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1336 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1337 cfg
->vector
= vector
;
1338 cpumask_copy(cfg
->domain
, tmp_mask
);
1342 free_cpumask_var(tmp_mask
);
1346 int assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1349 unsigned long flags
;
1351 raw_spin_lock_irqsave(&vector_lock
, flags
);
1352 err
= __assign_irq_vector(irq
, cfg
, mask
);
1353 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
1357 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1361 BUG_ON(!cfg
->vector
);
1363 vector
= cfg
->vector
;
1364 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1365 per_cpu(vector_irq
, cpu
)[vector
] = VECTOR_UNDEFINED
;
1368 cpumask_clear(cfg
->domain
);
1370 if (likely(!cfg
->move_in_progress
))
1372 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1373 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1374 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1376 per_cpu(vector_irq
, cpu
)[vector
] = VECTOR_UNDEFINED
;
1380 cfg
->move_in_progress
= 0;
1383 void __setup_vector_irq(int cpu
)
1385 /* Initialize vector_irq on a new cpu */
1387 struct irq_cfg
*cfg
;
1390 * vector_lock will make sure that we don't run into irq vector
1391 * assignments that might be happening on another cpu in parallel,
1392 * while we setup our initial vector to irq mappings.
1394 raw_spin_lock(&vector_lock
);
1395 /* Mark the inuse vectors */
1396 for_each_active_irq(irq
) {
1401 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1403 vector
= cfg
->vector
;
1404 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1406 /* Mark the free vectors */
1407 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1408 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1409 if (irq
<= VECTOR_UNDEFINED
)
1413 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1414 per_cpu(vector_irq
, cpu
)[vector
] = VECTOR_UNDEFINED
;
1416 raw_spin_unlock(&vector_lock
);
1419 static struct irq_chip ioapic_chip
;
1421 #ifdef CONFIG_X86_32
1422 static inline int IO_APIC_irq_trigger(int irq
)
1426 for_each_ioapic_pin(apic
, pin
) {
1427 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1428 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
, 0)))
1429 return irq_trigger(idx
);
1432 * nonexistent IRQs are edge default
1437 static inline int IO_APIC_irq_trigger(int irq
)
1443 static void ioapic_register_intr(unsigned int irq
, struct irq_cfg
*cfg
,
1444 unsigned long trigger
)
1446 struct irq_chip
*chip
= &ioapic_chip
;
1447 irq_flow_handler_t hdl
;
1450 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1451 trigger
== IOAPIC_LEVEL
) {
1452 irq_set_status_flags(irq
, IRQ_LEVEL
);
1455 irq_clear_status_flags(irq
, IRQ_LEVEL
);
1459 if (setup_remapped_irq(irq
, cfg
, chip
))
1460 fasteoi
= trigger
!= 0;
1462 hdl
= fasteoi
? handle_fasteoi_irq
: handle_edge_irq
;
1463 irq_set_chip_and_handler_name(irq
, chip
, hdl
,
1464 fasteoi
? "fasteoi" : "edge");
1467 int native_setup_ioapic_entry(int irq
, struct IO_APIC_route_entry
*entry
,
1468 unsigned int destination
, int vector
,
1469 struct io_apic_irq_attr
*attr
)
1471 memset(entry
, 0, sizeof(*entry
));
1473 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1474 entry
->dest_mode
= apic
->irq_dest_mode
;
1475 entry
->dest
= destination
;
1476 entry
->vector
= vector
;
1477 entry
->mask
= 0; /* enable IRQ */
1478 entry
->trigger
= attr
->trigger
;
1479 entry
->polarity
= attr
->polarity
;
1482 * Mask level triggered irqs.
1483 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1491 static void setup_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
,
1492 struct io_apic_irq_attr
*attr
)
1494 struct IO_APIC_route_entry entry
;
1497 if (!IO_APIC_IRQ(irq
))
1500 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1503 if (apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus(),
1505 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
1506 mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
);
1507 __clear_irq_vector(irq
, cfg
);
1512 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1513 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1514 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1515 attr
->ioapic
, mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
,
1516 cfg
->vector
, irq
, attr
->trigger
, attr
->polarity
, dest
);
1518 if (x86_io_apic_ops
.setup_entry(irq
, &entry
, dest
, cfg
->vector
, attr
)) {
1519 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1520 mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
);
1521 __clear_irq_vector(irq
, cfg
);
1526 ioapic_register_intr(irq
, cfg
, attr
->trigger
);
1527 if (irq
< nr_legacy_irqs())
1528 legacy_pic
->mask(irq
);
1530 ioapic_write_entry(attr
->ioapic
, attr
->ioapic_pin
, entry
);
1533 static void __init
setup_IO_APIC_irqs(void)
1535 unsigned int ioapic
, pin
;
1538 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1540 for_each_ioapic_pin(ioapic
, pin
) {
1541 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
1543 apic_printk(APIC_VERBOSE
,
1544 KERN_DEBUG
" apic %d pin %d not connected\n",
1545 mpc_ioapic_id(ioapic
), pin
);
1547 pin_2_irq(idx
, ioapic
, pin
,
1548 ioapic
? 0 : IOAPIC_MAP_ALLOC
);
1553 * Set up the timer pin, possibly with the 8259A-master behind.
1555 static void __init
setup_timer_IRQ0_pin(unsigned int ioapic_idx
,
1556 unsigned int pin
, int vector
)
1558 struct IO_APIC_route_entry entry
;
1561 memset(&entry
, 0, sizeof(entry
));
1564 * We use logical delivery to get the timer IRQ
1567 if (unlikely(apic
->cpu_mask_to_apicid_and(apic
->target_cpus(),
1568 apic
->target_cpus(), &dest
)))
1571 entry
.dest_mode
= apic
->irq_dest_mode
;
1572 entry
.mask
= 0; /* don't mask IRQ for edge */
1574 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1577 entry
.vector
= vector
;
1580 * The timer IRQ doesn't have to know that behind the
1581 * scene we may have a 8259A-master in AEOI mode ...
1583 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,
1587 * Add it to the IO-APIC irq-routing table:
1589 ioapic_write_entry(ioapic_idx
, pin
, entry
);
1592 void native_io_apic_print_entries(unsigned int apic
, unsigned int nr_entries
)
1596 pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n");
1598 for (i
= 0; i
<= nr_entries
; i
++) {
1599 struct IO_APIC_route_entry entry
;
1601 entry
= ioapic_read_entry(apic
, i
);
1603 pr_debug(" %02x %02X ", i
, entry
.dest
);
1604 pr_cont("%1d %1d %1d %1d %1d "
1610 entry
.delivery_status
,
1612 entry
.delivery_mode
,
1617 void intel_ir_io_apic_print_entries(unsigned int apic
,
1618 unsigned int nr_entries
)
1622 pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n");
1624 for (i
= 0; i
<= nr_entries
; i
++) {
1625 struct IR_IO_APIC_route_entry
*ir_entry
;
1626 struct IO_APIC_route_entry entry
;
1628 entry
= ioapic_read_entry(apic
, i
);
1630 ir_entry
= (struct IR_IO_APIC_route_entry
*)&entry
;
1632 pr_debug(" %02x %04X ", i
, ir_entry
->index
);
1633 pr_cont("%1d %1d %1d %1d %1d "
1634 "%1d %1d %X %02X\n",
1640 ir_entry
->delivery_status
,
1647 void ioapic_zap_locks(void)
1649 raw_spin_lock_init(&ioapic_lock
);
1652 __apicdebuginit(void) print_IO_APIC(int ioapic_idx
)
1654 union IO_APIC_reg_00 reg_00
;
1655 union IO_APIC_reg_01 reg_01
;
1656 union IO_APIC_reg_02 reg_02
;
1657 union IO_APIC_reg_03 reg_03
;
1658 unsigned long flags
;
1660 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1661 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
1662 reg_01
.raw
= io_apic_read(ioapic_idx
, 1);
1663 if (reg_01
.bits
.version
>= 0x10)
1664 reg_02
.raw
= io_apic_read(ioapic_idx
, 2);
1665 if (reg_01
.bits
.version
>= 0x20)
1666 reg_03
.raw
= io_apic_read(ioapic_idx
, 3);
1667 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1669 printk(KERN_DEBUG
"IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx
));
1670 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1671 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1672 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1673 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1675 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1676 printk(KERN_DEBUG
"....... : max redirection entries: %02X\n",
1677 reg_01
.bits
.entries
);
1679 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1680 printk(KERN_DEBUG
"....... : IO APIC version: %02X\n",
1681 reg_01
.bits
.version
);
1684 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1685 * but the value of reg_02 is read as the previous read register
1686 * value, so ignore it if reg_02 == reg_01.
1688 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1689 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1690 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1694 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1695 * or reg_03, but the value of reg_0[23] is read as the previous read
1696 * register value, so ignore it if reg_03 == reg_0[12].
1698 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1699 reg_03
.raw
!= reg_01
.raw
) {
1700 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1701 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1704 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1706 x86_io_apic_ops
.print_entries(ioapic_idx
, reg_01
.bits
.entries
);
1709 __apicdebuginit(void) print_IO_APICs(void)
1712 struct irq_cfg
*cfg
;
1714 struct irq_chip
*chip
;
1716 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1717 for_each_ioapic(ioapic_idx
)
1718 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1719 mpc_ioapic_id(ioapic_idx
),
1720 ioapics
[ioapic_idx
].nr_registers
);
1723 * We are a bit conservative about what we expect. We have to
1724 * know about every hardware change ASAP.
1726 printk(KERN_INFO
"testing the IO APIC.......................\n");
1728 for_each_ioapic(ioapic_idx
)
1729 print_IO_APIC(ioapic_idx
);
1731 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1732 for_each_active_irq(irq
) {
1733 struct irq_pin_list
*entry
;
1735 chip
= irq_get_chip(irq
);
1736 if (chip
!= &ioapic_chip
)
1742 entry
= cfg
->irq_2_pin
;
1745 printk(KERN_DEBUG
"IRQ%d ", irq
);
1746 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1747 pr_cont("-> %d:%d", entry
->apic
, entry
->pin
);
1751 printk(KERN_INFO
".................................... done.\n");
1754 __apicdebuginit(void) print_APIC_field(int base
)
1760 for (i
= 0; i
< 8; i
++)
1761 pr_cont("%08x", apic_read(base
+ i
*0x10));
1766 __apicdebuginit(void) print_local_APIC(void *dummy
)
1768 unsigned int i
, v
, ver
, maxlvt
;
1771 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1772 smp_processor_id(), hard_smp_processor_id());
1773 v
= apic_read(APIC_ID
);
1774 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1775 v
= apic_read(APIC_LVR
);
1776 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1777 ver
= GET_APIC_VERSION(v
);
1778 maxlvt
= lapic_get_maxlvt();
1780 v
= apic_read(APIC_TASKPRI
);
1781 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1783 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1784 if (!APIC_XAPIC(ver
)) {
1785 v
= apic_read(APIC_ARBPRI
);
1786 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1787 v
& APIC_ARBPRI_MASK
);
1789 v
= apic_read(APIC_PROCPRI
);
1790 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1794 * Remote read supported only in the 82489DX and local APIC for
1795 * Pentium processors.
1797 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1798 v
= apic_read(APIC_RRR
);
1799 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1802 v
= apic_read(APIC_LDR
);
1803 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1804 if (!x2apic_enabled()) {
1805 v
= apic_read(APIC_DFR
);
1806 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1808 v
= apic_read(APIC_SPIV
);
1809 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1811 printk(KERN_DEBUG
"... APIC ISR field:\n");
1812 print_APIC_field(APIC_ISR
);
1813 printk(KERN_DEBUG
"... APIC TMR field:\n");
1814 print_APIC_field(APIC_TMR
);
1815 printk(KERN_DEBUG
"... APIC IRR field:\n");
1816 print_APIC_field(APIC_IRR
);
1818 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1819 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1820 apic_write(APIC_ESR
, 0);
1822 v
= apic_read(APIC_ESR
);
1823 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1826 icr
= apic_icr_read();
1827 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1828 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1830 v
= apic_read(APIC_LVTT
);
1831 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1833 if (maxlvt
> 3) { /* PC is LVT#4. */
1834 v
= apic_read(APIC_LVTPC
);
1835 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1837 v
= apic_read(APIC_LVT0
);
1838 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1839 v
= apic_read(APIC_LVT1
);
1840 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1842 if (maxlvt
> 2) { /* ERR is LVT#3. */
1843 v
= apic_read(APIC_LVTERR
);
1844 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1847 v
= apic_read(APIC_TMICT
);
1848 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1849 v
= apic_read(APIC_TMCCT
);
1850 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1851 v
= apic_read(APIC_TDCR
);
1852 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1854 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1855 v
= apic_read(APIC_EFEAT
);
1856 maxlvt
= (v
>> 16) & 0xff;
1857 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1858 v
= apic_read(APIC_ECTRL
);
1859 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1860 for (i
= 0; i
< maxlvt
; i
++) {
1861 v
= apic_read(APIC_EILVTn(i
));
1862 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1868 __apicdebuginit(void) print_local_APICs(int maxcpu
)
1876 for_each_online_cpu(cpu
) {
1879 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1884 __apicdebuginit(void) print_PIC(void)
1887 unsigned long flags
;
1889 if (!nr_legacy_irqs())
1892 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1894 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
1896 v
= inb(0xa1) << 8 | inb(0x21);
1897 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1899 v
= inb(0xa0) << 8 | inb(0x20);
1900 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1904 v
= inb(0xa0) << 8 | inb(0x20);
1908 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
1910 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1912 v
= inb(0x4d1) << 8 | inb(0x4d0);
1913 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1916 static int __initdata show_lapic
= 1;
1917 static __init
int setup_show_lapic(char *arg
)
1921 if (strcmp(arg
, "all") == 0) {
1922 show_lapic
= CONFIG_NR_CPUS
;
1924 get_option(&arg
, &num
);
1931 __setup("show_lapic=", setup_show_lapic
);
1933 __apicdebuginit(int) print_ICs(void)
1935 if (apic_verbosity
== APIC_QUIET
)
1940 /* don't print out if apic is not there */
1941 if (!cpu_has_apic
&& !apic_from_smp_config())
1944 print_local_APICs(show_lapic
);
1950 late_initcall(print_ICs
);
1953 /* Where if anywhere is the i8259 connect in external int mode */
1954 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1956 void __init
enable_IO_APIC(void)
1958 int i8259_apic
, i8259_pin
;
1961 if (!nr_legacy_irqs())
1964 for_each_ioapic_pin(apic
, pin
) {
1965 /* See if any of the pins is in ExtINT mode */
1966 struct IO_APIC_route_entry entry
= ioapic_read_entry(apic
, pin
);
1968 /* If the interrupt line is enabled and in ExtInt mode
1969 * I have found the pin where the i8259 is connected.
1971 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1972 ioapic_i8259
.apic
= apic
;
1973 ioapic_i8259
.pin
= pin
;
1978 /* Look to see what if the MP table has reported the ExtINT */
1979 /* If we could not find the appropriate pin by looking at the ioapic
1980 * the i8259 probably is not connected the ioapic but give the
1981 * mptable a chance anyway.
1983 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1984 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1985 /* Trust the MP table if nothing is setup in the hardware */
1986 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1987 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1988 ioapic_i8259
.pin
= i8259_pin
;
1989 ioapic_i8259
.apic
= i8259_apic
;
1991 /* Complain if the MP table and the hardware disagree */
1992 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1993 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1995 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1999 * Do not trust the IO-APIC being empty at bootup
2004 void native_disable_io_apic(void)
2007 * If the i8259 is routed through an IOAPIC
2008 * Put that IOAPIC in virtual wire mode
2009 * so legacy interrupts can be delivered.
2011 if (ioapic_i8259
.pin
!= -1) {
2012 struct IO_APIC_route_entry entry
;
2014 memset(&entry
, 0, sizeof(entry
));
2015 entry
.mask
= 0; /* Enabled */
2016 entry
.trigger
= 0; /* Edge */
2018 entry
.polarity
= 0; /* High */
2019 entry
.delivery_status
= 0;
2020 entry
.dest_mode
= 0; /* Physical */
2021 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
2023 entry
.dest
= read_apic_id();
2026 * Add it to the IO-APIC irq-routing table:
2028 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2031 if (cpu_has_apic
|| apic_from_smp_config())
2032 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
2037 * Not an __init, needed by the reboot code
2039 void disable_IO_APIC(void)
2042 * Clear the IO-APIC before rebooting:
2046 if (!nr_legacy_irqs())
2049 x86_io_apic_ops
.disable();
2052 #ifdef CONFIG_X86_32
2054 * function to set the IO-APIC physical IDs based on the
2055 * values stored in the MPC table.
2057 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2059 void __init
setup_ioapic_ids_from_mpc_nocheck(void)
2061 union IO_APIC_reg_00 reg_00
;
2062 physid_mask_t phys_id_present_map
;
2065 unsigned char old_id
;
2066 unsigned long flags
;
2069 * This is broken; anything with a real cpu count has to
2070 * circumvent this idiocy regardless.
2072 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
2075 * Set the IOAPIC ID to the value stored in the MPC table.
2077 for_each_ioapic(ioapic_idx
) {
2078 /* Read the register 0 value */
2079 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2080 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
2081 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2083 old_id
= mpc_ioapic_id(ioapic_idx
);
2085 if (mpc_ioapic_id(ioapic_idx
) >= get_physical_broadcast()) {
2086 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2087 ioapic_idx
, mpc_ioapic_id(ioapic_idx
));
2088 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2090 ioapics
[ioapic_idx
].mp_config
.apicid
= reg_00
.bits
.ID
;
2094 * Sanity check, is the ID really free? Every APIC in a
2095 * system must have a unique ID or we get lots of nice
2096 * 'stuck on smp_invalidate_needed IPI wait' messages.
2098 if (apic
->check_apicid_used(&phys_id_present_map
,
2099 mpc_ioapic_id(ioapic_idx
))) {
2100 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2101 ioapic_idx
, mpc_ioapic_id(ioapic_idx
));
2102 for (i
= 0; i
< get_physical_broadcast(); i
++)
2103 if (!physid_isset(i
, phys_id_present_map
))
2105 if (i
>= get_physical_broadcast())
2106 panic("Max APIC ID exceeded!\n");
2107 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2109 physid_set(i
, phys_id_present_map
);
2110 ioapics
[ioapic_idx
].mp_config
.apicid
= i
;
2113 apic
->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx
),
2115 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2116 "phys_id_present_map\n",
2117 mpc_ioapic_id(ioapic_idx
));
2118 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2122 * We need to adjust the IRQ routing table
2123 * if the ID changed.
2125 if (old_id
!= mpc_ioapic_id(ioapic_idx
))
2126 for (i
= 0; i
< mp_irq_entries
; i
++)
2127 if (mp_irqs
[i
].dstapic
== old_id
)
2129 = mpc_ioapic_id(ioapic_idx
);
2132 * Update the ID register according to the right value
2133 * from the MPC table if they are different.
2135 if (mpc_ioapic_id(ioapic_idx
) == reg_00
.bits
.ID
)
2138 apic_printk(APIC_VERBOSE
, KERN_INFO
2139 "...changing IO-APIC physical APIC ID to %d ...",
2140 mpc_ioapic_id(ioapic_idx
));
2142 reg_00
.bits
.ID
= mpc_ioapic_id(ioapic_idx
);
2143 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2144 io_apic_write(ioapic_idx
, 0, reg_00
.raw
);
2145 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2150 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2151 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
2152 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2153 if (reg_00
.bits
.ID
!= mpc_ioapic_id(ioapic_idx
))
2154 pr_cont("could not set ID!\n");
2156 apic_printk(APIC_VERBOSE
, " ok.\n");
2160 void __init
setup_ioapic_ids_from_mpc(void)
2166 * Don't check I/O APIC IDs for xAPIC systems. They have
2167 * no meaning without the serial APIC bus.
2169 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2170 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2172 setup_ioapic_ids_from_mpc_nocheck();
2176 int no_timer_check __initdata
;
2178 static int __init
notimercheck(char *s
)
2183 __setup("no_timer_check", notimercheck
);
2186 * There is a nasty bug in some older SMP boards, their mptable lies
2187 * about the timer IRQ. We do the following to work around the situation:
2189 * - timer IRQ defaults to IO-APIC IRQ
2190 * - if this function detects that timer IRQs are defunct, then we fall
2191 * back to ISA timer IRQs
2193 static int __init
timer_irq_works(void)
2195 unsigned long t1
= jiffies
;
2196 unsigned long flags
;
2201 local_save_flags(flags
);
2203 /* Let ten ticks pass... */
2204 mdelay((10 * 1000) / HZ
);
2205 local_irq_restore(flags
);
2208 * Expect a few ticks at least, to be sure some possible
2209 * glue logic does not lock up after one or two first
2210 * ticks in a non-ExtINT mode. Also the local APIC
2211 * might have cached one ExtINT interrupt. Finally, at
2212 * least one tick may be lost due to delays.
2216 if (time_after(jiffies
, t1
+ 4))
2222 * In the SMP+IOAPIC case it might happen that there are an unspecified
2223 * number of pending IRQ events unhandled. These cases are very rare,
2224 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2225 * better to do it this way as thus we do not have to be aware of
2226 * 'pending' interrupts in the IRQ path, except at this point.
2229 * Edge triggered needs to resend any interrupt
2230 * that was delayed but this is now handled in the device
2235 * Starting up a edge-triggered IO-APIC interrupt is
2236 * nasty - we need to make sure that we get the edge.
2237 * If it is already asserted for some reason, we need
2238 * return 1 to indicate that is was pending.
2240 * This is not complete - we should be able to fake
2241 * an edge even if it isn't on the 8259A...
2244 static unsigned int startup_ioapic_irq(struct irq_data
*data
)
2246 int was_pending
= 0, irq
= data
->irq
;
2247 unsigned long flags
;
2249 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2250 if (irq
< nr_legacy_irqs()) {
2251 legacy_pic
->mask(irq
);
2252 if (legacy_pic
->irq_pending(irq
))
2255 __unmask_ioapic(data
->chip_data
);
2256 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2261 static int ioapic_retrigger_irq(struct irq_data
*data
)
2263 struct irq_cfg
*cfg
= data
->chip_data
;
2264 unsigned long flags
;
2267 raw_spin_lock_irqsave(&vector_lock
, flags
);
2268 cpu
= cpumask_first_and(cfg
->domain
, cpu_online_mask
);
2269 apic
->send_IPI_mask(cpumask_of(cpu
), cfg
->vector
);
2270 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2276 * Level and edge triggered IO-APIC interrupts need different handling,
2277 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2278 * handled with the level-triggered descriptor, but that one has slightly
2279 * more overhead. Level-triggered interrupts cannot be handled with the
2280 * edge-triggered handler, without risking IRQ storms and other ugly
2285 void send_cleanup_vector(struct irq_cfg
*cfg
)
2287 cpumask_var_t cleanup_mask
;
2289 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2291 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2292 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2294 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2295 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2296 free_cpumask_var(cleanup_mask
);
2298 cfg
->move_in_progress
= 0;
2301 asmlinkage __visible
void smp_irq_move_cleanup_interrupt(void)
2303 unsigned vector
, me
;
2309 me
= smp_processor_id();
2310 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2313 struct irq_desc
*desc
;
2314 struct irq_cfg
*cfg
;
2315 irq
= __this_cpu_read(vector_irq
[vector
]);
2317 if (irq
<= VECTOR_UNDEFINED
)
2320 desc
= irq_to_desc(irq
);
2328 raw_spin_lock(&desc
->lock
);
2331 * Check if the irq migration is in progress. If so, we
2332 * haven't received the cleanup request yet for this irq.
2334 if (cfg
->move_in_progress
)
2337 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2340 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2342 * Check if the vector that needs to be cleanedup is
2343 * registered at the cpu's IRR. If so, then this is not
2344 * the best time to clean it up. Lets clean it up in the
2345 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2348 if (irr
& (1 << (vector
% 32))) {
2349 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2352 __this_cpu_write(vector_irq
[vector
], VECTOR_UNDEFINED
);
2354 raw_spin_unlock(&desc
->lock
);
2360 static void __irq_complete_move(struct irq_cfg
*cfg
, unsigned vector
)
2364 if (likely(!cfg
->move_in_progress
))
2367 me
= smp_processor_id();
2369 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2370 send_cleanup_vector(cfg
);
2373 static void irq_complete_move(struct irq_cfg
*cfg
)
2375 __irq_complete_move(cfg
, ~get_irq_regs()->orig_ax
);
2378 void irq_force_complete_move(int irq
)
2380 struct irq_cfg
*cfg
= irq_cfg(irq
);
2385 __irq_complete_move(cfg
, cfg
->vector
);
2388 static inline void irq_complete_move(struct irq_cfg
*cfg
) { }
2391 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2394 struct irq_pin_list
*entry
;
2395 u8 vector
= cfg
->vector
;
2397 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2403 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2404 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2405 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2407 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2412 * Either sets data->affinity to a valid value, and returns
2413 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2414 * leaves data->affinity untouched.
2416 int __ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2417 unsigned int *dest_id
)
2419 struct irq_cfg
*cfg
= data
->chip_data
;
2420 unsigned int irq
= data
->irq
;
2423 if (!config_enabled(CONFIG_SMP
))
2426 if (!cpumask_intersects(mask
, cpu_online_mask
))
2429 err
= assign_irq_vector(irq
, cfg
, mask
);
2433 err
= apic
->cpu_mask_to_apicid_and(mask
, cfg
->domain
, dest_id
);
2435 if (assign_irq_vector(irq
, cfg
, data
->affinity
))
2436 pr_err("Failed to recover vector for irq %d\n", irq
);
2440 cpumask_copy(data
->affinity
, mask
);
2446 int native_ioapic_set_affinity(struct irq_data
*data
,
2447 const struct cpumask
*mask
,
2450 unsigned int dest
, irq
= data
->irq
;
2451 unsigned long flags
;
2454 if (!config_enabled(CONFIG_SMP
))
2457 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2458 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
2460 /* Only the high 8 bits are valid. */
2461 dest
= SET_APIC_LOGICAL_ID(dest
);
2462 __target_IO_APIC_irq(irq
, dest
, data
->chip_data
);
2463 ret
= IRQ_SET_MASK_OK_NOCOPY
;
2465 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2469 static void ack_apic_edge(struct irq_data
*data
)
2471 irq_complete_move(data
->chip_data
);
2476 atomic_t irq_mis_count
;
2478 #ifdef CONFIG_GENERIC_PENDING_IRQ
2479 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
2481 struct irq_pin_list
*entry
;
2482 unsigned long flags
;
2484 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2485 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2490 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
2491 /* Is the remote IRR bit set? */
2492 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
2493 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2497 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2502 static inline bool ioapic_irqd_mask(struct irq_data
*data
, struct irq_cfg
*cfg
)
2504 /* If we are moving the irq we need to mask it */
2505 if (unlikely(irqd_is_setaffinity_pending(data
))) {
2512 static inline void ioapic_irqd_unmask(struct irq_data
*data
,
2513 struct irq_cfg
*cfg
, bool masked
)
2515 if (unlikely(masked
)) {
2516 /* Only migrate the irq if the ack has been received.
2518 * On rare occasions the broadcast level triggered ack gets
2519 * delayed going to ioapics, and if we reprogram the
2520 * vector while Remote IRR is still set the irq will never
2523 * To prevent this scenario we read the Remote IRR bit
2524 * of the ioapic. This has two effects.
2525 * - On any sane system the read of the ioapic will
2526 * flush writes (and acks) going to the ioapic from
2528 * - We get to see if the ACK has actually been delivered.
2530 * Based on failed experiments of reprogramming the
2531 * ioapic entry from outside of irq context starting
2532 * with masking the ioapic entry and then polling until
2533 * Remote IRR was clear before reprogramming the
2534 * ioapic I don't trust the Remote IRR bit to be
2535 * completey accurate.
2537 * However there appears to be no other way to plug
2538 * this race, so if the Remote IRR bit is not
2539 * accurate and is causing problems then it is a hardware bug
2540 * and you can go talk to the chipset vendor about it.
2542 if (!io_apic_level_ack_pending(cfg
))
2543 irq_move_masked_irq(data
);
2548 static inline bool ioapic_irqd_mask(struct irq_data
*data
, struct irq_cfg
*cfg
)
2552 static inline void ioapic_irqd_unmask(struct irq_data
*data
,
2553 struct irq_cfg
*cfg
, bool masked
)
2558 static void ack_apic_level(struct irq_data
*data
)
2560 struct irq_cfg
*cfg
= data
->chip_data
;
2561 int i
, irq
= data
->irq
;
2565 irq_complete_move(cfg
);
2566 masked
= ioapic_irqd_mask(data
, cfg
);
2569 * It appears there is an erratum which affects at least version 0x11
2570 * of I/O APIC (that's the 82093AA and cores integrated into various
2571 * chipsets). Under certain conditions a level-triggered interrupt is
2572 * erroneously delivered as edge-triggered one but the respective IRR
2573 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2574 * message but it will never arrive and further interrupts are blocked
2575 * from the source. The exact reason is so far unknown, but the
2576 * phenomenon was observed when two consecutive interrupt requests
2577 * from a given source get delivered to the same CPU and the source is
2578 * temporarily disabled in between.
2580 * A workaround is to simulate an EOI message manually. We achieve it
2581 * by setting the trigger mode to edge and then to level when the edge
2582 * trigger mode gets detected in the TMR of a local APIC for a
2583 * level-triggered interrupt. We mask the source for the time of the
2584 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2585 * The idea is from Manfred Spraul. --macro
2587 * Also in the case when cpu goes offline, fixup_irqs() will forward
2588 * any unhandled interrupt on the offlined cpu to the new cpu
2589 * destination that is handling the corresponding interrupt. This
2590 * interrupt forwarding is done via IPI's. Hence, in this case also
2591 * level-triggered io-apic interrupt will be seen as an edge
2592 * interrupt in the IRR. And we can't rely on the cpu's EOI
2593 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2594 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2595 * supporting EOI register, we do an explicit EOI to clear the
2596 * remote IRR and on IO-APIC's which don't have an EOI register,
2597 * we use the above logic (mask+edge followed by unmask+level) from
2598 * Manfred Spraul to clear the remote IRR.
2601 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2604 * We must acknowledge the irq before we move it or the acknowledge will
2605 * not propagate properly.
2610 * Tail end of clearing remote IRR bit (either by delivering the EOI
2611 * message via io-apic EOI register write or simulating it using
2612 * mask+edge followed by unnask+level logic) manually when the
2613 * level triggered interrupt is seen as the edge triggered interrupt
2616 if (!(v
& (1 << (i
& 0x1f)))) {
2617 atomic_inc(&irq_mis_count
);
2619 eoi_ioapic_irq(irq
, cfg
);
2622 ioapic_irqd_unmask(data
, cfg
, masked
);
2625 static struct irq_chip ioapic_chip __read_mostly
= {
2627 .irq_startup
= startup_ioapic_irq
,
2628 .irq_mask
= mask_ioapic_irq
,
2629 .irq_unmask
= unmask_ioapic_irq
,
2630 .irq_ack
= ack_apic_edge
,
2631 .irq_eoi
= ack_apic_level
,
2632 .irq_set_affinity
= native_ioapic_set_affinity
,
2633 .irq_retrigger
= ioapic_retrigger_irq
,
2634 .flags
= IRQCHIP_SKIP_SET_WAKE
,
2637 static inline void init_IO_APIC_traps(void)
2639 struct irq_cfg
*cfg
;
2642 for_each_active_irq(irq
) {
2644 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2646 * Hmm.. We don't have an entry for this,
2647 * so default to an old-fashioned 8259
2648 * interrupt if we can..
2650 if (irq
< nr_legacy_irqs())
2651 legacy_pic
->make_irq(irq
);
2653 /* Strange. Oh, well.. */
2654 irq_set_chip(irq
, &no_irq_chip
);
2660 * The local APIC irq-chip implementation:
2663 static void mask_lapic_irq(struct irq_data
*data
)
2667 v
= apic_read(APIC_LVT0
);
2668 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2671 static void unmask_lapic_irq(struct irq_data
*data
)
2675 v
= apic_read(APIC_LVT0
);
2676 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2679 static void ack_lapic_irq(struct irq_data
*data
)
2684 static struct irq_chip lapic_chip __read_mostly
= {
2685 .name
= "local-APIC",
2686 .irq_mask
= mask_lapic_irq
,
2687 .irq_unmask
= unmask_lapic_irq
,
2688 .irq_ack
= ack_lapic_irq
,
2691 static void lapic_register_intr(int irq
)
2693 irq_clear_status_flags(irq
, IRQ_LEVEL
);
2694 irq_set_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2699 * This looks a bit hackish but it's about the only one way of sending
2700 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2701 * not support the ExtINT mode, unfortunately. We need to send these
2702 * cycles as some i82489DX-based boards have glue logic that keeps the
2703 * 8259A interrupt line asserted until INTA. --macro
2705 static inline void __init
unlock_ExtINT_logic(void)
2708 struct IO_APIC_route_entry entry0
, entry1
;
2709 unsigned char save_control
, save_freq_select
;
2711 pin
= find_isa_irq_pin(8, mp_INT
);
2716 apic
= find_isa_irq_apic(8, mp_INT
);
2722 entry0
= ioapic_read_entry(apic
, pin
);
2723 clear_IO_APIC_pin(apic
, pin
);
2725 memset(&entry1
, 0, sizeof(entry1
));
2727 entry1
.dest_mode
= 0; /* physical delivery */
2728 entry1
.mask
= 0; /* unmask IRQ now */
2729 entry1
.dest
= hard_smp_processor_id();
2730 entry1
.delivery_mode
= dest_ExtINT
;
2731 entry1
.polarity
= entry0
.polarity
;
2735 ioapic_write_entry(apic
, pin
, entry1
);
2737 save_control
= CMOS_READ(RTC_CONTROL
);
2738 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2739 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2741 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2746 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2750 CMOS_WRITE(save_control
, RTC_CONTROL
);
2751 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2752 clear_IO_APIC_pin(apic
, pin
);
2754 ioapic_write_entry(apic
, pin
, entry0
);
2757 static int disable_timer_pin_1 __initdata
;
2758 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2759 static int __init
disable_timer_pin_setup(char *arg
)
2761 disable_timer_pin_1
= 1;
2764 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2767 * This code may look a bit paranoid, but it's supposed to cooperate with
2768 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2769 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2770 * fanatically on his truly buggy board.
2772 * FIXME: really need to revamp this for all platforms.
2774 static inline void __init
check_timer(void)
2776 struct irq_cfg
*cfg
= irq_cfg(0);
2777 int node
= cpu_to_node(0);
2778 int apic1
, pin1
, apic2
, pin2
;
2779 unsigned long flags
;
2782 local_irq_save(flags
);
2785 * get/set the timer IRQ vector:
2787 legacy_pic
->mask(0);
2788 assign_irq_vector(0, cfg
, apic
->target_cpus());
2791 * As IRQ0 is to be enabled in the 8259A, the virtual
2792 * wire has to be disabled in the local APIC. Also
2793 * timer interrupts need to be acknowledged manually in
2794 * the 8259A for the i82489DX when using the NMI
2795 * watchdog as that APIC treats NMIs as level-triggered.
2796 * The AEOI mode will finish them in the 8259A
2799 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2800 legacy_pic
->init(1);
2802 pin1
= find_isa_irq_pin(0, mp_INT
);
2803 apic1
= find_isa_irq_apic(0, mp_INT
);
2804 pin2
= ioapic_i8259
.pin
;
2805 apic2
= ioapic_i8259
.apic
;
2807 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2808 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2809 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2812 * Some BIOS writers are clueless and report the ExtINTA
2813 * I/O APIC input from the cascaded 8259A as the timer
2814 * interrupt input. So just in case, if only one pin
2815 * was found above, try it both directly and through the
2819 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2823 } else if (pin2
== -1) {
2830 * Ok, does IRQ0 through the IOAPIC work?
2833 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2834 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2836 /* for edge trigger, setup_ioapic_irq already
2837 * leave it unmasked.
2838 * so only need to unmask if it is level-trigger
2839 * do we really have level trigger timer?
2842 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2843 if (idx
!= -1 && irq_trigger(idx
))
2846 if (timer_irq_works()) {
2847 if (disable_timer_pin_1
> 0)
2848 clear_IO_APIC_pin(0, pin1
);
2851 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2852 local_irq_disable();
2853 clear_IO_APIC_pin(apic1
, pin1
);
2855 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2856 "8254 timer not connected to IO-APIC\n");
2858 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2859 "(IRQ0) through the 8259A ...\n");
2860 apic_printk(APIC_QUIET
, KERN_INFO
2861 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2863 * legacy devices should be connected to IO APIC #0
2865 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2866 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2867 legacy_pic
->unmask(0);
2868 if (timer_irq_works()) {
2869 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2873 * Cleanup, just in case ...
2875 local_irq_disable();
2876 legacy_pic
->mask(0);
2877 clear_IO_APIC_pin(apic2
, pin2
);
2878 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2881 apic_printk(APIC_QUIET
, KERN_INFO
2882 "...trying to set up timer as Virtual Wire IRQ...\n");
2884 lapic_register_intr(0);
2885 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2886 legacy_pic
->unmask(0);
2888 if (timer_irq_works()) {
2889 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2892 local_irq_disable();
2893 legacy_pic
->mask(0);
2894 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2895 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2897 apic_printk(APIC_QUIET
, KERN_INFO
2898 "...trying to set up timer as ExtINT IRQ...\n");
2900 legacy_pic
->init(0);
2901 legacy_pic
->make_irq(0);
2902 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2904 unlock_ExtINT_logic();
2906 if (timer_irq_works()) {
2907 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2910 local_irq_disable();
2911 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2912 if (x2apic_preenabled
)
2913 apic_printk(APIC_QUIET
, KERN_INFO
2914 "Perhaps problem with the pre-enabled x2apic mode\n"
2915 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2916 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2917 "report. Then try booting with the 'noapic' option.\n");
2919 local_irq_restore(flags
);
2923 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2924 * to devices. However there may be an I/O APIC pin available for
2925 * this interrupt regardless. The pin may be left unconnected, but
2926 * typically it will be reused as an ExtINT cascade interrupt for
2927 * the master 8259A. In the MPS case such a pin will normally be
2928 * reported as an ExtINT interrupt in the MP table. With ACPI
2929 * there is no provision for ExtINT interrupts, and in the absence
2930 * of an override it would be treated as an ordinary ISA I/O APIC
2931 * interrupt, that is edge-triggered and unmasked by default. We
2932 * used to do this, but it caused problems on some systems because
2933 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2934 * the same ExtINT cascade interrupt to drive the local APIC of the
2935 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2936 * the I/O APIC in all cases now. No actual device should request
2937 * it anyway. --macro
2939 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2941 static int mp_irqdomain_create(int ioapic
)
2944 int hwirqs
= mp_ioapic_pin_count(ioapic
);
2945 struct ioapic
*ip
= &ioapics
[ioapic
];
2946 struct ioapic_domain_cfg
*cfg
= &ip
->irqdomain_cfg
;
2947 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
2949 size
= sizeof(struct mp_pin_info
) * mp_ioapic_pin_count(ioapic
);
2950 ip
->pin_info
= kzalloc(size
, GFP_KERNEL
);
2954 if (cfg
->type
== IOAPIC_DOMAIN_INVALID
)
2957 ip
->irqdomain
= irq_domain_add_linear(cfg
->dev
, hwirqs
, cfg
->ops
,
2958 (void *)(long)ioapic
);
2959 if(!ip
->irqdomain
) {
2960 kfree(ip
->pin_info
);
2961 ip
->pin_info
= NULL
;
2965 if (cfg
->type
== IOAPIC_DOMAIN_LEGACY
||
2966 cfg
->type
== IOAPIC_DOMAIN_STRICT
)
2967 ioapic_dynirq_base
= max(ioapic_dynirq_base
,
2968 gsi_cfg
->gsi_end
+ 1);
2970 if (gsi_cfg
->gsi_base
== 0)
2971 irq_set_default_host(ip
->irqdomain
);
2976 static void ioapic_destroy_irqdomain(int idx
)
2978 if (ioapics
[idx
].irqdomain
) {
2979 irq_domain_remove(ioapics
[idx
].irqdomain
);
2980 ioapics
[idx
].irqdomain
= NULL
;
2982 kfree(ioapics
[idx
].pin_info
);
2983 ioapics
[idx
].pin_info
= NULL
;
2986 void __init
setup_IO_APIC(void)
2991 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2993 io_apic_irqs
= nr_legacy_irqs() ? ~PIC_IRQS
: ~0UL;
2995 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2996 for_each_ioapic(ioapic
)
2997 BUG_ON(mp_irqdomain_create(ioapic
));
3000 * Set up IO-APIC IRQ routing.
3002 x86_init
.mpparse
.setup_ioapic_ids();
3005 setup_IO_APIC_irqs();
3006 init_IO_APIC_traps();
3007 if (nr_legacy_irqs())
3010 ioapic_initialized
= 1;
3014 * Called after all the initialization is done. If we didn't find any
3015 * APIC bugs then we can allow the modify fast path
3018 static int __init
io_apic_bug_finalize(void)
3020 if (sis_apic_bug
== -1)
3025 late_initcall(io_apic_bug_finalize
);
3027 static void resume_ioapic_id(int ioapic_idx
)
3029 unsigned long flags
;
3030 union IO_APIC_reg_00 reg_00
;
3032 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3033 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
3034 if (reg_00
.bits
.ID
!= mpc_ioapic_id(ioapic_idx
)) {
3035 reg_00
.bits
.ID
= mpc_ioapic_id(ioapic_idx
);
3036 io_apic_write(ioapic_idx
, 0, reg_00
.raw
);
3038 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3041 static void ioapic_resume(void)
3045 for_each_ioapic_reverse(ioapic_idx
)
3046 resume_ioapic_id(ioapic_idx
);
3048 restore_ioapic_entries();
3051 static struct syscore_ops ioapic_syscore_ops
= {
3052 .suspend
= save_ioapic_entries
,
3053 .resume
= ioapic_resume
,
3056 static int __init
ioapic_init_ops(void)
3058 register_syscore_ops(&ioapic_syscore_ops
);
3063 device_initcall(ioapic_init_ops
);
3066 * Dynamic irq allocate and deallocation. Should be replaced by irq domains!
3068 int arch_setup_hwirq(unsigned int irq
, int node
)
3070 struct irq_cfg
*cfg
;
3071 unsigned long flags
;
3074 cfg
= alloc_irq_cfg(irq
, node
);
3078 raw_spin_lock_irqsave(&vector_lock
, flags
);
3079 ret
= __assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3080 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3083 irq_set_chip_data(irq
, cfg
);
3085 free_irq_cfg(irq
, cfg
);
3089 void arch_teardown_hwirq(unsigned int irq
)
3091 struct irq_cfg
*cfg
= irq_cfg(irq
);
3092 unsigned long flags
;
3094 free_remapped_irq(irq
);
3095 raw_spin_lock_irqsave(&vector_lock
, flags
);
3096 __clear_irq_vector(irq
, cfg
);
3097 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3098 free_irq_cfg(irq
, cfg
);
3102 * MSI message composition
3104 void native_compose_msi_msg(struct pci_dev
*pdev
,
3105 unsigned int irq
, unsigned int dest
,
3106 struct msi_msg
*msg
, u8 hpet_id
)
3108 struct irq_cfg
*cfg
= irq_cfg(irq
);
3110 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3112 if (x2apic_enabled())
3113 msg
->address_hi
|= MSI_ADDR_EXT_DEST_ID(dest
);
3117 ((apic
->irq_dest_mode
== 0) ?
3118 MSI_ADDR_DEST_MODE_PHYSICAL
:
3119 MSI_ADDR_DEST_MODE_LOGICAL
) |
3120 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3121 MSI_ADDR_REDIRECTION_CPU
:
3122 MSI_ADDR_REDIRECTION_LOWPRI
) |
3123 MSI_ADDR_DEST_ID(dest
);
3126 MSI_DATA_TRIGGER_EDGE
|
3127 MSI_DATA_LEVEL_ASSERT
|
3128 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3129 MSI_DATA_DELIVERY_FIXED
:
3130 MSI_DATA_DELIVERY_LOWPRI
) |
3131 MSI_DATA_VECTOR(cfg
->vector
);
3134 #ifdef CONFIG_PCI_MSI
3135 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
,
3136 struct msi_msg
*msg
, u8 hpet_id
)
3138 struct irq_cfg
*cfg
;
3146 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3150 err
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3151 apic
->target_cpus(), &dest
);
3155 x86_msi
.compose_msi_msg(pdev
, irq
, dest
, msg
, hpet_id
);
3161 msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3163 struct irq_cfg
*cfg
= data
->chip_data
;
3168 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
3172 __get_cached_msi_msg(data
->msi_desc
, &msg
);
3174 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3175 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3176 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3177 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3179 __pci_write_msi_msg(data
->msi_desc
, &msg
);
3181 return IRQ_SET_MASK_OK_NOCOPY
;
3185 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3186 * which implement the MSI or MSI-X Capability Structure.
3188 static struct irq_chip msi_chip
= {
3190 .irq_unmask
= pci_msi_unmask_irq
,
3191 .irq_mask
= pci_msi_mask_irq
,
3192 .irq_ack
= ack_apic_edge
,
3193 .irq_set_affinity
= msi_set_affinity
,
3194 .irq_retrigger
= ioapic_retrigger_irq
,
3195 .flags
= IRQCHIP_SKIP_SET_WAKE
,
3198 int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
,
3199 unsigned int irq_base
, unsigned int irq_offset
)
3201 struct irq_chip
*chip
= &msi_chip
;
3203 unsigned int irq
= irq_base
+ irq_offset
;
3206 ret
= msi_compose_msg(dev
, irq
, &msg
, -1);
3210 irq_set_msi_desc_off(irq_base
, irq_offset
, msidesc
);
3213 * MSI-X message is written per-IRQ, the offset is always 0.
3214 * MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
3217 pci_write_msi_msg(irq
, &msg
);
3219 setup_remapped_irq(irq
, irq_cfg(irq
), chip
);
3221 irq_set_chip_and_handler_name(irq
, chip
, handle_edge_irq
, "edge");
3223 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3228 int native_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3230 struct msi_desc
*msidesc
;
3234 /* Multiple MSI vectors only supported with interrupt remapping */
3235 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3238 node
= dev_to_node(&dev
->dev
);
3240 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3241 irq
= irq_alloc_hwirq(node
);
3245 ret
= setup_msi_irq(dev
, msidesc
, irq
, 0);
3247 irq_free_hwirq(irq
);
3255 void native_teardown_msi_irq(unsigned int irq
)
3257 irq_free_hwirq(irq
);
3260 #ifdef CONFIG_DMAR_TABLE
3262 dmar_msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
3265 struct irq_cfg
*cfg
= data
->chip_data
;
3266 unsigned int dest
, irq
= data
->irq
;
3270 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
3274 dmar_msi_read(irq
, &msg
);
3276 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3277 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3278 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3279 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3280 msg
.address_hi
= MSI_ADDR_BASE_HI
| MSI_ADDR_EXT_DEST_ID(dest
);
3282 dmar_msi_write(irq
, &msg
);
3284 return IRQ_SET_MASK_OK_NOCOPY
;
3287 static struct irq_chip dmar_msi_type
= {
3289 .irq_unmask
= dmar_msi_unmask
,
3290 .irq_mask
= dmar_msi_mask
,
3291 .irq_ack
= ack_apic_edge
,
3292 .irq_set_affinity
= dmar_msi_set_affinity
,
3293 .irq_retrigger
= ioapic_retrigger_irq
,
3294 .flags
= IRQCHIP_SKIP_SET_WAKE
,
3297 int arch_setup_dmar_msi(unsigned int irq
)
3302 ret
= msi_compose_msg(NULL
, irq
, &msg
, -1);
3305 dmar_msi_write(irq
, &msg
);
3306 irq_set_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3312 #ifdef CONFIG_HPET_TIMER
3314 static int hpet_msi_set_affinity(struct irq_data
*data
,
3315 const struct cpumask
*mask
, bool force
)
3317 struct irq_cfg
*cfg
= data
->chip_data
;
3322 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
3326 hpet_msi_read(data
->handler_data
, &msg
);
3328 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3329 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3330 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3331 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3333 hpet_msi_write(data
->handler_data
, &msg
);
3335 return IRQ_SET_MASK_OK_NOCOPY
;
3338 static struct irq_chip hpet_msi_type
= {
3340 .irq_unmask
= hpet_msi_unmask
,
3341 .irq_mask
= hpet_msi_mask
,
3342 .irq_ack
= ack_apic_edge
,
3343 .irq_set_affinity
= hpet_msi_set_affinity
,
3344 .irq_retrigger
= ioapic_retrigger_irq
,
3345 .flags
= IRQCHIP_SKIP_SET_WAKE
,
3348 int default_setup_hpet_msi(unsigned int irq
, unsigned int id
)
3350 struct irq_chip
*chip
= &hpet_msi_type
;
3354 ret
= msi_compose_msg(NULL
, irq
, &msg
, id
);
3358 hpet_msi_write(irq_get_handler_data(irq
), &msg
);
3359 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
3360 setup_remapped_irq(irq
, irq_cfg(irq
), chip
);
3362 irq_set_chip_and_handler_name(irq
, chip
, handle_edge_irq
, "edge");
3367 #endif /* CONFIG_PCI_MSI */
3369 * Hypertransport interrupt support
3371 #ifdef CONFIG_HT_IRQ
3373 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3375 struct ht_irq_msg msg
;
3376 fetch_ht_irq_msg(irq
, &msg
);
3378 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3379 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3381 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3382 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3384 write_ht_irq_msg(irq
, &msg
);
3388 ht_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3390 struct irq_cfg
*cfg
= data
->chip_data
;
3394 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
3398 target_ht_irq(data
->irq
, dest
, cfg
->vector
);
3399 return IRQ_SET_MASK_OK_NOCOPY
;
3402 static struct irq_chip ht_irq_chip
= {
3404 .irq_mask
= mask_ht_irq
,
3405 .irq_unmask
= unmask_ht_irq
,
3406 .irq_ack
= ack_apic_edge
,
3407 .irq_set_affinity
= ht_set_affinity
,
3408 .irq_retrigger
= ioapic_retrigger_irq
,
3409 .flags
= IRQCHIP_SKIP_SET_WAKE
,
3412 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3414 struct irq_cfg
*cfg
;
3415 struct ht_irq_msg msg
;
3423 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3427 err
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3428 apic
->target_cpus(), &dest
);
3432 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3436 HT_IRQ_LOW_DEST_ID(dest
) |
3437 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3438 ((apic
->irq_dest_mode
== 0) ?
3439 HT_IRQ_LOW_DM_PHYSICAL
:
3440 HT_IRQ_LOW_DM_LOGICAL
) |
3441 HT_IRQ_LOW_RQEOI_EDGE
|
3442 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3443 HT_IRQ_LOW_MT_FIXED
:
3444 HT_IRQ_LOW_MT_ARBITRATED
) |
3445 HT_IRQ_LOW_IRQ_MASKED
;
3447 write_ht_irq_msg(irq
, &msg
);
3449 irq_set_chip_and_handler_name(irq
, &ht_irq_chip
,
3450 handle_edge_irq
, "edge");
3452 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3456 #endif /* CONFIG_HT_IRQ */
3459 io_apic_setup_irq_pin(unsigned int irq
, int node
, struct io_apic_irq_attr
*attr
)
3461 struct irq_cfg
*cfg
= alloc_irq_and_cfg_at(irq
, node
);
3466 ret
= __add_pin_to_irq_node(cfg
, node
, attr
->ioapic
, attr
->ioapic_pin
);
3468 setup_ioapic_irq(irq
, cfg
, attr
);
3472 static int io_apic_get_redir_entries(int ioapic
)
3474 union IO_APIC_reg_01 reg_01
;
3475 unsigned long flags
;
3477 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3478 reg_01
.raw
= io_apic_read(ioapic
, 1);
3479 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3481 /* The register returns the maximum index redir index
3482 * supported, which is one less than the total number of redir
3485 return reg_01
.bits
.entries
+ 1;
3488 unsigned int arch_dynirq_lower_bound(unsigned int from
)
3491 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
3492 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
3494 return ioapic_initialized
? ioapic_dynirq_base
: gsi_top
;
3497 int __init
arch_probe_nr_irqs(void)
3501 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3502 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3504 nr
= (gsi_top
+ nr_legacy_irqs()) + 8 * nr_cpu_ids
;
3505 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3507 * for MSI and HT dyn irq
3517 #ifdef CONFIG_X86_32
3518 static int io_apic_get_unique_id(int ioapic
, int apic_id
)
3520 union IO_APIC_reg_00 reg_00
;
3521 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3523 unsigned long flags
;
3527 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3528 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3529 * supports up to 16 on one shared APIC bus.
3531 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3532 * advantage of new APIC bus architecture.
3535 if (physids_empty(apic_id_map
))
3536 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
3538 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3539 reg_00
.raw
= io_apic_read(ioapic
, 0);
3540 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3542 if (apic_id
>= get_physical_broadcast()) {
3543 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3544 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3545 apic_id
= reg_00
.bits
.ID
;
3549 * Every APIC in a system must have a unique ID or we get lots of nice
3550 * 'stuck on smp_invalidate_needed IPI wait' messages.
3552 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
3554 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3555 if (!apic
->check_apicid_used(&apic_id_map
, i
))
3559 if (i
== get_physical_broadcast())
3560 panic("Max apic_id exceeded!\n");
3562 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3563 "trying %d\n", ioapic
, apic_id
, i
);
3568 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
3569 physids_or(apic_id_map
, apic_id_map
, tmp
);
3571 if (reg_00
.bits
.ID
!= apic_id
) {
3572 reg_00
.bits
.ID
= apic_id
;
3574 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3575 io_apic_write(ioapic
, 0, reg_00
.raw
);
3576 reg_00
.raw
= io_apic_read(ioapic
, 0);
3577 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3580 if (reg_00
.bits
.ID
!= apic_id
) {
3581 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
3587 apic_printk(APIC_VERBOSE
, KERN_INFO
3588 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3593 static u8
io_apic_unique_id(int idx
, u8 id
)
3595 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
3596 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
3597 return io_apic_get_unique_id(idx
, id
);
3602 static u8
io_apic_unique_id(int idx
, u8 id
)
3604 union IO_APIC_reg_00 reg_00
;
3605 DECLARE_BITMAP(used
, 256);
3606 unsigned long flags
;
3610 bitmap_zero(used
, 256);
3612 __set_bit(mpc_ioapic_id(i
), used
);
3614 /* Hand out the requested id if available */
3615 if (!test_bit(id
, used
))
3619 * Read the current id from the ioapic and keep it if
3622 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3623 reg_00
.raw
= io_apic_read(idx
, 0);
3624 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3625 new_id
= reg_00
.bits
.ID
;
3626 if (!test_bit(new_id
, used
)) {
3627 apic_printk(APIC_VERBOSE
, KERN_INFO
3628 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
3634 * Get the next free id and write it to the ioapic.
3636 new_id
= find_first_zero_bit(used
, 256);
3637 reg_00
.bits
.ID
= new_id
;
3638 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3639 io_apic_write(idx
, 0, reg_00
.raw
);
3640 reg_00
.raw
= io_apic_read(idx
, 0);
3641 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3643 BUG_ON(reg_00
.bits
.ID
!= new_id
);
3649 static int io_apic_get_version(int ioapic
)
3651 union IO_APIC_reg_01 reg_01
;
3652 unsigned long flags
;
3654 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3655 reg_01
.raw
= io_apic_read(ioapic
, 1);
3656 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3658 return reg_01
.bits
.version
;
3661 int acpi_get_override_irq(u32 gsi
, int *trigger
, int *polarity
)
3663 int ioapic
, pin
, idx
;
3665 if (skip_ioapic_setup
)
3668 ioapic
= mp_find_ioapic(gsi
);
3672 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
3676 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
3680 *trigger
= irq_trigger(idx
);
3681 *polarity
= irq_polarity(idx
);
3686 * This function currently is only a helper for the i386 smp boot process where
3687 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3688 * so mask in all cases should simply be apic->target_cpus()
3691 void __init
setup_ioapic_dest(void)
3693 int pin
, ioapic
, irq
, irq_entry
;
3694 const struct cpumask
*mask
;
3695 struct irq_data
*idata
;
3697 if (skip_ioapic_setup
== 1)
3700 for_each_ioapic_pin(ioapic
, pin
) {
3701 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3702 if (irq_entry
== -1)
3705 irq
= pin_2_irq(irq_entry
, ioapic
, pin
, 0);
3706 if (irq
< 0 || !mp_init_irq_at_boot(ioapic
, irq
))
3709 idata
= irq_get_irq_data(irq
);
3712 * Honour affinities which have been set in early boot
3714 if (!irqd_can_balance(idata
) || irqd_affinity_was_set(idata
))
3715 mask
= idata
->affinity
;
3717 mask
= apic
->target_cpus();
3719 x86_io_apic_ops
.set_affinity(idata
, mask
, false);
3725 #define IOAPIC_RESOURCE_NAME_SIZE 11
3727 static struct resource
*ioapic_resources
;
3729 static struct resource
* __init
ioapic_setup_resources(void)
3732 struct resource
*res
;
3741 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3744 mem
= alloc_bootmem(n
);
3747 mem
+= sizeof(struct resource
) * num
;
3750 for_each_ioapic(i
) {
3751 res
[num
].name
= mem
;
3752 res
[num
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3753 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
3754 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3756 ioapics
[i
].iomem_res
= res
;
3759 ioapic_resources
= res
;
3764 void __init
native_io_apic_init_mappings(void)
3766 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3767 struct resource
*ioapic_res
;
3770 ioapic_res
= ioapic_setup_resources();
3771 for_each_ioapic(i
) {
3772 if (smp_found_config
) {
3773 ioapic_phys
= mpc_ioapic_addr(i
);
3774 #ifdef CONFIG_X86_32
3777 "WARNING: bogus zero IO-APIC "
3778 "address found in MPTABLE, "
3779 "disabling IO/APIC support!\n");
3780 smp_found_config
= 0;
3781 skip_ioapic_setup
= 1;
3782 goto fake_ioapic_page
;
3786 #ifdef CONFIG_X86_32
3789 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
3790 ioapic_phys
= __pa(ioapic_phys
);
3792 set_fixmap_nocache(idx
, ioapic_phys
);
3793 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
3794 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
3798 ioapic_res
->start
= ioapic_phys
;
3799 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
3804 void __init
ioapic_insert_resources(void)
3807 struct resource
*r
= ioapic_resources
;
3812 "IO APIC resources couldn't be allocated.\n");
3816 for_each_ioapic(i
) {
3817 insert_resource(&iomem_resource
, r
);
3822 int mp_find_ioapic(u32 gsi
)
3826 if (nr_ioapics
== 0)
3829 /* Find the IOAPIC that manages this GSI. */
3830 for_each_ioapic(i
) {
3831 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(i
);
3832 if (gsi
>= gsi_cfg
->gsi_base
&& gsi
<= gsi_cfg
->gsi_end
)
3836 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
3840 int mp_find_ioapic_pin(int ioapic
, u32 gsi
)
3842 struct mp_ioapic_gsi
*gsi_cfg
;
3844 if (WARN_ON(ioapic
< 0))
3847 gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
3848 if (WARN_ON(gsi
> gsi_cfg
->gsi_end
))
3851 return gsi
- gsi_cfg
->gsi_base
;
3854 static int bad_ioapic_register(int idx
)
3856 union IO_APIC_reg_00 reg_00
;
3857 union IO_APIC_reg_01 reg_01
;
3858 union IO_APIC_reg_02 reg_02
;
3860 reg_00
.raw
= io_apic_read(idx
, 0);
3861 reg_01
.raw
= io_apic_read(idx
, 1);
3862 reg_02
.raw
= io_apic_read(idx
, 2);
3864 if (reg_00
.raw
== -1 && reg_01
.raw
== -1 && reg_02
.raw
== -1) {
3865 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3866 mpc_ioapic_addr(idx
));
3873 static int find_free_ioapic_entry(void)
3877 for (idx
= 0; idx
< MAX_IO_APICS
; idx
++)
3878 if (ioapics
[idx
].nr_registers
== 0)
3881 return MAX_IO_APICS
;
3885 * mp_register_ioapic - Register an IOAPIC device
3886 * @id: hardware IOAPIC ID
3887 * @address: physical address of IOAPIC register area
3888 * @gsi_base: base of GSI associated with the IOAPIC
3889 * @cfg: configuration information for the IOAPIC
3891 int mp_register_ioapic(int id
, u32 address
, u32 gsi_base
,
3892 struct ioapic_domain_cfg
*cfg
)
3894 bool hotplug
= !!ioapic_initialized
;
3895 struct mp_ioapic_gsi
*gsi_cfg
;
3896 int idx
, ioapic
, entries
;
3900 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
3903 for_each_ioapic(ioapic
)
3904 if (ioapics
[ioapic
].mp_config
.apicaddr
== address
) {
3905 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
3910 idx
= find_free_ioapic_entry();
3911 if (idx
>= MAX_IO_APICS
) {
3912 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3917 ioapics
[idx
].mp_config
.type
= MP_IOAPIC
;
3918 ioapics
[idx
].mp_config
.flags
= MPC_APIC_USABLE
;
3919 ioapics
[idx
].mp_config
.apicaddr
= address
;
3921 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
3922 if (bad_ioapic_register(idx
)) {
3923 clear_fixmap(FIX_IO_APIC_BASE_0
+ idx
);
3927 ioapics
[idx
].mp_config
.apicid
= io_apic_unique_id(idx
, id
);
3928 ioapics
[idx
].mp_config
.apicver
= io_apic_get_version(idx
);
3931 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3932 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3934 entries
= io_apic_get_redir_entries(idx
);
3935 gsi_end
= gsi_base
+ entries
- 1;
3936 for_each_ioapic(ioapic
) {
3937 gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
3938 if ((gsi_base
>= gsi_cfg
->gsi_base
&&
3939 gsi_base
<= gsi_cfg
->gsi_end
) ||
3940 (gsi_end
>= gsi_cfg
->gsi_base
&&
3941 gsi_end
<= gsi_cfg
->gsi_end
)) {
3942 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
3944 gsi_cfg
->gsi_base
, gsi_cfg
->gsi_end
);
3945 clear_fixmap(FIX_IO_APIC_BASE_0
+ idx
);
3949 gsi_cfg
= mp_ioapic_gsi_routing(idx
);
3950 gsi_cfg
->gsi_base
= gsi_base
;
3951 gsi_cfg
->gsi_end
= gsi_end
;
3953 ioapics
[idx
].irqdomain
= NULL
;
3954 ioapics
[idx
].irqdomain_cfg
= *cfg
;
3957 * If mp_register_ioapic() is called during early boot stage when
3958 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
3959 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
3962 if (mp_irqdomain_create(idx
)) {
3963 clear_fixmap(FIX_IO_APIC_BASE_0
+ idx
);
3966 alloc_ioapic_saved_registers(idx
);
3969 if (gsi_cfg
->gsi_end
>= gsi_top
)
3970 gsi_top
= gsi_cfg
->gsi_end
+ 1;
3971 if (nr_ioapics
<= idx
)
3972 nr_ioapics
= idx
+ 1;
3974 /* Set nr_registers to mark entry present */
3975 ioapics
[idx
].nr_registers
= entries
;
3977 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3978 idx
, mpc_ioapic_id(idx
),
3979 mpc_ioapic_ver(idx
), mpc_ioapic_addr(idx
),
3980 gsi_cfg
->gsi_base
, gsi_cfg
->gsi_end
);
3985 int mp_unregister_ioapic(u32 gsi_base
)
3989 struct mp_pin_info
*pin_info
;
3991 for_each_ioapic(ioapic
)
3992 if (ioapics
[ioapic
].gsi_config
.gsi_base
== gsi_base
) {
3997 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base
);
4001 for_each_pin(ioapic
, pin
) {
4002 pin_info
= mp_pin_info(ioapic
, pin
);
4003 if (pin_info
->count
) {
4004 pr_warn("pin%d on IOAPIC%d is still in use.\n",
4010 /* Mark entry not present */
4011 ioapics
[ioapic
].nr_registers
= 0;
4012 ioapic_destroy_irqdomain(ioapic
);
4013 free_ioapic_saved_registers(ioapic
);
4014 if (ioapics
[ioapic
].iomem_res
)
4015 release_resource(ioapics
[ioapic
].iomem_res
);
4016 clear_fixmap(FIX_IO_APIC_BASE_0
+ ioapic
);
4017 memset(&ioapics
[ioapic
], 0, sizeof(ioapics
[ioapic
]));
4022 int mp_ioapic_registered(u32 gsi_base
)
4026 for_each_ioapic(ioapic
)
4027 if (ioapics
[ioapic
].gsi_config
.gsi_base
== gsi_base
)
4033 int mp_irqdomain_map(struct irq_domain
*domain
, unsigned int virq
,
4034 irq_hw_number_t hwirq
)
4036 int ioapic
= (int)(long)domain
->host_data
;
4037 struct mp_pin_info
*info
= mp_pin_info(ioapic
, hwirq
);
4038 struct io_apic_irq_attr attr
;
4040 /* Get default attribute if not set by caller yet */
4042 u32 gsi
= mp_pin_to_gsi(ioapic
, hwirq
);
4044 if (acpi_get_override_irq(gsi
, &info
->trigger
,
4045 &info
->polarity
) < 0) {
4047 * PCI interrupts are always polarity one level
4053 info
->node
= NUMA_NO_NODE
;
4056 * setup_IO_APIC_irqs() programs all legacy IRQs with default
4057 * trigger and polarity attributes. Don't set the flag for that
4058 * case so the first legacy IRQ user could reprogram the pin
4059 * with real trigger and polarity attributes.
4061 if (virq
>= nr_legacy_irqs() || info
->count
)
4064 set_io_apic_irq_attr(&attr
, ioapic
, hwirq
, info
->trigger
,
4067 return io_apic_setup_irq_pin(virq
, info
->node
, &attr
);
4070 void mp_irqdomain_unmap(struct irq_domain
*domain
, unsigned int virq
)
4072 struct irq_data
*data
= irq_get_irq_data(virq
);
4073 struct irq_cfg
*cfg
= irq_cfg(virq
);
4074 int ioapic
= (int)(long)domain
->host_data
;
4075 int pin
= (int)data
->hwirq
;
4077 ioapic_mask_entry(ioapic
, pin
);
4078 __remove_pin_from_irq(cfg
, ioapic
, pin
);
4079 WARN_ON(cfg
->irq_2_pin
!= NULL
);
4080 arch_teardown_hwirq(virq
);
4083 int mp_set_gsi_attr(u32 gsi
, int trigger
, int polarity
, int node
)
4087 struct mp_pin_info
*info
;
4089 ioapic
= mp_find_ioapic(gsi
);
4093 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
4094 info
= mp_pin_info(ioapic
, pin
);
4095 trigger
= trigger
? 1 : 0;
4096 polarity
= polarity
? 1 : 0;
4098 mutex_lock(&ioapic_mutex
);
4100 info
->trigger
= trigger
;
4101 info
->polarity
= polarity
;
4104 } else if (info
->trigger
!= trigger
|| info
->polarity
!= polarity
) {
4107 mutex_unlock(&ioapic_mutex
);
4112 /* Enable IOAPIC early just for system timer */
4113 void __init
pre_init_apic_IRQ0(void)
4115 struct io_apic_irq_attr attr
= { 0, 0, 0, 0 };
4117 printk(KERN_INFO
"Early APIC setup for system timer0\n");
4119 physid_set_mask_of_physid(boot_cpu_physical_apicid
,
4120 &phys_cpu_present_map
);
4124 io_apic_setup_irq_pin(0, 0, &attr
);
4125 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,