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ath9k_hw: Add support for AR946/8x chipsets.
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / ath / ath9k / hw.c
blob4ace66c9d59d6fbb46a373de260ec4366e51d316
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20
21 #include "hw.h"
22 #include "hw-ops.h"
23 #include "rc.h"
24 #include "ar9003_mac.h"
25
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
27
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
32
33 static int __init ath9k_init(void)
34 {
35 return 0;
36 }
37 module_init(ath9k_init);
38
39 static void __exit ath9k_exit(void)
40 {
41 return;
42 }
43 module_exit(ath9k_exit);
44
45 /* Private hardware callbacks */
46
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48 {
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50 }
51
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55 }
56
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59 {
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61 }
62
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64 {
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69 }
70
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72 {
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
89
90 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
91 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
92 clockrate = 117;
93 else if (!ah->curchan) /* should really check for CCK instead */
94 clockrate = ATH9K_CLOCK_RATE_CCK;
95 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
96 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
97 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
98 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
99 else
100 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
101
102 if (conf_is_ht40(conf))
103 clockrate *= 2;
104
105 if (ah->curchan) {
106 if (IS_CHAN_HALF_RATE(ah->curchan))
107 clockrate /= 2;
108 if (IS_CHAN_QUARTER_RATE(ah->curchan))
109 clockrate /= 4;
110 }
111
112 common->clockrate = clockrate;
113 }
114
115 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
116 {
117 struct ath_common *common = ath9k_hw_common(ah);
118
119 return usecs * common->clockrate;
120 }
121
122 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
123 {
124 int i;
125
126 BUG_ON(timeout < AH_TIME_QUANTUM);
127
128 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
129 if ((REG_READ(ah, reg) & mask) == val)
130 return true;
131
132 udelay(AH_TIME_QUANTUM);
133 }
134
135 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
136 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
137 timeout, reg, REG_READ(ah, reg), mask, val);
138
139 return false;
140 }
141 EXPORT_SYMBOL(ath9k_hw_wait);
142
143 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
144 int column, unsigned int *writecnt)
145 {
146 int r;
147
148 ENABLE_REGWRITE_BUFFER(ah);
149 for (r = 0; r < array->ia_rows; r++) {
150 REG_WRITE(ah, INI_RA(array, r, 0),
151 INI_RA(array, r, column));
152 DO_DELAY(*writecnt);
153 }
154 REGWRITE_BUFFER_FLUSH(ah);
155 }
156
157 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
158 {
159 u32 retval;
160 int i;
161
162 for (i = 0, retval = 0; i < n; i++) {
163 retval = (retval << 1) | (val & 1);
164 val >>= 1;
165 }
166 return retval;
167 }
168
169 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
170 u8 phy, int kbps,
171 u32 frameLen, u16 rateix,
172 bool shortPreamble)
173 {
174 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
175
176 if (kbps == 0)
177 return 0;
178
179 switch (phy) {
180 case WLAN_RC_PHY_CCK:
181 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
182 if (shortPreamble)
183 phyTime >>= 1;
184 numBits = frameLen << 3;
185 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
186 break;
187 case WLAN_RC_PHY_OFDM:
188 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
189 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
190 numBits = OFDM_PLCP_BITS + (frameLen << 3);
191 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
192 txTime = OFDM_SIFS_TIME_QUARTER
193 + OFDM_PREAMBLE_TIME_QUARTER
194 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
195 } else if (ah->curchan &&
196 IS_CHAN_HALF_RATE(ah->curchan)) {
197 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
198 numBits = OFDM_PLCP_BITS + (frameLen << 3);
199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
200 txTime = OFDM_SIFS_TIME_HALF +
201 OFDM_PREAMBLE_TIME_HALF
202 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
203 } else {
204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
205 numBits = OFDM_PLCP_BITS + (frameLen << 3);
206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
208 + (numSymbols * OFDM_SYMBOL_TIME);
209 }
210 break;
211 default:
212 ath_err(ath9k_hw_common(ah),
213 "Unknown phy %u (rate ix %u)\n", phy, rateix);
214 txTime = 0;
215 break;
216 }
217
218 return txTime;
219 }
220 EXPORT_SYMBOL(ath9k_hw_computetxtime);
221
222 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
223 struct ath9k_channel *chan,
224 struct chan_centers *centers)
225 {
226 int8_t extoff;
227
228 if (!IS_CHAN_HT40(chan)) {
229 centers->ctl_center = centers->ext_center =
230 centers->synth_center = chan->channel;
231 return;
232 }
233
234 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
235 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
236 centers->synth_center =
237 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
238 extoff = 1;
239 } else {
240 centers->synth_center =
241 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
242 extoff = -1;
243 }
244
245 centers->ctl_center =
246 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
247 /* 25 MHz spacing is supported by hw but not on upper layers */
248 centers->ext_center =
249 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
250 }
251
252 /******************/
253 /* Chip Revisions */
254 /******************/
255
256 static void ath9k_hw_read_revisions(struct ath_hw *ah)
257 {
258 u32 val;
259
260 switch (ah->hw_version.devid) {
261 case AR5416_AR9100_DEVID:
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
263 break;
264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
266 if (ah->get_mac_revision) {
267 ah->hw_version.macRev = ah->get_mac_revision();
268 } else {
269 val = REG_READ(ah, AR_SREV);
270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
271 }
272 return;
273 case AR9300_DEVID_AR9340:
274 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
275 val = REG_READ(ah, AR_SREV);
276 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
277 return;
278 }
279
280 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
281
282 if (val == 0xFF) {
283 val = REG_READ(ah, AR_SREV);
284 ah->hw_version.macVersion =
285 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
286 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
287 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
288 } else {
289 if (!AR_SREV_9100(ah))
290 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
291
292 ah->hw_version.macRev = val & AR_SREV_REVISION;
293
294 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
295 ah->is_pciexpress = true;
296 }
297 }
298
299 /************************************/
300 /* HW Attach, Detach, Init Routines */
301 /************************************/
302
303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
304 {
305 if (!AR_SREV_5416(ah))
306 return;
307
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
317
318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
319 }
320
321 static void ath9k_hw_aspm_init(struct ath_hw *ah)
322 {
323 struct ath_common *common = ath9k_hw_common(ah);
324
325 if (common->bus_ops->aspm_init)
326 common->bus_ops->aspm_init(common);
327 }
328
329 /* This should work for all families including legacy */
330 static bool ath9k_hw_chip_test(struct ath_hw *ah)
331 {
332 struct ath_common *common = ath9k_hw_common(ah);
333 u32 regAddr[2] = { AR_STA_ID0 };
334 u32 regHold[2];
335 static const u32 patternData[4] = {
336 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
337 };
338 int i, j, loop_max;
339
340 if (!AR_SREV_9300_20_OR_LATER(ah)) {
341 loop_max = 2;
342 regAddr[1] = AR_PHY_BASE + (8 << 2);
343 } else
344 loop_max = 1;
345
346 for (i = 0; i < loop_max; i++) {
347 u32 addr = regAddr[i];
348 u32 wrData, rdData;
349
350 regHold[i] = REG_READ(ah, addr);
351 for (j = 0; j < 0x100; j++) {
352 wrData = (j << 16) | j;
353 REG_WRITE(ah, addr, wrData);
354 rdData = REG_READ(ah, addr);
355 if (rdData != wrData) {
356 ath_err(common,
357 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
358 addr, wrData, rdData);
359 return false;
360 }
361 }
362 for (j = 0; j < 4; j++) {
363 wrData = patternData[j];
364 REG_WRITE(ah, addr, wrData);
365 rdData = REG_READ(ah, addr);
366 if (wrData != rdData) {
367 ath_err(common,
368 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
369 addr, wrData, rdData);
370 return false;
371 }
372 }
373 REG_WRITE(ah, regAddr[i], regHold[i]);
374 }
375 udelay(100);
376
377 return true;
378 }
379
380 static void ath9k_hw_init_config(struct ath_hw *ah)
381 {
382 int i;
383
384 ah->config.dma_beacon_response_time = 2;
385 ah->config.sw_beacon_response_time = 10;
386 ah->config.additional_swba_backoff = 0;
387 ah->config.ack_6mb = 0x0;
388 ah->config.cwm_ignore_extcca = 0;
389 ah->config.pcie_clock_req = 0;
390 ah->config.pcie_waen = 0;
391 ah->config.analog_shiftreg = 1;
392 ah->config.enable_ani = true;
393
394 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
395 ah->config.spurchans[i][0] = AR_NO_SPUR;
396 ah->config.spurchans[i][1] = AR_NO_SPUR;
397 }
398
399 /* PAPRD needs some more work to be enabled */
400 ah->config.paprd_disable = 1;
401
402 ah->config.rx_intr_mitigation = true;
403 ah->config.pcieSerDesWrite = true;
404
405 /*
406 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
407 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
408 * This means we use it for all AR5416 devices, and the few
409 * minor PCI AR9280 devices out there.
410 *
411 * Serialization is required because these devices do not handle
412 * well the case of two concurrent reads/writes due to the latency
413 * involved. During one read/write another read/write can be issued
414 * on another CPU while the previous read/write may still be working
415 * on our hardware, if we hit this case the hardware poops in a loop.
416 * We prevent this by serializing reads and writes.
417 *
418 * This issue is not present on PCI-Express devices or pre-AR5416
419 * devices (legacy, 802.11abg).
420 */
421 if (num_possible_cpus() > 1)
422 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
423 }
424
425 static void ath9k_hw_init_defaults(struct ath_hw *ah)
426 {
427 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
428
429 regulatory->country_code = CTRY_DEFAULT;
430 regulatory->power_limit = MAX_RATE_POWER;
431 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
432
433 ah->hw_version.magic = AR5416_MAGIC;
434 ah->hw_version.subvendorid = 0;
435
436 ah->atim_window = 0;
437 ah->sta_id1_defaults =
438 AR_STA_ID1_CRPT_MIC_ENABLE |
439 AR_STA_ID1_MCAST_KSRCH;
440 if (AR_SREV_9100(ah))
441 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
442 ah->enable_32kHz_clock = DONT_USE_32KHZ;
443 ah->slottime = ATH9K_SLOT_TIME_9;
444 ah->globaltxtimeout = (u32) -1;
445 ah->power_mode = ATH9K_PM_UNDEFINED;
446 }
447
448 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
449 {
450 struct ath_common *common = ath9k_hw_common(ah);
451 u32 sum;
452 int i;
453 u16 eeval;
454 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
455
456 sum = 0;
457 for (i = 0; i < 3; i++) {
458 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
459 sum += eeval;
460 common->macaddr[2 * i] = eeval >> 8;
461 common->macaddr[2 * i + 1] = eeval & 0xff;
462 }
463 if (sum == 0 || sum == 0xffff * 3)
464 return -EADDRNOTAVAIL;
465
466 return 0;
467 }
468
469 static int ath9k_hw_post_init(struct ath_hw *ah)
470 {
471 struct ath_common *common = ath9k_hw_common(ah);
472 int ecode;
473
474 if (common->bus_ops->ath_bus_type != ATH_USB) {
475 if (!ath9k_hw_chip_test(ah))
476 return -ENODEV;
477 }
478
479 if (!AR_SREV_9300_20_OR_LATER(ah)) {
480 ecode = ar9002_hw_rf_claim(ah);
481 if (ecode != 0)
482 return ecode;
483 }
484
485 ecode = ath9k_hw_eeprom_init(ah);
486 if (ecode != 0)
487 return ecode;
488
489 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
490 "Eeprom VER: %d, REV: %d\n",
491 ah->eep_ops->get_eeprom_ver(ah),
492 ah->eep_ops->get_eeprom_rev(ah));
493
494 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
495 if (ecode) {
496 ath_err(ath9k_hw_common(ah),
497 "Failed allocating banks for external radio\n");
498 ath9k_hw_rf_free_ext_banks(ah);
499 return ecode;
500 }
501
502 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
503 ath9k_hw_ani_setup(ah);
504 ath9k_hw_ani_init(ah);
505 }
506
507 return 0;
508 }
509
510 static void ath9k_hw_attach_ops(struct ath_hw *ah)
511 {
512 if (AR_SREV_9300_20_OR_LATER(ah))
513 ar9003_hw_attach_ops(ah);
514 else
515 ar9002_hw_attach_ops(ah);
516 }
517
518 /* Called for all hardware families */
519 static int __ath9k_hw_init(struct ath_hw *ah)
520 {
521 struct ath_common *common = ath9k_hw_common(ah);
522 int r = 0;
523
524 ath9k_hw_read_revisions(ah);
525
526 /*
527 * Read back AR_WA into a permanent copy and set bits 14 and 17.
528 * We need to do this to avoid RMW of this register. We cannot
529 * read the reg when chip is asleep.
530 */
531 ah->WARegVal = REG_READ(ah, AR_WA);
532 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
533 AR_WA_ASPM_TIMER_BASED_DISABLE);
534
535 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
536 ath_err(common, "Couldn't reset chip\n");
537 return -EIO;
538 }
539
540 ath9k_hw_init_defaults(ah);
541 ath9k_hw_init_config(ah);
542
543 ath9k_hw_attach_ops(ah);
544
545 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
546 ath_err(common, "Couldn't wakeup chip\n");
547 return -EIO;
548 }
549
550 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
551 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
552 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
553 !ah->is_pciexpress)) {
554 ah->config.serialize_regmode =
555 SER_REG_MODE_ON;
556 } else {
557 ah->config.serialize_regmode =
558 SER_REG_MODE_OFF;
559 }
560 }
561
562 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
563 ah->config.serialize_regmode);
564
565 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
566 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
567 else
568 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
569
570 switch (ah->hw_version.macVersion) {
571 case AR_SREV_VERSION_5416_PCI:
572 case AR_SREV_VERSION_5416_PCIE:
573 case AR_SREV_VERSION_9160:
574 case AR_SREV_VERSION_9100:
575 case AR_SREV_VERSION_9280:
576 case AR_SREV_VERSION_9285:
577 case AR_SREV_VERSION_9287:
578 case AR_SREV_VERSION_9271:
579 case AR_SREV_VERSION_9300:
580 case AR_SREV_VERSION_9330:
581 case AR_SREV_VERSION_9485:
582 case AR_SREV_VERSION_9340:
583 case AR_SREV_VERSION_9480:
584 break;
585 default:
586 ath_err(common,
587 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
588 ah->hw_version.macVersion, ah->hw_version.macRev);
589 return -EOPNOTSUPP;
590 }
591
592 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
593 AR_SREV_9330(ah))
594 ah->is_pciexpress = false;
595
596 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
597 ath9k_hw_init_cal_settings(ah);
598
599 ah->ani_function = ATH9K_ANI_ALL;
600 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
601 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
602 if (!AR_SREV_9300_20_OR_LATER(ah))
603 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
604
605 ath9k_hw_init_mode_regs(ah);
606
607 if (!ah->is_pciexpress)
608 ath9k_hw_disablepcie(ah);
609
610 if (!AR_SREV_9300_20_OR_LATER(ah))
611 ar9002_hw_cck_chan14_spread(ah);
612
613 r = ath9k_hw_post_init(ah);
614 if (r)
615 return r;
616
617 ath9k_hw_init_mode_gain_regs(ah);
618 r = ath9k_hw_fill_cap_info(ah);
619 if (r)
620 return r;
621
622 if (ah->is_pciexpress)
623 ath9k_hw_aspm_init(ah);
624
625 r = ath9k_hw_init_macaddr(ah);
626 if (r) {
627 ath_err(common, "Failed to initialize MAC address\n");
628 return r;
629 }
630
631 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
632 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
633 else
634 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
635
636 if (AR_SREV_9330(ah))
637 ah->bb_watchdog_timeout_ms = 85;
638 else
639 ah->bb_watchdog_timeout_ms = 25;
640
641 common->state = ATH_HW_INITIALIZED;
642
643 return 0;
644 }
645
646 int ath9k_hw_init(struct ath_hw *ah)
647 {
648 int ret;
649 struct ath_common *common = ath9k_hw_common(ah);
650
651 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
652 switch (ah->hw_version.devid) {
653 case AR5416_DEVID_PCI:
654 case AR5416_DEVID_PCIE:
655 case AR5416_AR9100_DEVID:
656 case AR9160_DEVID_PCI:
657 case AR9280_DEVID_PCI:
658 case AR9280_DEVID_PCIE:
659 case AR9285_DEVID_PCIE:
660 case AR9287_DEVID_PCI:
661 case AR9287_DEVID_PCIE:
662 case AR2427_DEVID_PCIE:
663 case AR9300_DEVID_PCIE:
664 case AR9300_DEVID_AR9485_PCIE:
665 case AR9300_DEVID_AR9330:
666 case AR9300_DEVID_AR9340:
667 case AR9300_DEVID_AR9580:
668 case AR9300_DEVID_AR9480:
669 break;
670 default:
671 if (common->bus_ops->ath_bus_type == ATH_USB)
672 break;
673 ath_err(common, "Hardware device ID 0x%04x not supported\n",
674 ah->hw_version.devid);
675 return -EOPNOTSUPP;
676 }
677
678 ret = __ath9k_hw_init(ah);
679 if (ret) {
680 ath_err(common,
681 "Unable to initialize hardware; initialization status: %d\n",
682 ret);
683 return ret;
684 }
685
686 return 0;
687 }
688 EXPORT_SYMBOL(ath9k_hw_init);
689
690 static void ath9k_hw_init_qos(struct ath_hw *ah)
691 {
692 ENABLE_REGWRITE_BUFFER(ah);
693
694 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
695 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
696
697 REG_WRITE(ah, AR_QOS_NO_ACK,
698 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
699 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
700 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
701
702 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
703 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
704 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
705 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
706 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
707
708 REGWRITE_BUFFER_FLUSH(ah);
709 }
710
711 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
712 {
713 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
714 udelay(100);
715 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
716
717 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
718 udelay(100);
719
720 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
721 }
722 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
723
724 static void ath9k_hw_init_pll(struct ath_hw *ah,
725 struct ath9k_channel *chan)
726 {
727 u32 pll;
728
729 if (AR_SREV_9485(ah)) {
730
731 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
732 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
733 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
734 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
735 AR_CH0_DPLL2_KD, 0x40);
736 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
737 AR_CH0_DPLL2_KI, 0x4);
738
739 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
740 AR_CH0_BB_DPLL1_REFDIV, 0x5);
741 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
742 AR_CH0_BB_DPLL1_NINI, 0x58);
743 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
744 AR_CH0_BB_DPLL1_NFRAC, 0x0);
745
746 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
747 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
748 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
749 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
750 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
751 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
752
753 /* program BB PLL phase_shift to 0x6 */
754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
755 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
756
757 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
758 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
759 udelay(1000);
760 } else if (AR_SREV_9330(ah)) {
761 u32 ddr_dpll2, pll_control2, kd;
762
763 if (ah->is_clk_25mhz) {
764 ddr_dpll2 = 0x18e82f01;
765 pll_control2 = 0xe04a3d;
766 kd = 0x1d;
767 } else {
768 ddr_dpll2 = 0x19e82f01;
769 pll_control2 = 0x886666;
770 kd = 0x3d;
771 }
772
773 /* program DDR PLL ki and kd value */
774 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
775
776 /* program DDR PLL phase_shift */
777 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
778 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
779
780 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
781 udelay(1000);
782
783 /* program refdiv, nint, frac to RTC register */
784 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
785
786 /* program BB PLL kd and ki value */
787 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
788 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
789
790 /* program BB PLL phase_shift */
791 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
792 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
793 } else if (AR_SREV_9340(ah)) {
794 u32 regval, pll2_divint, pll2_divfrac, refdiv;
795
796 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
797 udelay(1000);
798
799 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
800 udelay(100);
801
802 if (ah->is_clk_25mhz) {
803 pll2_divint = 0x54;
804 pll2_divfrac = 0x1eb85;
805 refdiv = 3;
806 } else {
807 pll2_divint = 88;
808 pll2_divfrac = 0;
809 refdiv = 5;
810 }
811
812 regval = REG_READ(ah, AR_PHY_PLL_MODE);
813 regval |= (0x1 << 16);
814 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
815 udelay(100);
816
817 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
818 (pll2_divint << 18) | pll2_divfrac);
819 udelay(100);
820
821 regval = REG_READ(ah, AR_PHY_PLL_MODE);
822 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
823 (0x4 << 26) | (0x18 << 19);
824 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
825 REG_WRITE(ah, AR_PHY_PLL_MODE,
826 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
827 udelay(1000);
828 }
829
830 pll = ath9k_hw_compute_pll_control(ah, chan);
831
832 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
833
834 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
835 udelay(1000);
836
837 /* Switch the core clock for ar9271 to 117Mhz */
838 if (AR_SREV_9271(ah)) {
839 udelay(500);
840 REG_WRITE(ah, 0x50040, 0x304);
841 }
842
843 udelay(RTC_PLL_SETTLE_DELAY);
844
845 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
846
847 if (AR_SREV_9340(ah)) {
848 if (ah->is_clk_25mhz) {
849 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
850 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
851 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
852 } else {
853 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
854 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
855 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
856 }
857 udelay(100);
858 }
859 }
860
861 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
862 enum nl80211_iftype opmode)
863 {
864 u32 sync_default = AR_INTR_SYNC_DEFAULT;
865 u32 imr_reg = AR_IMR_TXERR |
866 AR_IMR_TXURN |
867 AR_IMR_RXERR |
868 AR_IMR_RXORN |
869 AR_IMR_BCNMISC;
870
871 if (AR_SREV_9340(ah))
872 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
873
874 if (AR_SREV_9300_20_OR_LATER(ah)) {
875 imr_reg |= AR_IMR_RXOK_HP;
876 if (ah->config.rx_intr_mitigation)
877 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
878 else
879 imr_reg |= AR_IMR_RXOK_LP;
880
881 } else {
882 if (ah->config.rx_intr_mitigation)
883 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
884 else
885 imr_reg |= AR_IMR_RXOK;
886 }
887
888 if (ah->config.tx_intr_mitigation)
889 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
890 else
891 imr_reg |= AR_IMR_TXOK;
892
893 if (opmode == NL80211_IFTYPE_AP)
894 imr_reg |= AR_IMR_MIB;
895
896 ENABLE_REGWRITE_BUFFER(ah);
897
898 REG_WRITE(ah, AR_IMR, imr_reg);
899 ah->imrs2_reg |= AR_IMR_S2_GTT;
900 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
901
902 if (!AR_SREV_9100(ah)) {
903 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
904 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
905 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
906 }
907
908 REGWRITE_BUFFER_FLUSH(ah);
909
910 if (AR_SREV_9300_20_OR_LATER(ah)) {
911 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
912 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
913 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
914 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
915 }
916 }
917
918 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
919 {
920 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
921 val = min(val, (u32) 0xFFFF);
922 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
923 }
924
925 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
926 {
927 u32 val = ath9k_hw_mac_to_clks(ah, us);
928 val = min(val, (u32) 0xFFFF);
929 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
930 }
931
932 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
933 {
934 u32 val = ath9k_hw_mac_to_clks(ah, us);
935 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
936 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
937 }
938
939 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
940 {
941 u32 val = ath9k_hw_mac_to_clks(ah, us);
942 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
943 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
944 }
945
946 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
947 {
948 if (tu > 0xFFFF) {
949 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
950 "bad global tx timeout %u\n", tu);
951 ah->globaltxtimeout = (u32) -1;
952 return false;
953 } else {
954 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
955 ah->globaltxtimeout = tu;
956 return true;
957 }
958 }
959
960 void ath9k_hw_init_global_settings(struct ath_hw *ah)
961 {
962 struct ath_common *common = ath9k_hw_common(ah);
963 struct ieee80211_conf *conf = &common->hw->conf;
964 const struct ath9k_channel *chan = ah->curchan;
965 int acktimeout, ctstimeout;
966 int slottime;
967 int sifstime;
968 int rx_lat = 0, tx_lat = 0, eifs = 0;
969 u32 reg;
970
971 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
972 ah->misc_mode);
973
974 if (!chan)
975 return;
976
977 if (ah->misc_mode != 0)
978 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
979
980 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
981 rx_lat = 41;
982 else
983 rx_lat = 37;
984 tx_lat = 54;
985
986 if (IS_CHAN_HALF_RATE(chan)) {
987 eifs = 175;
988 rx_lat *= 2;
989 tx_lat *= 2;
990 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
991 tx_lat += 11;
992
993 slottime = 13;
994 sifstime = 32;
995 } else if (IS_CHAN_QUARTER_RATE(chan)) {
996 eifs = 340;
997 rx_lat = (rx_lat * 4) - 1;
998 tx_lat *= 4;
999 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1000 tx_lat += 22;
1001
1002 slottime = 21;
1003 sifstime = 64;
1004 } else {
1005 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1006 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1007 reg = AR_USEC_ASYNC_FIFO;
1008 } else {
1009 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1010 common->clockrate;
1011 reg = REG_READ(ah, AR_USEC);
1012 }
1013 rx_lat = MS(reg, AR_USEC_RX_LAT);
1014 tx_lat = MS(reg, AR_USEC_TX_LAT);
1015
1016 slottime = ah->slottime;
1017 if (IS_CHAN_5GHZ(chan))
1018 sifstime = 16;
1019 else
1020 sifstime = 10;
1021 }
1022
1023 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1024 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
1025 ctstimeout = acktimeout;
1026
1027 /*
1028 * Workaround for early ACK timeouts, add an offset to match the
1029 * initval's 64us ack timeout value.
1030 * This was initially only meant to work around an issue with delayed
1031 * BA frames in some implementations, but it has been found to fix ACK
1032 * timeout issues in other cases as well.
1033 */
1034 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1035 acktimeout += 64 - sifstime - ah->slottime;
1036
1037 ath9k_hw_set_sifs_time(ah, sifstime);
1038 ath9k_hw_setslottime(ah, slottime);
1039 ath9k_hw_set_ack_timeout(ah, acktimeout);
1040 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1041 if (ah->globaltxtimeout != (u32) -1)
1042 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1043
1044 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1045 REG_RMW(ah, AR_USEC,
1046 (common->clockrate - 1) |
1047 SM(rx_lat, AR_USEC_RX_LAT) |
1048 SM(tx_lat, AR_USEC_TX_LAT),
1049 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1050
1051 }
1052 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1053
1054 void ath9k_hw_deinit(struct ath_hw *ah)
1055 {
1056 struct ath_common *common = ath9k_hw_common(ah);
1057
1058 if (common->state < ATH_HW_INITIALIZED)
1059 goto free_hw;
1060
1061 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1062
1063 free_hw:
1064 ath9k_hw_rf_free_ext_banks(ah);
1065 }
1066 EXPORT_SYMBOL(ath9k_hw_deinit);
1067
1068 /*******/
1069 /* INI */
1070 /*******/
1071
1072 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1073 {
1074 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1075
1076 if (IS_CHAN_B(chan))
1077 ctl |= CTL_11B;
1078 else if (IS_CHAN_G(chan))
1079 ctl |= CTL_11G;
1080 else
1081 ctl |= CTL_11A;
1082
1083 return ctl;
1084 }
1085
1086 /****************************************/
1087 /* Reset and Channel Switching Routines */
1088 /****************************************/
1089
1090 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1091 {
1092 struct ath_common *common = ath9k_hw_common(ah);
1093
1094 ENABLE_REGWRITE_BUFFER(ah);
1095
1096 /*
1097 * set AHB_MODE not to do cacheline prefetches
1098 */
1099 if (!AR_SREV_9300_20_OR_LATER(ah))
1100 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1101
1102 /*
1103 * let mac dma reads be in 128 byte chunks
1104 */
1105 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1106
1107 REGWRITE_BUFFER_FLUSH(ah);
1108
1109 /*
1110 * Restore TX Trigger Level to its pre-reset value.
1111 * The initial value depends on whether aggregation is enabled, and is
1112 * adjusted whenever underruns are detected.
1113 */
1114 if (!AR_SREV_9300_20_OR_LATER(ah))
1115 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1116
1117 ENABLE_REGWRITE_BUFFER(ah);
1118
1119 /*
1120 * let mac dma writes be in 128 byte chunks
1121 */
1122 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1123
1124 /*
1125 * Setup receive FIFO threshold to hold off TX activities
1126 */
1127 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1128
1129 if (AR_SREV_9300_20_OR_LATER(ah)) {
1130 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1131 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1132
1133 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1134 ah->caps.rx_status_len);
1135 }
1136
1137 /*
1138 * reduce the number of usable entries in PCU TXBUF to avoid
1139 * wrap around issues.
1140 */
1141 if (AR_SREV_9285(ah)) {
1142 /* For AR9285 the number of Fifos are reduced to half.
1143 * So set the usable tx buf size also to half to
1144 * avoid data/delimiter underruns
1145 */
1146 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1147 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1148 } else if (!AR_SREV_9271(ah)) {
1149 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1150 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1151 }
1152
1153 REGWRITE_BUFFER_FLUSH(ah);
1154
1155 if (AR_SREV_9300_20_OR_LATER(ah))
1156 ath9k_hw_reset_txstatus_ring(ah);
1157 }
1158
1159 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1160 {
1161 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1162 u32 set = AR_STA_ID1_KSRCH_MODE;
1163
1164 switch (opmode) {
1165 case NL80211_IFTYPE_ADHOC:
1166 case NL80211_IFTYPE_MESH_POINT:
1167 set |= AR_STA_ID1_ADHOC;
1168 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1169 break;
1170 case NL80211_IFTYPE_AP:
1171 set |= AR_STA_ID1_STA_AP;
1172 /* fall through */
1173 case NL80211_IFTYPE_STATION:
1174 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1175 break;
1176 default:
1177 if (!ah->is_monitoring)
1178 set = 0;
1179 break;
1180 }
1181 REG_RMW(ah, AR_STA_ID1, set, mask);
1182 }
1183
1184 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1185 u32 *coef_mantissa, u32 *coef_exponent)
1186 {
1187 u32 coef_exp, coef_man;
1188
1189 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1190 if ((coef_scaled >> coef_exp) & 0x1)
1191 break;
1192
1193 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1194
1195 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1196
1197 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1198 *coef_exponent = coef_exp - 16;
1199 }
1200
1201 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1202 {
1203 u32 rst_flags;
1204 u32 tmpReg;
1205
1206 if (AR_SREV_9100(ah)) {
1207 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1208 AR_RTC_DERIVED_CLK_PERIOD, 1);
1209 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1210 }
1211
1212 ENABLE_REGWRITE_BUFFER(ah);
1213
1214 if (AR_SREV_9300_20_OR_LATER(ah)) {
1215 REG_WRITE(ah, AR_WA, ah->WARegVal);
1216 udelay(10);
1217 }
1218
1219 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1220 AR_RTC_FORCE_WAKE_ON_INT);
1221
1222 if (AR_SREV_9100(ah)) {
1223 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1224 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1225 } else {
1226 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1227 if (tmpReg &
1228 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1229 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1230 u32 val;
1231 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1232
1233 val = AR_RC_HOSTIF;
1234 if (!AR_SREV_9300_20_OR_LATER(ah))
1235 val |= AR_RC_AHB;
1236 REG_WRITE(ah, AR_RC, val);
1237
1238 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1239 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1240
1241 rst_flags = AR_RTC_RC_MAC_WARM;
1242 if (type == ATH9K_RESET_COLD)
1243 rst_flags |= AR_RTC_RC_MAC_COLD;
1244 }
1245
1246 if (AR_SREV_9330(ah)) {
1247 int npend = 0;
1248 int i;
1249
1250 /* AR9330 WAR:
1251 * call external reset function to reset WMAC if:
1252 * - doing a cold reset
1253 * - we have pending frames in the TX queues
1254 */
1255
1256 for (i = 0; i < AR_NUM_QCU; i++) {
1257 npend = ath9k_hw_numtxpending(ah, i);
1258 if (npend)
1259 break;
1260 }
1261
1262 if (ah->external_reset &&
1263 (npend || type == ATH9K_RESET_COLD)) {
1264 int reset_err = 0;
1265
1266 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1267 "reset MAC via external reset\n");
1268
1269 reset_err = ah->external_reset();
1270 if (reset_err) {
1271 ath_err(ath9k_hw_common(ah),
1272 "External reset failed, err=%d\n",
1273 reset_err);
1274 return false;
1275 }
1276
1277 REG_WRITE(ah, AR_RTC_RESET, 1);
1278 }
1279 }
1280
1281 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1282
1283 REGWRITE_BUFFER_FLUSH(ah);
1284
1285 udelay(50);
1286
1287 REG_WRITE(ah, AR_RTC_RC, 0);
1288 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1289 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1290 "RTC stuck in MAC reset\n");
1291 return false;
1292 }
1293
1294 if (!AR_SREV_9100(ah))
1295 REG_WRITE(ah, AR_RC, 0);
1296
1297 if (AR_SREV_9100(ah))
1298 udelay(50);
1299
1300 return true;
1301 }
1302
1303 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1304 {
1305 ENABLE_REGWRITE_BUFFER(ah);
1306
1307 if (AR_SREV_9300_20_OR_LATER(ah)) {
1308 REG_WRITE(ah, AR_WA, ah->WARegVal);
1309 udelay(10);
1310 }
1311
1312 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1313 AR_RTC_FORCE_WAKE_ON_INT);
1314
1315 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1316 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1317
1318 REG_WRITE(ah, AR_RTC_RESET, 0);
1319
1320 REGWRITE_BUFFER_FLUSH(ah);
1321
1322 if (!AR_SREV_9300_20_OR_LATER(ah))
1323 udelay(2);
1324
1325 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1326 REG_WRITE(ah, AR_RC, 0);
1327
1328 REG_WRITE(ah, AR_RTC_RESET, 1);
1329
1330 if (!ath9k_hw_wait(ah,
1331 AR_RTC_STATUS,
1332 AR_RTC_STATUS_M,
1333 AR_RTC_STATUS_ON,
1334 AH_WAIT_TIMEOUT)) {
1335 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1336 "RTC not waking up\n");
1337 return false;
1338 }
1339
1340 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1341 }
1342
1343 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1344 {
1345
1346 if (AR_SREV_9300_20_OR_LATER(ah)) {
1347 REG_WRITE(ah, AR_WA, ah->WARegVal);
1348 udelay(10);
1349 }
1350
1351 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1352 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1353
1354 switch (type) {
1355 case ATH9K_RESET_POWER_ON:
1356 return ath9k_hw_set_reset_power_on(ah);
1357 case ATH9K_RESET_WARM:
1358 case ATH9K_RESET_COLD:
1359 return ath9k_hw_set_reset(ah, type);
1360 default:
1361 return false;
1362 }
1363 }
1364
1365 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1366 struct ath9k_channel *chan)
1367 {
1368 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1369 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1370 return false;
1371 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1372 return false;
1373
1374 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1375 return false;
1376
1377 ah->chip_fullsleep = false;
1378 ath9k_hw_init_pll(ah, chan);
1379 ath9k_hw_set_rfmode(ah, chan);
1380
1381 return true;
1382 }
1383
1384 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1385 struct ath9k_channel *chan)
1386 {
1387 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1388 struct ath_common *common = ath9k_hw_common(ah);
1389 struct ieee80211_channel *channel = chan->chan;
1390 u32 qnum;
1391 int r;
1392
1393 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1394 if (ath9k_hw_numtxpending(ah, qnum)) {
1395 ath_dbg(common, ATH_DBG_QUEUE,
1396 "Transmit frames pending on queue %d\n", qnum);
1397 return false;
1398 }
1399 }
1400
1401 if (!ath9k_hw_rfbus_req(ah)) {
1402 ath_err(common, "Could not kill baseband RX\n");
1403 return false;
1404 }
1405
1406 ath9k_hw_set_channel_regs(ah, chan);
1407
1408 r = ath9k_hw_rf_set_freq(ah, chan);
1409 if (r) {
1410 ath_err(common, "Failed to set channel\n");
1411 return false;
1412 }
1413 ath9k_hw_set_clockrate(ah);
1414
1415 ah->eep_ops->set_txpower(ah, chan,
1416 ath9k_regd_get_ctl(regulatory, chan),
1417 channel->max_antenna_gain * 2,
1418 channel->max_power * 2,
1419 min((u32) MAX_RATE_POWER,
1420 (u32) regulatory->power_limit), false);
1421
1422 ath9k_hw_rfbus_done(ah);
1423
1424 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1425 ath9k_hw_set_delta_slope(ah, chan);
1426
1427 ath9k_hw_spur_mitigate_freq(ah, chan);
1428
1429 return true;
1430 }
1431
1432 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1433 {
1434 u32 gpio_mask = ah->gpio_mask;
1435 int i;
1436
1437 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1438 if (!(gpio_mask & 1))
1439 continue;
1440
1441 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1442 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1443 }
1444 }
1445
1446 bool ath9k_hw_check_alive(struct ath_hw *ah)
1447 {
1448 int count = 50;
1449 u32 reg;
1450
1451 if (AR_SREV_9285_12_OR_LATER(ah))
1452 return true;
1453
1454 do {
1455 reg = REG_READ(ah, AR_OBS_BUS_1);
1456
1457 if ((reg & 0x7E7FFFEF) == 0x00702400)
1458 continue;
1459
1460 switch (reg & 0x7E000B00) {
1461 case 0x1E000000:
1462 case 0x52000B00:
1463 case 0x18000B00:
1464 continue;
1465 default:
1466 return true;
1467 }
1468 } while (count-- > 0);
1469
1470 return false;
1471 }
1472 EXPORT_SYMBOL(ath9k_hw_check_alive);
1473
1474 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1475 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1476 {
1477 struct ath_common *common = ath9k_hw_common(ah);
1478 u32 saveLedState;
1479 struct ath9k_channel *curchan = ah->curchan;
1480 u32 saveDefAntenna;
1481 u32 macStaId1;
1482 u64 tsf = 0;
1483 int i, r;
1484
1485 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1486 return -EIO;
1487
1488 if (curchan && !ah->chip_fullsleep)
1489 ath9k_hw_getnf(ah, curchan);
1490
1491 ah->caldata = caldata;
1492 if (caldata &&
1493 (chan->channel != caldata->channel ||
1494 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1495 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1496 /* Operating channel changed, reset channel calibration data */
1497 memset(caldata, 0, sizeof(*caldata));
1498 ath9k_init_nfcal_hist_buffer(ah, chan);
1499 }
1500 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1501
1502 if (bChannelChange &&
1503 (ah->chip_fullsleep != true) &&
1504 (ah->curchan != NULL) &&
1505 (chan->channel != ah->curchan->channel) &&
1506 ((chan->channelFlags & CHANNEL_ALL) ==
1507 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1508 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1509
1510 if (ath9k_hw_channel_change(ah, chan)) {
1511 ath9k_hw_loadnf(ah, ah->curchan);
1512 ath9k_hw_start_nfcal(ah, true);
1513 if (AR_SREV_9271(ah))
1514 ar9002_hw_load_ani_reg(ah, chan);
1515 return 0;
1516 }
1517 }
1518
1519 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1520 if (saveDefAntenna == 0)
1521 saveDefAntenna = 1;
1522
1523 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1524
1525 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1526 if (AR_SREV_9100(ah) ||
1527 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1528 tsf = ath9k_hw_gettsf64(ah);
1529
1530 saveLedState = REG_READ(ah, AR_CFG_LED) &
1531 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1532 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1533
1534 ath9k_hw_mark_phy_inactive(ah);
1535
1536 ah->paprd_table_write_done = false;
1537
1538 /* Only required on the first reset */
1539 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1540 REG_WRITE(ah,
1541 AR9271_RESET_POWER_DOWN_CONTROL,
1542 AR9271_RADIO_RF_RST);
1543 udelay(50);
1544 }
1545
1546 if (!ath9k_hw_chip_reset(ah, chan)) {
1547 ath_err(common, "Chip reset failed\n");
1548 return -EINVAL;
1549 }
1550
1551 /* Only required on the first reset */
1552 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1553 ah->htc_reset_init = false;
1554 REG_WRITE(ah,
1555 AR9271_RESET_POWER_DOWN_CONTROL,
1556 AR9271_GATE_MAC_CTL);
1557 udelay(50);
1558 }
1559
1560 /* Restore TSF */
1561 if (tsf)
1562 ath9k_hw_settsf64(ah, tsf);
1563
1564 if (AR_SREV_9280_20_OR_LATER(ah))
1565 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1566
1567 if (!AR_SREV_9300_20_OR_LATER(ah))
1568 ar9002_hw_enable_async_fifo(ah);
1569
1570 r = ath9k_hw_process_ini(ah, chan);
1571 if (r)
1572 return r;
1573
1574 /*
1575 * Some AR91xx SoC devices frequently fail to accept TSF writes
1576 * right after the chip reset. When that happens, write a new
1577 * value after the initvals have been applied, with an offset
1578 * based on measured time difference
1579 */
1580 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1581 tsf += 1500;
1582 ath9k_hw_settsf64(ah, tsf);
1583 }
1584
1585 /* Setup MFP options for CCMP */
1586 if (AR_SREV_9280_20_OR_LATER(ah)) {
1587 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1588 * frames when constructing CCMP AAD. */
1589 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1590 0xc7ff);
1591 ah->sw_mgmt_crypto = false;
1592 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1593 /* Disable hardware crypto for management frames */
1594 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1595 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1596 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1597 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1598 ah->sw_mgmt_crypto = true;
1599 } else
1600 ah->sw_mgmt_crypto = true;
1601
1602 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1603 ath9k_hw_set_delta_slope(ah, chan);
1604
1605 ath9k_hw_spur_mitigate_freq(ah, chan);
1606 ah->eep_ops->set_board_values(ah, chan);
1607
1608 ENABLE_REGWRITE_BUFFER(ah);
1609
1610 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1611 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1612 | macStaId1
1613 | AR_STA_ID1_RTS_USE_DEF
1614 | (ah->config.
1615 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1616 | ah->sta_id1_defaults);
1617 ath_hw_setbssidmask(common);
1618 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1619 ath9k_hw_write_associd(ah);
1620 REG_WRITE(ah, AR_ISR, ~0);
1621 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1622
1623 REGWRITE_BUFFER_FLUSH(ah);
1624
1625 ath9k_hw_set_operating_mode(ah, ah->opmode);
1626
1627 r = ath9k_hw_rf_set_freq(ah, chan);
1628 if (r)
1629 return r;
1630
1631 ath9k_hw_set_clockrate(ah);
1632
1633 ENABLE_REGWRITE_BUFFER(ah);
1634
1635 for (i = 0; i < AR_NUM_DCU; i++)
1636 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1637
1638 REGWRITE_BUFFER_FLUSH(ah);
1639
1640 ah->intr_txqs = 0;
1641 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1642 ath9k_hw_resettxqueue(ah, i);
1643
1644 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1645 ath9k_hw_ani_cache_ini_regs(ah);
1646 ath9k_hw_init_qos(ah);
1647
1648 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1649 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1650
1651 ath9k_hw_init_global_settings(ah);
1652
1653 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1654 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1655 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1656 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1657 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1658 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1659 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1660 }
1661
1662 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1663
1664 ath9k_hw_set_dma(ah);
1665
1666 REG_WRITE(ah, AR_OBS, 8);
1667
1668 if (ah->config.rx_intr_mitigation) {
1669 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1670 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1671 }
1672
1673 if (ah->config.tx_intr_mitigation) {
1674 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1675 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1676 }
1677
1678 ath9k_hw_init_bb(ah, chan);
1679
1680 if (!ath9k_hw_init_cal(ah, chan))
1681 return -EIO;
1682
1683 ENABLE_REGWRITE_BUFFER(ah);
1684
1685 ath9k_hw_restore_chainmask(ah);
1686 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1687
1688 REGWRITE_BUFFER_FLUSH(ah);
1689
1690 /*
1691 * For big endian systems turn on swapping for descriptors
1692 */
1693 if (AR_SREV_9100(ah)) {
1694 u32 mask;
1695 mask = REG_READ(ah, AR_CFG);
1696 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1697 ath_dbg(common, ATH_DBG_RESET,
1698 "CFG Byte Swap Set 0x%x\n", mask);
1699 } else {
1700 mask =
1701 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1702 REG_WRITE(ah, AR_CFG, mask);
1703 ath_dbg(common, ATH_DBG_RESET,
1704 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1705 }
1706 } else {
1707 if (common->bus_ops->ath_bus_type == ATH_USB) {
1708 /* Configure AR9271 target WLAN */
1709 if (AR_SREV_9271(ah))
1710 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1711 else
1712 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1713 }
1714 #ifdef __BIG_ENDIAN
1715 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1716 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1717 else
1718 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1719 #endif
1720 }
1721
1722 if (ah->btcoex_hw.enabled)
1723 ath9k_hw_btcoex_enable(ah);
1724
1725 if (AR_SREV_9300_20_OR_LATER(ah)) {
1726 ar9003_hw_bb_watchdog_config(ah);
1727
1728 ar9003_hw_disable_phy_restart(ah);
1729 }
1730
1731 ath9k_hw_apply_gpio_override(ah);
1732
1733 return 0;
1734 }
1735 EXPORT_SYMBOL(ath9k_hw_reset);
1736
1737 /******************************/
1738 /* Power Management (Chipset) */
1739 /******************************/
1740
1741 /*
1742 * Notify Power Mgt is disabled in self-generated frames.
1743 * If requested, force chip to sleep.
1744 */
1745 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1746 {
1747 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1748 if (setChip) {
1749 if (AR_SREV_9480(ah)) {
1750 REG_WRITE(ah, AR_TIMER_MODE,
1751 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
1752 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
1753 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
1754 REG_WRITE(ah, AR_SLP32_INC,
1755 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
1756 /* xxx Required for WLAN only case ? */
1757 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1758 udelay(100);
1759 }
1760
1761 /*
1762 * Clear the RTC force wake bit to allow the
1763 * mac to go to sleep.
1764 */
1765 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1766
1767 if (AR_SREV_9480(ah))
1768 udelay(100);
1769
1770 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1771 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1772
1773 /* Shutdown chip. Active low */
1774 if (!AR_SREV_5416(ah) &&
1775 !AR_SREV_9271(ah) && !AR_SREV_9480_10(ah)) {
1776 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1777 udelay(2);
1778 }
1779 }
1780
1781 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1782 if (!AR_SREV_9480(ah))
1783 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1784 }
1785
1786 /*
1787 * Notify Power Management is enabled in self-generating
1788 * frames. If request, set power mode of chip to
1789 * auto/normal. Duration in units of 128us (1/8 TU).
1790 */
1791 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1792 {
1793 u32 val;
1794
1795 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1796 if (setChip) {
1797 struct ath9k_hw_capabilities *pCap = &ah->caps;
1798
1799 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1800 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1801 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1802 AR_RTC_FORCE_WAKE_ON_INT);
1803 } else {
1804
1805 /* When chip goes into network sleep, it could be waken
1806 * up by MCI_INT interrupt caused by BT's HW messages
1807 * (LNA_xxx, CONT_xxx) which chould be in a very fast
1808 * rate (~100us). This will cause chip to leave and
1809 * re-enter network sleep mode frequently, which in
1810 * consequence will have WLAN MCI HW to generate lots of
1811 * SYS_WAKING and SYS_SLEEPING messages which will make
1812 * BT CPU to busy to process.
1813 */
1814 if (AR_SREV_9480(ah)) {
1815 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
1816 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
1817 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
1818 }
1819 /*
1820 * Clear the RTC force wake bit to allow the
1821 * mac to go to sleep.
1822 */
1823 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1824 AR_RTC_FORCE_WAKE_EN);
1825
1826 if (AR_SREV_9480(ah))
1827 udelay(30);
1828 }
1829 }
1830
1831 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1832 if (AR_SREV_9300_20_OR_LATER(ah))
1833 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1834 }
1835
1836 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1837 {
1838 u32 val;
1839 int i;
1840
1841 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1842 if (AR_SREV_9300_20_OR_LATER(ah)) {
1843 REG_WRITE(ah, AR_WA, ah->WARegVal);
1844 udelay(10);
1845 }
1846
1847 if (setChip) {
1848 if ((REG_READ(ah, AR_RTC_STATUS) &
1849 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1850 if (ath9k_hw_set_reset_reg(ah,
1851 ATH9K_RESET_POWER_ON) != true) {
1852 return false;
1853 }
1854 if (!AR_SREV_9300_20_OR_LATER(ah))
1855 ath9k_hw_init_pll(ah, NULL);
1856 }
1857 if (AR_SREV_9100(ah))
1858 REG_SET_BIT(ah, AR_RTC_RESET,
1859 AR_RTC_RESET_EN);
1860
1861 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1862 AR_RTC_FORCE_WAKE_EN);
1863 udelay(50);
1864
1865 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1866 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1867 if (val == AR_RTC_STATUS_ON)
1868 break;
1869 udelay(50);
1870 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1871 AR_RTC_FORCE_WAKE_EN);
1872 }
1873 if (i == 0) {
1874 ath_err(ath9k_hw_common(ah),
1875 "Failed to wakeup in %uus\n",
1876 POWER_UP_TIME / 20);
1877 return false;
1878 }
1879 }
1880
1881 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1882
1883 return true;
1884 }
1885
1886 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1887 {
1888 struct ath_common *common = ath9k_hw_common(ah);
1889 int status = true, setChip = true;
1890 static const char *modes[] = {
1891 "AWAKE",
1892 "FULL-SLEEP",
1893 "NETWORK SLEEP",
1894 "UNDEFINED"
1895 };
1896
1897 if (ah->power_mode == mode)
1898 return status;
1899
1900 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1901 modes[ah->power_mode], modes[mode]);
1902
1903 switch (mode) {
1904 case ATH9K_PM_AWAKE:
1905 status = ath9k_hw_set_power_awake(ah, setChip);
1906 break;
1907 case ATH9K_PM_FULL_SLEEP:
1908 ath9k_set_power_sleep(ah, setChip);
1909 ah->chip_fullsleep = true;
1910 break;
1911 case ATH9K_PM_NETWORK_SLEEP:
1912 ath9k_set_power_network_sleep(ah, setChip);
1913 break;
1914 default:
1915 ath_err(common, "Unknown power mode %u\n", mode);
1916 return false;
1917 }
1918 ah->power_mode = mode;
1919
1920 /*
1921 * XXX: If this warning never comes up after a while then
1922 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1923 * ath9k_hw_setpower() return type void.
1924 */
1925
1926 if (!(ah->ah_flags & AH_UNPLUGGED))
1927 ATH_DBG_WARN_ON_ONCE(!status);
1928
1929 return status;
1930 }
1931 EXPORT_SYMBOL(ath9k_hw_setpower);
1932
1933 /*******************/
1934 /* Beacon Handling */
1935 /*******************/
1936
1937 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1938 {
1939 int flags = 0;
1940
1941 ENABLE_REGWRITE_BUFFER(ah);
1942
1943 switch (ah->opmode) {
1944 case NL80211_IFTYPE_ADHOC:
1945 case NL80211_IFTYPE_MESH_POINT:
1946 REG_SET_BIT(ah, AR_TXCFG,
1947 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1948 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1949 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1950 flags |= AR_NDP_TIMER_EN;
1951 case NL80211_IFTYPE_AP:
1952 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1953 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1954 TU_TO_USEC(ah->config.dma_beacon_response_time));
1955 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1956 TU_TO_USEC(ah->config.sw_beacon_response_time));
1957 flags |=
1958 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1959 break;
1960 default:
1961 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1962 "%s: unsupported opmode: %d\n",
1963 __func__, ah->opmode);
1964 return;
1965 break;
1966 }
1967
1968 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1969 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1970 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1971 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1972
1973 REGWRITE_BUFFER_FLUSH(ah);
1974
1975 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1976 }
1977 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1978
1979 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1980 const struct ath9k_beacon_state *bs)
1981 {
1982 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1983 struct ath9k_hw_capabilities *pCap = &ah->caps;
1984 struct ath_common *common = ath9k_hw_common(ah);
1985
1986 ENABLE_REGWRITE_BUFFER(ah);
1987
1988 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1989
1990 REG_WRITE(ah, AR_BEACON_PERIOD,
1991 TU_TO_USEC(bs->bs_intval));
1992 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1993 TU_TO_USEC(bs->bs_intval));
1994
1995 REGWRITE_BUFFER_FLUSH(ah);
1996
1997 REG_RMW_FIELD(ah, AR_RSSI_THR,
1998 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1999
2000 beaconintval = bs->bs_intval;
2001
2002 if (bs->bs_sleepduration > beaconintval)
2003 beaconintval = bs->bs_sleepduration;
2004
2005 dtimperiod = bs->bs_dtimperiod;
2006 if (bs->bs_sleepduration > dtimperiod)
2007 dtimperiod = bs->bs_sleepduration;
2008
2009 if (beaconintval == dtimperiod)
2010 nextTbtt = bs->bs_nextdtim;
2011 else
2012 nextTbtt = bs->bs_nexttbtt;
2013
2014 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2015 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2016 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2017 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
2018
2019 ENABLE_REGWRITE_BUFFER(ah);
2020
2021 REG_WRITE(ah, AR_NEXT_DTIM,
2022 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2023 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2024
2025 REG_WRITE(ah, AR_SLEEP1,
2026 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2027 | AR_SLEEP1_ASSUME_DTIM);
2028
2029 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2030 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2031 else
2032 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2033
2034 REG_WRITE(ah, AR_SLEEP2,
2035 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2036
2037 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2038 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2039
2040 REGWRITE_BUFFER_FLUSH(ah);
2041
2042 REG_SET_BIT(ah, AR_TIMER_MODE,
2043 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2044 AR_DTIM_TIMER_EN);
2045
2046 /* TSF Out of Range Threshold */
2047 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2048 }
2049 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2050
2051 /*******************/
2052 /* HW Capabilities */
2053 /*******************/
2054
2055 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2056 {
2057 eeprom_chainmask &= chip_chainmask;
2058 if (eeprom_chainmask)
2059 return eeprom_chainmask;
2060 else
2061 return chip_chainmask;
2062 }
2063
2064 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2065 {
2066 struct ath9k_hw_capabilities *pCap = &ah->caps;
2067 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2068 struct ath_common *common = ath9k_hw_common(ah);
2069 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2070 unsigned int chip_chainmask;
2071
2072 u16 eeval;
2073 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2074
2075 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2076 regulatory->current_rd = eeval;
2077
2078 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2079 if (AR_SREV_9285_12_OR_LATER(ah))
2080 eeval |= AR9285_RDEXT_DEFAULT;
2081 regulatory->current_rd_ext = eeval;
2082
2083 if (ah->opmode != NL80211_IFTYPE_AP &&
2084 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2085 if (regulatory->current_rd == 0x64 ||
2086 regulatory->current_rd == 0x65)
2087 regulatory->current_rd += 5;
2088 else if (regulatory->current_rd == 0x41)
2089 regulatory->current_rd = 0x43;
2090 ath_dbg(common, ATH_DBG_REGULATORY,
2091 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2092 }
2093
2094 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2095 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2096 ath_err(common,
2097 "no band has been marked as supported in EEPROM\n");
2098 return -EINVAL;
2099 }
2100
2101 if (eeval & AR5416_OPFLAGS_11A)
2102 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2103
2104 if (eeval & AR5416_OPFLAGS_11G)
2105 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2106
2107 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2108 chip_chainmask = 1;
2109 else if (!AR_SREV_9280_20_OR_LATER(ah))
2110 chip_chainmask = 7;
2111 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2112 chip_chainmask = 3;
2113 else
2114 chip_chainmask = 7;
2115
2116 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2117 /*
2118 * For AR9271 we will temporarilly uses the rx chainmax as read from
2119 * the EEPROM.
2120 */
2121 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2122 !(eeval & AR5416_OPFLAGS_11A) &&
2123 !(AR_SREV_9271(ah)))
2124 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2125 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2126 else if (AR_SREV_9100(ah))
2127 pCap->rx_chainmask = 0x7;
2128 else
2129 /* Use rx_chainmask from EEPROM. */
2130 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2131
2132 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2133 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2134 ah->txchainmask = pCap->tx_chainmask;
2135 ah->rxchainmask = pCap->rx_chainmask;
2136
2137 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2138
2139 /* enable key search for every frame in an aggregate */
2140 if (AR_SREV_9300_20_OR_LATER(ah))
2141 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2142
2143 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2144
2145 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2146 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2147 else
2148 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2149
2150 if (AR_SREV_9271(ah))
2151 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2152 else if (AR_DEVID_7010(ah))
2153 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2154 else if (AR_SREV_9285_12_OR_LATER(ah))
2155 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2156 else if (AR_SREV_9280_20_OR_LATER(ah))
2157 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2158 else
2159 pCap->num_gpio_pins = AR_NUM_GPIO;
2160
2161 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2162 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2163 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2164 } else {
2165 pCap->rts_aggr_limit = (8 * 1024);
2166 }
2167
2168 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2169 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2170 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2171 ah->rfkill_gpio =
2172 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2173 ah->rfkill_polarity =
2174 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2175
2176 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2177 }
2178 #endif
2179 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2180 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2181 else
2182 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2183
2184 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2185 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2186 else
2187 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2188
2189 if (common->btcoex_enabled) {
2190 if (AR_SREV_9300_20_OR_LATER(ah)) {
2191 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2192 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
2193 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
2194 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
2195 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2196 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
2197 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
2198
2199 if (AR_SREV_9285(ah)) {
2200 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2201 btcoex_hw->btpriority_gpio =
2202 ATH_BTPRIORITY_GPIO_9285;
2203 } else {
2204 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2205 }
2206 }
2207 } else {
2208 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2209 }
2210
2211 if (AR_SREV_9300_20_OR_LATER(ah)) {
2212 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2213 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2214 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2215
2216 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2217 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2218 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2219 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2220 pCap->txs_len = sizeof(struct ar9003_txs);
2221 if (!ah->config.paprd_disable &&
2222 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2223 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2224 } else {
2225 pCap->tx_desc_len = sizeof(struct ath_desc);
2226 if (AR_SREV_9280_20(ah))
2227 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2228 }
2229
2230 if (AR_SREV_9300_20_OR_LATER(ah))
2231 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2232
2233 if (AR_SREV_9300_20_OR_LATER(ah))
2234 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2235
2236 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2237 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2238
2239 if (AR_SREV_9285(ah))
2240 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2241 ant_div_ctl1 =
2242 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2243 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2244 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2245 }
2246 if (AR_SREV_9300_20_OR_LATER(ah)) {
2247 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2248 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2249 }
2250
2251
2252 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2253 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2254 /*
2255 * enable the diversity-combining algorithm only when
2256 * both enable_lna_div and enable_fast_div are set
2257 * Table for Diversity
2258 * ant_div_alt_lnaconf bit 0-1
2259 * ant_div_main_lnaconf bit 2-3
2260 * ant_div_alt_gaintb bit 4
2261 * ant_div_main_gaintb bit 5
2262 * enable_ant_div_lnadiv bit 6
2263 * enable_ant_fast_div bit 7
2264 */
2265 if ((ant_div_ctl1 >> 0x6) == 0x3)
2266 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2267 }
2268
2269 if (AR_SREV_9485_10(ah)) {
2270 pCap->pcie_lcr_extsync_en = true;
2271 pCap->pcie_lcr_offset = 0x80;
2272 }
2273
2274 tx_chainmask = pCap->tx_chainmask;
2275 rx_chainmask = pCap->rx_chainmask;
2276 while (tx_chainmask || rx_chainmask) {
2277 if (tx_chainmask & BIT(0))
2278 pCap->max_txchains++;
2279 if (rx_chainmask & BIT(0))
2280 pCap->max_rxchains++;
2281
2282 tx_chainmask >>= 1;
2283 rx_chainmask >>= 1;
2284 }
2285
2286 return 0;
2287 }
2288
2289 /****************************/
2290 /* GPIO / RFKILL / Antennae */
2291 /****************************/
2292
2293 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2294 u32 gpio, u32 type)
2295 {
2296 int addr;
2297 u32 gpio_shift, tmp;
2298
2299 if (gpio > 11)
2300 addr = AR_GPIO_OUTPUT_MUX3;
2301 else if (gpio > 5)
2302 addr = AR_GPIO_OUTPUT_MUX2;
2303 else
2304 addr = AR_GPIO_OUTPUT_MUX1;
2305
2306 gpio_shift = (gpio % 6) * 5;
2307
2308 if (AR_SREV_9280_20_OR_LATER(ah)
2309 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2310 REG_RMW(ah, addr, (type << gpio_shift),
2311 (0x1f << gpio_shift));
2312 } else {
2313 tmp = REG_READ(ah, addr);
2314 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2315 tmp &= ~(0x1f << gpio_shift);
2316 tmp |= (type << gpio_shift);
2317 REG_WRITE(ah, addr, tmp);
2318 }
2319 }
2320
2321 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2322 {
2323 u32 gpio_shift;
2324
2325 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2326
2327 if (AR_DEVID_7010(ah)) {
2328 gpio_shift = gpio;
2329 REG_RMW(ah, AR7010_GPIO_OE,
2330 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2331 (AR7010_GPIO_OE_MASK << gpio_shift));
2332 return;
2333 }
2334
2335 gpio_shift = gpio << 1;
2336 REG_RMW(ah,
2337 AR_GPIO_OE_OUT,
2338 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2339 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2340 }
2341 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2342
2343 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2344 {
2345 #define MS_REG_READ(x, y) \
2346 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2347
2348 if (gpio >= ah->caps.num_gpio_pins)
2349 return 0xffffffff;
2350
2351 if (AR_DEVID_7010(ah)) {
2352 u32 val;
2353 val = REG_READ(ah, AR7010_GPIO_IN);
2354 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2355 } else if (AR_SREV_9300_20_OR_LATER(ah))
2356 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2357 AR_GPIO_BIT(gpio)) != 0;
2358 else if (AR_SREV_9271(ah))
2359 return MS_REG_READ(AR9271, gpio) != 0;
2360 else if (AR_SREV_9287_11_OR_LATER(ah))
2361 return MS_REG_READ(AR9287, gpio) != 0;
2362 else if (AR_SREV_9285_12_OR_LATER(ah))
2363 return MS_REG_READ(AR9285, gpio) != 0;
2364 else if (AR_SREV_9280_20_OR_LATER(ah))
2365 return MS_REG_READ(AR928X, gpio) != 0;
2366 else
2367 return MS_REG_READ(AR, gpio) != 0;
2368 }
2369 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2370
2371 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2372 u32 ah_signal_type)
2373 {
2374 u32 gpio_shift;
2375
2376 if (AR_DEVID_7010(ah)) {
2377 gpio_shift = gpio;
2378 REG_RMW(ah, AR7010_GPIO_OE,
2379 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2380 (AR7010_GPIO_OE_MASK << gpio_shift));
2381 return;
2382 }
2383
2384 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2385 gpio_shift = 2 * gpio;
2386 REG_RMW(ah,
2387 AR_GPIO_OE_OUT,
2388 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2389 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2390 }
2391 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2392
2393 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2394 {
2395 if (AR_DEVID_7010(ah)) {
2396 val = val ? 0 : 1;
2397 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2398 AR_GPIO_BIT(gpio));
2399 return;
2400 }
2401
2402 if (AR_SREV_9271(ah))
2403 val = ~val;
2404
2405 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2406 AR_GPIO_BIT(gpio));
2407 }
2408 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2409
2410 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2411 {
2412 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2413 }
2414 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2415
2416 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2417 {
2418 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2419 }
2420 EXPORT_SYMBOL(ath9k_hw_setantenna);
2421
2422 /*********************/
2423 /* General Operation */
2424 /*********************/
2425
2426 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2427 {
2428 u32 bits = REG_READ(ah, AR_RX_FILTER);
2429 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2430
2431 if (phybits & AR_PHY_ERR_RADAR)
2432 bits |= ATH9K_RX_FILTER_PHYRADAR;
2433 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2434 bits |= ATH9K_RX_FILTER_PHYERR;
2435
2436 return bits;
2437 }
2438 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2439
2440 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2441 {
2442 u32 phybits;
2443
2444 ENABLE_REGWRITE_BUFFER(ah);
2445
2446 if (AR_SREV_9480(ah))
2447 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2448
2449 REG_WRITE(ah, AR_RX_FILTER, bits);
2450
2451 phybits = 0;
2452 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2453 phybits |= AR_PHY_ERR_RADAR;
2454 if (bits & ATH9K_RX_FILTER_PHYERR)
2455 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2456 REG_WRITE(ah, AR_PHY_ERR, phybits);
2457
2458 if (phybits)
2459 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2460 else
2461 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2462
2463 REGWRITE_BUFFER_FLUSH(ah);
2464 }
2465 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2466
2467 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2468 {
2469 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2470 return false;
2471
2472 ath9k_hw_init_pll(ah, NULL);
2473 return true;
2474 }
2475 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2476
2477 bool ath9k_hw_disable(struct ath_hw *ah)
2478 {
2479 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2480 return false;
2481
2482 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2483 return false;
2484
2485 ath9k_hw_init_pll(ah, NULL);
2486 return true;
2487 }
2488 EXPORT_SYMBOL(ath9k_hw_disable);
2489
2490 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2491 {
2492 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2493 struct ath9k_channel *chan = ah->curchan;
2494 struct ieee80211_channel *channel = chan->chan;
2495 int reg_pwr = min_t(int, MAX_RATE_POWER, limit);
2496 int chan_pwr = channel->max_power * 2;
2497
2498 if (test)
2499 reg_pwr = chan_pwr = MAX_RATE_POWER;
2500
2501 regulatory->power_limit = reg_pwr;
2502
2503 ah->eep_ops->set_txpower(ah, chan,
2504 ath9k_regd_get_ctl(regulatory, chan),
2505 channel->max_antenna_gain * 2,
2506 chan_pwr, reg_pwr, test);
2507 }
2508 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2509
2510 void ath9k_hw_setopmode(struct ath_hw *ah)
2511 {
2512 ath9k_hw_set_operating_mode(ah, ah->opmode);
2513 }
2514 EXPORT_SYMBOL(ath9k_hw_setopmode);
2515
2516 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2517 {
2518 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2519 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2520 }
2521 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2522
2523 void ath9k_hw_write_associd(struct ath_hw *ah)
2524 {
2525 struct ath_common *common = ath9k_hw_common(ah);
2526
2527 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2528 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2529 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2530 }
2531 EXPORT_SYMBOL(ath9k_hw_write_associd);
2532
2533 #define ATH9K_MAX_TSF_READ 10
2534
2535 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2536 {
2537 u32 tsf_lower, tsf_upper1, tsf_upper2;
2538 int i;
2539
2540 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2541 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2542 tsf_lower = REG_READ(ah, AR_TSF_L32);
2543 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2544 if (tsf_upper2 == tsf_upper1)
2545 break;
2546 tsf_upper1 = tsf_upper2;
2547 }
2548
2549 WARN_ON( i == ATH9K_MAX_TSF_READ );
2550
2551 return (((u64)tsf_upper1 << 32) | tsf_lower);
2552 }
2553 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2554
2555 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2556 {
2557 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2558 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2559 }
2560 EXPORT_SYMBOL(ath9k_hw_settsf64);
2561
2562 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2563 {
2564 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2565 AH_TSF_WRITE_TIMEOUT))
2566 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2567 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2568
2569 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2570 }
2571 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2572
2573 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2574 {
2575 if (setting)
2576 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2577 else
2578 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2579 }
2580 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2581
2582 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2583 {
2584 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2585 u32 macmode;
2586
2587 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2588 macmode = AR_2040_JOINED_RX_CLEAR;
2589 else
2590 macmode = 0;
2591
2592 REG_WRITE(ah, AR_2040_MODE, macmode);
2593 }
2594
2595 /* HW Generic timers configuration */
2596
2597 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2598 {
2599 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2600 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2601 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2602 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2603 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2604 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2605 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2606 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2607 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2608 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2609 AR_NDP2_TIMER_MODE, 0x0002},
2610 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2611 AR_NDP2_TIMER_MODE, 0x0004},
2612 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2613 AR_NDP2_TIMER_MODE, 0x0008},
2614 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2615 AR_NDP2_TIMER_MODE, 0x0010},
2616 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2617 AR_NDP2_TIMER_MODE, 0x0020},
2618 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2619 AR_NDP2_TIMER_MODE, 0x0040},
2620 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2621 AR_NDP2_TIMER_MODE, 0x0080}
2622 };
2623
2624 /* HW generic timer primitives */
2625
2626 /* compute and clear index of rightmost 1 */
2627 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2628 {
2629 u32 b;
2630
2631 b = *mask;
2632 b &= (0-b);
2633 *mask &= ~b;
2634 b *= debruijn32;
2635 b >>= 27;
2636
2637 return timer_table->gen_timer_index[b];
2638 }
2639
2640 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2641 {
2642 return REG_READ(ah, AR_TSF_L32);
2643 }
2644 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2645
2646 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2647 void (*trigger)(void *),
2648 void (*overflow)(void *),
2649 void *arg,
2650 u8 timer_index)
2651 {
2652 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2653 struct ath_gen_timer *timer;
2654
2655 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2656
2657 if (timer == NULL) {
2658 ath_err(ath9k_hw_common(ah),
2659 "Failed to allocate memory for hw timer[%d]\n",
2660 timer_index);
2661 return NULL;
2662 }
2663
2664 /* allocate a hardware generic timer slot */
2665 timer_table->timers[timer_index] = timer;
2666 timer->index = timer_index;
2667 timer->trigger = trigger;
2668 timer->overflow = overflow;
2669 timer->arg = arg;
2670
2671 return timer;
2672 }
2673 EXPORT_SYMBOL(ath_gen_timer_alloc);
2674
2675 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2676 struct ath_gen_timer *timer,
2677 u32 trig_timeout,
2678 u32 timer_period)
2679 {
2680 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2681 u32 tsf, timer_next;
2682
2683 BUG_ON(!timer_period);
2684
2685 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2686
2687 tsf = ath9k_hw_gettsf32(ah);
2688
2689 timer_next = tsf + trig_timeout;
2690
2691 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2692 "current tsf %x period %x timer_next %x\n",
2693 tsf, timer_period, timer_next);
2694
2695 /*
2696 * Program generic timer registers
2697 */
2698 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2699 timer_next);
2700 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2701 timer_period);
2702 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2703 gen_tmr_configuration[timer->index].mode_mask);
2704
2705 if (AR_SREV_9480(ah)) {
2706 /*
2707 * Starting from AR9480, each generic timer can select which tsf
2708 * to use. But we still follow the old rule, 0 - 7 use tsf and
2709 * 8 - 15 use tsf2.
2710 */
2711 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2712 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2713 (1 << timer->index));
2714 else
2715 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2716 (1 << timer->index));
2717 }
2718
2719 /* Enable both trigger and thresh interrupt masks */
2720 REG_SET_BIT(ah, AR_IMR_S5,
2721 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2722 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2723 }
2724 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2725
2726 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2727 {
2728 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2729
2730 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2731 (timer->index >= ATH_MAX_GEN_TIMER)) {
2732 return;
2733 }
2734
2735 /* Clear generic timer enable bits. */
2736 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2737 gen_tmr_configuration[timer->index].mode_mask);
2738
2739 /* Disable both trigger and thresh interrupt masks */
2740 REG_CLR_BIT(ah, AR_IMR_S5,
2741 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2742 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2743
2744 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2745 }
2746 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2747
2748 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2749 {
2750 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2751
2752 /* free the hardware generic timer slot */
2753 timer_table->timers[timer->index] = NULL;
2754 kfree(timer);
2755 }
2756 EXPORT_SYMBOL(ath_gen_timer_free);
2757
2758 /*
2759 * Generic Timer Interrupts handling
2760 */
2761 void ath_gen_timer_isr(struct ath_hw *ah)
2762 {
2763 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2764 struct ath_gen_timer *timer;
2765 struct ath_common *common = ath9k_hw_common(ah);
2766 u32 trigger_mask, thresh_mask, index;
2767
2768 /* get hardware generic timer interrupt status */
2769 trigger_mask = ah->intr_gen_timer_trigger;
2770 thresh_mask = ah->intr_gen_timer_thresh;
2771 trigger_mask &= timer_table->timer_mask.val;
2772 thresh_mask &= timer_table->timer_mask.val;
2773
2774 trigger_mask &= ~thresh_mask;
2775
2776 while (thresh_mask) {
2777 index = rightmost_index(timer_table, &thresh_mask);
2778 timer = timer_table->timers[index];
2779 BUG_ON(!timer);
2780 ath_dbg(common, ATH_DBG_HWTIMER,
2781 "TSF overflow for Gen timer %d\n", index);
2782 timer->overflow(timer->arg);
2783 }
2784
2785 while (trigger_mask) {
2786 index = rightmost_index(timer_table, &trigger_mask);
2787 timer = timer_table->timers[index];
2788 BUG_ON(!timer);
2789 ath_dbg(common, ATH_DBG_HWTIMER,
2790 "Gen timer[%d] trigger\n", index);
2791 timer->trigger(timer->arg);
2792 }
2793 }
2794 EXPORT_SYMBOL(ath_gen_timer_isr);
2795
2796 /********/
2797 /* HTC */
2798 /********/
2799
2800 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2801 {
2802 ah->htc_reset_init = true;
2803 }
2804 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2805
2806 static struct {
2807 u32 version;
2808 const char * name;
2809 } ath_mac_bb_names[] = {
2810 /* Devices with external radios */
2811 { AR_SREV_VERSION_5416_PCI, "5416" },
2812 { AR_SREV_VERSION_5416_PCIE, "5418" },
2813 { AR_SREV_VERSION_9100, "9100" },
2814 { AR_SREV_VERSION_9160, "9160" },
2815 /* Single-chip solutions */
2816 { AR_SREV_VERSION_9280, "9280" },
2817 { AR_SREV_VERSION_9285, "9285" },
2818 { AR_SREV_VERSION_9287, "9287" },
2819 { AR_SREV_VERSION_9271, "9271" },
2820 { AR_SREV_VERSION_9300, "9300" },
2821 { AR_SREV_VERSION_9330, "9330" },
2822 { AR_SREV_VERSION_9340, "9340" },
2823 { AR_SREV_VERSION_9485, "9485" },
2824 { AR_SREV_VERSION_9480, "9480" },
2825 };
2826
2827 /* For devices with external radios */
2828 static struct {
2829 u16 version;
2830 const char * name;
2831 } ath_rf_names[] = {
2832 { 0, "5133" },
2833 { AR_RAD5133_SREV_MAJOR, "5133" },
2834 { AR_RAD5122_SREV_MAJOR, "5122" },
2835 { AR_RAD2133_SREV_MAJOR, "2133" },
2836 { AR_RAD2122_SREV_MAJOR, "2122" }
2837 };
2838
2839 /*
2840 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2841 */
2842 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2843 {
2844 int i;
2845
2846 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2847 if (ath_mac_bb_names[i].version == mac_bb_version) {
2848 return ath_mac_bb_names[i].name;
2849 }
2850 }
2851
2852 return "????";
2853 }
2854
2855 /*
2856 * Return the RF name. "????" is returned if the RF is unknown.
2857 * Used for devices with external radios.
2858 */
2859 static const char *ath9k_hw_rf_name(u16 rf_version)
2860 {
2861 int i;
2862
2863 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2864 if (ath_rf_names[i].version == rf_version) {
2865 return ath_rf_names[i].name;
2866 }
2867 }
2868
2869 return "????";
2870 }
2871
2872 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2873 {
2874 int used;
2875
2876 /* chipsets >= AR9280 are single-chip */
2877 if (AR_SREV_9280_20_OR_LATER(ah)) {
2878 used = snprintf(hw_name, len,
2879 "Atheros AR%s Rev:%x",
2880 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2881 ah->hw_version.macRev);
2882 }
2883 else {
2884 used = snprintf(hw_name, len,
2885 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2886 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2887 ah->hw_version.macRev,
2888 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2889 AR_RADIO_SREV_MAJOR)),
2890 ah->hw_version.phyRev);
2891 }
2892
2893 hw_name[used] = '\0';
2894 }
2895 EXPORT_SYMBOL(ath9k_hw_name);
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