arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2005 Texas Instruments, Inc.
   9  * Richard Woodruff <r-woodruff2@ti.com>
  10  *
  11  * Based on pm.c for omap1
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/pm.h>
  19 #include <linux/suspend.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/list.h>
  23 #include <linux/err.h>
  24 #include <linux/gpio.h>
  25
  26 #include <mach/sram.h>
  27 #include <mach/clockdomain.h>
  28 #include <mach/powerdomain.h>
  29 #include <mach/control.h>
  30 #include <mach/serial.h>
  31
  32 #include "cm.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "prm-regbits-34xx.h"
  35
  36 #include "prm.h"
  37 #include "pm.h"
  38
  39 struct power_state {
  40         struct powerdomain *pwrdm;
  41         u32 next_state;
  42 #ifdef CONFIG_SUSPEND
  43         u32 saved_state;
  44 #endif
  45         struct list_head node;
  46 };
  47
  48 static LIST_HEAD(pwrst_list);
  49
  50 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  51
  52 static struct powerdomain *mpu_pwrdm;
  53
  54 /* PRCM Interrupt Handler for wakeups */
  55 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
  56 {
  57         u32 wkst, irqstatus_mpu;
  58         u32 fclk, iclk;
  59
  60         /* WKUP */
  61         wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
  62         if (wkst) {
  63                 iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
  64                 fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
  65                 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
  66                 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
  67                 prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
  68                 while (prm_read_mod_reg(WKUP_MOD, PM_WKST))
  69                         cpu_relax();
  70                 cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
  71                 cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
  72         }
  73
  74         /* CORE */
  75         wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
  76         if (wkst) {
  77                 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
  78                 fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  79                 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
  80                 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
  81                 prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
  82                 while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
  83                         cpu_relax();
  84                 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
  85                 cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
  86         }
  87         wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
  88         if (wkst) {
  89                 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
  90                 fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
  91                 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
  92                 cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
  93                 prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
  94                 while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
  95                         cpu_relax();
  96                 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
  97                 cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
  98         }
  99
 100         /* PER */
 101         wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
 102         if (wkst) {
 103                 iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
 104                 fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
 105                 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
 106                 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
 107                 prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
 108                 while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST))
 109                         cpu_relax();
 110                 cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
 111                 cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
 112         }
 113
 114         if (omap_rev() > OMAP3430_REV_ES1_0) {
 115                 /* USBHOST */
 116                 wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
 117                 if (wkst) {
 118                         iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 119                                                CM_ICLKEN);
 120                         fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 121                                                CM_FCLKEN);
 122                         cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
 123                                             CM_ICLKEN);
 124                         cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
 125                                             CM_FCLKEN);
 126                         prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
 127                                           PM_WKST);
 128                         while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 129                                                 PM_WKST))
 130                                 cpu_relax();
 131                         cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
 132                                          CM_ICLKEN);
 133                         cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
 134                                          CM_FCLKEN);
 135                 }
 136         }
 137
 138         irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 139                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 140         prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 141                           OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 142
 143         while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET))
 144                 cpu_relax();
 145
 146         return IRQ_HANDLED;
 147 }
 148
 149 static void omap_sram_idle(void)
 150 {
 151         /* Variable to tell what needs to be saved and restored
 152          * in omap_sram_idle*/
 153         /* save_state = 0 => Nothing to save and restored */
 154         /* save_state = 1 => Only L1 and logic lost */
 155         /* save_state = 2 => Only L2 lost */
 156         /* save_state = 3 => L1, L2 and logic lost */
 157         int save_state = 0, mpu_next_state;
 158
 159         if (!_omap_sram_idle)
 160                 return;
 161
 162         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 163         switch (mpu_next_state) {
 164         case PWRDM_POWER_RET:
 165                 /* No need to save context */
 166                 save_state = 0;
 167                 break;
 168         default:
 169                 /* Invalid state */
 170                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 171                 return;
 172         }
 173         omap2_gpio_prepare_for_retention();
 174         omap_uart_prepare_idle(0);
 175         omap_uart_prepare_idle(1);
 176         omap_uart_prepare_idle(2);
 177
 178         _omap_sram_idle(NULL, save_state);
 179         cpu_init();
 180
 181         omap_uart_resume_idle(2);
 182         omap_uart_resume_idle(1);
 183         omap_uart_resume_idle(0);
 184         omap2_gpio_resume_after_retention();
 185 }
 186
 187 /*
 188  * Check if functional clocks are enabled before entering
 189  * sleep. This function could be behind CONFIG_PM_DEBUG
 190  * when all drivers are configuring their sysconfig registers
 191  * properly and using their clocks properly.
 192  */
 193 static int omap3_fclks_active(void)
 194 {
 195         u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
 196                 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
 197
 198         fck_core1 = cm_read_mod_reg(CORE_MOD,
 199                                     CM_FCLKEN1);
 200         if (omap_rev() > OMAP3430_REV_ES1_0) {
 201                 fck_core3 = cm_read_mod_reg(CORE_MOD,
 202                                             OMAP3430ES2_CM_FCLKEN3);
 203                 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 204                                           CM_FCLKEN);
 205                 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 206                                               CM_FCLKEN);
 207         } else
 208                 fck_sgx = cm_read_mod_reg(GFX_MOD,
 209                                           OMAP3430ES2_CM_FCLKEN3);
 210         fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
 211                                   CM_FCLKEN);
 212         fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
 213                                   CM_FCLKEN);
 214         fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
 215                                   CM_FCLKEN);
 216
 217         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
 218         fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
 219         fck_per &= ~OMAP3430_EN_UART3;
 220
 221         if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
 222             fck_cam | fck_per | fck_usbhost)
 223                 return 1;
 224         return 0;
 225 }
 226
 227 static int omap3_can_sleep(void)
 228 {
 229         if (!omap_uart_can_sleep())
 230                 return 0;
 231         if (omap3_fclks_active())
 232                 return 0;
 233         return 1;
 234 }
 235
 236 /* This sets pwrdm state (other than mpu & core. Currently only ON &
 237  * RET are supported. Function is assuming that clkdm doesn't have
 238  * hw_sup mode enabled. */
 239 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 240 {
 241         u32 cur_state;
 242         int sleep_switch = 0;
 243         int ret = 0;
 244
 245         if (pwrdm == NULL || IS_ERR(pwrdm))
 246                 return -EINVAL;
 247
 248         while (!(pwrdm->pwrsts & (1 << state))) {
 249                 if (state == PWRDM_POWER_OFF)
 250                         return ret;
 251                 state--;
 252         }
 253
 254         cur_state = pwrdm_read_next_pwrst(pwrdm);
 255         if (cur_state == state)
 256                 return ret;
 257
 258         if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
 259                 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
 260                 sleep_switch = 1;
 261                 pwrdm_wait_transition(pwrdm);
 262         }
 263
 264         ret = pwrdm_set_next_pwrst(pwrdm, state);
 265         if (ret) {
 266                 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
 267                        pwrdm->name);
 268                 goto err;
 269         }
 270
 271         if (sleep_switch) {
 272                 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
 273                 pwrdm_wait_transition(pwrdm);
 274         }
 275
 276 err:
 277         return ret;
 278 }
 279
 280 static void omap3_pm_idle(void)
 281 {
 282         local_irq_disable();
 283         local_fiq_disable();
 284
 285         if (!omap3_can_sleep())
 286                 goto out;
 287
 288         if (omap_irq_pending())
 289                 goto out;
 290
 291         omap_sram_idle();
 292
 293 out:
 294         local_fiq_enable();
 295         local_irq_enable();
 296 }
 297
 298 #ifdef CONFIG_SUSPEND
 299 static suspend_state_t suspend_state;
 300
 301 static int omap3_pm_prepare(void)
 302 {
 303         disable_hlt();
 304         return 0;
 305 }
 306
 307 static int omap3_pm_suspend(void)
 308 {
 309         struct power_state *pwrst;
 310         int state, ret = 0;
 311
 312         /* Read current next_pwrsts */
 313         list_for_each_entry(pwrst, &pwrst_list, node)
 314                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 315         /* Set ones wanted by suspend */
 316         list_for_each_entry(pwrst, &pwrst_list, node) {
 317                 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 318                         goto restore;
 319                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 320                         goto restore;
 321         }
 322
 323         omap_uart_prepare_suspend();
 324         omap_sram_idle();
 325
 326 restore:
 327         /* Restore next_pwrsts */
 328         list_for_each_entry(pwrst, &pwrst_list, node) {
 329                 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 330                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 331                 if (state > pwrst->next_state) {
 332                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 333                                "target state %d\n",
 334                                pwrst->pwrdm->name, pwrst->next_state);
 335                         ret = -1;
 336                 }
 337         }
 338         if (ret)
 339                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 340         else
 341                 printk(KERN_INFO "Successfully put all powerdomains "
 342                        "to target state\n");
 343
 344         return ret;
 345 }
 346
 347 static int omap3_pm_enter(suspend_state_t unused)
 348 {
 349         int ret = 0;
 350
 351         switch (suspend_state) {
 352         case PM_SUSPEND_STANDBY:
 353         case PM_SUSPEND_MEM:
 354                 ret = omap3_pm_suspend();
 355                 break;
 356         default:
 357                 ret = -EINVAL;
 358         }
 359
 360         return ret;
 361 }
 362
 363 static void omap3_pm_finish(void)
 364 {
 365         enable_hlt();
 366 }
 367
 368 /* Hooks to enable / disable UART interrupts during suspend */
 369 static int omap3_pm_begin(suspend_state_t state)
 370 {
 371         suspend_state = state;
 372         omap_uart_enable_irqs(0);
 373         return 0;
 374 }
 375
 376 static void omap3_pm_end(void)
 377 {
 378         suspend_state = PM_SUSPEND_ON;
 379         omap_uart_enable_irqs(1);
 380         return;
 381 }
 382
 383 static struct platform_suspend_ops omap_pm_ops = {
 384         .begin          = omap3_pm_begin,
 385         .end            = omap3_pm_end,
 386         .prepare        = omap3_pm_prepare,
 387         .enter          = omap3_pm_enter,
 388         .finish         = omap3_pm_finish,
 389         .valid          = suspend_valid_only_mem,
 390 };
 391 #endif /* CONFIG_SUSPEND */
 392
 393
 394 /**
 395  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 396  *                   retention
 397  *
 398  * In cases where IVA2 is activated by bootcode, it may prevent
 399  * full-chip retention or off-mode because it is not idle.  This
 400  * function forces the IVA2 into idle state so it can go
 401  * into retention/off and thus allow full-chip retention/off.
 402  *
 403  **/
 404 static void __init omap3_iva_idle(void)
 405 {
 406         /* ensure IVA2 clock is disabled */
 407         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 408
 409         /* if no clock activity, nothing else to do */
 410         if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 411               OMAP3430_CLKACTIVITY_IVA2_MASK))
 412                 return;
 413
 414         /* Reset IVA2 */
 415         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 416                           OMAP3430_RST2_IVA2 |
 417                           OMAP3430_RST3_IVA2,
 418                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 419
 420         /* Enable IVA2 clock */
 421         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
 422                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 423
 424         /* Set IVA2 boot mode to 'idle' */
 425         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 426                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 427
 428         /* Un-reset IVA2 */
 429         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
 430
 431         /* Disable IVA2 clock */
 432         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 433
 434         /* Reset IVA2 */
 435         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 436                           OMAP3430_RST2_IVA2 |
 437                           OMAP3430_RST3_IVA2,
 438                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 439 }
 440
 441 static void __init omap3_d2d_idle(void)
 442 {
 443         u16 mask, padconf;
 444
 445         /* In a stand alone OMAP3430 where there is not a stacked
 446          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 447          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 448          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 449         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 450         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 451         padconf |= mask;
 452         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 453
 454         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 455         padconf |= mask;
 456         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 457
 458         /* reset modem */
 459         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
 460                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
 461                           CORE_MOD, RM_RSTCTRL);
 462         prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
 463 }
 464
 465 static void __init prcm_setup_regs(void)
 466 {
 467         /* XXX Reset all wkdeps. This should be done when initializing
 468          * powerdomains */
 469         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 470         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 471         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 472         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 473         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 474         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 475         if (omap_rev() > OMAP3430_REV_ES1_0) {
 476                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 477                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 478         } else
 479                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 480
 481         /*
 482          * Enable interface clock autoidle for all modules.
 483          * Note that in the long run this should be done by clockfw
 484          */
 485         cm_write_mod_reg(
 486                 OMAP3430_AUTO_MODEM |
 487                 OMAP3430ES2_AUTO_MMC3 |
 488                 OMAP3430ES2_AUTO_ICR |
 489                 OMAP3430_AUTO_AES2 |
 490                 OMAP3430_AUTO_SHA12 |
 491                 OMAP3430_AUTO_DES2 |
 492                 OMAP3430_AUTO_MMC2 |
 493                 OMAP3430_AUTO_MMC1 |
 494                 OMAP3430_AUTO_MSPRO |
 495                 OMAP3430_AUTO_HDQ |
 496                 OMAP3430_AUTO_MCSPI4 |
 497                 OMAP3430_AUTO_MCSPI3 |
 498                 OMAP3430_AUTO_MCSPI2 |
 499                 OMAP3430_AUTO_MCSPI1 |
 500                 OMAP3430_AUTO_I2C3 |
 501                 OMAP3430_AUTO_I2C2 |
 502                 OMAP3430_AUTO_I2C1 |
 503                 OMAP3430_AUTO_UART2 |
 504                 OMAP3430_AUTO_UART1 |
 505                 OMAP3430_AUTO_GPT11 |
 506                 OMAP3430_AUTO_GPT10 |
 507                 OMAP3430_AUTO_MCBSP5 |
 508                 OMAP3430_AUTO_MCBSP1 |
 509                 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
 510                 OMAP3430_AUTO_MAILBOXES |
 511                 OMAP3430_AUTO_OMAPCTRL |
 512                 OMAP3430ES1_AUTO_FSHOSTUSB |
 513                 OMAP3430_AUTO_HSOTGUSB |
 514                 OMAP3430_AUTO_SAD2D |
 515                 OMAP3430_AUTO_SSI,
 516                 CORE_MOD, CM_AUTOIDLE1);
 517
 518         cm_write_mod_reg(
 519                 OMAP3430_AUTO_PKA |
 520                 OMAP3430_AUTO_AES1 |
 521                 OMAP3430_AUTO_RNG |
 522                 OMAP3430_AUTO_SHA11 |
 523                 OMAP3430_AUTO_DES1,
 524                 CORE_MOD, CM_AUTOIDLE2);
 525
 526         if (omap_rev() > OMAP3430_REV_ES1_0) {
 527                 cm_write_mod_reg(
 528                         OMAP3430_AUTO_MAD2D |
 529                         OMAP3430ES2_AUTO_USBTLL,
 530                         CORE_MOD, CM_AUTOIDLE3);
 531         }
 532
 533         cm_write_mod_reg(
 534                 OMAP3430_AUTO_WDT2 |
 535                 OMAP3430_AUTO_WDT1 |
 536                 OMAP3430_AUTO_GPIO1 |
 537                 OMAP3430_AUTO_32KSYNC |
 538                 OMAP3430_AUTO_GPT12 |
 539                 OMAP3430_AUTO_GPT1 ,
 540                 WKUP_MOD, CM_AUTOIDLE);
 541
 542         cm_write_mod_reg(
 543                 OMAP3430_AUTO_DSS,
 544                 OMAP3430_DSS_MOD,
 545                 CM_AUTOIDLE);
 546
 547         cm_write_mod_reg(
 548                 OMAP3430_AUTO_CAM,
 549                 OMAP3430_CAM_MOD,
 550                 CM_AUTOIDLE);
 551
 552         cm_write_mod_reg(
 553                 OMAP3430_AUTO_GPIO6 |
 554                 OMAP3430_AUTO_GPIO5 |
 555                 OMAP3430_AUTO_GPIO4 |
 556                 OMAP3430_AUTO_GPIO3 |
 557                 OMAP3430_AUTO_GPIO2 |
 558                 OMAP3430_AUTO_WDT3 |
 559                 OMAP3430_AUTO_UART3 |
 560                 OMAP3430_AUTO_GPT9 |
 561                 OMAP3430_AUTO_GPT8 |
 562                 OMAP3430_AUTO_GPT7 |
 563                 OMAP3430_AUTO_GPT6 |
 564                 OMAP3430_AUTO_GPT5 |
 565                 OMAP3430_AUTO_GPT4 |
 566                 OMAP3430_AUTO_GPT3 |
 567                 OMAP3430_AUTO_GPT2 |
 568                 OMAP3430_AUTO_MCBSP4 |
 569                 OMAP3430_AUTO_MCBSP3 |
 570                 OMAP3430_AUTO_MCBSP2,
 571                 OMAP3430_PER_MOD,
 572                 CM_AUTOIDLE);
 573
 574         if (omap_rev() > OMAP3430_REV_ES1_0) {
 575                 cm_write_mod_reg(
 576                         OMAP3430ES2_AUTO_USBHOST,
 577                         OMAP3430ES2_USBHOST_MOD,
 578                         CM_AUTOIDLE);
 579         }
 580
 581         /*
 582          * Set all plls to autoidle. This is needed until autoidle is
 583          * enabled by clockfw
 584          */
 585         cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 586                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 587         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 588                          MPU_MOD,
 589                          CM_AUTOIDLE2);
 590         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 591                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 592                          PLL_MOD,
 593                          CM_AUTOIDLE);
 594         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 595                          PLL_MOD,
 596                          CM_AUTOIDLE2);
 597
 598         /*
 599          * Enable control of expternal oscillator through
 600          * sys_clkreq. In the long run clock framework should
 601          * take care of this.
 602          */
 603         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 604                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 605                              OMAP3430_GR_MOD,
 606                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 607
 608         /* setup wakup source */
 609         prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
 610                           OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
 611                           WKUP_MOD, PM_WKEN);
 612         /* No need to write EN_IO, that is always enabled */
 613         prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
 614                           OMAP3430_EN_GPT12,
 615                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 616         /* For some reason IO doesn't generate wakeup event even if
 617          * it is selected to mpu wakeup goup */
 618         prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 619                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 620
 621         /* Don't attach IVA interrupts */
 622         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 623         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 624         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 625         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 626
 627         /* Clear any pending 'reset' flags */
 628         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 629         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 630         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 631         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 632         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 633         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 634         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 635
 636         /* Clear any pending PRCM interrupts */
 637         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 638
 639         /* Don't attach IVA interrupts */
 640         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 641         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 642         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 643         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 644
 645         /* Clear any pending 'reset' flags */
 646         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 647         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 648         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 649         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 650         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 651         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 652         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 653
 654         /* Clear any pending PRCM interrupts */
 655         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 656
 657         omap3_iva_idle();
 658         omap3_d2d_idle();
 659 }
 660
 661 static int __init pwrdms_setup(struct powerdomain *pwrdm)
 662 {
 663         struct power_state *pwrst;
 664
 665         if (!pwrdm->pwrsts)
 666                 return 0;
 667
 668         pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
 669         if (!pwrst)
 670                 return -ENOMEM;
 671         pwrst->pwrdm = pwrdm;
 672         pwrst->next_state = PWRDM_POWER_RET;
 673         list_add(&pwrst->node, &pwrst_list);
 674
 675         if (pwrdm_has_hdwr_sar(pwrdm))
 676                 pwrdm_enable_hdwr_sar(pwrdm);
 677
 678         return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 679 }
 680
 681 /*
 682  * Enable hw supervised mode for all clockdomains if it's
 683  * supported. Initiate sleep transition for other clockdomains, if
 684  * they are not used
 685  */
 686 static int __init clkdms_setup(struct clockdomain *clkdm)
 687 {
 688         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 689                 omap2_clkdm_allow_idle(clkdm);
 690         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 691                  atomic_read(&clkdm->usecount) == 0)
 692                 omap2_clkdm_sleep(clkdm);
 693         return 0;
 694 }
 695
 696 static int __init omap3_pm_init(void)
 697 {
 698         struct power_state *pwrst, *tmp;
 699         int ret;
 700
 701         if (!cpu_is_omap34xx())
 702                 return -ENODEV;
 703
 704         printk(KERN_ERR "Power Management for TI OMAP3.\n");
 705
 706         /* XXX prcm_setup_regs needs to be before enabling hw
 707          * supervised mode for powerdomains */
 708         prcm_setup_regs();
 709
 710         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 711                           (irq_handler_t)prcm_interrupt_handler,
 712                           IRQF_DISABLED, "prcm", NULL);
 713         if (ret) {
 714                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 715                        INT_34XX_PRCM_MPU_IRQ);
 716                 goto err1;
 717         }
 718
 719         ret = pwrdm_for_each(pwrdms_setup);
 720         if (ret) {
 721                 printk(KERN_ERR "Failed to setup powerdomains\n");
 722                 goto err2;
 723         }
 724
 725         (void) clkdm_for_each(clkdms_setup);
 726
 727         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 728         if (mpu_pwrdm == NULL) {
 729                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 730                 goto err2;
 731         }
 732
 733         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 734                                          omap34xx_cpu_suspend_sz);
 735
 736 #ifdef CONFIG_SUSPEND
 737         suspend_set_ops(&omap_pm_ops);
 738 #endif /* CONFIG_SUSPEND */
 739
 740         pm_idle = omap3_pm_idle;
 741
 742 err1:
 743         return ret;
 744 err2:
 745         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 746         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 747                 list_del(&pwrst->node);
 748                 kfree(pwrst);
 749         }
 750         return ret;
 751 }
 752
 753 late_initcall(omap3_pm_init);