2 * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
6 * Based on stmp3xxx_spdif_dai.c
7 * Vladimir Barinov <vbarinov@embeddedalley.com>
8 * Copyright 2008 SigmaTel, Inc
9 * Copyright 2008 Embedded Alley Solutions, Inc
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
16 #include <linux/bitrev.h>
17 #include <linux/clk.h>
18 #include <linux/clk-private.h>
19 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/regmap.h>
25 #include <sound/asoundef.h>
26 #include <sound/dmaengine_pcm.h>
27 #include <sound/soc.h>
29 #include "fsl_spdif.h"
32 #define FSL_SPDIF_TXFIFO_WML 0x8
33 #define FSL_SPDIF_RXFIFO_WML 0x8
35 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
36 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL | INT_URX_OV|\
37 INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR |\
38 INT_RXFIFO_RESYNC | INT_LOSS_LOCK | INT_DPLL_LOCKED)
40 /* Index list for the values that has if (DPLL Locked) condition */
41 static u8 srpc_dpll_locked
[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
42 #define SRPC_NODPLL_START1 0x5
43 #define SRPC_NODPLL_START2 0xc
45 #define DEFAULT_RXCLK_SRC 1
48 * SPDIF control structure
49 * Defines channel status, subcode and Q sub
51 struct spdif_mixer_control
{
52 /* spinlock to access control data */
55 /* IEC958 channel tx status bit */
56 unsigned char ch_status
[4];
59 unsigned char subcode
[2 * SPDIF_UBITS_SIZE
];
61 /* Q subcode part of user bits */
62 unsigned char qsub
[2 * SPDIF_QSUB_SIZE
];
64 /* Buffer offset for U/Q */
68 /* Ready buffer index of the two buffers */
73 * fsl_spdif_priv: Freescale SPDIF private data
75 * @fsl_spdif_control: SPDIF control data
76 * @cpu_dai_drv: cpu dai driver
77 * @pdev: platform device pointer
78 * @regmap: regmap handler
79 * @dpll_locked: dpll lock flag
80 * @txrate: the best rates for playback
81 * @txclk_df: STC_TXCLK_DF dividers value for playback
82 * @sysclk_df: STC_SYSCLK_DF dividers value for playback
83 * @txclk_src: STC_TXCLK_SRC values for playback
84 * @rxclk_src: SRPC_CLKSRC_SEL values for capture
85 * @txclk: tx clock sources for playback
86 * @rxclk: rx clock sources for capture
87 * @coreclk: core clock for register access via DMA
88 * @sysclk: system clock for rx clock rate measurement
89 * @dma_params_tx: DMA parameters for transmit channel
90 * @dma_params_rx: DMA parameters for receive channel
93 struct fsl_spdif_priv
{
94 struct spdif_mixer_control fsl_spdif_control
;
95 struct snd_soc_dai_driver cpu_dai_drv
;
96 struct platform_device
*pdev
;
97 struct regmap
*regmap
;
99 u16 txrate
[SPDIF_TXRATE_MAX
];
100 u8 txclk_df
[SPDIF_TXRATE_MAX
];
101 u8 sysclk_df
[SPDIF_TXRATE_MAX
];
102 u8 txclk_src
[SPDIF_TXRATE_MAX
];
104 struct clk
*txclk
[SPDIF_TXRATE_MAX
];
108 struct snd_dmaengine_dai_dma_data dma_params_tx
;
109 struct snd_dmaengine_dai_dma_data dma_params_rx
;
111 /* The name space will be allocated dynamically */
116 /* DPLL locked and lock loss interrupt handler */
117 static void spdif_irq_dpll_lock(struct fsl_spdif_priv
*spdif_priv
)
119 struct regmap
*regmap
= spdif_priv
->regmap
;
120 struct platform_device
*pdev
= spdif_priv
->pdev
;
123 regmap_read(regmap
, REG_SPDIF_SRPC
, &locked
);
124 locked
&= SRPC_DPLL_LOCKED
;
126 dev_dbg(&pdev
->dev
, "isr: Rx dpll %s \n",
127 locked
? "locked" : "loss lock");
129 spdif_priv
->dpll_locked
= locked
? true : false;
132 /* Receiver found illegal symbol interrupt handler */
133 static void spdif_irq_sym_error(struct fsl_spdif_priv
*spdif_priv
)
135 struct regmap
*regmap
= spdif_priv
->regmap
;
136 struct platform_device
*pdev
= spdif_priv
->pdev
;
138 dev_dbg(&pdev
->dev
, "isr: receiver found illegal symbol\n");
140 if (!spdif_priv
->dpll_locked
) {
141 /* DPLL unlocked seems no audio stream */
142 regmap_update_bits(regmap
, REG_SPDIF_SIE
, INT_SYM_ERR
, 0);
146 /* U/Q Channel receive register full */
147 static void spdif_irq_uqrx_full(struct fsl_spdif_priv
*spdif_priv
, char name
)
149 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
150 struct regmap
*regmap
= spdif_priv
->regmap
;
151 struct platform_device
*pdev
= spdif_priv
->pdev
;
152 u32
*pos
, size
, val
, reg
;
157 size
= SPDIF_UBITS_SIZE
;
162 size
= SPDIF_QSUB_SIZE
;
166 dev_err(&pdev
->dev
, "unsupported channel name\n");
170 dev_dbg(&pdev
->dev
, "isr: %c Channel receive register full\n", name
);
172 if (*pos
>= size
* 2) {
174 } else if (unlikely((*pos
% size
) + 3 > size
)) {
175 dev_err(&pdev
->dev
, "User bit receivce buffer overflow\n");
179 regmap_read(regmap
, reg
, &val
);
180 ctrl
->subcode
[*pos
++] = val
>> 16;
181 ctrl
->subcode
[*pos
++] = val
>> 8;
182 ctrl
->subcode
[*pos
++] = val
;
185 /* U/Q Channel sync found */
186 static void spdif_irq_uq_sync(struct fsl_spdif_priv
*spdif_priv
)
188 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
189 struct platform_device
*pdev
= spdif_priv
->pdev
;
191 dev_dbg(&pdev
->dev
, "isr: U/Q Channel sync found\n");
193 /* U/Q buffer reset */
197 /* Set ready to this buffer */
198 ctrl
->ready_buf
= (ctrl
->qpos
- 1) / SPDIF_QSUB_SIZE
+ 1;
201 /* U/Q Channel framing error */
202 static void spdif_irq_uq_err(struct fsl_spdif_priv
*spdif_priv
)
204 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
205 struct regmap
*regmap
= spdif_priv
->regmap
;
206 struct platform_device
*pdev
= spdif_priv
->pdev
;
209 dev_dbg(&pdev
->dev
, "isr: U/Q Channel framing error\n");
211 /* Read U/Q data to clear the irq and do buffer reset */
212 regmap_read(regmap
, REG_SPDIF_SRU
, &val
);
213 regmap_read(regmap
, REG_SPDIF_SRQ
, &val
);
215 /* Drop this U/Q buffer */
221 /* Get spdif interrupt status and clear the interrupt */
222 static u32
spdif_intr_status_clear(struct fsl_spdif_priv
*spdif_priv
)
224 struct regmap
*regmap
= spdif_priv
->regmap
;
227 regmap_read(regmap
, REG_SPDIF_SIS
, &val
);
228 regmap_read(regmap
, REG_SPDIF_SIE
, &val2
);
230 regmap_write(regmap
, REG_SPDIF_SIC
, val
& val2
);
235 static irqreturn_t
spdif_isr(int irq
, void *devid
)
237 struct fsl_spdif_priv
*spdif_priv
= (struct fsl_spdif_priv
*)devid
;
238 struct platform_device
*pdev
= spdif_priv
->pdev
;
241 sis
= spdif_intr_status_clear(spdif_priv
);
243 if (sis
& INT_DPLL_LOCKED
)
244 spdif_irq_dpll_lock(spdif_priv
);
246 if (sis
& INT_TXFIFO_UNOV
)
247 dev_dbg(&pdev
->dev
, "isr: Tx FIFO under/overrun\n");
249 if (sis
& INT_TXFIFO_RESYNC
)
250 dev_dbg(&pdev
->dev
, "isr: Tx FIFO resync\n");
253 dev_dbg(&pdev
->dev
, "isr: cstatus new\n");
255 if (sis
& INT_VAL_NOGOOD
)
256 dev_dbg(&pdev
->dev
, "isr: validity flag no good\n");
258 if (sis
& INT_SYM_ERR
)
259 spdif_irq_sym_error(spdif_priv
);
261 if (sis
& INT_BIT_ERR
)
262 dev_dbg(&pdev
->dev
, "isr: receiver found parity bit error\n");
264 if (sis
& INT_URX_FUL
)
265 spdif_irq_uqrx_full(spdif_priv
, 'U');
267 if (sis
& INT_URX_OV
)
268 dev_dbg(&pdev
->dev
, "isr: U Channel receive register overrun\n");
270 if (sis
& INT_QRX_FUL
)
271 spdif_irq_uqrx_full(spdif_priv
, 'Q');
273 if (sis
& INT_QRX_OV
)
274 dev_dbg(&pdev
->dev
, "isr: Q Channel receive register overrun\n");
276 if (sis
& INT_UQ_SYNC
)
277 spdif_irq_uq_sync(spdif_priv
);
279 if (sis
& INT_UQ_ERR
)
280 spdif_irq_uq_err(spdif_priv
);
282 if (sis
& INT_RXFIFO_UNOV
)
283 dev_dbg(&pdev
->dev
, "isr: Rx FIFO under/overrun\n");
285 if (sis
& INT_RXFIFO_RESYNC
)
286 dev_dbg(&pdev
->dev
, "isr: Rx FIFO resync\n");
288 if (sis
& INT_LOSS_LOCK
)
289 spdif_irq_dpll_lock(spdif_priv
);
291 /* FIXME: Write Tx FIFO to clear TxEm */
293 dev_dbg(&pdev
->dev
, "isr: Tx FIFO empty\n");
295 /* FIXME: Read Rx FIFO to clear RxFIFOFul */
296 if (sis
& INT_RXFIFO_FUL
)
297 dev_dbg(&pdev
->dev
, "isr: Rx FIFO full\n");
302 static int spdif_softreset(struct fsl_spdif_priv
*spdif_priv
)
304 struct regmap
*regmap
= spdif_priv
->regmap
;
305 u32 val
, cycle
= 1000;
307 regmap_write(regmap
, REG_SPDIF_SCR
, SCR_SOFT_RESET
);
310 * RESET bit would be cleared after finishing its reset procedure,
311 * which typically lasts 8 cycles. 1000 cycles will keep it safe.
314 regmap_read(regmap
, REG_SPDIF_SCR
, &val
);
315 } while ((val
& SCR_SOFT_RESET
) && cycle
--);
323 static void spdif_set_cstatus(struct spdif_mixer_control
*ctrl
,
326 ctrl
->ch_status
[3] &= ~mask
;
327 ctrl
->ch_status
[3] |= cstatus
& mask
;
330 static void spdif_write_channel_status(struct fsl_spdif_priv
*spdif_priv
)
332 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
333 struct regmap
*regmap
= spdif_priv
->regmap
;
334 struct platform_device
*pdev
= spdif_priv
->pdev
;
337 ch_status
= (bitrev8(ctrl
->ch_status
[0]) << 16) |
338 (bitrev8(ctrl
->ch_status
[1]) << 8) |
339 bitrev8(ctrl
->ch_status
[2]);
340 regmap_write(regmap
, REG_SPDIF_STCSCH
, ch_status
);
342 dev_dbg(&pdev
->dev
, "STCSCH: 0x%06x\n", ch_status
);
344 ch_status
= bitrev8(ctrl
->ch_status
[3]) << 16;
345 regmap_write(regmap
, REG_SPDIF_STCSCL
, ch_status
);
347 dev_dbg(&pdev
->dev
, "STCSCL: 0x%06x\n", ch_status
);
350 /* Set SPDIF PhaseConfig register for rx clock */
351 static int spdif_set_rx_clksrc(struct fsl_spdif_priv
*spdif_priv
,
352 enum spdif_gainsel gainsel
, int dpll_locked
)
354 struct regmap
*regmap
= spdif_priv
->regmap
;
355 u8 clksrc
= spdif_priv
->rxclk_src
;
357 if (clksrc
>= SRPC_CLKSRC_MAX
|| gainsel
>= GAINSEL_MULTI_MAX
)
360 regmap_update_bits(regmap
, REG_SPDIF_SRPC
,
361 SRPC_CLKSRC_SEL_MASK
| SRPC_GAINSEL_MASK
,
362 SRPC_CLKSRC_SEL_SET(clksrc
) | SRPC_GAINSEL_SET(gainsel
));
367 static int spdif_set_sample_rate(struct snd_pcm_substream
*substream
,
370 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
371 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
372 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
373 struct regmap
*regmap
= spdif_priv
->regmap
;
374 struct platform_device
*pdev
= spdif_priv
->pdev
;
375 unsigned long csfs
= 0;
377 u8 clk
, txclk_df
, sysclk_df
;
380 switch (sample_rate
) {
382 rate
= SPDIF_TXRATE_32000
;
383 csfs
= IEC958_AES3_CON_FS_32000
;
386 rate
= SPDIF_TXRATE_44100
;
387 csfs
= IEC958_AES3_CON_FS_44100
;
390 rate
= SPDIF_TXRATE_48000
;
391 csfs
= IEC958_AES3_CON_FS_48000
;
394 dev_err(&pdev
->dev
, "unsupported sample rate %d\n", sample_rate
);
398 clk
= spdif_priv
->txclk_src
[rate
];
399 if (clk
>= STC_TXCLK_SRC_MAX
) {
400 dev_err(&pdev
->dev
, "tx clock source is out of range\n");
404 txclk_df
= spdif_priv
->txclk_df
[rate
];
406 dev_err(&pdev
->dev
, "the txclk_df can't be zero\n");
410 sysclk_df
= spdif_priv
->sysclk_df
[rate
];
412 /* Don't mess up the clocks from other modules */
413 if (clk
!= STC_TXCLK_SPDIF_ROOT
)
417 * The S/PDIF block needs a clock of 64 * fs * txclk_df.
418 * So request 64 * fs * (txclk_df + 1) to get rounded.
420 ret
= clk_set_rate(spdif_priv
->txclk
[rate
], 64 * sample_rate
* (txclk_df
+ 1));
422 dev_err(&pdev
->dev
, "failed to set tx clock rate\n");
427 dev_dbg(&pdev
->dev
, "expected clock rate = %d\n",
428 (64 * sample_rate
* txclk_df
* sysclk_df
));
429 dev_dbg(&pdev
->dev
, "actual clock rate = %ld\n",
430 clk_get_rate(spdif_priv
->txclk
[rate
]));
432 /* set fs field in consumer channel status */
433 spdif_set_cstatus(ctrl
, IEC958_AES3_CON_FS
, csfs
);
435 /* select clock source and divisor */
436 stc
= STC_TXCLK_ALL_EN
| STC_TXCLK_SRC_SET(clk
) | STC_TXCLK_DF(txclk_df
);
437 mask
= STC_TXCLK_ALL_EN_MASK
| STC_TXCLK_SRC_MASK
| STC_TXCLK_DF_MASK
;
438 regmap_update_bits(regmap
, REG_SPDIF_STC
, mask
, stc
);
440 regmap_update_bits(regmap
, REG_SPDIF_STC
,
441 STC_SYSCLK_DF_MASK
, STC_SYSCLK_DF(sysclk_df
));
443 dev_dbg(&pdev
->dev
, "set sample rate to %dHz for %dHz playback\n",
444 spdif_priv
->txrate
[rate
], sample_rate
);
449 static int fsl_spdif_startup(struct snd_pcm_substream
*substream
,
450 struct snd_soc_dai
*cpu_dai
)
452 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
453 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
454 struct platform_device
*pdev
= spdif_priv
->pdev
;
455 struct regmap
*regmap
= spdif_priv
->regmap
;
459 /* Reset module and interrupts only for first initialization */
460 if (!cpu_dai
->active
) {
461 ret
= clk_prepare_enable(spdif_priv
->coreclk
);
463 dev_err(&pdev
->dev
, "failed to enable core clock\n");
467 ret
= spdif_softreset(spdif_priv
);
469 dev_err(&pdev
->dev
, "failed to soft reset\n");
473 /* Disable all the interrupts */
474 regmap_update_bits(regmap
, REG_SPDIF_SIE
, 0xffffff, 0);
477 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
478 scr
= SCR_TXFIFO_AUTOSYNC
| SCR_TXFIFO_CTRL_NORMAL
|
479 SCR_TXSEL_NORMAL
| SCR_USRC_SEL_CHIP
|
481 mask
= SCR_TXFIFO_AUTOSYNC_MASK
| SCR_TXFIFO_CTRL_MASK
|
482 SCR_TXSEL_MASK
| SCR_USRC_SEL_MASK
|
483 SCR_TXFIFO_FSEL_MASK
;
484 for (i
= 0; i
< SPDIF_TXRATE_MAX
; i
++)
485 clk_prepare_enable(spdif_priv
->txclk
[i
]);
487 scr
= SCR_RXFIFO_FSEL_IF8
| SCR_RXFIFO_AUTOSYNC
;
488 mask
= SCR_RXFIFO_FSEL_MASK
| SCR_RXFIFO_AUTOSYNC_MASK
|
489 SCR_RXFIFO_CTL_MASK
| SCR_RXFIFO_OFF_MASK
;
490 clk_prepare_enable(spdif_priv
->rxclk
);
492 regmap_update_bits(regmap
, REG_SPDIF_SCR
, mask
, scr
);
494 /* Power up SPDIF module */
495 regmap_update_bits(regmap
, REG_SPDIF_SCR
, SCR_LOW_POWER
, 0);
500 clk_disable_unprepare(spdif_priv
->coreclk
);
505 static void fsl_spdif_shutdown(struct snd_pcm_substream
*substream
,
506 struct snd_soc_dai
*cpu_dai
)
508 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
509 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
510 struct regmap
*regmap
= spdif_priv
->regmap
;
513 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
515 mask
= SCR_TXFIFO_AUTOSYNC_MASK
| SCR_TXFIFO_CTRL_MASK
|
516 SCR_TXSEL_MASK
| SCR_USRC_SEL_MASK
|
517 SCR_TXFIFO_FSEL_MASK
;
518 for (i
= 0; i
< SPDIF_TXRATE_MAX
; i
++)
519 clk_disable_unprepare(spdif_priv
->txclk
[i
]);
521 scr
= SCR_RXFIFO_OFF
| SCR_RXFIFO_CTL_ZERO
;
522 mask
= SCR_RXFIFO_FSEL_MASK
| SCR_RXFIFO_AUTOSYNC_MASK
|
523 SCR_RXFIFO_CTL_MASK
| SCR_RXFIFO_OFF_MASK
;
524 clk_disable_unprepare(spdif_priv
->rxclk
);
526 regmap_update_bits(regmap
, REG_SPDIF_SCR
, mask
, scr
);
528 /* Power down SPDIF module only if tx&rx are both inactive */
529 if (!cpu_dai
->active
) {
530 spdif_intr_status_clear(spdif_priv
);
531 regmap_update_bits(regmap
, REG_SPDIF_SCR
,
532 SCR_LOW_POWER
, SCR_LOW_POWER
);
533 clk_disable_unprepare(spdif_priv
->coreclk
);
537 static int fsl_spdif_hw_params(struct snd_pcm_substream
*substream
,
538 struct snd_pcm_hw_params
*params
,
539 struct snd_soc_dai
*dai
)
541 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
542 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
543 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
544 struct platform_device
*pdev
= spdif_priv
->pdev
;
545 u32 sample_rate
= params_rate(params
);
548 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
549 ret
= spdif_set_sample_rate(substream
, sample_rate
);
551 dev_err(&pdev
->dev
, "%s: set sample rate failed: %d\n",
552 __func__
, sample_rate
);
555 spdif_set_cstatus(ctrl
, IEC958_AES3_CON_CLOCK
,
556 IEC958_AES3_CON_CLOCK_1000PPM
);
557 spdif_write_channel_status(spdif_priv
);
559 /* Setup rx clock source */
560 ret
= spdif_set_rx_clksrc(spdif_priv
, SPDIF_DEFAULT_GAINSEL
, 1);
566 static int fsl_spdif_trigger(struct snd_pcm_substream
*substream
,
567 int cmd
, struct snd_soc_dai
*dai
)
569 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
570 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
571 struct regmap
*regmap
= spdif_priv
->regmap
;
572 int is_playack
= (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
);
573 u32 intr
= is_playack
? INTR_FOR_PLAYBACK
: INTR_FOR_CAPTURE
;
574 u32 dmaen
= is_playack
? SCR_DMA_TX_EN
: SCR_DMA_RX_EN
;;
577 case SNDRV_PCM_TRIGGER_START
:
578 case SNDRV_PCM_TRIGGER_RESUME
:
579 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
580 regmap_update_bits(regmap
, REG_SPDIF_SIE
, intr
, intr
);
581 regmap_update_bits(regmap
, REG_SPDIF_SCR
, dmaen
, dmaen
);
583 case SNDRV_PCM_TRIGGER_STOP
:
584 case SNDRV_PCM_TRIGGER_SUSPEND
:
585 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
586 regmap_update_bits(regmap
, REG_SPDIF_SCR
, dmaen
, 0);
587 regmap_update_bits(regmap
, REG_SPDIF_SIE
, intr
, 0);
596 static struct snd_soc_dai_ops fsl_spdif_dai_ops
= {
597 .startup
= fsl_spdif_startup
,
598 .hw_params
= fsl_spdif_hw_params
,
599 .trigger
= fsl_spdif_trigger
,
600 .shutdown
= fsl_spdif_shutdown
,
605 * FSL SPDIF IEC958 controller(mixer) functions
607 * Channel status get/put control
608 * User bit value get/put control
609 * Valid bit value get control
610 * DPLL lock status get control
611 * User bit sync mode selection control
614 static int fsl_spdif_info(struct snd_kcontrol
*kcontrol
,
615 struct snd_ctl_elem_info
*uinfo
)
617 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
623 static int fsl_spdif_pb_get(struct snd_kcontrol
*kcontrol
,
624 struct snd_ctl_elem_value
*uvalue
)
626 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
627 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
628 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
630 uvalue
->value
.iec958
.status
[0] = ctrl
->ch_status
[0];
631 uvalue
->value
.iec958
.status
[1] = ctrl
->ch_status
[1];
632 uvalue
->value
.iec958
.status
[2] = ctrl
->ch_status
[2];
633 uvalue
->value
.iec958
.status
[3] = ctrl
->ch_status
[3];
638 static int fsl_spdif_pb_put(struct snd_kcontrol
*kcontrol
,
639 struct snd_ctl_elem_value
*uvalue
)
641 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
642 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
643 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
645 ctrl
->ch_status
[0] = uvalue
->value
.iec958
.status
[0];
646 ctrl
->ch_status
[1] = uvalue
->value
.iec958
.status
[1];
647 ctrl
->ch_status
[2] = uvalue
->value
.iec958
.status
[2];
648 ctrl
->ch_status
[3] = uvalue
->value
.iec958
.status
[3];
650 spdif_write_channel_status(spdif_priv
);
655 /* Get channel status from SPDIF_RX_CCHAN register */
656 static int fsl_spdif_capture_get(struct snd_kcontrol
*kcontrol
,
657 struct snd_ctl_elem_value
*ucontrol
)
659 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
660 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
661 struct regmap
*regmap
= spdif_priv
->regmap
;
664 regmap_read(regmap
, REG_SPDIF_SIS
, &val
);
665 if (!(val
& INT_CNEW
)) {
669 regmap_read(regmap
, REG_SPDIF_SRCSH
, &cstatus
);
670 ucontrol
->value
.iec958
.status
[0] = (cstatus
>> 16) & 0xFF;
671 ucontrol
->value
.iec958
.status
[1] = (cstatus
>> 8) & 0xFF;
672 ucontrol
->value
.iec958
.status
[2] = cstatus
& 0xFF;
674 regmap_read(regmap
, REG_SPDIF_SRCSL
, &cstatus
);
675 ucontrol
->value
.iec958
.status
[3] = (cstatus
>> 16) & 0xFF;
676 ucontrol
->value
.iec958
.status
[4] = (cstatus
>> 8) & 0xFF;
677 ucontrol
->value
.iec958
.status
[5] = cstatus
& 0xFF;
680 regmap_write(regmap
, REG_SPDIF_SIC
, INT_CNEW
);
686 * Get User bits (subcode) from chip value which readed out
687 * in UChannel register.
689 static int fsl_spdif_subcode_get(struct snd_kcontrol
*kcontrol
,
690 struct snd_ctl_elem_value
*ucontrol
)
692 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
693 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
694 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
698 spin_lock_irqsave(&ctrl
->ctl_lock
, flags
);
699 if (ctrl
->ready_buf
) {
700 int idx
= (ctrl
->ready_buf
- 1) * SPDIF_UBITS_SIZE
;
701 memcpy(&ucontrol
->value
.iec958
.subcode
[0],
702 &ctrl
->subcode
[idx
], SPDIF_UBITS_SIZE
);
706 spin_unlock_irqrestore(&ctrl
->ctl_lock
, flags
);
711 /* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */
712 static int fsl_spdif_qinfo(struct snd_kcontrol
*kcontrol
,
713 struct snd_ctl_elem_info
*uinfo
)
715 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BYTES
;
716 uinfo
->count
= SPDIF_QSUB_SIZE
;
721 /* Get Q subcode from chip value which readed out in QChannel register */
722 static int fsl_spdif_qget(struct snd_kcontrol
*kcontrol
,
723 struct snd_ctl_elem_value
*ucontrol
)
725 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
726 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
727 struct spdif_mixer_control
*ctrl
= &spdif_priv
->fsl_spdif_control
;
731 spin_lock_irqsave(&ctrl
->ctl_lock
, flags
);
732 if (ctrl
->ready_buf
) {
733 int idx
= (ctrl
->ready_buf
- 1) * SPDIF_QSUB_SIZE
;
734 memcpy(&ucontrol
->value
.bytes
.data
[0],
735 &ctrl
->qsub
[idx
], SPDIF_QSUB_SIZE
);
739 spin_unlock_irqrestore(&ctrl
->ctl_lock
, flags
);
744 /* Valid bit infomation */
745 static int fsl_spdif_vbit_info(struct snd_kcontrol
*kcontrol
,
746 struct snd_ctl_elem_info
*uinfo
)
748 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
750 uinfo
->value
.integer
.min
= 0;
751 uinfo
->value
.integer
.max
= 1;
756 /* Get valid good bit from interrupt status register */
757 static int fsl_spdif_vbit_get(struct snd_kcontrol
*kcontrol
,
758 struct snd_ctl_elem_value
*ucontrol
)
760 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
761 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
762 struct regmap
*regmap
= spdif_priv
->regmap
;
765 regmap_read(regmap
, REG_SPDIF_SIS
, &val
);
766 ucontrol
->value
.integer
.value
[0] = (val
& INT_VAL_NOGOOD
) != 0;
767 regmap_write(regmap
, REG_SPDIF_SIC
, INT_VAL_NOGOOD
);
772 /* DPLL lock infomation */
773 static int fsl_spdif_rxrate_info(struct snd_kcontrol
*kcontrol
,
774 struct snd_ctl_elem_info
*uinfo
)
776 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
778 uinfo
->value
.integer
.min
= 16000;
779 uinfo
->value
.integer
.max
= 96000;
784 static u32 gainsel_multi
[GAINSEL_MULTI_MAX
] = {
785 24, 16, 12, 8, 6, 4, 3,
788 /* Get RX data clock rate given the SPDIF bus_clk */
789 static int spdif_get_rxclk_rate(struct fsl_spdif_priv
*spdif_priv
,
790 enum spdif_gainsel gainsel
)
792 struct regmap
*regmap
= spdif_priv
->regmap
;
793 struct platform_device
*pdev
= spdif_priv
->pdev
;
794 u64 tmpval64
, busclk_freq
= 0;
795 u32 freqmeas
, phaseconf
;
798 regmap_read(regmap
, REG_SPDIF_SRFM
, &freqmeas
);
799 regmap_read(regmap
, REG_SPDIF_SRPC
, &phaseconf
);
801 clksrc
= (phaseconf
>> SRPC_CLKSRC_SEL_OFFSET
) & 0xf;
802 if (srpc_dpll_locked
[clksrc
] && (phaseconf
& SRPC_DPLL_LOCKED
)) {
803 /* Get bus clock from system */
804 busclk_freq
= clk_get_rate(spdif_priv
->sysclk
);
807 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
808 tmpval64
= (u64
) busclk_freq
* freqmeas
;
809 do_div(tmpval64
, gainsel_multi
[gainsel
] * 1024);
810 do_div(tmpval64
, 128 * 1024);
812 dev_dbg(&pdev
->dev
, "FreqMeas: %d\n", freqmeas
);
813 dev_dbg(&pdev
->dev
, "BusclkFreq: %lld\n", busclk_freq
);
814 dev_dbg(&pdev
->dev
, "RxRate: %lld\n", tmpval64
);
816 return (int)tmpval64
;
820 * Get DPLL lock or not info from stable interrupt status register.
821 * User application must use this control to get locked,
822 * then can do next PCM operation
824 static int fsl_spdif_rxrate_get(struct snd_kcontrol
*kcontrol
,
825 struct snd_ctl_elem_value
*ucontrol
)
827 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
828 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
829 int rate
= spdif_get_rxclk_rate(spdif_priv
, SPDIF_DEFAULT_GAINSEL
);
831 if (spdif_priv
->dpll_locked
)
832 ucontrol
->value
.integer
.value
[0] = rate
;
834 ucontrol
->value
.integer
.value
[0] = 0;
839 /* User bit sync mode info */
840 static int fsl_spdif_usync_info(struct snd_kcontrol
*kcontrol
,
841 struct snd_ctl_elem_info
*uinfo
)
843 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
845 uinfo
->value
.integer
.min
= 0;
846 uinfo
->value
.integer
.max
= 1;
852 * User bit sync mode:
853 * 1 CD User channel subcode
856 static int fsl_spdif_usync_get(struct snd_kcontrol
*kcontrol
,
857 struct snd_ctl_elem_value
*ucontrol
)
859 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
860 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
861 struct regmap
*regmap
= spdif_priv
->regmap
;
864 regmap_read(regmap
, REG_SPDIF_SRCD
, &val
);
865 ucontrol
->value
.integer
.value
[0] = (val
& SRCD_CD_USER
) != 0;
871 * User bit sync mode:
872 * 1 CD User channel subcode
875 static int fsl_spdif_usync_put(struct snd_kcontrol
*kcontrol
,
876 struct snd_ctl_elem_value
*ucontrol
)
878 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
879 struct fsl_spdif_priv
*spdif_priv
= snd_soc_dai_get_drvdata(cpu_dai
);
880 struct regmap
*regmap
= spdif_priv
->regmap
;
881 u32 val
= ucontrol
->value
.integer
.value
[0] << SRCD_CD_USER_OFFSET
;
883 regmap_update_bits(regmap
, REG_SPDIF_SRCD
, SRCD_CD_USER
, val
);
888 /* FSL SPDIF IEC958 controller defines */
889 static struct snd_kcontrol_new fsl_spdif_ctrls
[] = {
890 /* Status cchanel controller */
892 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
893 .name
= SNDRV_CTL_NAME_IEC958("", PLAYBACK
, DEFAULT
),
894 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
895 SNDRV_CTL_ELEM_ACCESS_WRITE
|
896 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
897 .info
= fsl_spdif_info
,
898 .get
= fsl_spdif_pb_get
,
899 .put
= fsl_spdif_pb_put
,
902 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
903 .name
= SNDRV_CTL_NAME_IEC958("", CAPTURE
, DEFAULT
),
904 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
905 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
906 .info
= fsl_spdif_info
,
907 .get
= fsl_spdif_capture_get
,
909 /* User bits controller */
911 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
912 .name
= "IEC958 Subcode Capture Default",
913 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
914 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
915 .info
= fsl_spdif_info
,
916 .get
= fsl_spdif_subcode_get
,
919 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
920 .name
= "IEC958 Q-subcode Capture Default",
921 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
922 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
923 .info
= fsl_spdif_qinfo
,
924 .get
= fsl_spdif_qget
,
926 /* Valid bit error controller */
928 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
929 .name
= "IEC958 V-Bit Errors",
930 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
931 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
932 .info
= fsl_spdif_vbit_info
,
933 .get
= fsl_spdif_vbit_get
,
935 /* DPLL lock info get controller */
937 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
938 .name
= "RX Sample Rate",
939 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
940 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
941 .info
= fsl_spdif_rxrate_info
,
942 .get
= fsl_spdif_rxrate_get
,
944 /* User bit sync mode set/get controller */
946 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
947 .name
= "IEC958 USyncMode CDText",
948 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
949 SNDRV_CTL_ELEM_ACCESS_WRITE
|
950 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
951 .info
= fsl_spdif_usync_info
,
952 .get
= fsl_spdif_usync_get
,
953 .put
= fsl_spdif_usync_put
,
957 static int fsl_spdif_dai_probe(struct snd_soc_dai
*dai
)
959 struct fsl_spdif_priv
*spdif_private
= snd_soc_dai_get_drvdata(dai
);
961 snd_soc_dai_init_dma_data(dai
, &spdif_private
->dma_params_tx
,
962 &spdif_private
->dma_params_rx
);
964 snd_soc_add_dai_controls(dai
, fsl_spdif_ctrls
, ARRAY_SIZE(fsl_spdif_ctrls
));
969 static struct snd_soc_dai_driver fsl_spdif_dai
= {
970 .probe
= &fsl_spdif_dai_probe
,
974 .rates
= FSL_SPDIF_RATES_PLAYBACK
,
975 .formats
= FSL_SPDIF_FORMATS_PLAYBACK
,
980 .rates
= FSL_SPDIF_RATES_CAPTURE
,
981 .formats
= FSL_SPDIF_FORMATS_CAPTURE
,
983 .ops
= &fsl_spdif_dai_ops
,
986 static const struct snd_soc_component_driver fsl_spdif_component
= {
990 /* FSL SPDIF REGMAP */
992 static bool fsl_spdif_readable_reg(struct device
*dev
, unsigned int reg
)
1002 case REG_SPDIF_SRCSH
:
1003 case REG_SPDIF_SRCSL
:
1006 case REG_SPDIF_STCSCH
:
1007 case REG_SPDIF_STCSCL
:
1008 case REG_SPDIF_SRFM
:
1016 static bool fsl_spdif_writeable_reg(struct device
*dev
, unsigned int reg
)
1020 case REG_SPDIF_SRCD
:
1021 case REG_SPDIF_SRPC
:
1026 case REG_SPDIF_STCSCH
:
1027 case REG_SPDIF_STCSCL
:
1035 static struct regmap_config fsl_spdif_regmap_config
= {
1040 .max_register
= REG_SPDIF_STC
,
1041 .readable_reg
= fsl_spdif_readable_reg
,
1042 .writeable_reg
= fsl_spdif_writeable_reg
,
1045 static u32
fsl_spdif_txclk_caldiv(struct fsl_spdif_priv
*spdif_priv
,
1046 struct clk
*clk
, u64 savesub
,
1047 enum spdif_txrate index
, bool round
)
1049 const u32 rate
[] = { 32000, 44100, 48000 };
1050 bool is_sysclk
= clk
== spdif_priv
->sysclk
;
1051 u64 rate_ideal
, rate_actual
, sub
;
1052 u32 sysclk_dfmin
, sysclk_dfmax
;
1053 u32 txclk_df
, sysclk_df
, arate
;
1055 /* The sysclk has an extra divisor [2, 512] */
1056 sysclk_dfmin
= is_sysclk
? 2 : 1;
1057 sysclk_dfmax
= is_sysclk
? 512 : 1;
1059 for (sysclk_df
= sysclk_dfmin
; sysclk_df
<= sysclk_dfmax
; sysclk_df
++) {
1060 for (txclk_df
= 1; txclk_df
<= 128; txclk_df
++) {
1061 rate_ideal
= rate
[index
] * (txclk_df
+ 1) * 64;
1063 rate_actual
= clk_round_rate(clk
, rate_ideal
);
1065 rate_actual
= clk_get_rate(clk
);
1067 arate
= rate_actual
/ 64;
1068 arate
/= txclk_df
* sysclk_df
;
1070 if (arate
== rate
[index
]) {
1073 spdif_priv
->txclk_df
[index
] = txclk_df
;
1074 spdif_priv
->sysclk_df
[index
] = sysclk_df
;
1075 spdif_priv
->txrate
[index
] = arate
;
1077 } else if (arate
/ rate
[index
] == 1) {
1078 /* A little bigger than expect */
1079 sub
= (u64
)(arate
- rate
[index
]) * 100000;
1080 do_div(sub
, rate
[index
]);
1084 spdif_priv
->txclk_df
[index
] = txclk_df
;
1085 spdif_priv
->sysclk_df
[index
] = sysclk_df
;
1086 spdif_priv
->txrate
[index
] = arate
;
1087 } else if (rate
[index
] / arate
== 1) {
1088 /* A little smaller than expect */
1089 sub
= (u64
)(rate
[index
] - arate
) * 100000;
1090 do_div(sub
, rate
[index
]);
1094 spdif_priv
->txclk_df
[index
] = txclk_df
;
1095 spdif_priv
->sysclk_df
[index
] = sysclk_df
;
1096 spdif_priv
->txrate
[index
] = arate
;
1105 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv
*spdif_priv
,
1106 enum spdif_txrate index
)
1108 const u32 rate
[] = { 32000, 44100, 48000 };
1109 struct platform_device
*pdev
= spdif_priv
->pdev
;
1110 struct device
*dev
= &pdev
->dev
;
1111 u64 savesub
= 100000, ret
;
1116 for (i
= 0; i
< STC_TXCLK_SRC_MAX
; i
++) {
1117 sprintf(tmp
, "rxtx%d", i
);
1118 clk
= devm_clk_get(&pdev
->dev
, tmp
);
1120 dev_err(dev
, "no rxtx%d clock in devicetree\n", i
);
1121 return PTR_ERR(clk
);
1123 if (!clk_get_rate(clk
))
1126 ret
= fsl_spdif_txclk_caldiv(spdif_priv
, clk
, savesub
, index
,
1127 i
== STC_TXCLK_SPDIF_ROOT
);
1132 spdif_priv
->txclk
[index
] = clk
;
1133 spdif_priv
->txclk_src
[index
] = i
;
1135 /* To quick catch a divisor, we allow a 0.1% deviation */
1140 dev_dbg(&pdev
->dev
, "use rxtx%d as tx clock source for %dHz sample rate\n",
1141 spdif_priv
->txclk_src
[index
], rate
[index
]);
1142 dev_dbg(&pdev
->dev
, "use txclk df %d for %dHz sample rate\n",
1143 spdif_priv
->txclk_df
[index
], rate
[index
]);
1144 if (spdif_priv
->txclk
[index
] == spdif_priv
->sysclk
)
1145 dev_dbg(&pdev
->dev
, "use sysclk df %d for %dHz sample rate\n",
1146 spdif_priv
->sysclk_df
[index
], rate
[index
]);
1147 dev_dbg(&pdev
->dev
, "the best rate for %dHz sample rate is %dHz\n",
1148 rate
[index
], spdif_priv
->txrate
[index
]);
1153 static int fsl_spdif_probe(struct platform_device
*pdev
)
1155 struct device_node
*np
= pdev
->dev
.of_node
;
1156 struct fsl_spdif_priv
*spdif_priv
;
1157 struct spdif_mixer_control
*ctrl
;
1158 struct resource
*res
;
1165 spdif_priv
= devm_kzalloc(&pdev
->dev
,
1166 sizeof(struct fsl_spdif_priv
) + strlen(np
->name
) + 1,
1171 strcpy(spdif_priv
->name
, np
->name
);
1173 spdif_priv
->pdev
= pdev
;
1175 /* Initialize this copy of the CPU DAI driver structure */
1176 memcpy(&spdif_priv
->cpu_dai_drv
, &fsl_spdif_dai
, sizeof(fsl_spdif_dai
));
1177 spdif_priv
->cpu_dai_drv
.name
= spdif_priv
->name
;
1179 if (of_property_read_bool(np
, "big-endian"))
1180 fsl_spdif_regmap_config
.val_format_endian
= REGMAP_ENDIAN_BIG
;
1182 /* Get the addresses and IRQ */
1183 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1184 regs
= devm_ioremap_resource(&pdev
->dev
, res
);
1186 return PTR_ERR(regs
);
1188 spdif_priv
->regmap
= devm_regmap_init_mmio_clk(&pdev
->dev
,
1189 "core", regs
, &fsl_spdif_regmap_config
);
1190 if (IS_ERR(spdif_priv
->regmap
)) {
1191 dev_err(&pdev
->dev
, "regmap init failed\n");
1192 return PTR_ERR(spdif_priv
->regmap
);
1195 irq
= platform_get_irq(pdev
, 0);
1197 dev_err(&pdev
->dev
, "no irq for node %s\n", np
->full_name
);
1201 ret
= devm_request_irq(&pdev
->dev
, irq
, spdif_isr
, 0,
1202 spdif_priv
->name
, spdif_priv
);
1204 dev_err(&pdev
->dev
, "could not claim irq %u\n", irq
);
1208 /* Get system clock for rx clock rate calculation */
1209 spdif_priv
->sysclk
= devm_clk_get(&pdev
->dev
, "rxtx5");
1210 if (IS_ERR(spdif_priv
->sysclk
)) {
1211 dev_err(&pdev
->dev
, "no sys clock (rxtx5) in devicetree\n");
1212 return PTR_ERR(spdif_priv
->sysclk
);
1215 /* Get core clock for data register access via DMA */
1216 spdif_priv
->coreclk
= devm_clk_get(&pdev
->dev
, "core");
1217 if (IS_ERR(spdif_priv
->coreclk
)) {
1218 dev_err(&pdev
->dev
, "no core clock in devicetree\n");
1219 return PTR_ERR(spdif_priv
->coreclk
);
1222 /* Select clock source for rx/tx clock */
1223 spdif_priv
->rxclk
= devm_clk_get(&pdev
->dev
, "rxtx1");
1224 if (IS_ERR(spdif_priv
->rxclk
)) {
1225 dev_err(&pdev
->dev
, "no rxtx1 clock in devicetree\n");
1226 return PTR_ERR(spdif_priv
->rxclk
);
1228 spdif_priv
->rxclk_src
= DEFAULT_RXCLK_SRC
;
1230 for (i
= 0; i
< SPDIF_TXRATE_MAX
; i
++) {
1231 ret
= fsl_spdif_probe_txclk(spdif_priv
, i
);
1236 /* Initial spinlock for control data */
1237 ctrl
= &spdif_priv
->fsl_spdif_control
;
1238 spin_lock_init(&ctrl
->ctl_lock
);
1240 /* Init tx channel status default value */
1241 ctrl
->ch_status
[0] =
1242 IEC958_AES0_CON_NOT_COPYRIGHT
| IEC958_AES0_CON_EMPHASIS_5015
;
1243 ctrl
->ch_status
[1] = IEC958_AES1_CON_DIGDIGCONV_ID
;
1244 ctrl
->ch_status
[2] = 0x00;
1245 ctrl
->ch_status
[3] =
1246 IEC958_AES3_CON_FS_44100
| IEC958_AES3_CON_CLOCK_1000PPM
;
1248 spdif_priv
->dpll_locked
= false;
1250 spdif_priv
->dma_params_tx
.maxburst
= FSL_SPDIF_TXFIFO_WML
;
1251 spdif_priv
->dma_params_rx
.maxburst
= FSL_SPDIF_RXFIFO_WML
;
1252 spdif_priv
->dma_params_tx
.addr
= res
->start
+ REG_SPDIF_STL
;
1253 spdif_priv
->dma_params_rx
.addr
= res
->start
+ REG_SPDIF_SRL
;
1255 /* Register with ASoC */
1256 dev_set_drvdata(&pdev
->dev
, spdif_priv
);
1258 ret
= devm_snd_soc_register_component(&pdev
->dev
, &fsl_spdif_component
,
1259 &spdif_priv
->cpu_dai_drv
, 1);
1261 dev_err(&pdev
->dev
, "failed to register DAI: %d\n", ret
);
1265 ret
= imx_pcm_dma_init(pdev
);
1267 dev_err(&pdev
->dev
, "imx_pcm_dma_init failed: %d\n", ret
);
1272 static const struct of_device_id fsl_spdif_dt_ids
[] = {
1273 { .compatible
= "fsl,imx35-spdif", },
1274 { .compatible
= "fsl,vf610-spdif", },
1277 MODULE_DEVICE_TABLE(of
, fsl_spdif_dt_ids
);
1279 static struct platform_driver fsl_spdif_driver
= {
1281 .name
= "fsl-spdif-dai",
1282 .owner
= THIS_MODULE
,
1283 .of_match_table
= fsl_spdif_dt_ids
,
1285 .probe
= fsl_spdif_probe
,
1288 module_platform_driver(fsl_spdif_driver
);
1290 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1291 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1292 MODULE_LICENSE("GPL v2");
1293 MODULE_ALIAS("platform:fsl-spdif-dai");