drivers/irqchip/irq-bcm2836.c

   1 /*
   2  * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
   3  *
   4  * Copyright 2015 Broadcom
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/cpu.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/irqchip.h>
  21 #include <linux/irqdomain.h>
  22 #include <linux/irqchip/irq-bcm2836.h>
  23
  24 #include <asm/exception.h>
  25
  26 struct bcm2836_arm_irqchip_intc {
  27         struct irq_domain *domain;
  28         void __iomem *base;
  29 };
  30
  31 static struct bcm2836_arm_irqchip_intc intc  __read_mostly;
  32
  33 static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
  34                                                  unsigned int bit,
  35                                                  int cpu)
  36 {
  37         void __iomem *reg = intc.base + reg_offset + 4 * cpu;
  38
  39         writel(readl(reg) & ~BIT(bit), reg);
  40 }
  41
  42 static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
  43                                                    unsigned int bit,
  44                                                  int cpu)
  45 {
  46         void __iomem *reg = intc.base + reg_offset + 4 * cpu;
  47
  48         writel(readl(reg) | BIT(bit), reg);
  49 }
  50
  51 static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
  52 {
  53         bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
  54                                              d->hwirq - LOCAL_IRQ_CNTPSIRQ,
  55                                              smp_processor_id());
  56 }
  57
  58 static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
  59 {
  60         bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
  61                                                d->hwirq - LOCAL_IRQ_CNTPSIRQ,
  62                                                smp_processor_id());
  63 }
  64
  65 static struct irq_chip bcm2836_arm_irqchip_timer = {
  66         .name           = "bcm2836-timer",
  67         .irq_mask       = bcm2836_arm_irqchip_mask_timer_irq,
  68         .irq_unmask     = bcm2836_arm_irqchip_unmask_timer_irq,
  69 };
  70
  71 static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
  72 {
  73         writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
  74 }
  75
  76 static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
  77 {
  78         writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
  79 }
  80
  81 static struct irq_chip bcm2836_arm_irqchip_pmu = {
  82         .name           = "bcm2836-pmu",
  83         .irq_mask       = bcm2836_arm_irqchip_mask_pmu_irq,
  84         .irq_unmask     = bcm2836_arm_irqchip_unmask_pmu_irq,
  85 };
  86
  87 static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
  88 {
  89 }
  90
  91 static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
  92 {
  93 }
  94
  95 static struct irq_chip bcm2836_arm_irqchip_gpu = {
  96         .name           = "bcm2836-gpu",
  97         .irq_mask       = bcm2836_arm_irqchip_mask_gpu_irq,
  98         .irq_unmask     = bcm2836_arm_irqchip_unmask_gpu_irq,
  99 };
 100
 101 static void bcm2836_arm_irqchip_register_irq(int hwirq, struct irq_chip *chip)
 102 {
 103         int irq = irq_create_mapping(intc.domain, hwirq);
 104
 105         irq_set_percpu_devid(irq);
 106         irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq);
 107         irq_set_status_flags(irq, IRQ_NOAUTOEN);
 108 }
 109
 110 static void
 111 __exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
 112 {
 113         int cpu = smp_processor_id();
 114         u32 stat;
 115
 116         stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
 117         if (stat & BIT(LOCAL_IRQ_MAILBOX0)) {
 118 #ifdef CONFIG_SMP
 119                 void __iomem *mailbox0 = (intc.base +
 120                                           LOCAL_MAILBOX0_CLR0 + 16 * cpu);
 121                 u32 mbox_val = readl(mailbox0);
 122                 u32 ipi = ffs(mbox_val) - 1;
 123
 124                 writel(1 << ipi, mailbox0);
 125                 handle_IPI(ipi, regs);
 126 #endif
 127         } else if (stat) {
 128                 u32 hwirq = ffs(stat) - 1;
 129
 130                 handle_domain_irq(intc.domain, hwirq, regs);
 131         }
 132 }
 133
 134 #ifdef CONFIG_SMP
 135 static void bcm2836_arm_irqchip_send_ipi(const struct cpumask *mask,
 136                                          unsigned int ipi)
 137 {
 138         int cpu;
 139         void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
 140
 141         /*
 142          * Ensure that stores to normal memory are visible to the
 143          * other CPUs before issuing the IPI.
 144          */
 145         smp_wmb();
 146
 147         for_each_cpu(cpu, mask) {
 148                 writel(1 << ipi, mailbox0_base + 16 * cpu);
 149         }
 150 }
 151
 152 static int bcm2836_cpu_starting(unsigned int cpu)
 153 {
 154         bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
 155                                                cpu);
 156         return 0;
 157 }
 158
 159 static int bcm2836_cpu_dying(unsigned int cpu)
 160 {
 161         bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
 162                                              cpu);
 163         return 0;
 164 }
 165 #endif
 166
 167 static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
 168         .xlate = irq_domain_xlate_onecell
 169 };
 170
 171 static void
 172 bcm2836_arm_irqchip_smp_init(void)
 173 {
 174 #ifdef CONFIG_SMP
 175         /* Unmask IPIs to the boot CPU. */
 176         cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING,
 177                           "irqchip/bcm2836:starting", bcm2836_cpu_starting,
 178                           bcm2836_cpu_dying);
 179
 180         set_smp_cross_call(bcm2836_arm_irqchip_send_ipi);
 181 #endif
 182 }
 183
 184 /*
 185  * The LOCAL_IRQ_CNT* timer firings are based off of the external
 186  * oscillator with some scaling.  The firmware sets up CNTFRQ to
 187  * report 19.2Mhz, but doesn't set up the scaling registers.
 188  */
 189 static void bcm2835_init_local_timer_frequency(void)
 190 {
 191         /*
 192          * Set the timer to source from the 19.2Mhz crystal clock (bit
 193          * 8 unset), and only increment by 1 instead of 2 (bit 9
 194          * unset).
 195          */
 196         writel(0, intc.base + LOCAL_CONTROL);
 197
 198         /*
 199          * Set the timer prescaler to 1:1 (timer freq = input freq *
 200          * 2**31 / prescaler)
 201          */
 202         writel(0x80000000, intc.base + LOCAL_PRESCALER);
 203 }
 204
 205 static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
 206                                                       struct device_node *parent)
 207 {
 208         intc.base = of_iomap(node, 0);
 209         if (!intc.base) {
 210                 panic("%pOF: unable to map local interrupt registers\n", node);
 211         }
 212
 213         bcm2835_init_local_timer_frequency();
 214
 215         intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
 216                                             &bcm2836_arm_irqchip_intc_ops,
 217                                             NULL);
 218         if (!intc.domain)
 219                 panic("%pOF: unable to create IRQ domain\n", node);
 220
 221         bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPSIRQ,
 222                                          &bcm2836_arm_irqchip_timer);
 223         bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPNSIRQ,
 224                                          &bcm2836_arm_irqchip_timer);
 225         bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTHPIRQ,
 226                                          &bcm2836_arm_irqchip_timer);
 227         bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTVIRQ,
 228                                          &bcm2836_arm_irqchip_timer);
 229         bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_GPU_FAST,
 230                                          &bcm2836_arm_irqchip_gpu);
 231         bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_PMU_FAST,
 232                                          &bcm2836_arm_irqchip_pmu);
 233
 234         bcm2836_arm_irqchip_smp_init();
 235
 236         set_handle_irq(bcm2836_arm_irqchip_handle_irq);
 237         return 0;
 238 }
 239
 240 IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
 241                 bcm2836_arm_irqchip_l1_intc_of_init);