4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if MMU
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
46 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
52 select GENERIC_KERNEL_THREAD
54 The ARM series is a line of low-power-consumption RISC chip designs
55 licensed by ARM Ltd and targeted at embedded applications and
56 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
57 manufactured, but legacy ARM-based PC hardware remains popular in
58 Europe. There is an ARM Linux project with a web page at
59 <http://www.arm.linux.org.uk/>.
61 config ARM_HAS_SG_CHAIN
64 config NEED_SG_DMA_LENGTH
67 config ARM_DMA_USE_IOMMU
68 select NEED_SG_DMA_LENGTH
69 select ARM_HAS_SG_CHAIN
78 config SYS_SUPPORTS_APM_EMULATION
86 select GENERIC_ALLOCATOR
97 The Extended Industry Standard Architecture (EISA) bus was
98 developed as an open alternative to the IBM MicroChannel bus.
100 The EISA bus provided some of the features of the IBM MicroChannel
101 bus while maintaining backward compatibility with cards made for
102 the older ISA bus. The EISA bus saw limited use between 1988 and
103 1995 when it was made obsolete by the PCI bus.
105 Say Y here if you are building a kernel for an EISA-based machine.
112 config STACKTRACE_SUPPORT
116 config HAVE_LATENCYTOP_SUPPORT
121 config LOCKDEP_SUPPORT
125 config TRACE_IRQFLAGS_SUPPORT
129 config RWSEM_GENERIC_SPINLOCK
133 config RWSEM_XCHGADD_ALGORITHM
136 config ARCH_HAS_ILOG2_U32
139 config ARCH_HAS_ILOG2_U64
142 config ARCH_HAS_CPUFREQ
145 Internal node to signify that the ARCH has CPUFREQ support
146 and that the relevant menu configurations are displayed for
149 config GENERIC_HWEIGHT
153 config GENERIC_CALIBRATE_DELAY
157 config ARCH_MAY_HAVE_PC_FDC
163 config NEED_DMA_MAP_STATE
166 config ARCH_HAS_DMA_SET_COHERENT_MASK
169 config GENERIC_ISA_DMA
175 config NEED_RET_TO_USER
183 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
184 default DRAM_BASE if REMAP_VECTORS_TO_RAM
187 The base address of exception vectors.
189 config ARM_PATCH_PHYS_VIRT
190 bool "Patch physical to virtual translations at runtime" if EMBEDDED
192 depends on !XIP_KERNEL && MMU
193 depends on !ARCH_REALVIEW || !SPARSEMEM
195 Patch phys-to-virt and virt-to-phys translation functions at
196 boot and module load time according to the position of the
197 kernel in system memory.
199 This can only be used with non-XIP MMU kernels where the base
200 of physical memory is at a 16MB boundary.
202 Only disable this option if you know that you do not require
203 this feature (eg, building a kernel for a single machine) and
204 you need to shrink the kernel to the minimal size.
206 config NEED_MACH_IO_H
209 Select this when mach/io.h is required to provide special
210 definitions for this platform. The need for mach/io.h should
211 be avoided when possible.
213 config NEED_MACH_MEMORY_H
216 Select this when mach/memory.h is required to provide special
217 definitions for this platform. The need for mach/memory.h should
218 be avoided when possible.
221 hex "Physical address of main memory" if MMU
222 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
223 default DRAM_BASE if !MMU
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
232 source "init/Kconfig"
234 source "kernel/Kconfig.freezer"
239 bool "MMU-based Paged Memory Management Support"
242 Select if you want MMU-based virtualised addressing space
243 support by paged memory management. If unsure, say 'Y'.
246 # The "ARM system type" choice list is ordered alphabetically by option
247 # text. Please add new entries in the option alphabetic order.
250 prompt "ARM system type"
251 default ARCH_VERSATILE
254 bool "Altera SOCFPGA family"
255 select ARCH_WANT_OPTIONAL_GPIOLIB
263 select DW_APB_TIMER_OF
264 select GENERIC_CLOCKEVENTS
265 select GPIO_PL061 if GPIOLIB
270 This enables support for Altera SOCFPGA Cyclone V platform
272 config ARCH_INTEGRATOR
273 bool "ARM Ltd. Integrator family"
275 select ARCH_HAS_CPUFREQ
280 select GENERIC_CLOCKEVENTS
281 select PLAT_VERSATILE
282 select PLAT_VERSATILE_FPGA_IRQ
283 select NEED_MACH_IO_H
284 select NEED_MACH_MEMORY_H
286 select MULTI_IRQ_HANDLER
288 Support for ARM's Integrator platform.
291 bool "ARM Ltd. RealView family"
294 select HAVE_MACH_CLKDEV
296 select GENERIC_CLOCKEVENTS
297 select ARCH_WANT_OPTIONAL_GPIOLIB
298 select PLAT_VERSATILE
299 select PLAT_VERSATILE_CLOCK
300 select PLAT_VERSATILE_CLCD
301 select ARM_TIMER_SP804
302 select GPIO_PL061 if GPIOLIB
303 select NEED_MACH_MEMORY_H
305 This enables support for ARM Ltd RealView boards.
307 config ARCH_VERSATILE
308 bool "ARM Ltd. Versatile family"
312 select HAVE_MACH_CLKDEV
314 select GENERIC_CLOCKEVENTS
315 select ARCH_WANT_OPTIONAL_GPIOLIB
316 select NEED_MACH_IO_H if PCI
317 select PLAT_VERSATILE
318 select PLAT_VERSATILE_CLOCK
319 select PLAT_VERSATILE_CLCD
320 select PLAT_VERSATILE_FPGA_IRQ
321 select ARM_TIMER_SP804
323 This enables support for ARM Ltd Versatile board.
326 bool "ARM Ltd. Versatile Express family"
327 select ARCH_WANT_OPTIONAL_GPIOLIB
329 select ARM_TIMER_SP804
332 select GENERIC_CLOCKEVENTS
334 select HAVE_PATA_PLATFORM
337 select PLAT_VERSATILE
338 select PLAT_VERSATILE_CLCD
339 select REGULATOR_FIXED_VOLTAGE if REGULATOR
341 This enables support for the ARM Ltd Versatile Express boards.
345 select ARCH_REQUIRE_GPIOLIB
349 select NEED_MACH_IO_H if PCCARD
351 This enables support for systems based on Atmel
352 AT91RM9200 and AT91SAM9* processors.
355 bool "Broadcom BCMRING"
359 select ARM_TIMER_SP804
361 select GENERIC_CLOCKEVENTS
362 select ARCH_WANT_OPTIONAL_GPIOLIB
364 Support for Broadcom's BCMRing platform.
367 bool "Calxeda Highbank-based"
368 select ARCH_WANT_OPTIONAL_GPIOLIB
371 select ARM_TIMER_SP804
376 select GENERIC_CLOCKEVENTS
382 Support for the Calxeda Highbank SoC based boards.
385 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
387 select ARCH_USES_GETTIMEOFFSET
388 select NEED_MACH_MEMORY_H
390 Support for Cirrus Logic 711x/721x/731x based boards.
393 bool "Cavium Networks CNS3XXX family"
395 select GENERIC_CLOCKEVENTS
397 select MIGHT_HAVE_CACHE_L2X0
398 select MIGHT_HAVE_PCI
399 select PCI_DOMAINS if PCI
401 Support for Cavium Networks CNS3XXX platform.
404 bool "Cortina Systems Gemini"
406 select ARCH_REQUIRE_GPIOLIB
407 select ARCH_USES_GETTIMEOFFSET
409 Support for the Cortina Systems Gemini family SoCs
412 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
415 select ARCH_REQUIRE_GPIOLIB
416 select GENERIC_CLOCKEVENTS
418 select GENERIC_IRQ_CHIP
419 select MIGHT_HAVE_CACHE_L2X0
425 Support for CSR SiRFSoC ARM Cortex A9 Platform
432 select ARCH_USES_GETTIMEOFFSET
433 select NEED_MACH_IO_H
434 select NEED_MACH_MEMORY_H
436 This is an evaluation board for the StrongARM processor available
437 from Digital. It has limited hardware on-board, including an
438 Ethernet interface, two PCMCIA sockets, two serial ports and a
447 select ARCH_REQUIRE_GPIOLIB
448 select ARCH_HAS_HOLES_MEMORYMODEL
449 select ARCH_USES_GETTIMEOFFSET
450 select NEED_MACH_MEMORY_H
452 This enables support for the Cirrus EP93xx series of CPUs.
454 config ARCH_FOOTBRIDGE
458 select GENERIC_CLOCKEVENTS
460 select NEED_MACH_IO_H
461 select NEED_MACH_MEMORY_H
463 Support for systems based on the DC21285 companion chip
464 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
467 bool "Freescale MXC/iMX-based"
468 select GENERIC_CLOCKEVENTS
469 select ARCH_REQUIRE_GPIOLIB
472 select GENERIC_IRQ_CHIP
473 select MULTI_IRQ_HANDLER
477 Support for Freescale MXC/iMX-based family of processors
480 bool "Freescale MXS-based"
481 select GENERIC_CLOCKEVENTS
482 select ARCH_REQUIRE_GPIOLIB
486 select HAVE_CLK_PREPARE
490 Support for Freescale MXS-based family of processors
493 bool "Hilscher NetX based"
497 select GENERIC_CLOCKEVENTS
499 This enables support for systems based on the Hilscher NetX Soc
502 bool "Hynix HMS720x-based"
505 select ARCH_USES_GETTIMEOFFSET
507 This enables support for systems based on the Hynix HMS720x
515 select ARCH_SUPPORTS_MSI
517 select NEED_MACH_IO_H
518 select NEED_MACH_MEMORY_H
519 select NEED_RET_TO_USER
521 Support for Intel's IOP13XX (XScale) family of processors.
527 select NEED_MACH_IO_H
528 select NEED_RET_TO_USER
531 select ARCH_REQUIRE_GPIOLIB
533 Support for Intel's 80219 and IOP32X (XScale) family of
540 select NEED_MACH_IO_H
541 select NEED_RET_TO_USER
544 select ARCH_REQUIRE_GPIOLIB
546 Support for Intel's IOP33X (XScale) family of processors.
551 select ARCH_HAS_DMA_SET_COHERENT_MASK
554 select ARCH_REQUIRE_GPIOLIB
555 select GENERIC_CLOCKEVENTS
556 select MIGHT_HAVE_PCI
557 select NEED_MACH_IO_H
558 select DMABOUNCE if PCI
560 Support for Intel's IXP4XX (XScale) family of processors.
563 bool "Marvell SOCs with Device Tree support"
564 select GENERIC_CLOCKEVENTS
565 select MULTI_IRQ_HANDLER
568 select GENERIC_IRQ_CHIP
572 Support for the Marvell SoC Family with device tree support
578 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
580 select NEED_MACH_IO_H
583 Support for the Marvell Dove SoC 88AP510
586 bool "Marvell Kirkwood"
589 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
591 select NEED_MACH_IO_H
594 Support for the following Marvell Kirkwood series SoCs:
595 88F6180, 88F6192 and 88F6281.
601 select ARCH_REQUIRE_GPIOLIB
604 select USB_ARCH_HAS_OHCI
606 select GENERIC_CLOCKEVENTS
610 Support for the NXP LPC32XX family of processors
613 bool "Marvell MV78xx0"
616 select ARCH_REQUIRE_GPIOLIB
617 select GENERIC_CLOCKEVENTS
618 select NEED_MACH_IO_H
621 Support for the following Marvell MV78xx0 series SoCs:
629 select ARCH_REQUIRE_GPIOLIB
630 select GENERIC_CLOCKEVENTS
631 select NEED_MACH_IO_H
634 Support for the following Marvell Orion 5x series SoCs:
635 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
636 Orion-2 (5281), Orion-1-90 (6183).
639 bool "Marvell PXA168/910/MMP2"
641 select ARCH_REQUIRE_GPIOLIB
643 select GENERIC_CLOCKEVENTS
648 select GENERIC_ALLOCATOR
650 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
653 bool "Micrel/Kendin KS8695"
655 select ARCH_REQUIRE_GPIOLIB
656 select ARCH_USES_GETTIMEOFFSET
657 select NEED_MACH_MEMORY_H
659 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
660 System-on-Chip devices.
663 bool "Nuvoton W90X900 CPU"
665 select ARCH_REQUIRE_GPIOLIB
668 select GENERIC_CLOCKEVENTS
670 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
671 At present, the w90x900 has been renamed nuc900, regarding
672 the ARM series product line, you can login the following
673 link address to know more.
675 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
676 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
682 select GENERIC_CLOCKEVENTS
686 select MIGHT_HAVE_CACHE_L2X0
687 select NEED_MACH_IO_H if PCI
688 select ARCH_HAS_CPUFREQ
691 This enables support for NVIDIA Tegra based systems (Tegra APX,
692 Tegra 6xx and Tegra 2 series).
694 config ARCH_PICOXCELL
695 bool "Picochip picoXcell"
696 select ARCH_REQUIRE_GPIOLIB
697 select ARM_PATCH_PHYS_VIRT
701 select DW_APB_TIMER_OF
702 select GENERIC_CLOCKEVENTS
709 This enables support for systems based on the Picochip picoXcell
710 family of Femtocell devices. The picoxcell support requires device tree
714 bool "Philips Nexperia PNX4008 Mobile"
717 select ARCH_USES_GETTIMEOFFSET
719 This enables support for Philips PNX4008 mobile platform.
722 bool "PXA2xx/PXA3xx-based"
725 select ARCH_HAS_CPUFREQ
728 select ARCH_REQUIRE_GPIOLIB
729 select GENERIC_CLOCKEVENTS
734 select MULTI_IRQ_HANDLER
735 select ARM_CPU_SUSPEND if PM
738 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
743 select GENERIC_CLOCKEVENTS
744 select ARCH_REQUIRE_GPIOLIB
747 Support for Qualcomm MSM/QSD based systems. This runs on the
748 apps processor of the MSM/QSD and depends on a shared memory
749 interface to the modem processor which runs the baseband
750 stack and controls some vital subsystems
751 (clock and power control, etc).
754 bool "Renesas SH-Mobile / R-Mobile"
757 select HAVE_MACH_CLKDEV
759 select GENERIC_CLOCKEVENTS
760 select MIGHT_HAVE_CACHE_L2X0
763 select MULTI_IRQ_HANDLER
764 select PM_GENERIC_DOMAINS if PM
765 select NEED_MACH_MEMORY_H
767 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
773 select ARCH_MAY_HAVE_PC_FDC
774 select HAVE_PATA_PLATFORM
777 select ARCH_SPARSEMEM_ENABLE
778 select ARCH_USES_GETTIMEOFFSET
780 select NEED_MACH_IO_H
781 select NEED_MACH_MEMORY_H
783 On the Acorn Risc-PC, Linux can support the internal IDE disk and
784 CD-ROM interface, serial and parallel port, and the floppy drive.
791 select ARCH_SPARSEMEM_ENABLE
793 select ARCH_HAS_CPUFREQ
795 select GENERIC_CLOCKEVENTS
797 select ARCH_REQUIRE_GPIOLIB
799 select NEED_MACH_MEMORY_H
802 Support for StrongARM 11x0 based boards.
805 bool "Samsung S3C24XX SoCs"
807 select ARCH_HAS_CPUFREQ
810 select ARCH_USES_GETTIMEOFFSET
811 select HAVE_S3C2410_I2C if I2C
812 select HAVE_S3C_RTC if RTC_CLASS
813 select HAVE_S3C2410_WATCHDOG if WATCHDOG
814 select NEED_MACH_IO_H
816 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
817 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
818 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
819 Samsung SMDK2410 development board (and derivatives).
822 bool "Samsung S3C64XX"
830 select ARCH_USES_GETTIMEOFFSET
831 select ARCH_HAS_CPUFREQ
832 select ARCH_REQUIRE_GPIOLIB
833 select SAMSUNG_CLKSRC
834 select SAMSUNG_IRQ_VIC_TIMER
835 select S3C_GPIO_TRACK
837 select USB_ARCH_HAS_OHCI
838 select SAMSUNG_GPIOLIB_4BIT
839 select HAVE_S3C2410_I2C if I2C
840 select HAVE_S3C2410_WATCHDOG if WATCHDOG
842 Samsung S3C64XX series based systems
845 bool "Samsung S5P6440 S5P6450"
851 select HAVE_S3C2410_WATCHDOG if WATCHDOG
852 select GENERIC_CLOCKEVENTS
853 select HAVE_S3C2410_I2C if I2C
854 select HAVE_S3C_RTC if RTC_CLASS
856 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
860 bool "Samsung S5PC100"
865 select ARCH_USES_GETTIMEOFFSET
866 select HAVE_S3C2410_I2C if I2C
867 select HAVE_S3C_RTC if RTC_CLASS
868 select HAVE_S3C2410_WATCHDOG if WATCHDOG
870 Samsung S5PC100 series based systems
873 bool "Samsung S5PV210/S5PC110"
875 select ARCH_SPARSEMEM_ENABLE
876 select ARCH_HAS_HOLES_MEMORYMODEL
881 select ARCH_HAS_CPUFREQ
882 select GENERIC_CLOCKEVENTS
883 select HAVE_S3C2410_I2C if I2C
884 select HAVE_S3C_RTC if RTC_CLASS
885 select HAVE_S3C2410_WATCHDOG if WATCHDOG
886 select NEED_MACH_MEMORY_H
888 Samsung S5PV210/S5PC110 series based systems
891 bool "SAMSUNG EXYNOS"
893 select ARCH_SPARSEMEM_ENABLE
894 select ARCH_HAS_HOLES_MEMORYMODEL
898 select ARCH_HAS_CPUFREQ
899 select GENERIC_CLOCKEVENTS
900 select HAVE_S3C_RTC if RTC_CLASS
901 select HAVE_S3C2410_I2C if I2C
902 select HAVE_S3C2410_WATCHDOG if WATCHDOG
903 select NEED_MACH_MEMORY_H
905 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
914 select ARCH_USES_GETTIMEOFFSET
915 select NEED_MACH_MEMORY_H
916 select NEED_MACH_IO_H
918 Support for the StrongARM based Digital DNARD machine, also known
919 as "Shark" (<http://www.shark-linux.de/shark.html>).
922 bool "ST-Ericsson U300 Series"
928 select ARM_PATCH_PHYS_VIRT
930 select GENERIC_CLOCKEVENTS
934 select ARCH_REQUIRE_GPIOLIB
936 Support for ST-Ericsson U300 series mobile platforms.
939 bool "ST-Ericsson U8500 Series"
943 select GENERIC_CLOCKEVENTS
945 select ARCH_REQUIRE_GPIOLIB
946 select ARCH_HAS_CPUFREQ
948 select MIGHT_HAVE_CACHE_L2X0
950 Support for ST-Ericsson's Ux500 architecture
953 bool "STMicroelectronics Nomadik"
958 select GENERIC_CLOCKEVENTS
960 select MIGHT_HAVE_CACHE_L2X0
961 select ARCH_REQUIRE_GPIOLIB
963 Support for the Nomadik platform by ST-Ericsson
967 select GENERIC_CLOCKEVENTS
968 select ARCH_REQUIRE_GPIOLIB
972 select GENERIC_ALLOCATOR
973 select GENERIC_IRQ_CHIP
974 select ARCH_HAS_HOLES_MEMORYMODEL
976 Support for TI's DaVinci platform.
982 select ARCH_REQUIRE_GPIOLIB
983 select ARCH_HAS_CPUFREQ
985 select GENERIC_CLOCKEVENTS
986 select ARCH_HAS_HOLES_MEMORYMODEL
988 Support for TI's OMAP platform (OMAP1/2/3/4).
993 select ARCH_REQUIRE_GPIOLIB
997 select GENERIC_CLOCKEVENTS
1000 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1003 bool "VIA/WonderMedia 85xx"
1006 select ARCH_HAS_CPUFREQ
1007 select GENERIC_CLOCKEVENTS
1008 select ARCH_REQUIRE_GPIOLIB
1010 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1013 bool "Xilinx Zynq ARM Cortex A9 Platform"
1015 select GENERIC_CLOCKEVENTS
1016 select CLKDEV_LOOKUP
1020 select MIGHT_HAVE_CACHE_L2X0
1023 Support for Xilinx Zynq ARM Cortex A9 Platform
1027 # This is sorted alphabetically by mach-* pathname. However, plat-*
1028 # Kconfigs may be included either alphabetically (according to the
1029 # plat- suffix) or along side the corresponding mach-* source.
1031 source "arch/arm/mach-mvebu/Kconfig"
1033 source "arch/arm/mach-at91/Kconfig"
1035 source "arch/arm/mach-bcmring/Kconfig"
1037 source "arch/arm/mach-clps711x/Kconfig"
1039 source "arch/arm/mach-cns3xxx/Kconfig"
1041 source "arch/arm/mach-davinci/Kconfig"
1043 source "arch/arm/mach-dove/Kconfig"
1045 source "arch/arm/mach-ep93xx/Kconfig"
1047 source "arch/arm/mach-footbridge/Kconfig"
1049 source "arch/arm/mach-gemini/Kconfig"
1051 source "arch/arm/mach-h720x/Kconfig"
1053 source "arch/arm/mach-integrator/Kconfig"
1055 source "arch/arm/mach-iop32x/Kconfig"
1057 source "arch/arm/mach-iop33x/Kconfig"
1059 source "arch/arm/mach-iop13xx/Kconfig"
1061 source "arch/arm/mach-ixp4xx/Kconfig"
1063 source "arch/arm/mach-kirkwood/Kconfig"
1065 source "arch/arm/mach-ks8695/Kconfig"
1067 source "arch/arm/mach-msm/Kconfig"
1069 source "arch/arm/mach-mv78xx0/Kconfig"
1071 source "arch/arm/plat-mxc/Kconfig"
1073 source "arch/arm/mach-mxs/Kconfig"
1075 source "arch/arm/mach-netx/Kconfig"
1077 source "arch/arm/mach-nomadik/Kconfig"
1078 source "arch/arm/plat-nomadik/Kconfig"
1080 source "arch/arm/plat-omap/Kconfig"
1082 source "arch/arm/mach-omap1/Kconfig"
1084 source "arch/arm/mach-omap2/Kconfig"
1086 source "arch/arm/mach-orion5x/Kconfig"
1088 source "arch/arm/mach-pxa/Kconfig"
1089 source "arch/arm/plat-pxa/Kconfig"
1091 source "arch/arm/mach-mmp/Kconfig"
1093 source "arch/arm/mach-realview/Kconfig"
1095 source "arch/arm/mach-sa1100/Kconfig"
1097 source "arch/arm/plat-samsung/Kconfig"
1098 source "arch/arm/plat-s3c24xx/Kconfig"
1100 source "arch/arm/plat-spear/Kconfig"
1102 source "arch/arm/mach-s3c24xx/Kconfig"
1104 source "arch/arm/mach-s3c2412/Kconfig"
1105 source "arch/arm/mach-s3c2440/Kconfig"
1109 source "arch/arm/mach-s3c64xx/Kconfig"
1112 source "arch/arm/mach-s5p64x0/Kconfig"
1114 source "arch/arm/mach-s5pc100/Kconfig"
1116 source "arch/arm/mach-s5pv210/Kconfig"
1118 source "arch/arm/mach-exynos/Kconfig"
1120 source "arch/arm/mach-shmobile/Kconfig"
1122 source "arch/arm/mach-tegra/Kconfig"
1124 source "arch/arm/mach-u300/Kconfig"
1126 source "arch/arm/mach-ux500/Kconfig"
1128 source "arch/arm/mach-versatile/Kconfig"
1130 source "arch/arm/mach-vexpress/Kconfig"
1131 source "arch/arm/plat-versatile/Kconfig"
1133 source "arch/arm/mach-vt8500/Kconfig"
1135 source "arch/arm/mach-w90x900/Kconfig"
1137 # Definitions to make life easier
1143 select GENERIC_CLOCKEVENTS
1148 select GENERIC_IRQ_CHIP
1155 config PLAT_VERSATILE
1158 config ARM_TIMER_SP804
1161 select HAVE_SCHED_CLOCK
1163 source arch/arm/mm/Kconfig
1167 default 16 if ARCH_EP93XX
1171 bool "Enable iWMMXt support"
1172 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1173 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1175 Enable support for iWMMXt context switching at run time if
1176 running on a CPU that supports it.
1180 depends on CPU_XSCALE
1184 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1185 (!ARCH_OMAP3 || OMAP3_EMU)
1189 config MULTI_IRQ_HANDLER
1192 Allow each machine to specify it's own IRQ handler at run time.
1195 source "arch/arm/Kconfig-nommu"
1198 config ARM_ERRATA_326103
1199 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1202 Executing a SWP instruction to read-only memory does not set bit 11
1203 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1204 treat the access as a read, preventing a COW from occurring and
1205 causing the faulting task to livelock.
1207 config ARM_ERRATA_411920
1208 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1209 depends on CPU_V6 || CPU_V6K
1211 Invalidation of the Instruction Cache operation can
1212 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1213 It does not affect the MPCore. This option enables the ARM Ltd.
1214 recommended workaround.
1216 config ARM_ERRATA_430973
1217 bool "ARM errata: Stale prediction on replaced interworking branch"
1220 This option enables the workaround for the 430973 Cortex-A8
1221 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1222 interworking branch is replaced with another code sequence at the
1223 same virtual address, whether due to self-modifying code or virtual
1224 to physical address re-mapping, Cortex-A8 does not recover from the
1225 stale interworking branch prediction. This results in Cortex-A8
1226 executing the new code sequence in the incorrect ARM or Thumb state.
1227 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1228 and also flushes the branch target cache at every context switch.
1229 Note that setting specific bits in the ACTLR register may not be
1230 available in non-secure mode.
1232 config ARM_ERRATA_458693
1233 bool "ARM errata: Processor deadlock when a false hazard is created"
1236 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1237 erratum. For very specific sequences of memory operations, it is
1238 possible for a hazard condition intended for a cache line to instead
1239 be incorrectly associated with a different cache line. This false
1240 hazard might then cause a processor deadlock. The workaround enables
1241 the L1 caching of the NEON accesses and disables the PLD instruction
1242 in the ACTLR register. Note that setting specific bits in the ACTLR
1243 register may not be available in non-secure mode.
1245 config ARM_ERRATA_460075
1246 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1249 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1250 erratum. Any asynchronous access to the L2 cache may encounter a
1251 situation in which recent store transactions to the L2 cache are lost
1252 and overwritten with stale memory contents from external memory. The
1253 workaround disables the write-allocate mode for the L2 cache via the
1254 ACTLR register. Note that setting specific bits in the ACTLR register
1255 may not be available in non-secure mode.
1257 config ARM_ERRATA_742230
1258 bool "ARM errata: DMB operation may be faulty"
1259 depends on CPU_V7 && SMP
1261 This option enables the workaround for the 742230 Cortex-A9
1262 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1263 between two write operations may not ensure the correct visibility
1264 ordering of the two writes. This workaround sets a specific bit in
1265 the diagnostic register of the Cortex-A9 which causes the DMB
1266 instruction to behave as a DSB, ensuring the correct behaviour of
1269 config ARM_ERRATA_742231
1270 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1271 depends on CPU_V7 && SMP
1273 This option enables the workaround for the 742231 Cortex-A9
1274 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1275 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1276 accessing some data located in the same cache line, may get corrupted
1277 data due to bad handling of the address hazard when the line gets
1278 replaced from one of the CPUs at the same time as another CPU is
1279 accessing it. This workaround sets specific bits in the diagnostic
1280 register of the Cortex-A9 which reduces the linefill issuing
1281 capabilities of the processor.
1283 config PL310_ERRATA_588369
1284 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1285 depends on CACHE_L2X0
1287 The PL310 L2 cache controller implements three types of Clean &
1288 Invalidate maintenance operations: by Physical Address
1289 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1290 They are architecturally defined to behave as the execution of a
1291 clean operation followed immediately by an invalidate operation,
1292 both performing to the same memory location. This functionality
1293 is not correctly implemented in PL310 as clean lines are not
1294 invalidated as a result of these operations.
1296 config ARM_ERRATA_720789
1297 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1300 This option enables the workaround for the 720789 Cortex-A9 (prior to
1301 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1302 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1303 As a consequence of this erratum, some TLB entries which should be
1304 invalidated are not, resulting in an incoherency in the system page
1305 tables. The workaround changes the TLB flushing routines to invalidate
1306 entries regardless of the ASID.
1308 config PL310_ERRATA_727915
1309 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1310 depends on CACHE_L2X0
1312 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1313 operation (offset 0x7FC). This operation runs in background so that
1314 PL310 can handle normal accesses while it is in progress. Under very
1315 rare circumstances, due to this erratum, write data can be lost when
1316 PL310 treats a cacheable write transaction during a Clean &
1317 Invalidate by Way operation.
1319 config ARM_ERRATA_743622
1320 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1323 This option enables the workaround for the 743622 Cortex-A9
1324 (r2p*) erratum. Under very rare conditions, a faulty
1325 optimisation in the Cortex-A9 Store Buffer may lead to data
1326 corruption. This workaround sets a specific bit in the diagnostic
1327 register of the Cortex-A9 which disables the Store Buffer
1328 optimisation, preventing the defect from occurring. This has no
1329 visible impact on the overall performance or power consumption of the
1332 config ARM_ERRATA_751472
1333 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1336 This option enables the workaround for the 751472 Cortex-A9 (prior
1337 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1338 completion of a following broadcasted operation if the second
1339 operation is received by a CPU before the ICIALLUIS has completed,
1340 potentially leading to corrupted entries in the cache or TLB.
1342 config PL310_ERRATA_753970
1343 bool "PL310 errata: cache sync operation may be faulty"
1344 depends on CACHE_PL310
1346 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1348 Under some condition the effect of cache sync operation on
1349 the store buffer still remains when the operation completes.
1350 This means that the store buffer is always asked to drain and
1351 this prevents it from merging any further writes. The workaround
1352 is to replace the normal offset of cache sync operation (0x730)
1353 by another offset targeting an unmapped PL310 register 0x740.
1354 This has the same effect as the cache sync operation: store buffer
1355 drain and waiting for all buffers empty.
1357 config ARM_ERRATA_754322
1358 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1361 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1362 r3p*) erratum. A speculative memory access may cause a page table walk
1363 which starts prior to an ASID switch but completes afterwards. This
1364 can populate the micro-TLB with a stale entry which may be hit with
1365 the new ASID. This workaround places two dsb instructions in the mm
1366 switching code so that no page table walks can cross the ASID switch.
1368 config ARM_ERRATA_754327
1369 bool "ARM errata: no automatic Store Buffer drain"
1370 depends on CPU_V7 && SMP
1372 This option enables the workaround for the 754327 Cortex-A9 (prior to
1373 r2p0) erratum. The Store Buffer does not have any automatic draining
1374 mechanism and therefore a livelock may occur if an external agent
1375 continuously polls a memory location waiting to observe an update.
1376 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1377 written polling loops from denying visibility of updates to memory.
1379 config ARM_ERRATA_364296
1380 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1381 depends on CPU_V6 && !SMP
1383 This options enables the workaround for the 364296 ARM1136
1384 r0p2 erratum (possible cache data corruption with
1385 hit-under-miss enabled). It sets the undocumented bit 31 in
1386 the auxiliary control register and the FI bit in the control
1387 register, thus disabling hit-under-miss without putting the
1388 processor into full low interrupt latency mode. ARM11MPCore
1391 config ARM_ERRATA_764369
1392 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1393 depends on CPU_V7 && SMP
1395 This option enables the workaround for erratum 764369
1396 affecting Cortex-A9 MPCore with two or more processors (all
1397 current revisions). Under certain timing circumstances, a data
1398 cache line maintenance operation by MVA targeting an Inner
1399 Shareable memory region may fail to proceed up to either the
1400 Point of Coherency or to the Point of Unification of the
1401 system. This workaround adds a DSB instruction before the
1402 relevant cache maintenance functions and sets a specific bit
1403 in the diagnostic control register of the SCU.
1405 config PL310_ERRATA_769419
1406 bool "PL310 errata: no automatic Store Buffer drain"
1407 depends on CACHE_L2X0
1409 On revisions of the PL310 prior to r3p2, the Store Buffer does
1410 not automatically drain. This can cause normal, non-cacheable
1411 writes to be retained when the memory system is idle, leading
1412 to suboptimal I/O performance for drivers using coherent DMA.
1413 This option adds a write barrier to the cpu_idle loop so that,
1414 on systems with an outer cache, the store buffer is drained
1419 source "arch/arm/common/Kconfig"
1429 Find out whether you have ISA slots on your motherboard. ISA is the
1430 name of a bus system, i.e. the way the CPU talks to the other stuff
1431 inside your box. Other bus systems are PCI, EISA, MicroChannel
1432 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1433 newer boards don't support it. If you have ISA, say Y, otherwise N.
1435 # Select ISA DMA controller support
1440 # Select ISA DMA interface
1445 bool "PCI support" if MIGHT_HAVE_PCI
1447 Find out whether you have a PCI motherboard. PCI is the name of a
1448 bus system, i.e. the way the CPU talks to the other stuff inside
1449 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1450 VESA. If you have PCI, say Y, otherwise N.
1456 config PCI_NANOENGINE
1457 bool "BSE nanoEngine PCI support"
1458 depends on SA1100_NANOENGINE
1460 Enable PCI on the BSE nanoEngine board.
1465 # Select the host bridge type
1466 config PCI_HOST_VIA82C505
1468 depends on PCI && ARCH_SHARK
1471 config PCI_HOST_ITE8152
1473 depends on PCI && MACH_ARMCORE
1477 source "drivers/pci/Kconfig"
1479 source "drivers/pcmcia/Kconfig"
1483 menu "Kernel Features"
1488 This option should be selected by machines which have an SMP-
1491 The only effect of this option is to make the SMP-related
1492 options available to the user for configuration.
1495 bool "Symmetric Multi-Processing"
1496 depends on CPU_V6K || CPU_V7
1497 depends on GENERIC_CLOCKEVENTS
1500 select USE_GENERIC_SMP_HELPERS
1501 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1503 This enables support for systems with more than one CPU. If you have
1504 a system with only one CPU, like most personal computers, say N. If
1505 you have a system with more than one CPU, say Y.
1507 If you say N here, the kernel will run on single and multiprocessor
1508 machines, but will use only one CPU of a multiprocessor machine. If
1509 you say Y here, the kernel will run on many, but not all, single
1510 processor machines. On a single processor machine, the kernel will
1511 run faster if you say N here.
1513 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1514 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1515 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1517 If you don't know what to do here, say N.
1520 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1521 depends on EXPERIMENTAL
1522 depends on SMP && !XIP_KERNEL
1525 SMP kernels contain instructions which fail on non-SMP processors.
1526 Enabling this option allows the kernel to modify itself to make
1527 these instructions safe. Disabling it allows about 1K of space
1530 If you don't know what to do here, say Y.
1532 config ARM_CPU_TOPOLOGY
1533 bool "Support cpu topology definition"
1534 depends on SMP && CPU_V7
1537 Support ARM cpu topology definition. The MPIDR register defines
1538 affinity between processors which is then used to describe the cpu
1539 topology of an ARM System.
1542 bool "Multi-core scheduler support"
1543 depends on ARM_CPU_TOPOLOGY
1545 Multi-core scheduler support improves the CPU scheduler's decision
1546 making when dealing with multi-core CPU chips at a cost of slightly
1547 increased overhead in some places. If unsure say N here.
1550 bool "SMT scheduler support"
1551 depends on ARM_CPU_TOPOLOGY
1553 Improves the CPU scheduler's decision making when dealing with
1554 MultiThreading at a cost of slightly increased overhead in some
1555 places. If unsure say N here.
1560 This option enables support for the ARM system coherency unit
1562 config ARM_ARCH_TIMER
1563 bool "Architected timer support"
1566 This option enables support for the ARM architected timer
1572 This options enables support for the ARM timer and watchdog unit
1575 prompt "Memory split"
1578 Select the desired split between kernel and user memory.
1580 If you are not absolutely sure what you are doing, leave this
1584 bool "3G/1G user/kernel split"
1586 bool "2G/2G user/kernel split"
1588 bool "1G/3G user/kernel split"
1593 default 0x40000000 if VMSPLIT_1G
1594 default 0x80000000 if VMSPLIT_2G
1598 int "Maximum number of CPUs (2-32)"
1604 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1605 depends on SMP && HOTPLUG && EXPERIMENTAL
1607 Say Y here to experiment with turning CPUs off and on. CPUs
1608 can be controlled through /sys/devices/system/cpu.
1611 bool "Use local timer interrupts"
1614 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1616 Enable support for local timers on SMP platforms, rather then the
1617 legacy IPI broadcast method. Local timers allows the system
1618 accounting to be spread across the timer interval, preventing a
1619 "thundering herd" at every timer tick.
1623 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1624 default 355 if ARCH_U8500
1625 default 264 if MACH_H4700
1626 default 512 if SOC_OMAP5
1629 Maximum number of GPIOs in the system.
1631 If unsure, leave the default value.
1633 source kernel/Kconfig.preempt
1637 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1638 ARCH_S5PV210 || ARCH_EXYNOS4
1639 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1640 default AT91_TIMER_HZ if ARCH_AT91
1641 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1644 config THUMB2_KERNEL
1645 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1646 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1648 select ARM_ASM_UNIFIED
1651 By enabling this option, the kernel will be compiled in
1652 Thumb-2 mode. A compiler/assembler that understand the unified
1653 ARM-Thumb syntax is needed.
1657 config THUMB2_AVOID_R_ARM_THM_JUMP11
1658 bool "Work around buggy Thumb-2 short branch relocations in gas"
1659 depends on THUMB2_KERNEL && MODULES
1662 Various binutils versions can resolve Thumb-2 branches to
1663 locally-defined, preemptible global symbols as short-range "b.n"
1664 branch instructions.
1666 This is a problem, because there's no guarantee the final
1667 destination of the symbol, or any candidate locations for a
1668 trampoline, are within range of the branch. For this reason, the
1669 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1670 relocation in modules at all, and it makes little sense to add
1673 The symptom is that the kernel fails with an "unsupported
1674 relocation" error when loading some modules.
1676 Until fixed tools are available, passing
1677 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1678 code which hits this problem, at the cost of a bit of extra runtime
1679 stack usage in some cases.
1681 The problem is described in more detail at:
1682 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1684 Only Thumb-2 kernels are affected.
1686 Unless you are sure your tools don't have this problem, say Y.
1688 config ARM_ASM_UNIFIED
1692 bool "Use the ARM EABI to compile the kernel"
1694 This option allows for the kernel to be compiled using the latest
1695 ARM ABI (aka EABI). This is only useful if you are using a user
1696 space environment that is also compiled with EABI.
1698 Since there are major incompatibilities between the legacy ABI and
1699 EABI, especially with regard to structure member alignment, this
1700 option also changes the kernel syscall calling convention to
1701 disambiguate both ABIs and allow for backward compatibility support
1702 (selected with CONFIG_OABI_COMPAT).
1704 To use this you need GCC version 4.0.0 or later.
1707 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1708 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1711 This option preserves the old syscall interface along with the
1712 new (ARM EABI) one. It also provides a compatibility layer to
1713 intercept syscalls that have structure arguments which layout
1714 in memory differs between the legacy ABI and the new ARM EABI
1715 (only for non "thumb" binaries). This option adds a tiny
1716 overhead to all syscalls and produces a slightly larger kernel.
1717 If you know you'll be using only pure EABI user space then you
1718 can say N here. If this option is not selected and you attempt
1719 to execute a legacy ABI binary then the result will be
1720 UNPREDICTABLE (in fact it can be predicted that it won't work
1721 at all). If in doubt say Y.
1723 config ARCH_HAS_HOLES_MEMORYMODEL
1726 config ARCH_SPARSEMEM_ENABLE
1729 config ARCH_SPARSEMEM_DEFAULT
1730 def_bool ARCH_SPARSEMEM_ENABLE
1732 config ARCH_SELECT_MEMORY_MODEL
1733 def_bool ARCH_SPARSEMEM_ENABLE
1735 config HAVE_ARCH_PFN_VALID
1736 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1739 bool "High Memory Support"
1742 The address space of ARM processors is only 4 Gigabytes large
1743 and it has to accommodate user address space, kernel address
1744 space as well as some memory mapped IO. That means that, if you
1745 have a large amount of physical memory and/or IO, not all of the
1746 memory can be "permanently mapped" by the kernel. The physical
1747 memory that is not permanently mapped is called "high memory".
1749 Depending on the selected kernel/user memory split, minimum
1750 vmalloc space and actual amount of RAM, you may not need this
1751 option which should result in a slightly faster kernel.
1756 bool "Allocate 2nd-level pagetables from highmem"
1759 config HW_PERF_EVENTS
1760 bool "Enable hardware performance counter support for perf events"
1761 depends on PERF_EVENTS && CPU_HAS_PMU
1764 Enable hardware performance counter support for perf events. If
1765 disabled, perf events will use software events only.
1769 config FORCE_MAX_ZONEORDER
1770 int "Maximum zone order" if ARCH_SHMOBILE
1771 range 11 64 if ARCH_SHMOBILE
1772 default "9" if SA1111
1775 The kernel memory allocator divides physically contiguous memory
1776 blocks into "zones", where each zone is a power of two number of
1777 pages. This option selects the largest power of two that the kernel
1778 keeps in the memory allocator. If you need to allocate very large
1779 blocks of physically contiguous memory, then you may need to
1780 increase this value.
1782 This config option is actually maximum order plus one. For example,
1783 a value of 11 means that the largest free memory block is 2^10 pages.
1786 bool "Timer and CPU usage LEDs"
1787 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1788 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1789 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1790 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1791 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1792 ARCH_AT91 || ARCH_DAVINCI || \
1793 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1795 If you say Y here, the LEDs on your machine will be used
1796 to provide useful information about your current system status.
1798 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1799 be able to select which LEDs are active using the options below. If
1800 you are compiling a kernel for the EBSA-110 or the LART however, the
1801 red LED will simply flash regularly to indicate that the system is
1802 still functional. It is safe to say Y here if you have a CATS
1803 system, but the driver will do nothing.
1806 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1807 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1808 || MACH_OMAP_PERSEUS2
1810 depends on !GENERIC_CLOCKEVENTS
1811 default y if ARCH_EBSA110
1813 If you say Y here, one of the system LEDs (the green one on the
1814 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1815 will flash regularly to indicate that the system is still
1816 operational. This is mainly useful to kernel hackers who are
1817 debugging unstable kernels.
1819 The LART uses the same LED for both Timer LED and CPU usage LED
1820 functions. You may choose to use both, but the Timer LED function
1821 will overrule the CPU usage LED.
1824 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1826 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1827 || MACH_OMAP_PERSEUS2
1830 If you say Y here, the red LED will be used to give a good real
1831 time indication of CPU usage, by lighting whenever the idle task
1832 is not currently executing.
1834 The LART uses the same LED for both Timer LED and CPU usage LED
1835 functions. You may choose to use both, but the Timer LED function
1836 will overrule the CPU usage LED.
1838 config ALIGNMENT_TRAP
1840 depends on CPU_CP15_MMU
1841 default y if !ARCH_EBSA110
1842 select HAVE_PROC_CPU if PROC_FS
1844 ARM processors cannot fetch/store information which is not
1845 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1846 address divisible by 4. On 32-bit ARM processors, these non-aligned
1847 fetch/store instructions will be emulated in software if you say
1848 here, which has a severe performance impact. This is necessary for
1849 correct operation of some network protocols. With an IP-only
1850 configuration it is safe to say N, otherwise say Y.
1852 config UACCESS_WITH_MEMCPY
1853 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1854 depends on MMU && EXPERIMENTAL
1855 default y if CPU_FEROCEON
1857 Implement faster copy_to_user and clear_user methods for CPU
1858 cores where a 8-word STM instruction give significantly higher
1859 memory write throughput than a sequence of individual 32bit stores.
1861 A possible side effect is a slight increase in scheduling latency
1862 between threads sharing the same address space if they invoke
1863 such copy operations with large buffers.
1865 However, if the CPU data cache is using a write-allocate mode,
1866 this option is unlikely to provide any performance gain.
1870 prompt "Enable seccomp to safely compute untrusted bytecode"
1872 This kernel feature is useful for number crunching applications
1873 that may need to compute untrusted bytecode during their
1874 execution. By using pipes or other transports made available to
1875 the process as file descriptors supporting the read/write
1876 syscalls, it's possible to isolate those applications in
1877 their own address space using seccomp. Once seccomp is
1878 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1879 and the task is only allowed to execute a few safe syscalls
1880 defined by each seccomp mode.
1882 config CC_STACKPROTECTOR
1883 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1884 depends on EXPERIMENTAL
1886 This option turns on the -fstack-protector GCC feature. This
1887 feature puts, at the beginning of functions, a canary value on
1888 the stack just before the return address, and validates
1889 the value just before actually returning. Stack based buffer
1890 overflows (that need to overwrite this return address) now also
1891 overwrite the canary, which gets detected and the attack is then
1892 neutralized via a kernel panic.
1893 This feature requires gcc version 4.2 or above.
1895 config DEPRECATED_PARAM_STRUCT
1896 bool "Provide old way to pass kernel parameters"
1898 This was deprecated in 2001 and announced to live on for 5 years.
1899 Some old boot loaders still use this way.
1906 bool "Flattened Device Tree support"
1908 select OF_EARLY_FLATTREE
1911 Include support for flattened device tree machine descriptions.
1913 # Compressed boot loader in ROM. Yes, we really want to ask about
1914 # TEXT and BSS so we preserve their values in the config files.
1915 config ZBOOT_ROM_TEXT
1916 hex "Compressed ROM boot loader base address"
1919 The physical address at which the ROM-able zImage is to be
1920 placed in the target. Platforms which normally make use of
1921 ROM-able zImage formats normally set this to a suitable
1922 value in their defconfig file.
1924 If ZBOOT_ROM is not enabled, this has no effect.
1926 config ZBOOT_ROM_BSS
1927 hex "Compressed ROM boot loader BSS address"
1930 The base address of an area of read/write memory in the target
1931 for the ROM-able zImage which must be available while the
1932 decompressor is running. It must be large enough to hold the
1933 entire decompressed kernel plus an additional 128 KiB.
1934 Platforms which normally make use of ROM-able zImage formats
1935 normally set this to a suitable value in their defconfig file.
1937 If ZBOOT_ROM is not enabled, this has no effect.
1940 bool "Compressed boot loader in ROM/flash"
1941 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1943 Say Y here if you intend to execute your compressed kernel image
1944 (zImage) directly from ROM or flash. If unsure, say N.
1947 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1948 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1949 default ZBOOT_ROM_NONE
1951 Include experimental SD/MMC loading code in the ROM-able zImage.
1952 With this enabled it is possible to write the ROM-able zImage
1953 kernel image to an MMC or SD card and boot the kernel straight
1954 from the reset vector. At reset the processor Mask ROM will load
1955 the first part of the ROM-able zImage which in turn loads the
1956 rest the kernel image to RAM.
1958 config ZBOOT_ROM_NONE
1959 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1961 Do not load image from SD or MMC
1963 config ZBOOT_ROM_MMCIF
1964 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1966 Load image from MMCIF hardware block.
1968 config ZBOOT_ROM_SH_MOBILE_SDHI
1969 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1971 Load image from SDHI hardware block
1975 config ARM_APPENDED_DTB
1976 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1977 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1979 With this option, the boot code will look for a device tree binary
1980 (DTB) appended to zImage
1981 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1983 This is meant as a backward compatibility convenience for those
1984 systems with a bootloader that can't be upgraded to accommodate
1985 the documented boot protocol using a device tree.
1987 Beware that there is very little in terms of protection against
1988 this option being confused by leftover garbage in memory that might
1989 look like a DTB header after a reboot if no actual DTB is appended
1990 to zImage. Do not leave this option active in a production kernel
1991 if you don't intend to always append a DTB. Proper passing of the
1992 location into r2 of a bootloader provided DTB is always preferable
1995 config ARM_ATAG_DTB_COMPAT
1996 bool "Supplement the appended DTB with traditional ATAG information"
1997 depends on ARM_APPENDED_DTB
1999 Some old bootloaders can't be updated to a DTB capable one, yet
2000 they provide ATAGs with memory configuration, the ramdisk address,
2001 the kernel cmdline string, etc. Such information is dynamically
2002 provided by the bootloader and can't always be stored in a static
2003 DTB. To allow a device tree enabled kernel to be used with such
2004 bootloaders, this option allows zImage to extract the information
2005 from the ATAG list and store it at run time into the appended DTB.
2008 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2009 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2011 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2012 bool "Use bootloader kernel arguments if available"
2014 Uses the command-line options passed by the boot loader instead of
2015 the device tree bootargs property. If the boot loader doesn't provide
2016 any, the device tree bootargs property will be used.
2018 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2019 bool "Extend with bootloader kernel arguments"
2021 The command-line arguments provided by the boot loader will be
2022 appended to the the device tree bootargs property.
2027 string "Default kernel command string"
2030 On some architectures (EBSA110 and CATS), there is currently no way
2031 for the boot loader to pass arguments to the kernel. For these
2032 architectures, you should supply some command-line options at build
2033 time by entering them here. As a minimum, you should specify the
2034 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2037 prompt "Kernel command line type" if CMDLINE != ""
2038 default CMDLINE_FROM_BOOTLOADER
2040 config CMDLINE_FROM_BOOTLOADER
2041 bool "Use bootloader kernel arguments if available"
2043 Uses the command-line options passed by the boot loader. If
2044 the boot loader doesn't provide any, the default kernel command
2045 string provided in CMDLINE will be used.
2047 config CMDLINE_EXTEND
2048 bool "Extend bootloader kernel arguments"
2050 The command-line arguments provided by the boot loader will be
2051 appended to the default kernel command string.
2053 config CMDLINE_FORCE
2054 bool "Always use the default kernel command string"
2056 Always use the default kernel command string, even if the boot
2057 loader passes other arguments to the kernel.
2058 This is useful if you cannot or don't want to change the
2059 command-line options your boot loader passes to the kernel.
2063 bool "Kernel Execute-In-Place from ROM"
2064 depends on !ZBOOT_ROM && !ARM_LPAE
2066 Execute-In-Place allows the kernel to run from non-volatile storage
2067 directly addressable by the CPU, such as NOR flash. This saves RAM
2068 space since the text section of the kernel is not loaded from flash
2069 to RAM. Read-write sections, such as the data section and stack,
2070 are still copied to RAM. The XIP kernel is not compressed since
2071 it has to run directly from flash, so it will take more space to
2072 store it. The flash address used to link the kernel object files,
2073 and for storing it, is configuration dependent. Therefore, if you
2074 say Y here, you must know the proper physical address where to
2075 store the kernel image depending on your own flash memory usage.
2077 Also note that the make target becomes "make xipImage" rather than
2078 "make zImage" or "make Image". The final kernel binary to put in
2079 ROM memory will be arch/arm/boot/xipImage.
2083 config XIP_PHYS_ADDR
2084 hex "XIP Kernel Physical Location"
2085 depends on XIP_KERNEL
2086 default "0x00080000"
2088 This is the physical address in your flash memory the kernel will
2089 be linked for and stored to. This address is dependent on your
2093 bool "Kexec system call (EXPERIMENTAL)"
2094 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2096 kexec is a system call that implements the ability to shutdown your
2097 current kernel, and to start another kernel. It is like a reboot
2098 but it is independent of the system firmware. And like a reboot
2099 you can start any kernel with it, not just Linux.
2101 It is an ongoing process to be certain the hardware in a machine
2102 is properly shutdown, so do not be surprised if this code does not
2103 initially work for you. It may help to enable device hotplugging
2107 bool "Export atags in procfs"
2111 Should the atags used to boot the kernel be exported in an "atags"
2112 file in procfs. Useful with kexec.
2115 bool "Build kdump crash kernel (EXPERIMENTAL)"
2116 depends on EXPERIMENTAL
2118 Generate crash dump after being started by kexec. This should
2119 be normally only set in special crash dump kernels which are
2120 loaded in the main kernel with kexec-tools into a specially
2121 reserved region and then later executed after a crash by
2122 kdump/kexec. The crash dump kernel must be compiled to a
2123 memory address not used by the main kernel
2125 For more details see Documentation/kdump/kdump.txt
2127 config AUTO_ZRELADDR
2128 bool "Auto calculation of the decompressed kernel image address"
2129 depends on !ZBOOT_ROM && !ARCH_U300
2131 ZRELADDR is the physical address where the decompressed kernel
2132 image will be placed. If AUTO_ZRELADDR is selected, the address
2133 will be determined at run-time by masking the current IP with
2134 0xf8000000. This assumes the zImage being placed in the first 128MB
2135 from start of memory.
2139 menu "CPU Power Management"
2143 source "drivers/cpufreq/Kconfig"
2146 tristate "CPUfreq driver for i.MX CPUs"
2147 depends on ARCH_MXC && CPU_FREQ
2148 select CPU_FREQ_TABLE
2150 This enables the CPUfreq driver for i.MX CPUs.
2152 config CPU_FREQ_SA1100
2155 config CPU_FREQ_SA1110
2158 config CPU_FREQ_INTEGRATOR
2159 tristate "CPUfreq driver for ARM Integrator CPUs"
2160 depends on ARCH_INTEGRATOR && CPU_FREQ
2163 This enables the CPUfreq driver for ARM Integrator CPUs.
2165 For details, take a look at <file:Documentation/cpu-freq>.
2171 depends on CPU_FREQ && ARCH_PXA && PXA25x
2173 select CPU_FREQ_TABLE
2174 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2179 Internal configuration node for common cpufreq on Samsung SoC
2181 config CPU_FREQ_S3C24XX
2182 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2183 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2186 This enables the CPUfreq driver for the Samsung S3C24XX family
2189 For details, take a look at <file:Documentation/cpu-freq>.
2193 config CPU_FREQ_S3C24XX_PLL
2194 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2195 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2197 Compile in support for changing the PLL frequency from the
2198 S3C24XX series CPUfreq driver. The PLL takes time to settle
2199 after a frequency change, so by default it is not enabled.
2201 This also means that the PLL tables for the selected CPU(s) will
2202 be built which may increase the size of the kernel image.
2204 config CPU_FREQ_S3C24XX_DEBUG
2205 bool "Debug CPUfreq Samsung driver core"
2206 depends on CPU_FREQ_S3C24XX
2208 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2210 config CPU_FREQ_S3C24XX_IODEBUG
2211 bool "Debug CPUfreq Samsung driver IO timing"
2212 depends on CPU_FREQ_S3C24XX
2214 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2216 config CPU_FREQ_S3C24XX_DEBUGFS
2217 bool "Export debugfs for CPUFreq"
2218 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2220 Export status information via debugfs.
2224 source "drivers/cpuidle/Kconfig"
2228 menu "Floating point emulation"
2230 comment "At least one emulation must be selected"
2233 bool "NWFPE math emulation"
2234 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2236 Say Y to include the NWFPE floating point emulator in the kernel.
2237 This is necessary to run most binaries. Linux does not currently
2238 support floating point hardware so you need to say Y here even if
2239 your machine has an FPA or floating point co-processor podule.
2241 You may say N here if you are going to load the Acorn FPEmulator
2242 early in the bootup.
2245 bool "Support extended precision"
2246 depends on FPE_NWFPE
2248 Say Y to include 80-bit support in the kernel floating-point
2249 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2250 Note that gcc does not generate 80-bit operations by default,
2251 so in most cases this option only enlarges the size of the
2252 floating point emulator without any good reason.
2254 You almost surely want to say N here.
2257 bool "FastFPE math emulation (EXPERIMENTAL)"
2258 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2260 Say Y here to include the FAST floating point emulator in the kernel.
2261 This is an experimental much faster emulator which now also has full
2262 precision for the mantissa. It does not support any exceptions.
2263 It is very simple, and approximately 3-6 times faster than NWFPE.
2265 It should be sufficient for most programs. It may be not suitable
2266 for scientific calculations, but you have to check this for yourself.
2267 If you do not feel you need a faster FP emulation you should better
2271 bool "VFP-format floating point maths"
2272 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2274 Say Y to include VFP support code in the kernel. This is needed
2275 if your hardware includes a VFP unit.
2277 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2278 release notes and additional status information.
2280 Say N if your target does not have VFP hardware.
2288 bool "Advanced SIMD (NEON) Extension support"
2289 depends on VFPv3 && CPU_V7
2291 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2296 menu "Userspace binary formats"
2298 source "fs/Kconfig.binfmt"
2301 tristate "RISC OS personality"
2304 Say Y here to include the kernel code necessary if you want to run
2305 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2306 experimental; if this sounds frightening, say N and sleep in peace.
2307 You can also say M here to compile this support as a module (which
2308 will be called arthur).
2312 menu "Power management options"
2314 source "kernel/power/Kconfig"
2316 config ARCH_SUSPEND_POSSIBLE
2317 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2318 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2319 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2322 config ARM_CPU_SUSPEND
2327 source "net/Kconfig"
2329 source "drivers/Kconfig"
2333 source "arch/arm/Kconfig.debug"
2335 source "security/Kconfig"
2337 source "crypto/Kconfig"
2339 source "lib/Kconfig"