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spi: pic32-sqi: Fix linker error, undefined reference to `bad_dma_ops'.
[linux-2.6/btrfs-unstable.git] / drivers / tty / synclinkmp.c
blob90da0c712262d81b92891aec8103c95a9df44634
1 /*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/seq_file.h>
54 #include <linux/slab.h>
55 #include <linux/netdevice.h>
56 #include <linux/vmalloc.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/ioctl.h>
60
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
70
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
73 #else
74 #define SYNCLINK_GENERIC_HDLC 0
75 #endif
76
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82 #include <asm/uaccess.h>
83
84 static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
98 };
99
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
107
108 #define BUFFERLISTSIZE 4096
109
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
112 {
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
116 u8 pad1;
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
119 u8 pad2;
120 } SCADESC, *PSCADESC;
121
122 typedef struct _SCADESC_EX
123 {
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
128
129 /* The queue of BH actions to be performed */
130
131 #define BH_RECEIVE 1
132 #define BH_TRANSMIT 2
133 #define BH_STATUS 4
134
135 #define IO_PIN_SHUTDOWN_LIMIT 100
136
137 struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146 };
147
148 /*
149 * Device instance data structure
150 */
151 typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
153 int magic;
154 struct tty_port port;
155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
158
159 struct mgsl_icount icount;
160
161 int timeout;
162 int x_char; /* xon/xoff character */
163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
177
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
180
181 u32 max_frame_size; /* as set by device config */
182
183 u32 pending_bh;
184
185 bool bh_running; /* Protection from multiple */
186 int isr_overflow;
187 bool bh_requested;
188
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
192 int ri_chkcount;
193
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
210 bool rx_enabled;
211 bool rx_overflow;
212
213 bool tx_enabled;
214 bool tx_active;
215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25]; /* device instance name */
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
232
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
235 bool irq_requested; /* true if IRQ requested */
236
237 MGSL_PARAMS params; /* communications parameters */
238
239 unsigned char serial_signals; /* current serial signal states */
240
241 bool irq_occurred; /* for diagnostics use */
242 unsigned int init_error; /* Initialization startup error */
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
250 u32 phys_sca_base;
251 u32 sca_offset;
252 bool sca_base_requested;
253
254 unsigned char* lcr_base; /* local config registers (PCI only) */
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
262 bool sca_statctrl_requested;
263
264 u32 misc_ctrl_value;
265 char *flag_buf;
266 bool drop_rts_on_tx_done;
267
268 struct _input_signal_events input_signal_events;
269
270 /* SPPP/Cisco HDLC device parts */
271 int netcount;
272 spinlock_t netlock;
273
274 #if SYNCLINK_GENERIC_HDLC
275 struct net_device *netdev;
276 #endif
277
278 } SLMP_INFO;
279
280 #define MGSL_MAGIC 0x5401
281
282 /*
283 * define serial signal status change macros
284 */
285 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
286 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
287 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
288 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
289
290 /* Common Register macros */
291 #define LPR 0x00
292 #define PABR0 0x02
293 #define PABR1 0x03
294 #define WCRL 0x04
295 #define WCRM 0x05
296 #define WCRH 0x06
297 #define DPCR 0x08
298 #define DMER 0x09
299 #define ISR0 0x10
300 #define ISR1 0x11
301 #define ISR2 0x12
302 #define IER0 0x14
303 #define IER1 0x15
304 #define IER2 0x16
305 #define ITCR 0x18
306 #define INTVR 0x1a
307 #define IMVR 0x1c
308
309 /* MSCI Register macros */
310 #define TRB 0x20
311 #define TRBL 0x20
312 #define TRBH 0x21
313 #define SR0 0x22
314 #define SR1 0x23
315 #define SR2 0x24
316 #define SR3 0x25
317 #define FST 0x26
318 #define IE0 0x28
319 #define IE1 0x29
320 #define IE2 0x2a
321 #define FIE 0x2b
322 #define CMD 0x2c
323 #define MD0 0x2e
324 #define MD1 0x2f
325 #define MD2 0x30
326 #define CTL 0x31
327 #define SA0 0x32
328 #define SA1 0x33
329 #define IDL 0x34
330 #define TMC 0x35
331 #define RXS 0x36
332 #define TXS 0x37
333 #define TRC0 0x38
334 #define TRC1 0x39
335 #define RRC 0x3a
336 #define CST0 0x3c
337 #define CST1 0x3d
338
339 /* Timer Register Macros */
340 #define TCNT 0x60
341 #define TCNTL 0x60
342 #define TCNTH 0x61
343 #define TCONR 0x62
344 #define TCONRL 0x62
345 #define TCONRH 0x63
346 #define TMCS 0x64
347 #define TEPR 0x65
348
349 /* DMA Controller Register macros */
350 #define DARL 0x80
351 #define DARH 0x81
352 #define DARB 0x82
353 #define BAR 0x80
354 #define BARL 0x80
355 #define BARH 0x81
356 #define BARB 0x82
357 #define SAR 0x84
358 #define SARL 0x84
359 #define SARH 0x85
360 #define SARB 0x86
361 #define CPB 0x86
362 #define CDA 0x88
363 #define CDAL 0x88
364 #define CDAH 0x89
365 #define EDA 0x8a
366 #define EDAL 0x8a
367 #define EDAH 0x8b
368 #define BFL 0x8c
369 #define BFLL 0x8c
370 #define BFLH 0x8d
371 #define BCR 0x8e
372 #define BCRL 0x8e
373 #define BCRH 0x8f
374 #define DSR 0x90
375 #define DMR 0x91
376 #define FCT 0x93
377 #define DIR 0x94
378 #define DCMD 0x95
379
380 /* combine with timer or DMA register address */
381 #define TIMER0 0x00
382 #define TIMER1 0x08
383 #define TIMER2 0x10
384 #define TIMER3 0x18
385 #define RXDMA 0x00
386 #define TXDMA 0x20
387
388 /* SCA Command Codes */
389 #define NOOP 0x00
390 #define TXRESET 0x01
391 #define TXENABLE 0x02
392 #define TXDISABLE 0x03
393 #define TXCRCINIT 0x04
394 #define TXCRCEXCL 0x05
395 #define TXEOM 0x06
396 #define TXABORT 0x07
397 #define MPON 0x08
398 #define TXBUFCLR 0x09
399 #define RXRESET 0x11
400 #define RXENABLE 0x12
401 #define RXDISABLE 0x13
402 #define RXCRCINIT 0x14
403 #define RXREJECT 0x15
404 #define SEARCHMP 0x16
405 #define RXCRCEXCL 0x17
406 #define RXCRCCALC 0x18
407 #define CHRESET 0x21
408 #define HUNT 0x31
409
410 /* DMA command codes */
411 #define SWABORT 0x01
412 #define FEICLEAR 0x02
413
414 /* IE0 */
415 #define TXINTE BIT7
416 #define RXINTE BIT6
417 #define TXRDYE BIT1
418 #define RXRDYE BIT0
419
420 /* IE1 & SR1 */
421 #define UDRN BIT7
422 #define IDLE BIT6
423 #define SYNCD BIT4
424 #define FLGD BIT4
425 #define CCTS BIT3
426 #define CDCD BIT2
427 #define BRKD BIT1
428 #define ABTD BIT1
429 #define GAPD BIT1
430 #define BRKE BIT0
431 #define IDLD BIT0
432
433 /* IE2 & SR2 */
434 #define EOM BIT7
435 #define PMP BIT6
436 #define SHRT BIT6
437 #define PE BIT5
438 #define ABT BIT5
439 #define FRME BIT4
440 #define RBIT BIT4
441 #define OVRN BIT3
442 #define CRCE BIT2
443
444
445 /*
446 * Global linked list of SyncLink devices
447 */
448 static SLMP_INFO *synclinkmp_device_list = NULL;
449 static int synclinkmp_adapter_count = -1;
450 static int synclinkmp_device_count = 0;
451
452 /*
453 * Set this param to non-zero to load eax with the
454 * .text section address and breakpoint on module load.
455 * This is useful for use with gdb and add-symbol-file command.
456 */
457 static bool break_on_load = 0;
458
459 /*
460 * Driver major number, defaults to zero to get auto
461 * assigned major number. May be forced as module parameter.
462 */
463 static int ttymajor = 0;
464
465 /*
466 * Array of user specified options for ISA adapters.
467 */
468 static int debug_level = 0;
469 static int maxframe[MAX_DEVICES] = {0,};
470
471 module_param(break_on_load, bool, 0);
472 module_param(ttymajor, int, 0);
473 module_param(debug_level, int, 0);
474 module_param_array(maxframe, int, NULL, 0);
475
476 static char *driver_name = "SyncLink MultiPort driver";
477 static char *driver_version = "$Revision: 4.38 $";
478
479 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
480 static void synclinkmp_remove_one(struct pci_dev *dev);
481
482 static struct pci_device_id synclinkmp_pci_tbl[] = {
483 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
484 { 0, }, /* terminate list */
485 };
486 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
487
488 MODULE_LICENSE("GPL");
489
490 static struct pci_driver synclinkmp_pci_driver = {
491 .name = "synclinkmp",
492 .id_table = synclinkmp_pci_tbl,
493 .probe = synclinkmp_init_one,
494 .remove = synclinkmp_remove_one,
495 };
496
497
498 static struct tty_driver *serial_driver;
499
500 /* number of characters left in xmit buffer before we ask for more */
501 #define WAKEUP_CHARS 256
502
503
504 /* tty callbacks */
505
506 static int open(struct tty_struct *tty, struct file * filp);
507 static void close(struct tty_struct *tty, struct file * filp);
508 static void hangup(struct tty_struct *tty);
509 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
510
511 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
512 static int put_char(struct tty_struct *tty, unsigned char ch);
513 static void send_xchar(struct tty_struct *tty, char ch);
514 static void wait_until_sent(struct tty_struct *tty, int timeout);
515 static int write_room(struct tty_struct *tty);
516 static void flush_chars(struct tty_struct *tty);
517 static void flush_buffer(struct tty_struct *tty);
518 static void tx_hold(struct tty_struct *tty);
519 static void tx_release(struct tty_struct *tty);
520
521 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
522 static int chars_in_buffer(struct tty_struct *tty);
523 static void throttle(struct tty_struct * tty);
524 static void unthrottle(struct tty_struct * tty);
525 static int set_break(struct tty_struct *tty, int break_state);
526
527 #if SYNCLINK_GENERIC_HDLC
528 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
529 static void hdlcdev_tx_done(SLMP_INFO *info);
530 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
531 static int hdlcdev_init(SLMP_INFO *info);
532 static void hdlcdev_exit(SLMP_INFO *info);
533 #endif
534
535 /* ioctl handlers */
536
537 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
538 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
539 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
541 static int set_txidle(SLMP_INFO *info, int idle_mode);
542 static int tx_enable(SLMP_INFO *info, int enable);
543 static int tx_abort(SLMP_INFO *info);
544 static int rx_enable(SLMP_INFO *info, int enable);
545 static int modem_input_wait(SLMP_INFO *info,int arg);
546 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
547 static int tiocmget(struct tty_struct *tty);
548 static int tiocmset(struct tty_struct *tty,
549 unsigned int set, unsigned int clear);
550 static int set_break(struct tty_struct *tty, int break_state);
551
552 static int add_device(SLMP_INFO *info);
553 static int device_init(int adapter_num, struct pci_dev *pdev);
554 static int claim_resources(SLMP_INFO *info);
555 static void release_resources(SLMP_INFO *info);
556
557 static int startup(SLMP_INFO *info);
558 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
559 static int carrier_raised(struct tty_port *port);
560 static void shutdown(SLMP_INFO *info);
561 static void program_hw(SLMP_INFO *info);
562 static void change_params(SLMP_INFO *info);
563
564 static bool init_adapter(SLMP_INFO *info);
565 static bool register_test(SLMP_INFO *info);
566 static bool irq_test(SLMP_INFO *info);
567 static bool loopback_test(SLMP_INFO *info);
568 static int adapter_test(SLMP_INFO *info);
569 static bool memory_test(SLMP_INFO *info);
570
571 static void reset_adapter(SLMP_INFO *info);
572 static void reset_port(SLMP_INFO *info);
573 static void async_mode(SLMP_INFO *info);
574 static void hdlc_mode(SLMP_INFO *info);
575
576 static void rx_stop(SLMP_INFO *info);
577 static void rx_start(SLMP_INFO *info);
578 static void rx_reset_buffers(SLMP_INFO *info);
579 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
580 static bool rx_get_frame(SLMP_INFO *info);
581
582 static void tx_start(SLMP_INFO *info);
583 static void tx_stop(SLMP_INFO *info);
584 static void tx_load_fifo(SLMP_INFO *info);
585 static void tx_set_idle(SLMP_INFO *info);
586 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
587
588 static void get_signals(SLMP_INFO *info);
589 static void set_signals(SLMP_INFO *info);
590 static void enable_loopback(SLMP_INFO *info, int enable);
591 static void set_rate(SLMP_INFO *info, u32 data_rate);
592
593 static int bh_action(SLMP_INFO *info);
594 static void bh_handler(struct work_struct *work);
595 static void bh_receive(SLMP_INFO *info);
596 static void bh_transmit(SLMP_INFO *info);
597 static void bh_status(SLMP_INFO *info);
598 static void isr_timer(SLMP_INFO *info);
599 static void isr_rxint(SLMP_INFO *info);
600 static void isr_rxrdy(SLMP_INFO *info);
601 static void isr_txint(SLMP_INFO *info);
602 static void isr_txrdy(SLMP_INFO *info);
603 static void isr_rxdmaok(SLMP_INFO *info);
604 static void isr_rxdmaerror(SLMP_INFO *info);
605 static void isr_txdmaok(SLMP_INFO *info);
606 static void isr_txdmaerror(SLMP_INFO *info);
607 static void isr_io_pin(SLMP_INFO *info, u16 status);
608
609 static int alloc_dma_bufs(SLMP_INFO *info);
610 static void free_dma_bufs(SLMP_INFO *info);
611 static int alloc_buf_list(SLMP_INFO *info);
612 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
613 static int alloc_tmp_rx_buf(SLMP_INFO *info);
614 static void free_tmp_rx_buf(SLMP_INFO *info);
615
616 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
617 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
618 static void tx_timeout(unsigned long context);
619 static void status_timeout(unsigned long context);
620
621 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
623 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
624 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
625 static unsigned char read_status_reg(SLMP_INFO * info);
626 static void write_control_reg(SLMP_INFO * info);
627
628
629 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
630 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
631 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
632
633 static u32 misc_ctrl_value = 0x007e4040;
634 static u32 lcr1_brdr_value = 0x00800028;
635
636 static u32 read_ahead_count = 8;
637
638 /* DPCR, DMA Priority Control
639 *
640 * 07..05 Not used, must be 0
641 * 04 BRC, bus release condition: 0=all transfers complete
642 * 1=release after 1 xfer on all channels
643 * 03 CCC, channel change condition: 0=every cycle
644 * 1=after each channel completes all xfers
645 * 02..00 PR<2..0>, priority 100=round robin
646 *
647 * 00000100 = 0x00
648 */
649 static unsigned char dma_priority = 0x04;
650
651 // Number of bytes that can be written to shared RAM
652 // in a single write operation
653 static u32 sca_pci_load_interval = 64;
654
655 /*
656 * 1st function defined in .text section. Calling this function in
657 * init_module() followed by a breakpoint allows a remote debugger
658 * (gdb) to get the .text address for the add-symbol-file command.
659 * This allows remote debugging of dynamically loadable modules.
660 */
661 static void* synclinkmp_get_text_ptr(void);
662 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
663
664 static inline int sanity_check(SLMP_INFO *info,
665 char *name, const char *routine)
666 {
667 #ifdef SANITY_CHECK
668 static const char *badmagic =
669 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
670 static const char *badinfo =
671 "Warning: null synclinkmp_struct for (%s) in %s\n";
672
673 if (!info) {
674 printk(badinfo, name, routine);
675 return 1;
676 }
677 if (info->magic != MGSL_MAGIC) {
678 printk(badmagic, name, routine);
679 return 1;
680 }
681 #else
682 if (!info)
683 return 1;
684 #endif
685 return 0;
686 }
687
688 /**
689 * line discipline callback wrappers
690 *
691 * The wrappers maintain line discipline references
692 * while calling into the line discipline.
693 *
694 * ldisc_receive_buf - pass receive data to line discipline
695 */
696
697 static void ldisc_receive_buf(struct tty_struct *tty,
698 const __u8 *data, char *flags, int count)
699 {
700 struct tty_ldisc *ld;
701 if (!tty)
702 return;
703 ld = tty_ldisc_ref(tty);
704 if (ld) {
705 if (ld->ops->receive_buf)
706 ld->ops->receive_buf(tty, data, flags, count);
707 tty_ldisc_deref(ld);
708 }
709 }
710
711 /* tty callbacks */
712
713 static int install(struct tty_driver *driver, struct tty_struct *tty)
714 {
715 SLMP_INFO *info;
716 int line = tty->index;
717
718 if (line >= synclinkmp_device_count) {
719 printk("%s(%d): open with invalid line #%d.\n",
720 __FILE__,__LINE__,line);
721 return -ENODEV;
722 }
723
724 info = synclinkmp_device_list;
725 while (info && info->line != line)
726 info = info->next_device;
727 if (sanity_check(info, tty->name, "open"))
728 return -ENODEV;
729 if (info->init_error) {
730 printk("%s(%d):%s device is not allocated, init error=%d\n",
731 __FILE__, __LINE__, info->device_name,
732 info->init_error);
733 return -ENODEV;
734 }
735
736 tty->driver_data = info;
737
738 return tty_port_install(&info->port, driver, tty);
739 }
740
741 /* Called when a port is opened. Init and enable port.
742 */
743 static int open(struct tty_struct *tty, struct file *filp)
744 {
745 SLMP_INFO *info = tty->driver_data;
746 unsigned long flags;
747 int retval;
748
749 info->port.tty = tty;
750
751 if (debug_level >= DEBUG_LEVEL_INFO)
752 printk("%s(%d):%s open(), old ref count = %d\n",
753 __FILE__,__LINE__,tty->driver->name, info->port.count);
754
755 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
756
757 spin_lock_irqsave(&info->netlock, flags);
758 if (info->netcount) {
759 retval = -EBUSY;
760 spin_unlock_irqrestore(&info->netlock, flags);
761 goto cleanup;
762 }
763 info->port.count++;
764 spin_unlock_irqrestore(&info->netlock, flags);
765
766 if (info->port.count == 1) {
767 /* 1st open on this device, init hardware */
768 retval = startup(info);
769 if (retval < 0)
770 goto cleanup;
771 }
772
773 retval = block_til_ready(tty, filp, info);
774 if (retval) {
775 if (debug_level >= DEBUG_LEVEL_INFO)
776 printk("%s(%d):%s block_til_ready() returned %d\n",
777 __FILE__,__LINE__, info->device_name, retval);
778 goto cleanup;
779 }
780
781 if (debug_level >= DEBUG_LEVEL_INFO)
782 printk("%s(%d):%s open() success\n",
783 __FILE__,__LINE__, info->device_name);
784 retval = 0;
785
786 cleanup:
787 if (retval) {
788 if (tty->count == 1)
789 info->port.tty = NULL; /* tty layer will release tty struct */
790 if(info->port.count)
791 info->port.count--;
792 }
793
794 return retval;
795 }
796
797 /* Called when port is closed. Wait for remaining data to be
798 * sent. Disable port and free resources.
799 */
800 static void close(struct tty_struct *tty, struct file *filp)
801 {
802 SLMP_INFO * info = tty->driver_data;
803
804 if (sanity_check(info, tty->name, "close"))
805 return;
806
807 if (debug_level >= DEBUG_LEVEL_INFO)
808 printk("%s(%d):%s close() entry, count=%d\n",
809 __FILE__,__LINE__, info->device_name, info->port.count);
810
811 if (tty_port_close_start(&info->port, tty, filp) == 0)
812 goto cleanup;
813
814 mutex_lock(&info->port.mutex);
815 if (info->port.flags & ASYNC_INITIALIZED)
816 wait_until_sent(tty, info->timeout);
817
818 flush_buffer(tty);
819 tty_ldisc_flush(tty);
820 shutdown(info);
821 mutex_unlock(&info->port.mutex);
822
823 tty_port_close_end(&info->port, tty);
824 info->port.tty = NULL;
825 cleanup:
826 if (debug_level >= DEBUG_LEVEL_INFO)
827 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
828 tty->driver->name, info->port.count);
829 }
830
831 /* Called by tty_hangup() when a hangup is signaled.
832 * This is the same as closing all open descriptors for the port.
833 */
834 static void hangup(struct tty_struct *tty)
835 {
836 SLMP_INFO *info = tty->driver_data;
837 unsigned long flags;
838
839 if (debug_level >= DEBUG_LEVEL_INFO)
840 printk("%s(%d):%s hangup()\n",
841 __FILE__,__LINE__, info->device_name );
842
843 if (sanity_check(info, tty->name, "hangup"))
844 return;
845
846 mutex_lock(&info->port.mutex);
847 flush_buffer(tty);
848 shutdown(info);
849
850 spin_lock_irqsave(&info->port.lock, flags);
851 info->port.count = 0;
852 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
853 info->port.tty = NULL;
854 spin_unlock_irqrestore(&info->port.lock, flags);
855 mutex_unlock(&info->port.mutex);
856
857 wake_up_interruptible(&info->port.open_wait);
858 }
859
860 /* Set new termios settings
861 */
862 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
863 {
864 SLMP_INFO *info = tty->driver_data;
865 unsigned long flags;
866
867 if (debug_level >= DEBUG_LEVEL_INFO)
868 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
869 tty->driver->name );
870
871 change_params(info);
872
873 /* Handle transition to B0 status */
874 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
875 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
876 spin_lock_irqsave(&info->lock,flags);
877 set_signals(info);
878 spin_unlock_irqrestore(&info->lock,flags);
879 }
880
881 /* Handle transition away from B0 status */
882 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
883 info->serial_signals |= SerialSignal_DTR;
884 if (!C_CRTSCTS(tty) || !test_bit(TTY_THROTTLED, &tty->flags))
885 info->serial_signals |= SerialSignal_RTS;
886 spin_lock_irqsave(&info->lock,flags);
887 set_signals(info);
888 spin_unlock_irqrestore(&info->lock,flags);
889 }
890
891 /* Handle turning off CRTSCTS */
892 if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
893 tty->hw_stopped = 0;
894 tx_release(tty);
895 }
896 }
897
898 /* Send a block of data
899 *
900 * Arguments:
901 *
902 * tty pointer to tty information structure
903 * buf pointer to buffer containing send data
904 * count size of send data in bytes
905 *
906 * Return Value: number of characters written
907 */
908 static int write(struct tty_struct *tty,
909 const unsigned char *buf, int count)
910 {
911 int c, ret = 0;
912 SLMP_INFO *info = tty->driver_data;
913 unsigned long flags;
914
915 if (debug_level >= DEBUG_LEVEL_INFO)
916 printk("%s(%d):%s write() count=%d\n",
917 __FILE__,__LINE__,info->device_name,count);
918
919 if (sanity_check(info, tty->name, "write"))
920 goto cleanup;
921
922 if (!info->tx_buf)
923 goto cleanup;
924
925 if (info->params.mode == MGSL_MODE_HDLC) {
926 if (count > info->max_frame_size) {
927 ret = -EIO;
928 goto cleanup;
929 }
930 if (info->tx_active)
931 goto cleanup;
932 if (info->tx_count) {
933 /* send accumulated data from send_char() calls */
934 /* as frame and wait before accepting more data. */
935 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
936 goto start;
937 }
938 ret = info->tx_count = count;
939 tx_load_dma_buffer(info, buf, count);
940 goto start;
941 }
942
943 for (;;) {
944 c = min_t(int, count,
945 min(info->max_frame_size - info->tx_count - 1,
946 info->max_frame_size - info->tx_put));
947 if (c <= 0)
948 break;
949
950 memcpy(info->tx_buf + info->tx_put, buf, c);
951
952 spin_lock_irqsave(&info->lock,flags);
953 info->tx_put += c;
954 if (info->tx_put >= info->max_frame_size)
955 info->tx_put -= info->max_frame_size;
956 info->tx_count += c;
957 spin_unlock_irqrestore(&info->lock,flags);
958
959 buf += c;
960 count -= c;
961 ret += c;
962 }
963
964 if (info->params.mode == MGSL_MODE_HDLC) {
965 if (count) {
966 ret = info->tx_count = 0;
967 goto cleanup;
968 }
969 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
970 }
971 start:
972 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
973 spin_lock_irqsave(&info->lock,flags);
974 if (!info->tx_active)
975 tx_start(info);
976 spin_unlock_irqrestore(&info->lock,flags);
977 }
978
979 cleanup:
980 if (debug_level >= DEBUG_LEVEL_INFO)
981 printk( "%s(%d):%s write() returning=%d\n",
982 __FILE__,__LINE__,info->device_name,ret);
983 return ret;
984 }
985
986 /* Add a character to the transmit buffer.
987 */
988 static int put_char(struct tty_struct *tty, unsigned char ch)
989 {
990 SLMP_INFO *info = tty->driver_data;
991 unsigned long flags;
992 int ret = 0;
993
994 if ( debug_level >= DEBUG_LEVEL_INFO ) {
995 printk( "%s(%d):%s put_char(%d)\n",
996 __FILE__,__LINE__,info->device_name,ch);
997 }
998
999 if (sanity_check(info, tty->name, "put_char"))
1000 return 0;
1001
1002 if (!info->tx_buf)
1003 return 0;
1004
1005 spin_lock_irqsave(&info->lock,flags);
1006
1007 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1008 !info->tx_active ) {
1009
1010 if (info->tx_count < info->max_frame_size - 1) {
1011 info->tx_buf[info->tx_put++] = ch;
1012 if (info->tx_put >= info->max_frame_size)
1013 info->tx_put -= info->max_frame_size;
1014 info->tx_count++;
1015 ret = 1;
1016 }
1017 }
1018
1019 spin_unlock_irqrestore(&info->lock,flags);
1020 return ret;
1021 }
1022
1023 /* Send a high-priority XON/XOFF character
1024 */
1025 static void send_xchar(struct tty_struct *tty, char ch)
1026 {
1027 SLMP_INFO *info = tty->driver_data;
1028 unsigned long flags;
1029
1030 if (debug_level >= DEBUG_LEVEL_INFO)
1031 printk("%s(%d):%s send_xchar(%d)\n",
1032 __FILE__,__LINE__, info->device_name, ch );
1033
1034 if (sanity_check(info, tty->name, "send_xchar"))
1035 return;
1036
1037 info->x_char = ch;
1038 if (ch) {
1039 /* Make sure transmit interrupts are on */
1040 spin_lock_irqsave(&info->lock,flags);
1041 if (!info->tx_enabled)
1042 tx_start(info);
1043 spin_unlock_irqrestore(&info->lock,flags);
1044 }
1045 }
1046
1047 /* Wait until the transmitter is empty.
1048 */
1049 static void wait_until_sent(struct tty_struct *tty, int timeout)
1050 {
1051 SLMP_INFO * info = tty->driver_data;
1052 unsigned long orig_jiffies, char_time;
1053
1054 if (!info )
1055 return;
1056
1057 if (debug_level >= DEBUG_LEVEL_INFO)
1058 printk("%s(%d):%s wait_until_sent() entry\n",
1059 __FILE__,__LINE__, info->device_name );
1060
1061 if (sanity_check(info, tty->name, "wait_until_sent"))
1062 return;
1063
1064 if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags))
1065 goto exit;
1066
1067 orig_jiffies = jiffies;
1068
1069 /* Set check interval to 1/5 of estimated time to
1070 * send a character, and make it at least 1. The check
1071 * interval should also be less than the timeout.
1072 * Note: use tight timings here to satisfy the NIST-PCTS.
1073 */
1074
1075 if ( info->params.data_rate ) {
1076 char_time = info->timeout/(32 * 5);
1077 if (!char_time)
1078 char_time++;
1079 } else
1080 char_time = 1;
1081
1082 if (timeout)
1083 char_time = min_t(unsigned long, char_time, timeout);
1084
1085 if ( info->params.mode == MGSL_MODE_HDLC ) {
1086 while (info->tx_active) {
1087 msleep_interruptible(jiffies_to_msecs(char_time));
1088 if (signal_pending(current))
1089 break;
1090 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1091 break;
1092 }
1093 } else {
1094 /*
1095 * TODO: determine if there is something similar to USC16C32
1096 * TXSTATUS_ALL_SENT status
1097 */
1098 while ( info->tx_active && info->tx_enabled) {
1099 msleep_interruptible(jiffies_to_msecs(char_time));
1100 if (signal_pending(current))
1101 break;
1102 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1103 break;
1104 }
1105 }
1106
1107 exit:
1108 if (debug_level >= DEBUG_LEVEL_INFO)
1109 printk("%s(%d):%s wait_until_sent() exit\n",
1110 __FILE__,__LINE__, info->device_name );
1111 }
1112
1113 /* Return the count of free bytes in transmit buffer
1114 */
1115 static int write_room(struct tty_struct *tty)
1116 {
1117 SLMP_INFO *info = tty->driver_data;
1118 int ret;
1119
1120 if (sanity_check(info, tty->name, "write_room"))
1121 return 0;
1122
1123 if (info->params.mode == MGSL_MODE_HDLC) {
1124 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1125 } else {
1126 ret = info->max_frame_size - info->tx_count - 1;
1127 if (ret < 0)
1128 ret = 0;
1129 }
1130
1131 if (debug_level >= DEBUG_LEVEL_INFO)
1132 printk("%s(%d):%s write_room()=%d\n",
1133 __FILE__, __LINE__, info->device_name, ret);
1134
1135 return ret;
1136 }
1137
1138 /* enable transmitter and send remaining buffered characters
1139 */
1140 static void flush_chars(struct tty_struct *tty)
1141 {
1142 SLMP_INFO *info = tty->driver_data;
1143 unsigned long flags;
1144
1145 if ( debug_level >= DEBUG_LEVEL_INFO )
1146 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1147 __FILE__,__LINE__,info->device_name,info->tx_count);
1148
1149 if (sanity_check(info, tty->name, "flush_chars"))
1150 return;
1151
1152 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1153 !info->tx_buf)
1154 return;
1155
1156 if ( debug_level >= DEBUG_LEVEL_INFO )
1157 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1158 __FILE__,__LINE__,info->device_name );
1159
1160 spin_lock_irqsave(&info->lock,flags);
1161
1162 if (!info->tx_active) {
1163 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1164 info->tx_count ) {
1165 /* operating in synchronous (frame oriented) mode */
1166 /* copy data from circular tx_buf to */
1167 /* transmit DMA buffer. */
1168 tx_load_dma_buffer(info,
1169 info->tx_buf,info->tx_count);
1170 }
1171 tx_start(info);
1172 }
1173
1174 spin_unlock_irqrestore(&info->lock,flags);
1175 }
1176
1177 /* Discard all data in the send buffer
1178 */
1179 static void flush_buffer(struct tty_struct *tty)
1180 {
1181 SLMP_INFO *info = tty->driver_data;
1182 unsigned long flags;
1183
1184 if (debug_level >= DEBUG_LEVEL_INFO)
1185 printk("%s(%d):%s flush_buffer() entry\n",
1186 __FILE__,__LINE__, info->device_name );
1187
1188 if (sanity_check(info, tty->name, "flush_buffer"))
1189 return;
1190
1191 spin_lock_irqsave(&info->lock,flags);
1192 info->tx_count = info->tx_put = info->tx_get = 0;
1193 del_timer(&info->tx_timer);
1194 spin_unlock_irqrestore(&info->lock,flags);
1195
1196 tty_wakeup(tty);
1197 }
1198
1199 /* throttle (stop) transmitter
1200 */
1201 static void tx_hold(struct tty_struct *tty)
1202 {
1203 SLMP_INFO *info = tty->driver_data;
1204 unsigned long flags;
1205
1206 if (sanity_check(info, tty->name, "tx_hold"))
1207 return;
1208
1209 if ( debug_level >= DEBUG_LEVEL_INFO )
1210 printk("%s(%d):%s tx_hold()\n",
1211 __FILE__,__LINE__,info->device_name);
1212
1213 spin_lock_irqsave(&info->lock,flags);
1214 if (info->tx_enabled)
1215 tx_stop(info);
1216 spin_unlock_irqrestore(&info->lock,flags);
1217 }
1218
1219 /* release (start) transmitter
1220 */
1221 static void tx_release(struct tty_struct *tty)
1222 {
1223 SLMP_INFO *info = tty->driver_data;
1224 unsigned long flags;
1225
1226 if (sanity_check(info, tty->name, "tx_release"))
1227 return;
1228
1229 if ( debug_level >= DEBUG_LEVEL_INFO )
1230 printk("%s(%d):%s tx_release()\n",
1231 __FILE__,__LINE__,info->device_name);
1232
1233 spin_lock_irqsave(&info->lock,flags);
1234 if (!info->tx_enabled)
1235 tx_start(info);
1236 spin_unlock_irqrestore(&info->lock,flags);
1237 }
1238
1239 /* Service an IOCTL request
1240 *
1241 * Arguments:
1242 *
1243 * tty pointer to tty instance data
1244 * cmd IOCTL command code
1245 * arg command argument/context
1246 *
1247 * Return Value: 0 if success, otherwise error code
1248 */
1249 static int ioctl(struct tty_struct *tty,
1250 unsigned int cmd, unsigned long arg)
1251 {
1252 SLMP_INFO *info = tty->driver_data;
1253 void __user *argp = (void __user *)arg;
1254
1255 if (debug_level >= DEBUG_LEVEL_INFO)
1256 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1257 info->device_name, cmd );
1258
1259 if (sanity_check(info, tty->name, "ioctl"))
1260 return -ENODEV;
1261
1262 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1263 (cmd != TIOCMIWAIT)) {
1264 if (tty->flags & (1 << TTY_IO_ERROR))
1265 return -EIO;
1266 }
1267
1268 switch (cmd) {
1269 case MGSL_IOCGPARAMS:
1270 return get_params(info, argp);
1271 case MGSL_IOCSPARAMS:
1272 return set_params(info, argp);
1273 case MGSL_IOCGTXIDLE:
1274 return get_txidle(info, argp);
1275 case MGSL_IOCSTXIDLE:
1276 return set_txidle(info, (int)arg);
1277 case MGSL_IOCTXENABLE:
1278 return tx_enable(info, (int)arg);
1279 case MGSL_IOCRXENABLE:
1280 return rx_enable(info, (int)arg);
1281 case MGSL_IOCTXABORT:
1282 return tx_abort(info);
1283 case MGSL_IOCGSTATS:
1284 return get_stats(info, argp);
1285 case MGSL_IOCWAITEVENT:
1286 return wait_mgsl_event(info, argp);
1287 case MGSL_IOCLOOPTXDONE:
1288 return 0; // TODO: Not supported, need to document
1289 /* Wait for modem input (DCD,RI,DSR,CTS) change
1290 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1291 */
1292 case TIOCMIWAIT:
1293 return modem_input_wait(info,(int)arg);
1294
1295 /*
1296 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1297 * Return: write counters to the user passed counter struct
1298 * NB: both 1->0 and 0->1 transitions are counted except for
1299 * RI where only 0->1 is counted.
1300 */
1301 default:
1302 return -ENOIOCTLCMD;
1303 }
1304 return 0;
1305 }
1306
1307 static int get_icount(struct tty_struct *tty,
1308 struct serial_icounter_struct *icount)
1309 {
1310 SLMP_INFO *info = tty->driver_data;
1311 struct mgsl_icount cnow; /* kernel counter temps */
1312 unsigned long flags;
1313
1314 spin_lock_irqsave(&info->lock,flags);
1315 cnow = info->icount;
1316 spin_unlock_irqrestore(&info->lock,flags);
1317
1318 icount->cts = cnow.cts;
1319 icount->dsr = cnow.dsr;
1320 icount->rng = cnow.rng;
1321 icount->dcd = cnow.dcd;
1322 icount->rx = cnow.rx;
1323 icount->tx = cnow.tx;
1324 icount->frame = cnow.frame;
1325 icount->overrun = cnow.overrun;
1326 icount->parity = cnow.parity;
1327 icount->brk = cnow.brk;
1328 icount->buf_overrun = cnow.buf_overrun;
1329
1330 return 0;
1331 }
1332
1333 /*
1334 * /proc fs routines....
1335 */
1336
1337 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1338 {
1339 char stat_buf[30];
1340 unsigned long flags;
1341
1342 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1343 "\tIRQ=%d MaxFrameSize=%u\n",
1344 info->device_name,
1345 info->phys_sca_base,
1346 info->phys_memory_base,
1347 info->phys_statctrl_base,
1348 info->phys_lcr_base,
1349 info->irq_level,
1350 info->max_frame_size );
1351
1352 /* output current serial signal states */
1353 spin_lock_irqsave(&info->lock,flags);
1354 get_signals(info);
1355 spin_unlock_irqrestore(&info->lock,flags);
1356
1357 stat_buf[0] = 0;
1358 stat_buf[1] = 0;
1359 if (info->serial_signals & SerialSignal_RTS)
1360 strcat(stat_buf, "|RTS");
1361 if (info->serial_signals & SerialSignal_CTS)
1362 strcat(stat_buf, "|CTS");
1363 if (info->serial_signals & SerialSignal_DTR)
1364 strcat(stat_buf, "|DTR");
1365 if (info->serial_signals & SerialSignal_DSR)
1366 strcat(stat_buf, "|DSR");
1367 if (info->serial_signals & SerialSignal_DCD)
1368 strcat(stat_buf, "|CD");
1369 if (info->serial_signals & SerialSignal_RI)
1370 strcat(stat_buf, "|RI");
1371
1372 if (info->params.mode == MGSL_MODE_HDLC) {
1373 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1374 info->icount.txok, info->icount.rxok);
1375 if (info->icount.txunder)
1376 seq_printf(m, " txunder:%d", info->icount.txunder);
1377 if (info->icount.txabort)
1378 seq_printf(m, " txabort:%d", info->icount.txabort);
1379 if (info->icount.rxshort)
1380 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1381 if (info->icount.rxlong)
1382 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1383 if (info->icount.rxover)
1384 seq_printf(m, " rxover:%d", info->icount.rxover);
1385 if (info->icount.rxcrc)
1386 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1387 } else {
1388 seq_printf(m, "\tASYNC tx:%d rx:%d",
1389 info->icount.tx, info->icount.rx);
1390 if (info->icount.frame)
1391 seq_printf(m, " fe:%d", info->icount.frame);
1392 if (info->icount.parity)
1393 seq_printf(m, " pe:%d", info->icount.parity);
1394 if (info->icount.brk)
1395 seq_printf(m, " brk:%d", info->icount.brk);
1396 if (info->icount.overrun)
1397 seq_printf(m, " oe:%d", info->icount.overrun);
1398 }
1399
1400 /* Append serial signal status to end */
1401 seq_printf(m, " %s\n", stat_buf+1);
1402
1403 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1404 info->tx_active,info->bh_requested,info->bh_running,
1405 info->pending_bh);
1406 }
1407
1408 /* Called to print information about devices
1409 */
1410 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1411 {
1412 SLMP_INFO *info;
1413
1414 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1415
1416 info = synclinkmp_device_list;
1417 while( info ) {
1418 line_info(m, info);
1419 info = info->next_device;
1420 }
1421 return 0;
1422 }
1423
1424 static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1425 {
1426 return single_open(file, synclinkmp_proc_show, NULL);
1427 }
1428
1429 static const struct file_operations synclinkmp_proc_fops = {
1430 .owner = THIS_MODULE,
1431 .open = synclinkmp_proc_open,
1432 .read = seq_read,
1433 .llseek = seq_lseek,
1434 .release = single_release,
1435 };
1436
1437 /* Return the count of bytes in transmit buffer
1438 */
1439 static int chars_in_buffer(struct tty_struct *tty)
1440 {
1441 SLMP_INFO *info = tty->driver_data;
1442
1443 if (sanity_check(info, tty->name, "chars_in_buffer"))
1444 return 0;
1445
1446 if (debug_level >= DEBUG_LEVEL_INFO)
1447 printk("%s(%d):%s chars_in_buffer()=%d\n",
1448 __FILE__, __LINE__, info->device_name, info->tx_count);
1449
1450 return info->tx_count;
1451 }
1452
1453 /* Signal remote device to throttle send data (our receive data)
1454 */
1455 static void throttle(struct tty_struct * tty)
1456 {
1457 SLMP_INFO *info = tty->driver_data;
1458 unsigned long flags;
1459
1460 if (debug_level >= DEBUG_LEVEL_INFO)
1461 printk("%s(%d):%s throttle() entry\n",
1462 __FILE__,__LINE__, info->device_name );
1463
1464 if (sanity_check(info, tty->name, "throttle"))
1465 return;
1466
1467 if (I_IXOFF(tty))
1468 send_xchar(tty, STOP_CHAR(tty));
1469
1470 if (C_CRTSCTS(tty)) {
1471 spin_lock_irqsave(&info->lock,flags);
1472 info->serial_signals &= ~SerialSignal_RTS;
1473 set_signals(info);
1474 spin_unlock_irqrestore(&info->lock,flags);
1475 }
1476 }
1477
1478 /* Signal remote device to stop throttling send data (our receive data)
1479 */
1480 static void unthrottle(struct tty_struct * tty)
1481 {
1482 SLMP_INFO *info = tty->driver_data;
1483 unsigned long flags;
1484
1485 if (debug_level >= DEBUG_LEVEL_INFO)
1486 printk("%s(%d):%s unthrottle() entry\n",
1487 __FILE__,__LINE__, info->device_name );
1488
1489 if (sanity_check(info, tty->name, "unthrottle"))
1490 return;
1491
1492 if (I_IXOFF(tty)) {
1493 if (info->x_char)
1494 info->x_char = 0;
1495 else
1496 send_xchar(tty, START_CHAR(tty));
1497 }
1498
1499 if (C_CRTSCTS(tty)) {
1500 spin_lock_irqsave(&info->lock,flags);
1501 info->serial_signals |= SerialSignal_RTS;
1502 set_signals(info);
1503 spin_unlock_irqrestore(&info->lock,flags);
1504 }
1505 }
1506
1507 /* set or clear transmit break condition
1508 * break_state -1=set break condition, 0=clear
1509 */
1510 static int set_break(struct tty_struct *tty, int break_state)
1511 {
1512 unsigned char RegValue;
1513 SLMP_INFO * info = tty->driver_data;
1514 unsigned long flags;
1515
1516 if (debug_level >= DEBUG_LEVEL_INFO)
1517 printk("%s(%d):%s set_break(%d)\n",
1518 __FILE__,__LINE__, info->device_name, break_state);
1519
1520 if (sanity_check(info, tty->name, "set_break"))
1521 return -EINVAL;
1522
1523 spin_lock_irqsave(&info->lock,flags);
1524 RegValue = read_reg(info, CTL);
1525 if (break_state == -1)
1526 RegValue |= BIT3;
1527 else
1528 RegValue &= ~BIT3;
1529 write_reg(info, CTL, RegValue);
1530 spin_unlock_irqrestore(&info->lock,flags);
1531 return 0;
1532 }
1533
1534 #if SYNCLINK_GENERIC_HDLC
1535
1536 /**
1537 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1538 * set encoding and frame check sequence (FCS) options
1539 *
1540 * dev pointer to network device structure
1541 * encoding serial encoding setting
1542 * parity FCS setting
1543 *
1544 * returns 0 if success, otherwise error code
1545 */
1546 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1547 unsigned short parity)
1548 {
1549 SLMP_INFO *info = dev_to_port(dev);
1550 unsigned char new_encoding;
1551 unsigned short new_crctype;
1552
1553 /* return error if TTY interface open */
1554 if (info->port.count)
1555 return -EBUSY;
1556
1557 switch (encoding)
1558 {
1559 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1560 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1561 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1562 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1563 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1564 default: return -EINVAL;
1565 }
1566
1567 switch (parity)
1568 {
1569 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1570 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1571 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1572 default: return -EINVAL;
1573 }
1574
1575 info->params.encoding = new_encoding;
1576 info->params.crc_type = new_crctype;
1577
1578 /* if network interface up, reprogram hardware */
1579 if (info->netcount)
1580 program_hw(info);
1581
1582 return 0;
1583 }
1584
1585 /**
1586 * called by generic HDLC layer to send frame
1587 *
1588 * skb socket buffer containing HDLC frame
1589 * dev pointer to network device structure
1590 */
1591 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1592 struct net_device *dev)
1593 {
1594 SLMP_INFO *info = dev_to_port(dev);
1595 unsigned long flags;
1596
1597 if (debug_level >= DEBUG_LEVEL_INFO)
1598 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1599
1600 /* stop sending until this frame completes */
1601 netif_stop_queue(dev);
1602
1603 /* copy data to device buffers */
1604 info->tx_count = skb->len;
1605 tx_load_dma_buffer(info, skb->data, skb->len);
1606
1607 /* update network statistics */
1608 dev->stats.tx_packets++;
1609 dev->stats.tx_bytes += skb->len;
1610
1611 /* done with socket buffer, so free it */
1612 dev_kfree_skb(skb);
1613
1614 /* save start time for transmit timeout detection */
1615 dev->trans_start = jiffies;
1616
1617 /* start hardware transmitter if necessary */
1618 spin_lock_irqsave(&info->lock,flags);
1619 if (!info->tx_active)
1620 tx_start(info);
1621 spin_unlock_irqrestore(&info->lock,flags);
1622
1623 return NETDEV_TX_OK;
1624 }
1625
1626 /**
1627 * called by network layer when interface enabled
1628 * claim resources and initialize hardware
1629 *
1630 * dev pointer to network device structure
1631 *
1632 * returns 0 if success, otherwise error code
1633 */
1634 static int hdlcdev_open(struct net_device *dev)
1635 {
1636 SLMP_INFO *info = dev_to_port(dev);
1637 int rc;
1638 unsigned long flags;
1639
1640 if (debug_level >= DEBUG_LEVEL_INFO)
1641 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1642
1643 /* generic HDLC layer open processing */
1644 rc = hdlc_open(dev);
1645 if (rc)
1646 return rc;
1647
1648 /* arbitrate between network and tty opens */
1649 spin_lock_irqsave(&info->netlock, flags);
1650 if (info->port.count != 0 || info->netcount != 0) {
1651 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1652 spin_unlock_irqrestore(&info->netlock, flags);
1653 return -EBUSY;
1654 }
1655 info->netcount=1;
1656 spin_unlock_irqrestore(&info->netlock, flags);
1657
1658 /* claim resources and init adapter */
1659 if ((rc = startup(info)) != 0) {
1660 spin_lock_irqsave(&info->netlock, flags);
1661 info->netcount=0;
1662 spin_unlock_irqrestore(&info->netlock, flags);
1663 return rc;
1664 }
1665
1666 /* assert RTS and DTR, apply hardware settings */
1667 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1668 program_hw(info);
1669
1670 /* enable network layer transmit */
1671 dev->trans_start = jiffies;
1672 netif_start_queue(dev);
1673
1674 /* inform generic HDLC layer of current DCD status */
1675 spin_lock_irqsave(&info->lock, flags);
1676 get_signals(info);
1677 spin_unlock_irqrestore(&info->lock, flags);
1678 if (info->serial_signals & SerialSignal_DCD)
1679 netif_carrier_on(dev);
1680 else
1681 netif_carrier_off(dev);
1682 return 0;
1683 }
1684
1685 /**
1686 * called by network layer when interface is disabled
1687 * shutdown hardware and release resources
1688 *
1689 * dev pointer to network device structure
1690 *
1691 * returns 0 if success, otherwise error code
1692 */
1693 static int hdlcdev_close(struct net_device *dev)
1694 {
1695 SLMP_INFO *info = dev_to_port(dev);
1696 unsigned long flags;
1697
1698 if (debug_level >= DEBUG_LEVEL_INFO)
1699 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1700
1701 netif_stop_queue(dev);
1702
1703 /* shutdown adapter and release resources */
1704 shutdown(info);
1705
1706 hdlc_close(dev);
1707
1708 spin_lock_irqsave(&info->netlock, flags);
1709 info->netcount=0;
1710 spin_unlock_irqrestore(&info->netlock, flags);
1711
1712 return 0;
1713 }
1714
1715 /**
1716 * called by network layer to process IOCTL call to network device
1717 *
1718 * dev pointer to network device structure
1719 * ifr pointer to network interface request structure
1720 * cmd IOCTL command code
1721 *
1722 * returns 0 if success, otherwise error code
1723 */
1724 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1725 {
1726 const size_t size = sizeof(sync_serial_settings);
1727 sync_serial_settings new_line;
1728 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1729 SLMP_INFO *info = dev_to_port(dev);
1730 unsigned int flags;
1731
1732 if (debug_level >= DEBUG_LEVEL_INFO)
1733 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1734
1735 /* return error if TTY interface open */
1736 if (info->port.count)
1737 return -EBUSY;
1738
1739 if (cmd != SIOCWANDEV)
1740 return hdlc_ioctl(dev, ifr, cmd);
1741
1742 switch(ifr->ifr_settings.type) {
1743 case IF_GET_IFACE: /* return current sync_serial_settings */
1744
1745 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1746 if (ifr->ifr_settings.size < size) {
1747 ifr->ifr_settings.size = size; /* data size wanted */
1748 return -ENOBUFS;
1749 }
1750
1751 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1752 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1753 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1754 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1755
1756 memset(&new_line, 0, sizeof(new_line));
1757 switch (flags){
1758 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1759 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1760 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1761 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1762 default: new_line.clock_type = CLOCK_DEFAULT;
1763 }
1764
1765 new_line.clock_rate = info->params.clock_speed;
1766 new_line.loopback = info->params.loopback ? 1:0;
1767
1768 if (copy_to_user(line, &new_line, size))
1769 return -EFAULT;
1770 return 0;
1771
1772 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1773
1774 if(!capable(CAP_NET_ADMIN))
1775 return -EPERM;
1776 if (copy_from_user(&new_line, line, size))
1777 return -EFAULT;
1778
1779 switch (new_line.clock_type)
1780 {
1781 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1782 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1783 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1784 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1785 case CLOCK_DEFAULT: flags = info->params.flags &
1786 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1787 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1788 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1789 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1790 default: return -EINVAL;
1791 }
1792
1793 if (new_line.loopback != 0 && new_line.loopback != 1)
1794 return -EINVAL;
1795
1796 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1797 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1798 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1799 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1800 info->params.flags |= flags;
1801
1802 info->params.loopback = new_line.loopback;
1803
1804 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1805 info->params.clock_speed = new_line.clock_rate;
1806 else
1807 info->params.clock_speed = 0;
1808
1809 /* if network interface up, reprogram hardware */
1810 if (info->netcount)
1811 program_hw(info);
1812 return 0;
1813
1814 default:
1815 return hdlc_ioctl(dev, ifr, cmd);
1816 }
1817 }
1818
1819 /**
1820 * called by network layer when transmit timeout is detected
1821 *
1822 * dev pointer to network device structure
1823 */
1824 static void hdlcdev_tx_timeout(struct net_device *dev)
1825 {
1826 SLMP_INFO *info = dev_to_port(dev);
1827 unsigned long flags;
1828
1829 if (debug_level >= DEBUG_LEVEL_INFO)
1830 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1831
1832 dev->stats.tx_errors++;
1833 dev->stats.tx_aborted_errors++;
1834
1835 spin_lock_irqsave(&info->lock,flags);
1836 tx_stop(info);
1837 spin_unlock_irqrestore(&info->lock,flags);
1838
1839 netif_wake_queue(dev);
1840 }
1841
1842 /**
1843 * called by device driver when transmit completes
1844 * reenable network layer transmit if stopped
1845 *
1846 * info pointer to device instance information
1847 */
1848 static void hdlcdev_tx_done(SLMP_INFO *info)
1849 {
1850 if (netif_queue_stopped(info->netdev))
1851 netif_wake_queue(info->netdev);
1852 }
1853
1854 /**
1855 * called by device driver when frame received
1856 * pass frame to network layer
1857 *
1858 * info pointer to device instance information
1859 * buf pointer to buffer contianing frame data
1860 * size count of data bytes in buf
1861 */
1862 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1863 {
1864 struct sk_buff *skb = dev_alloc_skb(size);
1865 struct net_device *dev = info->netdev;
1866
1867 if (debug_level >= DEBUG_LEVEL_INFO)
1868 printk("hdlcdev_rx(%s)\n",dev->name);
1869
1870 if (skb == NULL) {
1871 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1872 dev->name);
1873 dev->stats.rx_dropped++;
1874 return;
1875 }
1876
1877 memcpy(skb_put(skb, size), buf, size);
1878
1879 skb->protocol = hdlc_type_trans(skb, dev);
1880
1881 dev->stats.rx_packets++;
1882 dev->stats.rx_bytes += size;
1883
1884 netif_rx(skb);
1885 }
1886
1887 static const struct net_device_ops hdlcdev_ops = {
1888 .ndo_open = hdlcdev_open,
1889 .ndo_stop = hdlcdev_close,
1890 .ndo_change_mtu = hdlc_change_mtu,
1891 .ndo_start_xmit = hdlc_start_xmit,
1892 .ndo_do_ioctl = hdlcdev_ioctl,
1893 .ndo_tx_timeout = hdlcdev_tx_timeout,
1894 };
1895
1896 /**
1897 * called by device driver when adding device instance
1898 * do generic HDLC initialization
1899 *
1900 * info pointer to device instance information
1901 *
1902 * returns 0 if success, otherwise error code
1903 */
1904 static int hdlcdev_init(SLMP_INFO *info)
1905 {
1906 int rc;
1907 struct net_device *dev;
1908 hdlc_device *hdlc;
1909
1910 /* allocate and initialize network and HDLC layer objects */
1911
1912 dev = alloc_hdlcdev(info);
1913 if (!dev) {
1914 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1915 return -ENOMEM;
1916 }
1917
1918 /* for network layer reporting purposes only */
1919 dev->mem_start = info->phys_sca_base;
1920 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1921 dev->irq = info->irq_level;
1922
1923 /* network layer callbacks and settings */
1924 dev->netdev_ops = &hdlcdev_ops;
1925 dev->watchdog_timeo = 10 * HZ;
1926 dev->tx_queue_len = 50;
1927
1928 /* generic HDLC layer callbacks and settings */
1929 hdlc = dev_to_hdlc(dev);
1930 hdlc->attach = hdlcdev_attach;
1931 hdlc->xmit = hdlcdev_xmit;
1932
1933 /* register objects with HDLC layer */
1934 rc = register_hdlc_device(dev);
1935 if (rc) {
1936 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1937 free_netdev(dev);
1938 return rc;
1939 }
1940
1941 info->netdev = dev;
1942 return 0;
1943 }
1944
1945 /**
1946 * called by device driver when removing device instance
1947 * do generic HDLC cleanup
1948 *
1949 * info pointer to device instance information
1950 */
1951 static void hdlcdev_exit(SLMP_INFO *info)
1952 {
1953 unregister_hdlc_device(info->netdev);
1954 free_netdev(info->netdev);
1955 info->netdev = NULL;
1956 }
1957
1958 #endif /* CONFIG_HDLC */
1959
1960
1961 /* Return next bottom half action to perform.
1962 * Return Value: BH action code or 0 if nothing to do.
1963 */
1964 static int bh_action(SLMP_INFO *info)
1965 {
1966 unsigned long flags;
1967 int rc = 0;
1968
1969 spin_lock_irqsave(&info->lock,flags);
1970
1971 if (info->pending_bh & BH_RECEIVE) {
1972 info->pending_bh &= ~BH_RECEIVE;
1973 rc = BH_RECEIVE;
1974 } else if (info->pending_bh & BH_TRANSMIT) {
1975 info->pending_bh &= ~BH_TRANSMIT;
1976 rc = BH_TRANSMIT;
1977 } else if (info->pending_bh & BH_STATUS) {
1978 info->pending_bh &= ~BH_STATUS;
1979 rc = BH_STATUS;
1980 }
1981
1982 if (!rc) {
1983 /* Mark BH routine as complete */
1984 info->bh_running = false;
1985 info->bh_requested = false;
1986 }
1987
1988 spin_unlock_irqrestore(&info->lock,flags);
1989
1990 return rc;
1991 }
1992
1993 /* Perform bottom half processing of work items queued by ISR.
1994 */
1995 static void bh_handler(struct work_struct *work)
1996 {
1997 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
1998 int action;
1999
2000 if ( debug_level >= DEBUG_LEVEL_BH )
2001 printk( "%s(%d):%s bh_handler() entry\n",
2002 __FILE__,__LINE__,info->device_name);
2003
2004 info->bh_running = true;
2005
2006 while((action = bh_action(info)) != 0) {
2007
2008 /* Process work item */
2009 if ( debug_level >= DEBUG_LEVEL_BH )
2010 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2011 __FILE__,__LINE__,info->device_name, action);
2012
2013 switch (action) {
2014
2015 case BH_RECEIVE:
2016 bh_receive(info);
2017 break;
2018 case BH_TRANSMIT:
2019 bh_transmit(info);
2020 break;
2021 case BH_STATUS:
2022 bh_status(info);
2023 break;
2024 default:
2025 /* unknown work item ID */
2026 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2027 __FILE__,__LINE__,info->device_name,action);
2028 break;
2029 }
2030 }
2031
2032 if ( debug_level >= DEBUG_LEVEL_BH )
2033 printk( "%s(%d):%s bh_handler() exit\n",
2034 __FILE__,__LINE__,info->device_name);
2035 }
2036
2037 static void bh_receive(SLMP_INFO *info)
2038 {
2039 if ( debug_level >= DEBUG_LEVEL_BH )
2040 printk( "%s(%d):%s bh_receive()\n",
2041 __FILE__,__LINE__,info->device_name);
2042
2043 while( rx_get_frame(info) );
2044 }
2045
2046 static void bh_transmit(SLMP_INFO *info)
2047 {
2048 struct tty_struct *tty = info->port.tty;
2049
2050 if ( debug_level >= DEBUG_LEVEL_BH )
2051 printk( "%s(%d):%s bh_transmit() entry\n",
2052 __FILE__,__LINE__,info->device_name);
2053
2054 if (tty)
2055 tty_wakeup(tty);
2056 }
2057
2058 static void bh_status(SLMP_INFO *info)
2059 {
2060 if ( debug_level >= DEBUG_LEVEL_BH )
2061 printk( "%s(%d):%s bh_status() entry\n",
2062 __FILE__,__LINE__,info->device_name);
2063
2064 info->ri_chkcount = 0;
2065 info->dsr_chkcount = 0;
2066 info->dcd_chkcount = 0;
2067 info->cts_chkcount = 0;
2068 }
2069
2070 static void isr_timer(SLMP_INFO * info)
2071 {
2072 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2073
2074 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2075 write_reg(info, IER2, 0);
2076
2077 /* TMCS, Timer Control/Status Register
2078 *
2079 * 07 CMF, Compare match flag (read only) 1=match
2080 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2081 * 05 Reserved, must be 0
2082 * 04 TME, Timer Enable
2083 * 03..00 Reserved, must be 0
2084 *
2085 * 0000 0000
2086 */
2087 write_reg(info, (unsigned char)(timer + TMCS), 0);
2088
2089 info->irq_occurred = true;
2090
2091 if ( debug_level >= DEBUG_LEVEL_ISR )
2092 printk("%s(%d):%s isr_timer()\n",
2093 __FILE__,__LINE__,info->device_name);
2094 }
2095
2096 static void isr_rxint(SLMP_INFO * info)
2097 {
2098 struct tty_struct *tty = info->port.tty;
2099 struct mgsl_icount *icount = &info->icount;
2100 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2101 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2102
2103 /* clear status bits */
2104 if (status)
2105 write_reg(info, SR1, status);
2106
2107 if (status2)
2108 write_reg(info, SR2, status2);
2109
2110 if ( debug_level >= DEBUG_LEVEL_ISR )
2111 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2112 __FILE__,__LINE__,info->device_name,status,status2);
2113
2114 if (info->params.mode == MGSL_MODE_ASYNC) {
2115 if (status & BRKD) {
2116 icount->brk++;
2117
2118 /* process break detection if tty control
2119 * is not set to ignore it
2120 */
2121 if (!(status & info->ignore_status_mask1)) {
2122 if (info->read_status_mask1 & BRKD) {
2123 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2124 if (tty && (info->port.flags & ASYNC_SAK))
2125 do_SAK(tty);
2126 }
2127 }
2128 }
2129 }
2130 else {
2131 if (status & (FLGD|IDLD)) {
2132 if (status & FLGD)
2133 info->icount.exithunt++;
2134 else if (status & IDLD)
2135 info->icount.rxidle++;
2136 wake_up_interruptible(&info->event_wait_q);
2137 }
2138 }
2139
2140 if (status & CDCD) {
2141 /* simulate a common modem status change interrupt
2142 * for our handler
2143 */
2144 get_signals( info );
2145 isr_io_pin(info,
2146 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2147 }
2148 }
2149
2150 /*
2151 * handle async rx data interrupts
2152 */
2153 static void isr_rxrdy(SLMP_INFO * info)
2154 {
2155 u16 status;
2156 unsigned char DataByte;
2157 struct mgsl_icount *icount = &info->icount;
2158
2159 if ( debug_level >= DEBUG_LEVEL_ISR )
2160 printk("%s(%d):%s isr_rxrdy\n",
2161 __FILE__,__LINE__,info->device_name);
2162
2163 while((status = read_reg(info,CST0)) & BIT0)
2164 {
2165 int flag = 0;
2166 bool over = false;
2167 DataByte = read_reg(info,TRB);
2168
2169 icount->rx++;
2170
2171 if ( status & (PE + FRME + OVRN) ) {
2172 printk("%s(%d):%s rxerr=%04X\n",
2173 __FILE__,__LINE__,info->device_name,status);
2174
2175 /* update error statistics */
2176 if (status & PE)
2177 icount->parity++;
2178 else if (status & FRME)
2179 icount->frame++;
2180 else if (status & OVRN)
2181 icount->overrun++;
2182
2183 /* discard char if tty control flags say so */
2184 if (status & info->ignore_status_mask2)
2185 continue;
2186
2187 status &= info->read_status_mask2;
2188
2189 if (status & PE)
2190 flag = TTY_PARITY;
2191 else if (status & FRME)
2192 flag = TTY_FRAME;
2193 if (status & OVRN) {
2194 /* Overrun is special, since it's
2195 * reported immediately, and doesn't
2196 * affect the current character
2197 */
2198 over = true;
2199 }
2200 } /* end of if (error) */
2201
2202 tty_insert_flip_char(&info->port, DataByte, flag);
2203 if (over)
2204 tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
2205 }
2206
2207 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2208 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2209 __FILE__,__LINE__,info->device_name,
2210 icount->rx,icount->brk,icount->parity,
2211 icount->frame,icount->overrun);
2212 }
2213
2214 tty_flip_buffer_push(&info->port);
2215 }
2216
2217 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2218 {
2219 if ( debug_level >= DEBUG_LEVEL_ISR )
2220 printk("%s(%d):%s isr_txeom status=%02x\n",
2221 __FILE__,__LINE__,info->device_name,status);
2222
2223 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2224 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2225 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2226
2227 if (status & UDRN) {
2228 write_reg(info, CMD, TXRESET);
2229 write_reg(info, CMD, TXENABLE);
2230 } else
2231 write_reg(info, CMD, TXBUFCLR);
2232
2233 /* disable and clear tx interrupts */
2234 info->ie0_value &= ~TXRDYE;
2235 info->ie1_value &= ~(IDLE + UDRN);
2236 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2237 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2238
2239 if ( info->tx_active ) {
2240 if (info->params.mode != MGSL_MODE_ASYNC) {
2241 if (status & UDRN)
2242 info->icount.txunder++;
2243 else if (status & IDLE)
2244 info->icount.txok++;
2245 }
2246
2247 info->tx_active = false;
2248 info->tx_count = info->tx_put = info->tx_get = 0;
2249
2250 del_timer(&info->tx_timer);
2251
2252 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2253 info->serial_signals &= ~SerialSignal_RTS;
2254 info->drop_rts_on_tx_done = false;
2255 set_signals(info);
2256 }
2257
2258 #if SYNCLINK_GENERIC_HDLC
2259 if (info->netcount)
2260 hdlcdev_tx_done(info);
2261 else
2262 #endif
2263 {
2264 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2265 tx_stop(info);
2266 return;
2267 }
2268 info->pending_bh |= BH_TRANSMIT;
2269 }
2270 }
2271 }
2272
2273
2274 /*
2275 * handle tx status interrupts
2276 */
2277 static void isr_txint(SLMP_INFO * info)
2278 {
2279 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2280
2281 /* clear status bits */
2282 write_reg(info, SR1, status);
2283
2284 if ( debug_level >= DEBUG_LEVEL_ISR )
2285 printk("%s(%d):%s isr_txint status=%02x\n",
2286 __FILE__,__LINE__,info->device_name,status);
2287
2288 if (status & (UDRN + IDLE))
2289 isr_txeom(info, status);
2290
2291 if (status & CCTS) {
2292 /* simulate a common modem status change interrupt
2293 * for our handler
2294 */
2295 get_signals( info );
2296 isr_io_pin(info,
2297 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2298
2299 }
2300 }
2301
2302 /*
2303 * handle async tx data interrupts
2304 */
2305 static void isr_txrdy(SLMP_INFO * info)
2306 {
2307 if ( debug_level >= DEBUG_LEVEL_ISR )
2308 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2309 __FILE__,__LINE__,info->device_name,info->tx_count);
2310
2311 if (info->params.mode != MGSL_MODE_ASYNC) {
2312 /* disable TXRDY IRQ, enable IDLE IRQ */
2313 info->ie0_value &= ~TXRDYE;
2314 info->ie1_value |= IDLE;
2315 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2316 return;
2317 }
2318
2319 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2320 tx_stop(info);
2321 return;
2322 }
2323
2324 if ( info->tx_count )
2325 tx_load_fifo( info );
2326 else {
2327 info->tx_active = false;
2328 info->ie0_value &= ~TXRDYE;
2329 write_reg(info, IE0, info->ie0_value);
2330 }
2331
2332 if (info->tx_count < WAKEUP_CHARS)
2333 info->pending_bh |= BH_TRANSMIT;
2334 }
2335
2336 static void isr_rxdmaok(SLMP_INFO * info)
2337 {
2338 /* BIT7 = EOT (end of transfer)
2339 * BIT6 = EOM (end of message/frame)
2340 */
2341 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2342
2343 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2344 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2345
2346 if ( debug_level >= DEBUG_LEVEL_ISR )
2347 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2348 __FILE__,__LINE__,info->device_name,status);
2349
2350 info->pending_bh |= BH_RECEIVE;
2351 }
2352
2353 static void isr_rxdmaerror(SLMP_INFO * info)
2354 {
2355 /* BIT5 = BOF (buffer overflow)
2356 * BIT4 = COF (counter overflow)
2357 */
2358 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2359
2360 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2361 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2362
2363 if ( debug_level >= DEBUG_LEVEL_ISR )
2364 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2365 __FILE__,__LINE__,info->device_name,status);
2366
2367 info->rx_overflow = true;
2368 info->pending_bh |= BH_RECEIVE;
2369 }
2370
2371 static void isr_txdmaok(SLMP_INFO * info)
2372 {
2373 unsigned char status_reg1 = read_reg(info, SR1);
2374
2375 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2376 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2377 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2378
2379 if ( debug_level >= DEBUG_LEVEL_ISR )
2380 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2381 __FILE__,__LINE__,info->device_name,status_reg1);
2382
2383 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2384 write_reg16(info, TRC0, 0);
2385 info->ie0_value |= TXRDYE;
2386 write_reg(info, IE0, info->ie0_value);
2387 }
2388
2389 static void isr_txdmaerror(SLMP_INFO * info)
2390 {
2391 /* BIT5 = BOF (buffer overflow)
2392 * BIT4 = COF (counter overflow)
2393 */
2394 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2395
2396 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2397 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2398
2399 if ( debug_level >= DEBUG_LEVEL_ISR )
2400 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2401 __FILE__,__LINE__,info->device_name,status);
2402 }
2403
2404 /* handle input serial signal changes
2405 */
2406 static void isr_io_pin( SLMP_INFO *info, u16 status )
2407 {
2408 struct mgsl_icount *icount;
2409
2410 if ( debug_level >= DEBUG_LEVEL_ISR )
2411 printk("%s(%d):isr_io_pin status=%04X\n",
2412 __FILE__,__LINE__,status);
2413
2414 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2415 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2416 icount = &info->icount;
2417 /* update input line counters */
2418 if (status & MISCSTATUS_RI_LATCHED) {
2419 icount->rng++;
2420 if ( status & SerialSignal_RI )
2421 info->input_signal_events.ri_up++;
2422 else
2423 info->input_signal_events.ri_down++;
2424 }
2425 if (status & MISCSTATUS_DSR_LATCHED) {
2426 icount->dsr++;
2427 if ( status & SerialSignal_DSR )
2428 info->input_signal_events.dsr_up++;
2429 else
2430 info->input_signal_events.dsr_down++;
2431 }
2432 if (status & MISCSTATUS_DCD_LATCHED) {
2433 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2434 info->ie1_value &= ~CDCD;
2435 write_reg(info, IE1, info->ie1_value);
2436 }
2437 icount->dcd++;
2438 if (status & SerialSignal_DCD) {
2439 info->input_signal_events.dcd_up++;
2440 } else
2441 info->input_signal_events.dcd_down++;
2442 #if SYNCLINK_GENERIC_HDLC
2443 if (info->netcount) {
2444 if (status & SerialSignal_DCD)
2445 netif_carrier_on(info->netdev);
2446 else
2447 netif_carrier_off(info->netdev);
2448 }
2449 #endif
2450 }
2451 if (status & MISCSTATUS_CTS_LATCHED)
2452 {
2453 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2454 info->ie1_value &= ~CCTS;
2455 write_reg(info, IE1, info->ie1_value);
2456 }
2457 icount->cts++;
2458 if ( status & SerialSignal_CTS )
2459 info->input_signal_events.cts_up++;
2460 else
2461 info->input_signal_events.cts_down++;
2462 }
2463 wake_up_interruptible(&info->status_event_wait_q);
2464 wake_up_interruptible(&info->event_wait_q);
2465
2466 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2467 (status & MISCSTATUS_DCD_LATCHED) ) {
2468 if ( debug_level >= DEBUG_LEVEL_ISR )
2469 printk("%s CD now %s...", info->device_name,
2470 (status & SerialSignal_DCD) ? "on" : "off");
2471 if (status & SerialSignal_DCD)
2472 wake_up_interruptible(&info->port.open_wait);
2473 else {
2474 if ( debug_level >= DEBUG_LEVEL_ISR )
2475 printk("doing serial hangup...");
2476 if (info->port.tty)
2477 tty_hangup(info->port.tty);
2478 }
2479 }
2480
2481 if (tty_port_cts_enabled(&info->port) &&
2482 (status & MISCSTATUS_CTS_LATCHED) ) {
2483 if ( info->port.tty ) {
2484 if (info->port.tty->hw_stopped) {
2485 if (status & SerialSignal_CTS) {
2486 if ( debug_level >= DEBUG_LEVEL_ISR )
2487 printk("CTS tx start...");
2488 info->port.tty->hw_stopped = 0;
2489 tx_start(info);
2490 info->pending_bh |= BH_TRANSMIT;
2491 return;
2492 }
2493 } else {
2494 if (!(status & SerialSignal_CTS)) {
2495 if ( debug_level >= DEBUG_LEVEL_ISR )
2496 printk("CTS tx stop...");
2497 info->port.tty->hw_stopped = 1;
2498 tx_stop(info);
2499 }
2500 }
2501 }
2502 }
2503 }
2504
2505 info->pending_bh |= BH_STATUS;
2506 }
2507
2508 /* Interrupt service routine entry point.
2509 *
2510 * Arguments:
2511 * irq interrupt number that caused interrupt
2512 * dev_id device ID supplied during interrupt registration
2513 * regs interrupted processor context
2514 */
2515 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2516 {
2517 SLMP_INFO *info = dev_id;
2518 unsigned char status, status0, status1=0;
2519 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2520 unsigned char timerstatus0, timerstatus1=0;
2521 unsigned char shift;
2522 unsigned int i;
2523 unsigned short tmp;
2524
2525 if ( debug_level >= DEBUG_LEVEL_ISR )
2526 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2527 __FILE__, __LINE__, info->irq_level);
2528
2529 spin_lock(&info->lock);
2530
2531 for(;;) {
2532
2533 /* get status for SCA0 (ports 0-1) */
2534 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2535 status0 = (unsigned char)tmp;
2536 dmastatus0 = (unsigned char)(tmp>>8);
2537 timerstatus0 = read_reg(info, ISR2);
2538
2539 if ( debug_level >= DEBUG_LEVEL_ISR )
2540 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2541 __FILE__, __LINE__, info->device_name,
2542 status0, dmastatus0, timerstatus0);
2543
2544 if (info->port_count == 4) {
2545 /* get status for SCA1 (ports 2-3) */
2546 tmp = read_reg16(info->port_array[2], ISR0);
2547 status1 = (unsigned char)tmp;
2548 dmastatus1 = (unsigned char)(tmp>>8);
2549 timerstatus1 = read_reg(info->port_array[2], ISR2);
2550
2551 if ( debug_level >= DEBUG_LEVEL_ISR )
2552 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2553 __FILE__,__LINE__,info->device_name,
2554 status1,dmastatus1,timerstatus1);
2555 }
2556
2557 if (!status0 && !dmastatus0 && !timerstatus0 &&
2558 !status1 && !dmastatus1 && !timerstatus1)
2559 break;
2560
2561 for(i=0; i < info->port_count ; i++) {
2562 if (info->port_array[i] == NULL)
2563 continue;
2564 if (i < 2) {
2565 status = status0;
2566 dmastatus = dmastatus0;
2567 } else {
2568 status = status1;
2569 dmastatus = dmastatus1;
2570 }
2571
2572 shift = i & 1 ? 4 :0;
2573
2574 if (status & BIT0 << shift)
2575 isr_rxrdy(info->port_array[i]);
2576 if (status & BIT1 << shift)
2577 isr_txrdy(info->port_array[i]);
2578 if (status & BIT2 << shift)
2579 isr_rxint(info->port_array[i]);
2580 if (status & BIT3 << shift)
2581 isr_txint(info->port_array[i]);
2582
2583 if (dmastatus & BIT0 << shift)
2584 isr_rxdmaerror(info->port_array[i]);
2585 if (dmastatus & BIT1 << shift)
2586 isr_rxdmaok(info->port_array[i]);
2587 if (dmastatus & BIT2 << shift)
2588 isr_txdmaerror(info->port_array[i]);
2589 if (dmastatus & BIT3 << shift)
2590 isr_txdmaok(info->port_array[i]);
2591 }
2592
2593 if (timerstatus0 & (BIT5 | BIT4))
2594 isr_timer(info->port_array[0]);
2595 if (timerstatus0 & (BIT7 | BIT6))
2596 isr_timer(info->port_array[1]);
2597 if (timerstatus1 & (BIT5 | BIT4))
2598 isr_timer(info->port_array[2]);
2599 if (timerstatus1 & (BIT7 | BIT6))
2600 isr_timer(info->port_array[3]);
2601 }
2602
2603 for(i=0; i < info->port_count ; i++) {
2604 SLMP_INFO * port = info->port_array[i];
2605
2606 /* Request bottom half processing if there's something
2607 * for it to do and the bh is not already running.
2608 *
2609 * Note: startup adapter diags require interrupts.
2610 * do not request bottom half processing if the
2611 * device is not open in a normal mode.
2612 */
2613 if ( port && (port->port.count || port->netcount) &&
2614 port->pending_bh && !port->bh_running &&
2615 !port->bh_requested ) {
2616 if ( debug_level >= DEBUG_LEVEL_ISR )
2617 printk("%s(%d):%s queueing bh task.\n",
2618 __FILE__,__LINE__,port->device_name);
2619 schedule_work(&port->task);
2620 port->bh_requested = true;
2621 }
2622 }
2623
2624 spin_unlock(&info->lock);
2625
2626 if ( debug_level >= DEBUG_LEVEL_ISR )
2627 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2628 __FILE__, __LINE__, info->irq_level);
2629 return IRQ_HANDLED;
2630 }
2631
2632 /* Initialize and start device.
2633 */
2634 static int startup(SLMP_INFO * info)
2635 {
2636 if ( debug_level >= DEBUG_LEVEL_INFO )
2637 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2638
2639 if (info->port.flags & ASYNC_INITIALIZED)
2640 return 0;
2641
2642 if (!info->tx_buf) {
2643 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2644 if (!info->tx_buf) {
2645 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2646 __FILE__,__LINE__,info->device_name);
2647 return -ENOMEM;
2648 }
2649 }
2650
2651 info->pending_bh = 0;
2652
2653 memset(&info->icount, 0, sizeof(info->icount));
2654
2655 /* program hardware for current parameters */
2656 reset_port(info);
2657
2658 change_params(info);
2659
2660 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2661
2662 if (info->port.tty)
2663 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2664
2665 info->port.flags |= ASYNC_INITIALIZED;
2666
2667 return 0;
2668 }
2669
2670 /* Called by close() and hangup() to shutdown hardware
2671 */
2672 static void shutdown(SLMP_INFO * info)
2673 {
2674 unsigned long flags;
2675
2676 if (!(info->port.flags & ASYNC_INITIALIZED))
2677 return;
2678
2679 if (debug_level >= DEBUG_LEVEL_INFO)
2680 printk("%s(%d):%s synclinkmp_shutdown()\n",
2681 __FILE__,__LINE__, info->device_name );
2682
2683 /* clear status wait queue because status changes */
2684 /* can't happen after shutting down the hardware */
2685 wake_up_interruptible(&info->status_event_wait_q);
2686 wake_up_interruptible(&info->event_wait_q);
2687
2688 del_timer(&info->tx_timer);
2689 del_timer(&info->status_timer);
2690
2691 kfree(info->tx_buf);
2692 info->tx_buf = NULL;
2693
2694 spin_lock_irqsave(&info->lock,flags);
2695
2696 reset_port(info);
2697
2698 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2699 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2700 set_signals(info);
2701 }
2702
2703 spin_unlock_irqrestore(&info->lock,flags);
2704
2705 if (info->port.tty)
2706 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2707
2708 info->port.flags &= ~ASYNC_INITIALIZED;
2709 }
2710
2711 static void program_hw(SLMP_INFO *info)
2712 {
2713 unsigned long flags;
2714
2715 spin_lock_irqsave(&info->lock,flags);
2716
2717 rx_stop(info);
2718 tx_stop(info);
2719
2720 info->tx_count = info->tx_put = info->tx_get = 0;
2721
2722 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2723 hdlc_mode(info);
2724 else
2725 async_mode(info);
2726
2727 set_signals(info);
2728
2729 info->dcd_chkcount = 0;
2730 info->cts_chkcount = 0;
2731 info->ri_chkcount = 0;
2732 info->dsr_chkcount = 0;
2733
2734 info->ie1_value |= (CDCD|CCTS);
2735 write_reg(info, IE1, info->ie1_value);
2736
2737 get_signals(info);
2738
2739 if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
2740 rx_start(info);
2741
2742 spin_unlock_irqrestore(&info->lock,flags);
2743 }
2744
2745 /* Reconfigure adapter based on new parameters
2746 */
2747 static void change_params(SLMP_INFO *info)
2748 {
2749 unsigned cflag;
2750 int bits_per_char;
2751
2752 if (!info->port.tty)
2753 return;
2754
2755 if (debug_level >= DEBUG_LEVEL_INFO)
2756 printk("%s(%d):%s change_params()\n",
2757 __FILE__,__LINE__, info->device_name );
2758
2759 cflag = info->port.tty->termios.c_cflag;
2760
2761 /* if B0 rate (hangup) specified then negate RTS and DTR */
2762 /* otherwise assert RTS and DTR */
2763 if (cflag & CBAUD)
2764 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
2765 else
2766 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2767
2768 /* byte size and parity */
2769
2770 switch (cflag & CSIZE) {
2771 case CS5: info->params.data_bits = 5; break;
2772 case CS6: info->params.data_bits = 6; break;
2773 case CS7: info->params.data_bits = 7; break;
2774 case CS8: info->params.data_bits = 8; break;
2775 /* Never happens, but GCC is too dumb to figure it out */
2776 default: info->params.data_bits = 7; break;
2777 }
2778
2779 if (cflag & CSTOPB)
2780 info->params.stop_bits = 2;
2781 else
2782 info->params.stop_bits = 1;
2783
2784 info->params.parity = ASYNC_PARITY_NONE;
2785 if (cflag & PARENB) {
2786 if (cflag & PARODD)
2787 info->params.parity = ASYNC_PARITY_ODD;
2788 else
2789 info->params.parity = ASYNC_PARITY_EVEN;
2790 #ifdef CMSPAR
2791 if (cflag & CMSPAR)
2792 info->params.parity = ASYNC_PARITY_SPACE;
2793 #endif
2794 }
2795
2796 /* calculate number of jiffies to transmit a full
2797 * FIFO (32 bytes) at specified data rate
2798 */
2799 bits_per_char = info->params.data_bits +
2800 info->params.stop_bits + 1;
2801
2802 /* if port data rate is set to 460800 or less then
2803 * allow tty settings to override, otherwise keep the
2804 * current data rate.
2805 */
2806 if (info->params.data_rate <= 460800) {
2807 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2808 }
2809
2810 if ( info->params.data_rate ) {
2811 info->timeout = (32*HZ*bits_per_char) /
2812 info->params.data_rate;
2813 }
2814 info->timeout += HZ/50; /* Add .02 seconds of slop */
2815
2816 if (cflag & CRTSCTS)
2817 info->port.flags |= ASYNC_CTS_FLOW;
2818 else
2819 info->port.flags &= ~ASYNC_CTS_FLOW;
2820
2821 if (cflag & CLOCAL)
2822 info->port.flags &= ~ASYNC_CHECK_CD;
2823 else
2824 info->port.flags |= ASYNC_CHECK_CD;
2825
2826 /* process tty input control flags */
2827
2828 info->read_status_mask2 = OVRN;
2829 if (I_INPCK(info->port.tty))
2830 info->read_status_mask2 |= PE | FRME;
2831 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2832 info->read_status_mask1 |= BRKD;
2833 if (I_IGNPAR(info->port.tty))
2834 info->ignore_status_mask2 |= PE | FRME;
2835 if (I_IGNBRK(info->port.tty)) {
2836 info->ignore_status_mask1 |= BRKD;
2837 /* If ignoring parity and break indicators, ignore
2838 * overruns too. (For real raw support).
2839 */
2840 if (I_IGNPAR(info->port.tty))
2841 info->ignore_status_mask2 |= OVRN;
2842 }
2843
2844 program_hw(info);
2845 }
2846
2847 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2848 {
2849 int err;
2850
2851 if (debug_level >= DEBUG_LEVEL_INFO)
2852 printk("%s(%d):%s get_params()\n",
2853 __FILE__,__LINE__, info->device_name);
2854
2855 if (!user_icount) {
2856 memset(&info->icount, 0, sizeof(info->icount));
2857 } else {
2858 mutex_lock(&info->port.mutex);
2859 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2860 mutex_unlock(&info->port.mutex);
2861 if (err)
2862 return -EFAULT;
2863 }
2864
2865 return 0;
2866 }
2867
2868 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2869 {
2870 int err;
2871 if (debug_level >= DEBUG_LEVEL_INFO)
2872 printk("%s(%d):%s get_params()\n",
2873 __FILE__,__LINE__, info->device_name);
2874
2875 mutex_lock(&info->port.mutex);
2876 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2877 mutex_unlock(&info->port.mutex);
2878 if (err) {
2879 if ( debug_level >= DEBUG_LEVEL_INFO )
2880 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2881 __FILE__,__LINE__,info->device_name);
2882 return -EFAULT;
2883 }
2884
2885 return 0;
2886 }
2887
2888 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2889 {
2890 unsigned long flags;
2891 MGSL_PARAMS tmp_params;
2892 int err;
2893
2894 if (debug_level >= DEBUG_LEVEL_INFO)
2895 printk("%s(%d):%s set_params\n",
2896 __FILE__,__LINE__,info->device_name );
2897 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2898 if (err) {
2899 if ( debug_level >= DEBUG_LEVEL_INFO )
2900 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2901 __FILE__,__LINE__,info->device_name);
2902 return -EFAULT;
2903 }
2904
2905 mutex_lock(&info->port.mutex);
2906 spin_lock_irqsave(&info->lock,flags);
2907 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2908 spin_unlock_irqrestore(&info->lock,flags);
2909
2910 change_params(info);
2911 mutex_unlock(&info->port.mutex);
2912
2913 return 0;
2914 }
2915
2916 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2917 {
2918 int err;
2919
2920 if (debug_level >= DEBUG_LEVEL_INFO)
2921 printk("%s(%d):%s get_txidle()=%d\n",
2922 __FILE__,__LINE__, info->device_name, info->idle_mode);
2923
2924 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2925 if (err) {
2926 if ( debug_level >= DEBUG_LEVEL_INFO )
2927 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2928 __FILE__,__LINE__,info->device_name);
2929 return -EFAULT;
2930 }
2931
2932 return 0;
2933 }
2934
2935 static int set_txidle(SLMP_INFO * info, int idle_mode)
2936 {
2937 unsigned long flags;
2938
2939 if (debug_level >= DEBUG_LEVEL_INFO)
2940 printk("%s(%d):%s set_txidle(%d)\n",
2941 __FILE__,__LINE__,info->device_name, idle_mode );
2942
2943 spin_lock_irqsave(&info->lock,flags);
2944 info->idle_mode = idle_mode;
2945 tx_set_idle( info );
2946 spin_unlock_irqrestore(&info->lock,flags);
2947 return 0;
2948 }
2949
2950 static int tx_enable(SLMP_INFO * info, int enable)
2951 {
2952 unsigned long flags;
2953
2954 if (debug_level >= DEBUG_LEVEL_INFO)
2955 printk("%s(%d):%s tx_enable(%d)\n",
2956 __FILE__,__LINE__,info->device_name, enable);
2957
2958 spin_lock_irqsave(&info->lock,flags);
2959 if ( enable ) {
2960 if ( !info->tx_enabled ) {
2961 tx_start(info);
2962 }
2963 } else {
2964 if ( info->tx_enabled )
2965 tx_stop(info);
2966 }
2967 spin_unlock_irqrestore(&info->lock,flags);
2968 return 0;
2969 }
2970
2971 /* abort send HDLC frame
2972 */
2973 static int tx_abort(SLMP_INFO * info)
2974 {
2975 unsigned long flags;
2976
2977 if (debug_level >= DEBUG_LEVEL_INFO)
2978 printk("%s(%d):%s tx_abort()\n",
2979 __FILE__,__LINE__,info->device_name);
2980
2981 spin_lock_irqsave(&info->lock,flags);
2982 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2983 info->ie1_value &= ~UDRN;
2984 info->ie1_value |= IDLE;
2985 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
2986 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
2987
2988 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
2989 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2990
2991 write_reg(info, CMD, TXABORT);
2992 }
2993 spin_unlock_irqrestore(&info->lock,flags);
2994 return 0;
2995 }
2996
2997 static int rx_enable(SLMP_INFO * info, int enable)
2998 {
2999 unsigned long flags;
3000
3001 if (debug_level >= DEBUG_LEVEL_INFO)
3002 printk("%s(%d):%s rx_enable(%d)\n",
3003 __FILE__,__LINE__,info->device_name,enable);
3004
3005 spin_lock_irqsave(&info->lock,flags);
3006 if ( enable ) {
3007 if ( !info->rx_enabled )
3008 rx_start(info);
3009 } else {
3010 if ( info->rx_enabled )
3011 rx_stop(info);
3012 }
3013 spin_unlock_irqrestore(&info->lock,flags);
3014 return 0;
3015 }
3016
3017 /* wait for specified event to occur
3018 */
3019 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3020 {
3021 unsigned long flags;
3022 int s;
3023 int rc=0;
3024 struct mgsl_icount cprev, cnow;
3025 int events;
3026 int mask;
3027 struct _input_signal_events oldsigs, newsigs;
3028 DECLARE_WAITQUEUE(wait, current);
3029
3030 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3031 if (rc) {
3032 return -EFAULT;
3033 }
3034
3035 if (debug_level >= DEBUG_LEVEL_INFO)
3036 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3037 __FILE__,__LINE__,info->device_name,mask);
3038
3039 spin_lock_irqsave(&info->lock,flags);
3040
3041 /* return immediately if state matches requested events */
3042 get_signals(info);
3043 s = info->serial_signals;
3044
3045 events = mask &
3046 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3047 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3048 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3049 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3050 if (events) {
3051 spin_unlock_irqrestore(&info->lock,flags);
3052 goto exit;
3053 }
3054
3055 /* save current irq counts */
3056 cprev = info->icount;
3057 oldsigs = info->input_signal_events;
3058
3059 /* enable hunt and idle irqs if needed */
3060 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3061 unsigned char oldval = info->ie1_value;
3062 unsigned char newval = oldval +
3063 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3064 (mask & MgslEvent_IdleReceived ? IDLD:0);
3065 if ( oldval != newval ) {
3066 info->ie1_value = newval;
3067 write_reg(info, IE1, info->ie1_value);
3068 }
3069 }
3070
3071 set_current_state(TASK_INTERRUPTIBLE);
3072 add_wait_queue(&info->event_wait_q, &wait);
3073
3074 spin_unlock_irqrestore(&info->lock,flags);
3075
3076 for(;;) {
3077 schedule();
3078 if (signal_pending(current)) {
3079 rc = -ERESTARTSYS;
3080 break;
3081 }
3082
3083 /* get current irq counts */
3084 spin_lock_irqsave(&info->lock,flags);
3085 cnow = info->icount;
3086 newsigs = info->input_signal_events;
3087 set_current_state(TASK_INTERRUPTIBLE);
3088 spin_unlock_irqrestore(&info->lock,flags);
3089
3090 /* if no change, wait aborted for some reason */
3091 if (newsigs.dsr_up == oldsigs.dsr_up &&
3092 newsigs.dsr_down == oldsigs.dsr_down &&
3093 newsigs.dcd_up == oldsigs.dcd_up &&
3094 newsigs.dcd_down == oldsigs.dcd_down &&
3095 newsigs.cts_up == oldsigs.cts_up &&
3096 newsigs.cts_down == oldsigs.cts_down &&
3097 newsigs.ri_up == oldsigs.ri_up &&
3098 newsigs.ri_down == oldsigs.ri_down &&
3099 cnow.exithunt == cprev.exithunt &&
3100 cnow.rxidle == cprev.rxidle) {
3101 rc = -EIO;
3102 break;
3103 }
3104
3105 events = mask &
3106 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3107 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3108 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3109 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3110 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3111 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3112 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3113 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3114 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3115 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3116 if (events)
3117 break;
3118
3119 cprev = cnow;
3120 oldsigs = newsigs;
3121 }
3122
3123 remove_wait_queue(&info->event_wait_q, &wait);
3124 set_current_state(TASK_RUNNING);
3125
3126
3127 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3128 spin_lock_irqsave(&info->lock,flags);
3129 if (!waitqueue_active(&info->event_wait_q)) {
3130 /* disable enable exit hunt mode/idle rcvd IRQs */
3131 info->ie1_value &= ~(FLGD|IDLD);
3132 write_reg(info, IE1, info->ie1_value);
3133 }
3134 spin_unlock_irqrestore(&info->lock,flags);
3135 }
3136 exit:
3137 if ( rc == 0 )
3138 PUT_USER(rc, events, mask_ptr);
3139
3140 return rc;
3141 }
3142
3143 static int modem_input_wait(SLMP_INFO *info,int arg)
3144 {
3145 unsigned long flags;
3146 int rc;
3147 struct mgsl_icount cprev, cnow;
3148 DECLARE_WAITQUEUE(wait, current);
3149
3150 /* save current irq counts */
3151 spin_lock_irqsave(&info->lock,flags);
3152 cprev = info->icount;
3153 add_wait_queue(&info->status_event_wait_q, &wait);
3154 set_current_state(TASK_INTERRUPTIBLE);
3155 spin_unlock_irqrestore(&info->lock,flags);
3156
3157 for(;;) {
3158 schedule();
3159 if (signal_pending(current)) {
3160 rc = -ERESTARTSYS;
3161 break;
3162 }
3163
3164 /* get new irq counts */
3165 spin_lock_irqsave(&info->lock,flags);
3166 cnow = info->icount;
3167 set_current_state(TASK_INTERRUPTIBLE);
3168 spin_unlock_irqrestore(&info->lock,flags);
3169
3170 /* if no change, wait aborted for some reason */
3171 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3172 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3173 rc = -EIO;
3174 break;
3175 }
3176
3177 /* check for change in caller specified modem input */
3178 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3179 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3180 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3181 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3182 rc = 0;
3183 break;
3184 }
3185
3186 cprev = cnow;
3187 }
3188 remove_wait_queue(&info->status_event_wait_q, &wait);
3189 set_current_state(TASK_RUNNING);
3190 return rc;
3191 }
3192
3193 /* return the state of the serial control and status signals
3194 */
3195 static int tiocmget(struct tty_struct *tty)
3196 {
3197 SLMP_INFO *info = tty->driver_data;
3198 unsigned int result;
3199 unsigned long flags;
3200
3201 spin_lock_irqsave(&info->lock,flags);
3202 get_signals(info);
3203 spin_unlock_irqrestore(&info->lock,flags);
3204
3205 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
3206 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
3207 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
3208 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) |
3209 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
3210 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
3211
3212 if (debug_level >= DEBUG_LEVEL_INFO)
3213 printk("%s(%d):%s tiocmget() value=%08X\n",
3214 __FILE__,__LINE__, info->device_name, result );
3215 return result;
3216 }
3217
3218 /* set modem control signals (DTR/RTS)
3219 */
3220 static int tiocmset(struct tty_struct *tty,
3221 unsigned int set, unsigned int clear)
3222 {
3223 SLMP_INFO *info = tty->driver_data;
3224 unsigned long flags;
3225
3226 if (debug_level >= DEBUG_LEVEL_INFO)
3227 printk("%s(%d):%s tiocmset(%x,%x)\n",
3228 __FILE__,__LINE__,info->device_name, set, clear);
3229
3230 if (set & TIOCM_RTS)
3231 info->serial_signals |= SerialSignal_RTS;
3232 if (set & TIOCM_DTR)
3233 info->serial_signals |= SerialSignal_DTR;
3234 if (clear & TIOCM_RTS)
3235 info->serial_signals &= ~SerialSignal_RTS;
3236 if (clear & TIOCM_DTR)
3237 info->serial_signals &= ~SerialSignal_DTR;
3238
3239 spin_lock_irqsave(&info->lock,flags);
3240 set_signals(info);
3241 spin_unlock_irqrestore(&info->lock,flags);
3242
3243 return 0;
3244 }
3245
3246 static int carrier_raised(struct tty_port *port)
3247 {
3248 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3249 unsigned long flags;
3250
3251 spin_lock_irqsave(&info->lock,flags);
3252 get_signals(info);
3253 spin_unlock_irqrestore(&info->lock,flags);
3254
3255 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3256 }
3257
3258 static void dtr_rts(struct tty_port *port, int on)
3259 {
3260 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3261 unsigned long flags;
3262
3263 spin_lock_irqsave(&info->lock,flags);
3264 if (on)
3265 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3266 else
3267 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3268 set_signals(info);
3269 spin_unlock_irqrestore(&info->lock,flags);
3270 }
3271
3272 /* Block the current process until the specified port is ready to open.
3273 */
3274 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3275 SLMP_INFO *info)
3276 {
3277 DECLARE_WAITQUEUE(wait, current);
3278 int retval;
3279 bool do_clocal = false;
3280 unsigned long flags;
3281 int cd;
3282 struct tty_port *port = &info->port;
3283
3284 if (debug_level >= DEBUG_LEVEL_INFO)
3285 printk("%s(%d):%s block_til_ready()\n",
3286 __FILE__,__LINE__, tty->driver->name );
3287
3288 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3289 /* nonblock mode is set or port is not enabled */
3290 /* just verify that callout device is not active */
3291 port->flags |= ASYNC_NORMAL_ACTIVE;
3292 return 0;
3293 }
3294
3295 if (C_CLOCAL(tty))
3296 do_clocal = true;
3297
3298 /* Wait for carrier detect and the line to become
3299 * free (i.e., not in use by the callout). While we are in
3300 * this loop, port->count is dropped by one, so that
3301 * close() knows when to free things. We restore it upon
3302 * exit, either normal or abnormal.
3303 */
3304
3305 retval = 0;
3306 add_wait_queue(&port->open_wait, &wait);
3307
3308 if (debug_level >= DEBUG_LEVEL_INFO)
3309 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3310 __FILE__,__LINE__, tty->driver->name, port->count );
3311
3312 spin_lock_irqsave(&info->lock, flags);
3313 port->count--;
3314 spin_unlock_irqrestore(&info->lock, flags);
3315 port->blocked_open++;
3316
3317 while (1) {
3318 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3319 tty_port_raise_dtr_rts(port);
3320
3321 set_current_state(TASK_INTERRUPTIBLE);
3322
3323 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3324 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3325 -EAGAIN : -ERESTARTSYS;
3326 break;
3327 }
3328
3329 cd = tty_port_carrier_raised(port);
3330 if (do_clocal || cd)
3331 break;
3332
3333 if (signal_pending(current)) {
3334 retval = -ERESTARTSYS;
3335 break;
3336 }
3337
3338 if (debug_level >= DEBUG_LEVEL_INFO)
3339 printk("%s(%d):%s block_til_ready() count=%d\n",
3340 __FILE__,__LINE__, tty->driver->name, port->count );
3341
3342 tty_unlock(tty);
3343 schedule();
3344 tty_lock(tty);
3345 }
3346
3347 set_current_state(TASK_RUNNING);
3348 remove_wait_queue(&port->open_wait, &wait);
3349 if (!tty_hung_up_p(filp))
3350 port->count++;
3351 port->blocked_open--;
3352
3353 if (debug_level >= DEBUG_LEVEL_INFO)
3354 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3355 __FILE__,__LINE__, tty->driver->name, port->count );
3356
3357 if (!retval)
3358 port->flags |= ASYNC_NORMAL_ACTIVE;
3359
3360 return retval;
3361 }
3362
3363 static int alloc_dma_bufs(SLMP_INFO *info)
3364 {
3365 unsigned short BuffersPerFrame;
3366 unsigned short BufferCount;
3367
3368 // Force allocation to start at 64K boundary for each port.
3369 // This is necessary because *all* buffer descriptors for a port
3370 // *must* be in the same 64K block. All descriptors on a port
3371 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3372 // into the CBP register.
3373 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3374
3375 /* Calculate the number of DMA buffers necessary to hold the */
3376 /* largest allowable frame size. Note: If the max frame size is */
3377 /* not an even multiple of the DMA buffer size then we need to */
3378 /* round the buffer count per frame up one. */
3379
3380 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3381 if ( info->max_frame_size % SCABUFSIZE )
3382 BuffersPerFrame++;
3383
3384 /* calculate total number of data buffers (SCABUFSIZE) possible
3385 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3386 * for the descriptor list (BUFFERLISTSIZE).
3387 */
3388 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3389
3390 /* limit number of buffers to maximum amount of descriptors */
3391 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3392 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3393
3394 /* use enough buffers to transmit one max size frame */
3395 info->tx_buf_count = BuffersPerFrame + 1;
3396
3397 /* never use more than half the available buffers for transmit */
3398 if (info->tx_buf_count > (BufferCount/2))
3399 info->tx_buf_count = BufferCount/2;
3400
3401 if (info->tx_buf_count > SCAMAXDESC)
3402 info->tx_buf_count = SCAMAXDESC;
3403
3404 /* use remaining buffers for receive */
3405 info->rx_buf_count = BufferCount - info->tx_buf_count;
3406
3407 if (info->rx_buf_count > SCAMAXDESC)
3408 info->rx_buf_count = SCAMAXDESC;
3409
3410 if ( debug_level >= DEBUG_LEVEL_INFO )
3411 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3412 __FILE__,__LINE__, info->device_name,
3413 info->tx_buf_count,info->rx_buf_count);
3414
3415 if ( alloc_buf_list( info ) < 0 ||
3416 alloc_frame_bufs(info,
3417 info->rx_buf_list,
3418 info->rx_buf_list_ex,
3419 info->rx_buf_count) < 0 ||
3420 alloc_frame_bufs(info,
3421 info->tx_buf_list,
3422 info->tx_buf_list_ex,
3423 info->tx_buf_count) < 0 ||
3424 alloc_tmp_rx_buf(info) < 0 ) {
3425 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3426 __FILE__,__LINE__, info->device_name);
3427 return -ENOMEM;
3428 }
3429
3430 rx_reset_buffers( info );
3431
3432 return 0;
3433 }
3434
3435 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3436 */
3437 static int alloc_buf_list(SLMP_INFO *info)
3438 {
3439 unsigned int i;
3440
3441 /* build list in adapter shared memory */
3442 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3443 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3444 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3445
3446 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3447
3448 /* Save virtual address pointers to the receive and */
3449 /* transmit buffer lists. (Receive 1st). These pointers will */
3450 /* be used by the processor to access the lists. */
3451 info->rx_buf_list = (SCADESC *)info->buffer_list;
3452
3453 info->tx_buf_list = (SCADESC *)info->buffer_list;
3454 info->tx_buf_list += info->rx_buf_count;
3455
3456 /* Build links for circular buffer entry lists (tx and rx)
3457 *
3458 * Note: links are physical addresses read by the SCA device
3459 * to determine the next buffer entry to use.
3460 */
3461
3462 for ( i = 0; i < info->rx_buf_count; i++ ) {
3463 /* calculate and store physical address of this buffer entry */
3464 info->rx_buf_list_ex[i].phys_entry =
3465 info->buffer_list_phys + (i * SCABUFSIZE);
3466
3467 /* calculate and store physical address of */
3468 /* next entry in cirular list of entries */
3469 info->rx_buf_list[i].next = info->buffer_list_phys;
3470 if ( i < info->rx_buf_count - 1 )
3471 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3472
3473 info->rx_buf_list[i].length = SCABUFSIZE;
3474 }
3475
3476 for ( i = 0; i < info->tx_buf_count; i++ ) {
3477 /* calculate and store physical address of this buffer entry */
3478 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3479 ((info->rx_buf_count + i) * sizeof(SCADESC));
3480
3481 /* calculate and store physical address of */
3482 /* next entry in cirular list of entries */
3483
3484 info->tx_buf_list[i].next = info->buffer_list_phys +
3485 info->rx_buf_count * sizeof(SCADESC);
3486
3487 if ( i < info->tx_buf_count - 1 )
3488 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3489 }
3490
3491 return 0;
3492 }
3493
3494 /* Allocate the frame DMA buffers used by the specified buffer list.
3495 */
3496 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3497 {
3498 int i;
3499 unsigned long phys_addr;
3500
3501 for ( i = 0; i < count; i++ ) {
3502 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3503 phys_addr = info->port_array[0]->last_mem_alloc;
3504 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3505
3506 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3507 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3508 }
3509
3510 return 0;
3511 }
3512
3513 static void free_dma_bufs(SLMP_INFO *info)
3514 {
3515 info->buffer_list = NULL;
3516 info->rx_buf_list = NULL;
3517 info->tx_buf_list = NULL;
3518 }
3519
3520 /* allocate buffer large enough to hold max_frame_size.
3521 * This buffer is used to pass an assembled frame to the line discipline.
3522 */
3523 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3524 {
3525 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3526 if (info->tmp_rx_buf == NULL)
3527 return -ENOMEM;
3528 /* unused flag buffer to satisfy receive_buf calling interface */
3529 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3530 if (!info->flag_buf) {
3531 kfree(info->tmp_rx_buf);
3532 info->tmp_rx_buf = NULL;
3533 return -ENOMEM;
3534 }
3535 return 0;
3536 }
3537
3538 static void free_tmp_rx_buf(SLMP_INFO *info)
3539 {
3540 kfree(info->tmp_rx_buf);
3541 info->tmp_rx_buf = NULL;
3542 kfree(info->flag_buf);
3543 info->flag_buf = NULL;
3544 }
3545
3546 static int claim_resources(SLMP_INFO *info)
3547 {
3548 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3549 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3550 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3551 info->init_error = DiagStatus_AddressConflict;
3552 goto errout;
3553 }
3554 else
3555 info->shared_mem_requested = true;
3556
3557 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3558 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3559 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3560 info->init_error = DiagStatus_AddressConflict;
3561 goto errout;
3562 }
3563 else
3564 info->lcr_mem_requested = true;
3565
3566 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3567 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3568 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3569 info->init_error = DiagStatus_AddressConflict;
3570 goto errout;
3571 }
3572 else
3573 info->sca_base_requested = true;
3574
3575 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3576 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3577 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3578 info->init_error = DiagStatus_AddressConflict;
3579 goto errout;
3580 }
3581 else
3582 info->sca_statctrl_requested = true;
3583
3584 info->memory_base = ioremap_nocache(info->phys_memory_base,
3585 SCA_MEM_SIZE);
3586 if (!info->memory_base) {
3587 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3588 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3589 info->init_error = DiagStatus_CantAssignPciResources;
3590 goto errout;
3591 }
3592
3593 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3594 if (!info->lcr_base) {
3595 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3596 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3597 info->init_error = DiagStatus_CantAssignPciResources;
3598 goto errout;
3599 }
3600 info->lcr_base += info->lcr_offset;
3601
3602 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3603 if (!info->sca_base) {
3604 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3605 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3606 info->init_error = DiagStatus_CantAssignPciResources;
3607 goto errout;
3608 }
3609 info->sca_base += info->sca_offset;
3610
3611 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3612 PAGE_SIZE);
3613 if (!info->statctrl_base) {
3614 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3615 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3616 info->init_error = DiagStatus_CantAssignPciResources;
3617 goto errout;
3618 }
3619 info->statctrl_base += info->statctrl_offset;
3620
3621 if ( !memory_test(info) ) {
3622 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3623 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3624 info->init_error = DiagStatus_MemoryError;
3625 goto errout;
3626 }
3627
3628 return 0;
3629
3630 errout:
3631 release_resources( info );
3632 return -ENODEV;
3633 }
3634
3635 static void release_resources(SLMP_INFO *info)
3636 {
3637 if ( debug_level >= DEBUG_LEVEL_INFO )
3638 printk( "%s(%d):%s release_resources() entry\n",
3639 __FILE__,__LINE__,info->device_name );
3640
3641 if ( info->irq_requested ) {
3642 free_irq(info->irq_level, info);
3643 info->irq_requested = false;
3644 }
3645
3646 if ( info->shared_mem_requested ) {
3647 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3648 info->shared_mem_requested = false;
3649 }
3650 if ( info->lcr_mem_requested ) {
3651 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3652 info->lcr_mem_requested = false;
3653 }
3654 if ( info->sca_base_requested ) {
3655 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3656 info->sca_base_requested = false;
3657 }
3658 if ( info->sca_statctrl_requested ) {
3659 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3660 info->sca_statctrl_requested = false;
3661 }
3662
3663 if (info->memory_base){
3664 iounmap(info->memory_base);
3665 info->memory_base = NULL;
3666 }
3667
3668 if (info->sca_base) {
3669 iounmap(info->sca_base - info->sca_offset);
3670 info->sca_base=NULL;
3671 }
3672
3673 if (info->statctrl_base) {
3674 iounmap(info->statctrl_base - info->statctrl_offset);
3675 info->statctrl_base=NULL;
3676 }
3677
3678 if (info->lcr_base){
3679 iounmap(info->lcr_base - info->lcr_offset);
3680 info->lcr_base = NULL;
3681 }
3682
3683 if ( debug_level >= DEBUG_LEVEL_INFO )
3684 printk( "%s(%d):%s release_resources() exit\n",
3685 __FILE__,__LINE__,info->device_name );
3686 }
3687
3688 /* Add the specified device instance data structure to the
3689 * global linked list of devices and increment the device count.
3690 */
3691 static int add_device(SLMP_INFO *info)
3692 {
3693 info->next_device = NULL;
3694 info->line = synclinkmp_device_count;
3695 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3696
3697 if (info->line < MAX_DEVICES) {
3698 if (maxframe[info->line])
3699 info->max_frame_size = maxframe[info->line];
3700 }
3701
3702 synclinkmp_device_count++;
3703
3704 if ( !synclinkmp_device_list )
3705 synclinkmp_device_list = info;
3706 else {
3707 SLMP_INFO *current_dev = synclinkmp_device_list;
3708 while( current_dev->next_device )
3709 current_dev = current_dev->next_device;
3710 current_dev->next_device = info;
3711 }
3712
3713 if ( info->max_frame_size < 4096 )
3714 info->max_frame_size = 4096;
3715 else if ( info->max_frame_size > 65535 )
3716 info->max_frame_size = 65535;
3717
3718 printk( "SyncLink MultiPort %s: "
3719 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3720 info->device_name,
3721 info->phys_sca_base,
3722 info->phys_memory_base,
3723 info->phys_statctrl_base,
3724 info->phys_lcr_base,
3725 info->irq_level,
3726 info->max_frame_size );
3727
3728 #if SYNCLINK_GENERIC_HDLC
3729 return hdlcdev_init(info);
3730 #else
3731 return 0;
3732 #endif
3733 }
3734
3735 static const struct tty_port_operations port_ops = {
3736 .carrier_raised = carrier_raised,
3737 .dtr_rts = dtr_rts,
3738 };
3739
3740 /* Allocate and initialize a device instance structure
3741 *
3742 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3743 */
3744 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3745 {
3746 SLMP_INFO *info;
3747
3748 info = kzalloc(sizeof(SLMP_INFO),
3749 GFP_KERNEL);
3750
3751 if (!info) {
3752 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3753 __FILE__,__LINE__, adapter_num, port_num);
3754 } else {
3755 tty_port_init(&info->port);
3756 info->port.ops = &port_ops;
3757 info->magic = MGSL_MAGIC;
3758 INIT_WORK(&info->task, bh_handler);
3759 info->max_frame_size = 4096;
3760 info->port.close_delay = 5*HZ/10;
3761 info->port.closing_wait = 30*HZ;
3762 init_waitqueue_head(&info->status_event_wait_q);
3763 init_waitqueue_head(&info->event_wait_q);
3764 spin_lock_init(&info->netlock);
3765 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3766 info->idle_mode = HDLC_TXIDLE_FLAGS;
3767 info->adapter_num = adapter_num;
3768 info->port_num = port_num;
3769
3770 /* Copy configuration info to device instance data */
3771 info->irq_level = pdev->irq;
3772 info->phys_lcr_base = pci_resource_start(pdev,0);
3773 info->phys_sca_base = pci_resource_start(pdev,2);
3774 info->phys_memory_base = pci_resource_start(pdev,3);
3775 info->phys_statctrl_base = pci_resource_start(pdev,4);
3776
3777 /* Because veremap only works on page boundaries we must map
3778 * a larger area than is actually implemented for the LCR
3779 * memory range. We map a full page starting at the page boundary.
3780 */
3781 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3782 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3783
3784 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3785 info->phys_sca_base &= ~(PAGE_SIZE-1);
3786
3787 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3788 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3789
3790 info->bus_type = MGSL_BUS_TYPE_PCI;
3791 info->irq_flags = IRQF_SHARED;
3792
3793 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3794 setup_timer(&info->status_timer, status_timeout,
3795 (unsigned long)info);
3796
3797 /* Store the PCI9050 misc control register value because a flaw
3798 * in the PCI9050 prevents LCR registers from being read if
3799 * BIOS assigns an LCR base address with bit 7 set.
3800 *
3801 * Only the misc control register is accessed for which only
3802 * write access is needed, so set an initial value and change
3803 * bits to the device instance data as we write the value
3804 * to the actual misc control register.
3805 */
3806 info->misc_ctrl_value = 0x087e4546;
3807
3808 /* initial port state is unknown - if startup errors
3809 * occur, init_error will be set to indicate the
3810 * problem. Once the port is fully initialized,
3811 * this value will be set to 0 to indicate the
3812 * port is available.
3813 */
3814 info->init_error = -1;
3815 }
3816
3817 return info;
3818 }
3819
3820 static int device_init(int adapter_num, struct pci_dev *pdev)
3821 {
3822 SLMP_INFO *port_array[SCA_MAX_PORTS];
3823 int port, rc;
3824
3825 /* allocate device instances for up to SCA_MAX_PORTS devices */
3826 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3827 port_array[port] = alloc_dev(adapter_num,port,pdev);
3828 if( port_array[port] == NULL ) {
3829 for (--port; port >= 0; --port) {
3830 tty_port_destroy(&port_array[port]->port);
3831 kfree(port_array[port]);
3832 }
3833 return -ENOMEM;
3834 }
3835 }
3836
3837 /* give copy of port_array to all ports and add to device list */
3838 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3839 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3840 rc = add_device( port_array[port] );
3841 if (rc)
3842 goto err_add;
3843 spin_lock_init(&port_array[port]->lock);
3844 }
3845
3846 /* Allocate and claim adapter resources */
3847 if ( !claim_resources(port_array[0]) ) {
3848
3849 alloc_dma_bufs(port_array[0]);
3850
3851 /* copy resource information from first port to others */
3852 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3853 port_array[port]->lock = port_array[0]->lock;
3854 port_array[port]->irq_level = port_array[0]->irq_level;
3855 port_array[port]->memory_base = port_array[0]->memory_base;
3856 port_array[port]->sca_base = port_array[0]->sca_base;
3857 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3858 port_array[port]->lcr_base = port_array[0]->lcr_base;
3859 alloc_dma_bufs(port_array[port]);
3860 }
3861
3862 rc = request_irq(port_array[0]->irq_level,
3863 synclinkmp_interrupt,
3864 port_array[0]->irq_flags,
3865 port_array[0]->device_name,
3866 port_array[0]);
3867 if ( rc ) {
3868 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3869 __FILE__,__LINE__,
3870 port_array[0]->device_name,
3871 port_array[0]->irq_level );
3872 goto err_irq;
3873 }
3874 port_array[0]->irq_requested = true;
3875 adapter_test(port_array[0]);
3876 }
3877 return 0;
3878 err_irq:
3879 release_resources( port_array[0] );
3880 err_add:
3881 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3882 tty_port_destroy(&port_array[port]->port);
3883 kfree(port_array[port]);
3884 }
3885 return rc;
3886 }
3887
3888 static const struct tty_operations ops = {
3889 .install = install,
3890 .open = open,
3891 .close = close,
3892 .write = write,
3893 .put_char = put_char,
3894 .flush_chars = flush_chars,
3895 .write_room = write_room,
3896 .chars_in_buffer = chars_in_buffer,
3897 .flush_buffer = flush_buffer,
3898 .ioctl = ioctl,
3899 .throttle = throttle,
3900 .unthrottle = unthrottle,
3901 .send_xchar = send_xchar,
3902 .break_ctl = set_break,
3903 .wait_until_sent = wait_until_sent,
3904 .set_termios = set_termios,
3905 .stop = tx_hold,
3906 .start = tx_release,
3907 .hangup = hangup,
3908 .tiocmget = tiocmget,
3909 .tiocmset = tiocmset,
3910 .get_icount = get_icount,
3911 .proc_fops = &synclinkmp_proc_fops,
3912 };
3913
3914
3915 static void synclinkmp_cleanup(void)
3916 {
3917 int rc;
3918 SLMP_INFO *info;
3919 SLMP_INFO *tmp;
3920
3921 printk("Unloading %s %s\n", driver_name, driver_version);
3922
3923 if (serial_driver) {
3924 rc = tty_unregister_driver(serial_driver);
3925 if (rc)
3926 printk("%s(%d) failed to unregister tty driver err=%d\n",
3927 __FILE__,__LINE__,rc);
3928 put_tty_driver(serial_driver);
3929 }
3930
3931 /* reset devices */
3932 info = synclinkmp_device_list;
3933 while(info) {
3934 reset_port(info);
3935 info = info->next_device;
3936 }
3937
3938 /* release devices */
3939 info = synclinkmp_device_list;
3940 while(info) {
3941 #if SYNCLINK_GENERIC_HDLC
3942 hdlcdev_exit(info);
3943 #endif
3944 free_dma_bufs(info);
3945 free_tmp_rx_buf(info);
3946 if ( info->port_num == 0 ) {
3947 if (info->sca_base)
3948 write_reg(info, LPR, 1); /* set low power mode */
3949 release_resources(info);
3950 }
3951 tmp = info;
3952 info = info->next_device;
3953 tty_port_destroy(&tmp->port);
3954 kfree(tmp);
3955 }
3956
3957 pci_unregister_driver(&synclinkmp_pci_driver);
3958 }
3959
3960 /* Driver initialization entry point.
3961 */
3962
3963 static int __init synclinkmp_init(void)
3964 {
3965 int rc;
3966
3967 if (break_on_load) {
3968 synclinkmp_get_text_ptr();
3969 BREAKPOINT();
3970 }
3971
3972 printk("%s %s\n", driver_name, driver_version);
3973
3974 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3975 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3976 return rc;
3977 }
3978
3979 serial_driver = alloc_tty_driver(128);
3980 if (!serial_driver) {
3981 rc = -ENOMEM;
3982 goto error;
3983 }
3984
3985 /* Initialize the tty_driver structure */
3986
3987 serial_driver->driver_name = "synclinkmp";
3988 serial_driver->name = "ttySLM";
3989 serial_driver->major = ttymajor;
3990 serial_driver->minor_start = 64;
3991 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3992 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3993 serial_driver->init_termios = tty_std_termios;
3994 serial_driver->init_termios.c_cflag =
3995 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3996 serial_driver->init_termios.c_ispeed = 9600;
3997 serial_driver->init_termios.c_ospeed = 9600;
3998 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3999 tty_set_operations(serial_driver, &ops);
4000 if ((rc = tty_register_driver(serial_driver)) < 0) {
4001 printk("%s(%d):Couldn't register serial driver\n",
4002 __FILE__,__LINE__);
4003 put_tty_driver(serial_driver);
4004 serial_driver = NULL;
4005 goto error;
4006 }
4007
4008 printk("%s %s, tty major#%d\n",
4009 driver_name, driver_version,
4010 serial_driver->major);
4011
4012 return 0;
4013
4014 error:
4015 synclinkmp_cleanup();
4016 return rc;
4017 }
4018
4019 static void __exit synclinkmp_exit(void)
4020 {
4021 synclinkmp_cleanup();
4022 }
4023
4024 module_init(synclinkmp_init);
4025 module_exit(synclinkmp_exit);
4026
4027 /* Set the port for internal loopback mode.
4028 * The TxCLK and RxCLK signals are generated from the BRG and
4029 * the TxD is looped back to the RxD internally.
4030 */
4031 static void enable_loopback(SLMP_INFO *info, int enable)
4032 {
4033 if (enable) {
4034 /* MD2 (Mode Register 2)
4035 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4036 */
4037 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4038
4039 /* degate external TxC clock source */
4040 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4041 write_control_reg(info);
4042
4043 /* RXS/TXS (Rx/Tx clock source)
4044 * 07 Reserved, must be 0
4045 * 06..04 Clock Source, 100=BRG
4046 * 03..00 Clock Divisor, 0000=1
4047 */
4048 write_reg(info, RXS, 0x40);
4049 write_reg(info, TXS, 0x40);
4050
4051 } else {
4052 /* MD2 (Mode Register 2)
4053 * 01..00 CNCT<1..0> Channel connection, 0=normal
4054 */
4055 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4056
4057 /* RXS/TXS (Rx/Tx clock source)
4058 * 07 Reserved, must be 0
4059 * 06..04 Clock Source, 000=RxC/TxC Pin
4060 * 03..00 Clock Divisor, 0000=1
4061 */
4062 write_reg(info, RXS, 0x00);
4063 write_reg(info, TXS, 0x00);
4064 }
4065
4066 /* set LinkSpeed if available, otherwise default to 2Mbps */
4067 if (info->params.clock_speed)
4068 set_rate(info, info->params.clock_speed);
4069 else
4070 set_rate(info, 3686400);
4071 }
4072
4073 /* Set the baud rate register to the desired speed
4074 *
4075 * data_rate data rate of clock in bits per second
4076 * A data rate of 0 disables the AUX clock.
4077 */
4078 static void set_rate( SLMP_INFO *info, u32 data_rate )
4079 {
4080 u32 TMCValue;
4081 unsigned char BRValue;
4082 u32 Divisor=0;
4083
4084 /* fBRG = fCLK/(TMC * 2^BR)
4085 */
4086 if (data_rate != 0) {
4087 Divisor = 14745600/data_rate;
4088 if (!Divisor)
4089 Divisor = 1;
4090
4091 TMCValue = Divisor;
4092
4093 BRValue = 0;
4094 if (TMCValue != 1 && TMCValue != 2) {
4095 /* BRValue of 0 provides 50/50 duty cycle *only* when
4096 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4097 * 50/50 duty cycle.
4098 */
4099 BRValue = 1;
4100 TMCValue >>= 1;
4101 }
4102
4103 /* while TMCValue is too big for TMC register, divide
4104 * by 2 and increment BR exponent.
4105 */
4106 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4107 TMCValue >>= 1;
4108
4109 write_reg(info, TXS,
4110 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4111 write_reg(info, RXS,
4112 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4113 write_reg(info, TMC, (unsigned char)TMCValue);
4114 }
4115 else {
4116 write_reg(info, TXS,0);
4117 write_reg(info, RXS,0);
4118 write_reg(info, TMC, 0);
4119 }
4120 }
4121
4122 /* Disable receiver
4123 */
4124 static void rx_stop(SLMP_INFO *info)
4125 {
4126 if (debug_level >= DEBUG_LEVEL_ISR)
4127 printk("%s(%d):%s rx_stop()\n",
4128 __FILE__,__LINE__, info->device_name );
4129
4130 write_reg(info, CMD, RXRESET);
4131
4132 info->ie0_value &= ~RXRDYE;
4133 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4134
4135 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4136 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4137 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4138
4139 info->rx_enabled = false;
4140 info->rx_overflow = false;
4141 }
4142
4143 /* enable the receiver
4144 */
4145 static void rx_start(SLMP_INFO *info)
4146 {
4147 int i;
4148
4149 if (debug_level >= DEBUG_LEVEL_ISR)
4150 printk("%s(%d):%s rx_start()\n",
4151 __FILE__,__LINE__, info->device_name );
4152
4153 write_reg(info, CMD, RXRESET);
4154
4155 if ( info->params.mode == MGSL_MODE_HDLC ) {
4156 /* HDLC, disabe IRQ on rxdata */
4157 info->ie0_value &= ~RXRDYE;
4158 write_reg(info, IE0, info->ie0_value);
4159
4160 /* Reset all Rx DMA buffers and program rx dma */
4161 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4162 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4163
4164 for (i = 0; i < info->rx_buf_count; i++) {
4165 info->rx_buf_list[i].status = 0xff;
4166
4167 // throttle to 4 shared memory writes at a time to prevent
4168 // hogging local bus (keep latency time for DMA requests low).
4169 if (!(i % 4))
4170 read_status_reg(info);
4171 }
4172 info->current_rx_buf = 0;
4173
4174 /* set current/1st descriptor address */
4175 write_reg16(info, RXDMA + CDA,
4176 info->rx_buf_list_ex[0].phys_entry);
4177
4178 /* set new last rx descriptor address */
4179 write_reg16(info, RXDMA + EDA,
4180 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4181
4182 /* set buffer length (shared by all rx dma data buffers) */
4183 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4184
4185 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4186 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4187 } else {
4188 /* async, enable IRQ on rxdata */
4189 info->ie0_value |= RXRDYE;
4190 write_reg(info, IE0, info->ie0_value);
4191 }
4192
4193 write_reg(info, CMD, RXENABLE);
4194
4195 info->rx_overflow = false;
4196 info->rx_enabled = true;
4197 }
4198
4199 /* Enable the transmitter and send a transmit frame if
4200 * one is loaded in the DMA buffers.
4201 */
4202 static void tx_start(SLMP_INFO *info)
4203 {
4204 if (debug_level >= DEBUG_LEVEL_ISR)
4205 printk("%s(%d):%s tx_start() tx_count=%d\n",
4206 __FILE__,__LINE__, info->device_name,info->tx_count );
4207
4208 if (!info->tx_enabled ) {
4209 write_reg(info, CMD, TXRESET);
4210 write_reg(info, CMD, TXENABLE);
4211 info->tx_enabled = true;
4212 }
4213
4214 if ( info->tx_count ) {
4215
4216 /* If auto RTS enabled and RTS is inactive, then assert */
4217 /* RTS and set a flag indicating that the driver should */
4218 /* negate RTS when the transmission completes. */
4219
4220 info->drop_rts_on_tx_done = false;
4221
4222 if (info->params.mode != MGSL_MODE_ASYNC) {
4223
4224 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4225 get_signals( info );
4226 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4227 info->serial_signals |= SerialSignal_RTS;
4228 set_signals( info );
4229 info->drop_rts_on_tx_done = true;
4230 }
4231 }
4232
4233 write_reg16(info, TRC0,
4234 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4235
4236 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4237 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4238
4239 /* set TX CDA (current descriptor address) */
4240 write_reg16(info, TXDMA + CDA,
4241 info->tx_buf_list_ex[0].phys_entry);
4242
4243 /* set TX EDA (last descriptor address) */
4244 write_reg16(info, TXDMA + EDA,
4245 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4246
4247 /* enable underrun IRQ */
4248 info->ie1_value &= ~IDLE;
4249 info->ie1_value |= UDRN;
4250 write_reg(info, IE1, info->ie1_value);
4251 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4252
4253 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4254 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4255
4256 mod_timer(&info->tx_timer, jiffies +
4257 msecs_to_jiffies(5000));
4258 }
4259 else {
4260 tx_load_fifo(info);
4261 /* async, enable IRQ on txdata */
4262 info->ie0_value |= TXRDYE;
4263 write_reg(info, IE0, info->ie0_value);
4264 }
4265
4266 info->tx_active = true;
4267 }
4268 }
4269
4270 /* stop the transmitter and DMA
4271 */
4272 static void tx_stop( SLMP_INFO *info )
4273 {
4274 if (debug_level >= DEBUG_LEVEL_ISR)
4275 printk("%s(%d):%s tx_stop()\n",
4276 __FILE__,__LINE__, info->device_name );
4277
4278 del_timer(&info->tx_timer);
4279
4280 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4281 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4282
4283 write_reg(info, CMD, TXRESET);
4284
4285 info->ie1_value &= ~(UDRN + IDLE);
4286 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4287 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4288
4289 info->ie0_value &= ~TXRDYE;
4290 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4291
4292 info->tx_enabled = false;
4293 info->tx_active = false;
4294 }
4295
4296 /* Fill the transmit FIFO until the FIFO is full or
4297 * there is no more data to load.
4298 */
4299 static void tx_load_fifo(SLMP_INFO *info)
4300 {
4301 u8 TwoBytes[2];
4302
4303 /* do nothing is now tx data available and no XON/XOFF pending */
4304
4305 if ( !info->tx_count && !info->x_char )
4306 return;
4307
4308 /* load the Transmit FIFO until FIFOs full or all data sent */
4309
4310 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4311
4312 /* there is more space in the transmit FIFO and */
4313 /* there is more data in transmit buffer */
4314
4315 if ( (info->tx_count > 1) && !info->x_char ) {
4316 /* write 16-bits */
4317 TwoBytes[0] = info->tx_buf[info->tx_get++];
4318 if (info->tx_get >= info->max_frame_size)
4319 info->tx_get -= info->max_frame_size;
4320 TwoBytes[1] = info->tx_buf[info->tx_get++];
4321 if (info->tx_get >= info->max_frame_size)
4322 info->tx_get -= info->max_frame_size;
4323
4324 write_reg16(info, TRB, *((u16 *)TwoBytes));
4325
4326 info->tx_count -= 2;
4327 info->icount.tx += 2;
4328 } else {
4329 /* only 1 byte left to transmit or 1 FIFO slot left */
4330
4331 if (info->x_char) {
4332 /* transmit pending high priority char */
4333 write_reg(info, TRB, info->x_char);
4334 info->x_char = 0;
4335 } else {
4336 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4337 if (info->tx_get >= info->max_frame_size)
4338 info->tx_get -= info->max_frame_size;
4339 info->tx_count--;
4340 }
4341 info->icount.tx++;
4342 }
4343 }
4344 }
4345
4346 /* Reset a port to a known state
4347 */
4348 static void reset_port(SLMP_INFO *info)
4349 {
4350 if (info->sca_base) {
4351
4352 tx_stop(info);
4353 rx_stop(info);
4354
4355 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4356 set_signals(info);
4357
4358 /* disable all port interrupts */
4359 info->ie0_value = 0;
4360 info->ie1_value = 0;
4361 info->ie2_value = 0;
4362 write_reg(info, IE0, info->ie0_value);
4363 write_reg(info, IE1, info->ie1_value);
4364 write_reg(info, IE2, info->ie2_value);
4365
4366 write_reg(info, CMD, CHRESET);
4367 }
4368 }
4369
4370 /* Reset all the ports to a known state.
4371 */
4372 static void reset_adapter(SLMP_INFO *info)
4373 {
4374 int i;
4375
4376 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4377 if (info->port_array[i])
4378 reset_port(info->port_array[i]);
4379 }
4380 }
4381
4382 /* Program port for asynchronous communications.
4383 */
4384 static void async_mode(SLMP_INFO *info)
4385 {
4386
4387 unsigned char RegValue;
4388
4389 tx_stop(info);
4390 rx_stop(info);
4391
4392 /* MD0, Mode Register 0
4393 *
4394 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4395 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4396 * 03 Reserved, must be 0
4397 * 02 CRCCC, CRC Calculation, 0=disabled
4398 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4399 *
4400 * 0000 0000
4401 */
4402 RegValue = 0x00;
4403 if (info->params.stop_bits != 1)
4404 RegValue |= BIT1;
4405 write_reg(info, MD0, RegValue);
4406
4407 /* MD1, Mode Register 1
4408 *
4409 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4410 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4411 * 03..02 RXCHR<1..0>, rx char size
4412 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4413 *
4414 * 0100 0000
4415 */
4416 RegValue = 0x40;
4417 switch (info->params.data_bits) {
4418 case 7: RegValue |= BIT4 + BIT2; break;
4419 case 6: RegValue |= BIT5 + BIT3; break;
4420 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4421 }
4422 if (info->params.parity != ASYNC_PARITY_NONE) {
4423 RegValue |= BIT1;
4424 if (info->params.parity == ASYNC_PARITY_ODD)
4425 RegValue |= BIT0;
4426 }
4427 write_reg(info, MD1, RegValue);
4428
4429 /* MD2, Mode Register 2
4430 *
4431 * 07..02 Reserved, must be 0
4432 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4433 *
4434 * 0000 0000
4435 */
4436 RegValue = 0x00;
4437 if (info->params.loopback)
4438 RegValue |= (BIT1 + BIT0);
4439 write_reg(info, MD2, RegValue);
4440
4441 /* RXS, Receive clock source
4442 *
4443 * 07 Reserved, must be 0
4444 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4445 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4446 */
4447 RegValue=BIT6;
4448 write_reg(info, RXS, RegValue);
4449
4450 /* TXS, Transmit clock source
4451 *
4452 * 07 Reserved, must be 0
4453 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4454 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4455 */
4456 RegValue=BIT6;
4457 write_reg(info, TXS, RegValue);
4458
4459 /* Control Register
4460 *
4461 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4462 */
4463 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4464 write_control_reg(info);
4465
4466 tx_set_idle(info);
4467
4468 /* RRC Receive Ready Control 0
4469 *
4470 * 07..05 Reserved, must be 0
4471 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4472 */
4473 write_reg(info, RRC, 0x00);
4474
4475 /* TRC0 Transmit Ready Control 0
4476 *
4477 * 07..05 Reserved, must be 0
4478 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4479 */
4480 write_reg(info, TRC0, 0x10);
4481
4482 /* TRC1 Transmit Ready Control 1
4483 *
4484 * 07..05 Reserved, must be 0
4485 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4486 */
4487 write_reg(info, TRC1, 0x1e);
4488
4489 /* CTL, MSCI control register
4490 *
4491 * 07..06 Reserved, set to 0
4492 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4493 * 04 IDLC, idle control, 0=mark 1=idle register
4494 * 03 BRK, break, 0=off 1 =on (async)
4495 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4496 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4497 * 00 RTS, RTS output control, 0=active 1=inactive
4498 *
4499 * 0001 0001
4500 */
4501 RegValue = 0x10;
4502 if (!(info->serial_signals & SerialSignal_RTS))
4503 RegValue |= 0x01;
4504 write_reg(info, CTL, RegValue);
4505
4506 /* enable status interrupts */
4507 info->ie0_value |= TXINTE + RXINTE;
4508 write_reg(info, IE0, info->ie0_value);
4509
4510 /* enable break detect interrupt */
4511 info->ie1_value = BRKD;
4512 write_reg(info, IE1, info->ie1_value);
4513
4514 /* enable rx overrun interrupt */
4515 info->ie2_value = OVRN;
4516 write_reg(info, IE2, info->ie2_value);
4517
4518 set_rate( info, info->params.data_rate * 16 );
4519 }
4520
4521 /* Program the SCA for HDLC communications.
4522 */
4523 static void hdlc_mode(SLMP_INFO *info)
4524 {
4525 unsigned char RegValue;
4526 u32 DpllDivisor;
4527
4528 // Can't use DPLL because SCA outputs recovered clock on RxC when
4529 // DPLL mode selected. This causes output contention with RxC receiver.
4530 // Use of DPLL would require external hardware to disable RxC receiver
4531 // when DPLL mode selected.
4532 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4533
4534 /* disable DMA interrupts */
4535 write_reg(info, TXDMA + DIR, 0);
4536 write_reg(info, RXDMA + DIR, 0);
4537
4538 /* MD0, Mode Register 0
4539 *
4540 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4541 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4542 * 03 Reserved, must be 0
4543 * 02 CRCCC, CRC Calculation, 1=enabled
4544 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4545 * 00 CRC0, CRC initial value, 1 = all 1s
4546 *
4547 * 1000 0001
4548 */
4549 RegValue = 0x81;
4550 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4551 RegValue |= BIT4;
4552 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4553 RegValue |= BIT4;
4554 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4555 RegValue |= BIT2 + BIT1;
4556 write_reg(info, MD0, RegValue);
4557
4558 /* MD1, Mode Register 1
4559 *
4560 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4561 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4562 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4563 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4564 *
4565 * 0000 0000
4566 */
4567 RegValue = 0x00;
4568 write_reg(info, MD1, RegValue);
4569
4570 /* MD2, Mode Register 2
4571 *
4572 * 07 NRZFM, 0=NRZ, 1=FM
4573 * 06..05 CODE<1..0> Encoding, 00=NRZ
4574 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4575 * 02 Reserved, must be 0
4576 * 01..00 CNCT<1..0> Channel connection, 0=normal
4577 *
4578 * 0000 0000
4579 */
4580 RegValue = 0x00;
4581 switch(info->params.encoding) {
4582 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4583 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4584 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4585 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4586 #if 0
4587 case HDLC_ENCODING_NRZB: /* not supported */
4588 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4589 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4590 #endif
4591 }
4592 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4593 DpllDivisor = 16;
4594 RegValue |= BIT3;
4595 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4596 DpllDivisor = 8;
4597 } else {
4598 DpllDivisor = 32;
4599 RegValue |= BIT4;
4600 }
4601 write_reg(info, MD2, RegValue);
4602
4603
4604 /* RXS, Receive clock source
4605 *
4606 * 07 Reserved, must be 0
4607 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4608 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4609 */
4610 RegValue=0;
4611 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4612 RegValue |= BIT6;
4613 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4614 RegValue |= BIT6 + BIT5;
4615 write_reg(info, RXS, RegValue);
4616
4617 /* TXS, Transmit clock source
4618 *
4619 * 07 Reserved, must be 0
4620 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4621 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4622 */
4623 RegValue=0;
4624 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4625 RegValue |= BIT6;
4626 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4627 RegValue |= BIT6 + BIT5;
4628 write_reg(info, TXS, RegValue);
4629
4630 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4631 set_rate(info, info->params.clock_speed * DpllDivisor);
4632 else
4633 set_rate(info, info->params.clock_speed);
4634
4635 /* GPDATA (General Purpose I/O Data Register)
4636 *
4637 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4638 */
4639 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4640 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4641 else
4642 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4643 write_control_reg(info);
4644
4645 /* RRC Receive Ready Control 0
4646 *
4647 * 07..05 Reserved, must be 0
4648 * 04..00 RRC<4..0> Rx FIFO trigger active
4649 */
4650 write_reg(info, RRC, rx_active_fifo_level);
4651
4652 /* TRC0 Transmit Ready Control 0
4653 *
4654 * 07..05 Reserved, must be 0
4655 * 04..00 TRC<4..0> Tx FIFO trigger active
4656 */
4657 write_reg(info, TRC0, tx_active_fifo_level);
4658
4659 /* TRC1 Transmit Ready Control 1
4660 *
4661 * 07..05 Reserved, must be 0
4662 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4663 */
4664 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4665
4666 /* DMR, DMA Mode Register
4667 *
4668 * 07..05 Reserved, must be 0
4669 * 04 TMOD, Transfer Mode: 1=chained-block
4670 * 03 Reserved, must be 0
4671 * 02 NF, Number of Frames: 1=multi-frame
4672 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4673 * 00 Reserved, must be 0
4674 *
4675 * 0001 0100
4676 */
4677 write_reg(info, TXDMA + DMR, 0x14);
4678 write_reg(info, RXDMA + DMR, 0x14);
4679
4680 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4681 write_reg(info, RXDMA + CPB,
4682 (unsigned char)(info->buffer_list_phys >> 16));
4683
4684 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4685 write_reg(info, TXDMA + CPB,
4686 (unsigned char)(info->buffer_list_phys >> 16));
4687
4688 /* enable status interrupts. other code enables/disables
4689 * the individual sources for these two interrupt classes.
4690 */
4691 info->ie0_value |= TXINTE + RXINTE;
4692 write_reg(info, IE0, info->ie0_value);
4693
4694 /* CTL, MSCI control register
4695 *
4696 * 07..06 Reserved, set to 0
4697 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4698 * 04 IDLC, idle control, 0=mark 1=idle register
4699 * 03 BRK, break, 0=off 1 =on (async)
4700 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4701 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4702 * 00 RTS, RTS output control, 0=active 1=inactive
4703 *
4704 * 0001 0001
4705 */
4706 RegValue = 0x10;
4707 if (!(info->serial_signals & SerialSignal_RTS))
4708 RegValue |= 0x01;
4709 write_reg(info, CTL, RegValue);
4710
4711 /* preamble not supported ! */
4712
4713 tx_set_idle(info);
4714 tx_stop(info);
4715 rx_stop(info);
4716
4717 set_rate(info, info->params.clock_speed);
4718
4719 if (info->params.loopback)
4720 enable_loopback(info,1);
4721 }
4722
4723 /* Set the transmit HDLC idle mode
4724 */
4725 static void tx_set_idle(SLMP_INFO *info)
4726 {
4727 unsigned char RegValue = 0xff;
4728
4729 /* Map API idle mode to SCA register bits */
4730 switch(info->idle_mode) {
4731 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4732 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4733 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4734 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4735 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4736 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4737 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4738 }
4739
4740 write_reg(info, IDL, RegValue);
4741 }
4742
4743 /* Query the adapter for the state of the V24 status (input) signals.
4744 */
4745 static void get_signals(SLMP_INFO *info)
4746 {
4747 u16 status = read_reg(info, SR3);
4748 u16 gpstatus = read_status_reg(info);
4749 u16 testbit;
4750
4751 /* clear all serial signals except RTS and DTR */
4752 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
4753
4754 /* set serial signal bits to reflect MISR */
4755
4756 if (!(status & BIT3))
4757 info->serial_signals |= SerialSignal_CTS;
4758
4759 if ( !(status & BIT2))
4760 info->serial_signals |= SerialSignal_DCD;
4761
4762 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4763 if (!(gpstatus & testbit))
4764 info->serial_signals |= SerialSignal_RI;
4765
4766 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4767 if (!(gpstatus & testbit))
4768 info->serial_signals |= SerialSignal_DSR;
4769 }
4770
4771 /* Set the state of RTS and DTR based on contents of
4772 * serial_signals member of device context.
4773 */
4774 static void set_signals(SLMP_INFO *info)
4775 {
4776 unsigned char RegValue;
4777 u16 EnableBit;
4778
4779 RegValue = read_reg(info, CTL);
4780 if (info->serial_signals & SerialSignal_RTS)
4781 RegValue &= ~BIT0;
4782 else
4783 RegValue |= BIT0;
4784 write_reg(info, CTL, RegValue);
4785
4786 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4787 EnableBit = BIT1 << (info->port_num*2);
4788 if (info->serial_signals & SerialSignal_DTR)
4789 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4790 else
4791 info->port_array[0]->ctrlreg_value |= EnableBit;
4792 write_control_reg(info);
4793 }
4794
4795 /*******************/
4796 /* DMA Buffer Code */
4797 /*******************/
4798
4799 /* Set the count for all receive buffers to SCABUFSIZE
4800 * and set the current buffer to the first buffer. This effectively
4801 * makes all buffers free and discards any data in buffers.
4802 */
4803 static void rx_reset_buffers(SLMP_INFO *info)
4804 {
4805 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4806 }
4807
4808 /* Free the buffers used by a received frame
4809 *
4810 * info pointer to device instance data
4811 * first index of 1st receive buffer of frame
4812 * last index of last receive buffer of frame
4813 */
4814 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4815 {
4816 bool done = false;
4817
4818 while(!done) {
4819 /* reset current buffer for reuse */
4820 info->rx_buf_list[first].status = 0xff;
4821
4822 if (first == last) {
4823 done = true;
4824 /* set new last rx descriptor address */
4825 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4826 }
4827
4828 first++;
4829 if (first == info->rx_buf_count)
4830 first = 0;
4831 }
4832
4833 /* set current buffer to next buffer after last buffer of frame */
4834 info->current_rx_buf = first;
4835 }
4836
4837 /* Return a received frame from the receive DMA buffers.
4838 * Only frames received without errors are returned.
4839 *
4840 * Return Value: true if frame returned, otherwise false
4841 */
4842 static bool rx_get_frame(SLMP_INFO *info)
4843 {
4844 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4845 unsigned short status;
4846 unsigned int framesize = 0;
4847 bool ReturnCode = false;
4848 unsigned long flags;
4849 struct tty_struct *tty = info->port.tty;
4850 unsigned char addr_field = 0xff;
4851 SCADESC *desc;
4852 SCADESC_EX *desc_ex;
4853
4854 CheckAgain:
4855 /* assume no frame returned, set zero length */
4856 framesize = 0;
4857 addr_field = 0xff;
4858
4859 /*
4860 * current_rx_buf points to the 1st buffer of the next available
4861 * receive frame. To find the last buffer of the frame look for
4862 * a non-zero status field in the buffer entries. (The status
4863 * field is set by the 16C32 after completing a receive frame.
4864 */
4865 StartIndex = EndIndex = info->current_rx_buf;
4866
4867 for ( ;; ) {
4868 desc = &info->rx_buf_list[EndIndex];
4869 desc_ex = &info->rx_buf_list_ex[EndIndex];
4870
4871 if (desc->status == 0xff)
4872 goto Cleanup; /* current desc still in use, no frames available */
4873
4874 if (framesize == 0 && info->params.addr_filter != 0xff)
4875 addr_field = desc_ex->virt_addr[0];
4876
4877 framesize += desc->length;
4878
4879 /* Status != 0 means last buffer of frame */
4880 if (desc->status)
4881 break;
4882
4883 EndIndex++;
4884 if (EndIndex == info->rx_buf_count)
4885 EndIndex = 0;
4886
4887 if (EndIndex == info->current_rx_buf) {
4888 /* all buffers have been 'used' but none mark */
4889 /* the end of a frame. Reset buffers and receiver. */
4890 if ( info->rx_enabled ){
4891 spin_lock_irqsave(&info->lock,flags);
4892 rx_start(info);
4893 spin_unlock_irqrestore(&info->lock,flags);
4894 }
4895 goto Cleanup;
4896 }
4897
4898 }
4899
4900 /* check status of receive frame */
4901
4902 /* frame status is byte stored after frame data
4903 *
4904 * 7 EOM (end of msg), 1 = last buffer of frame
4905 * 6 Short Frame, 1 = short frame
4906 * 5 Abort, 1 = frame aborted
4907 * 4 Residue, 1 = last byte is partial
4908 * 3 Overrun, 1 = overrun occurred during frame reception
4909 * 2 CRC, 1 = CRC error detected
4910 *
4911 */
4912 status = desc->status;
4913
4914 /* ignore CRC bit if not using CRC (bit is undefined) */
4915 /* Note:CRC is not save to data buffer */
4916 if (info->params.crc_type == HDLC_CRC_NONE)
4917 status &= ~BIT2;
4918
4919 if (framesize == 0 ||
4920 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4921 /* discard 0 byte frames, this seems to occur sometime
4922 * when remote is idling flags.
4923 */
4924 rx_free_frame_buffers(info, StartIndex, EndIndex);
4925 goto CheckAgain;
4926 }
4927
4928 if (framesize < 2)
4929 status |= BIT6;
4930
4931 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4932 /* received frame has errors,
4933 * update counts and mark frame size as 0
4934 */
4935 if (status & BIT6)
4936 info->icount.rxshort++;
4937 else if (status & BIT5)
4938 info->icount.rxabort++;
4939 else if (status & BIT3)
4940 info->icount.rxover++;
4941 else
4942 info->icount.rxcrc++;
4943
4944 framesize = 0;
4945 #if SYNCLINK_GENERIC_HDLC
4946 {
4947 info->netdev->stats.rx_errors++;
4948 info->netdev->stats.rx_frame_errors++;
4949 }
4950 #endif
4951 }
4952
4953 if ( debug_level >= DEBUG_LEVEL_BH )
4954 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4955 __FILE__,__LINE__,info->device_name,status,framesize);
4956
4957 if ( debug_level >= DEBUG_LEVEL_DATA )
4958 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4959 min_t(unsigned int, framesize, SCABUFSIZE), 0);
4960
4961 if (framesize) {
4962 if (framesize > info->max_frame_size)
4963 info->icount.rxlong++;
4964 else {
4965 /* copy dma buffer(s) to contiguous intermediate buffer */
4966 int copy_count = framesize;
4967 int index = StartIndex;
4968 unsigned char *ptmp = info->tmp_rx_buf;
4969 info->tmp_rx_buf_count = framesize;
4970
4971 info->icount.rxok++;
4972
4973 while(copy_count) {
4974 int partial_count = min(copy_count,SCABUFSIZE);
4975 memcpy( ptmp,
4976 info->rx_buf_list_ex[index].virt_addr,
4977 partial_count );
4978 ptmp += partial_count;
4979 copy_count -= partial_count;
4980
4981 if ( ++index == info->rx_buf_count )
4982 index = 0;
4983 }
4984
4985 #if SYNCLINK_GENERIC_HDLC
4986 if (info->netcount)
4987 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4988 else
4989 #endif
4990 ldisc_receive_buf(tty,info->tmp_rx_buf,
4991 info->flag_buf, framesize);
4992 }
4993 }
4994 /* Free the buffers used by this frame. */
4995 rx_free_frame_buffers( info, StartIndex, EndIndex );
4996
4997 ReturnCode = true;
4998
4999 Cleanup:
5000 if ( info->rx_enabled && info->rx_overflow ) {
5001 /* Receiver is enabled, but needs to restarted due to
5002 * rx buffer overflow. If buffers are empty, restart receiver.
5003 */
5004 if (info->rx_buf_list[EndIndex].status == 0xff) {
5005 spin_lock_irqsave(&info->lock,flags);
5006 rx_start(info);
5007 spin_unlock_irqrestore(&info->lock,flags);
5008 }
5009 }
5010
5011 return ReturnCode;
5012 }
5013
5014 /* load the transmit DMA buffer with data
5015 */
5016 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5017 {
5018 unsigned short copy_count;
5019 unsigned int i = 0;
5020 SCADESC *desc;
5021 SCADESC_EX *desc_ex;
5022
5023 if ( debug_level >= DEBUG_LEVEL_DATA )
5024 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5025
5026 /* Copy source buffer to one or more DMA buffers, starting with
5027 * the first transmit dma buffer.
5028 */
5029 for(i=0;;)
5030 {
5031 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5032
5033 desc = &info->tx_buf_list[i];
5034 desc_ex = &info->tx_buf_list_ex[i];
5035
5036 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5037
5038 desc->length = copy_count;
5039 desc->status = 0;
5040
5041 buf += copy_count;
5042 count -= copy_count;
5043
5044 if (!count)
5045 break;
5046
5047 i++;
5048 if (i >= info->tx_buf_count)
5049 i = 0;
5050 }
5051
5052 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5053 info->last_tx_buf = ++i;
5054 }
5055
5056 static bool register_test(SLMP_INFO *info)
5057 {
5058 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5059 static unsigned int count = ARRAY_SIZE(testval);
5060 unsigned int i;
5061 bool rc = true;
5062 unsigned long flags;
5063
5064 spin_lock_irqsave(&info->lock,flags);
5065 reset_port(info);
5066
5067 /* assume failure */
5068 info->init_error = DiagStatus_AddressFailure;
5069
5070 /* Write bit patterns to various registers but do it out of */
5071 /* sync, then read back and verify values. */
5072
5073 for (i = 0 ; i < count ; i++) {
5074 write_reg(info, TMC, testval[i]);
5075 write_reg(info, IDL, testval[(i+1)%count]);
5076 write_reg(info, SA0, testval[(i+2)%count]);
5077 write_reg(info, SA1, testval[(i+3)%count]);
5078
5079 if ( (read_reg(info, TMC) != testval[i]) ||
5080 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5081 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5082 (read_reg(info, SA1) != testval[(i+3)%count]) )
5083 {
5084 rc = false;
5085 break;
5086 }
5087 }
5088
5089 reset_port(info);
5090 spin_unlock_irqrestore(&info->lock,flags);
5091
5092 return rc;
5093 }
5094
5095 static bool irq_test(SLMP_INFO *info)
5096 {
5097 unsigned long timeout;
5098 unsigned long flags;
5099
5100 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5101
5102 spin_lock_irqsave(&info->lock,flags);
5103 reset_port(info);
5104
5105 /* assume failure */
5106 info->init_error = DiagStatus_IrqFailure;
5107 info->irq_occurred = false;
5108
5109 /* setup timer0 on SCA0 to interrupt */
5110
5111 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5112 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5113
5114 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5115 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5116
5117
5118 /* TMCS, Timer Control/Status Register
5119 *
5120 * 07 CMF, Compare match flag (read only) 1=match
5121 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5122 * 05 Reserved, must be 0
5123 * 04 TME, Timer Enable
5124 * 03..00 Reserved, must be 0
5125 *
5126 * 0101 0000
5127 */
5128 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5129
5130 spin_unlock_irqrestore(&info->lock,flags);
5131
5132 timeout=100;
5133 while( timeout-- && !info->irq_occurred ) {
5134 msleep_interruptible(10);
5135 }
5136
5137 spin_lock_irqsave(&info->lock,flags);
5138 reset_port(info);
5139 spin_unlock_irqrestore(&info->lock,flags);
5140
5141 return info->irq_occurred;
5142 }
5143
5144 /* initialize individual SCA device (2 ports)
5145 */
5146 static bool sca_init(SLMP_INFO *info)
5147 {
5148 /* set wait controller to single mem partition (low), no wait states */
5149 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5150 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5151 write_reg(info, WCRL, 0); /* wait controller low range */
5152 write_reg(info, WCRM, 0); /* wait controller mid range */
5153 write_reg(info, WCRH, 0); /* wait controller high range */
5154
5155 /* DPCR, DMA Priority Control
5156 *
5157 * 07..05 Not used, must be 0
5158 * 04 BRC, bus release condition: 0=all transfers complete
5159 * 03 CCC, channel change condition: 0=every cycle
5160 * 02..00 PR<2..0>, priority 100=round robin
5161 *
5162 * 00000100 = 0x04
5163 */
5164 write_reg(info, DPCR, dma_priority);
5165
5166 /* DMA Master Enable, BIT7: 1=enable all channels */
5167 write_reg(info, DMER, 0x80);
5168
5169 /* enable all interrupt classes */
5170 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5171 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5172 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5173
5174 /* ITCR, interrupt control register
5175 * 07 IPC, interrupt priority, 0=MSCI->DMA
5176 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5177 * 04 VOS, Vector Output, 0=unmodified vector
5178 * 03..00 Reserved, must be 0
5179 */
5180 write_reg(info, ITCR, 0);
5181
5182 return true;
5183 }
5184
5185 /* initialize adapter hardware
5186 */
5187 static bool init_adapter(SLMP_INFO *info)
5188 {
5189 int i;
5190
5191 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5192 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5193 u32 readval;
5194
5195 info->misc_ctrl_value |= BIT30;
5196 *MiscCtrl = info->misc_ctrl_value;
5197
5198 /*
5199 * Force at least 170ns delay before clearing
5200 * reset bit. Each read from LCR takes at least
5201 * 30ns so 10 times for 300ns to be safe.
5202 */
5203 for(i=0;i<10;i++)
5204 readval = *MiscCtrl;
5205
5206 info->misc_ctrl_value &= ~BIT30;
5207 *MiscCtrl = info->misc_ctrl_value;
5208
5209 /* init control reg (all DTRs off, all clksel=input) */
5210 info->ctrlreg_value = 0xaa;
5211 write_control_reg(info);
5212
5213 {
5214 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5215 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5216
5217 switch(read_ahead_count)
5218 {
5219 case 16:
5220 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5221 break;
5222 case 8:
5223 lcr1_brdr_value |= BIT5 + BIT4;
5224 break;
5225 case 4:
5226 lcr1_brdr_value |= BIT5 + BIT3;
5227 break;
5228 case 0:
5229 lcr1_brdr_value |= BIT5;
5230 break;
5231 }
5232
5233 *LCR1BRDR = lcr1_brdr_value;
5234 *MiscCtrl = misc_ctrl_value;
5235 }
5236
5237 sca_init(info->port_array[0]);
5238 sca_init(info->port_array[2]);
5239
5240 return true;
5241 }
5242
5243 /* Loopback an HDLC frame to test the hardware
5244 * interrupt and DMA functions.
5245 */
5246 static bool loopback_test(SLMP_INFO *info)
5247 {
5248 #define TESTFRAMESIZE 20
5249
5250 unsigned long timeout;
5251 u16 count = TESTFRAMESIZE;
5252 unsigned char buf[TESTFRAMESIZE];
5253 bool rc = false;
5254 unsigned long flags;
5255
5256 struct tty_struct *oldtty = info->port.tty;
5257 u32 speed = info->params.clock_speed;
5258
5259 info->params.clock_speed = 3686400;
5260 info->port.tty = NULL;
5261
5262 /* assume failure */
5263 info->init_error = DiagStatus_DmaFailure;
5264
5265 /* build and send transmit frame */
5266 for (count = 0; count < TESTFRAMESIZE;++count)
5267 buf[count] = (unsigned char)count;
5268
5269 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5270
5271 /* program hardware for HDLC and enabled receiver */
5272 spin_lock_irqsave(&info->lock,flags);
5273 hdlc_mode(info);
5274 enable_loopback(info,1);
5275 rx_start(info);
5276 info->tx_count = count;
5277 tx_load_dma_buffer(info,buf,count);
5278 tx_start(info);
5279 spin_unlock_irqrestore(&info->lock,flags);
5280
5281 /* wait for receive complete */
5282 /* Set a timeout for waiting for interrupt. */
5283 for ( timeout = 100; timeout; --timeout ) {
5284 msleep_interruptible(10);
5285
5286 if (rx_get_frame(info)) {
5287 rc = true;
5288 break;
5289 }
5290 }
5291
5292 /* verify received frame length and contents */
5293 if (rc &&
5294 ( info->tmp_rx_buf_count != count ||
5295 memcmp(buf, info->tmp_rx_buf,count))) {
5296 rc = false;
5297 }
5298
5299 spin_lock_irqsave(&info->lock,flags);
5300 reset_adapter(info);
5301 spin_unlock_irqrestore(&info->lock,flags);
5302
5303 info->params.clock_speed = speed;
5304 info->port.tty = oldtty;
5305
5306 return rc;
5307 }
5308
5309 /* Perform diagnostics on hardware
5310 */
5311 static int adapter_test( SLMP_INFO *info )
5312 {
5313 unsigned long flags;
5314 if ( debug_level >= DEBUG_LEVEL_INFO )
5315 printk( "%s(%d):Testing device %s\n",
5316 __FILE__,__LINE__,info->device_name );
5317
5318 spin_lock_irqsave(&info->lock,flags);
5319 init_adapter(info);
5320 spin_unlock_irqrestore(&info->lock,flags);
5321
5322 info->port_array[0]->port_count = 0;
5323
5324 if ( register_test(info->port_array[0]) &&
5325 register_test(info->port_array[1])) {
5326
5327 info->port_array[0]->port_count = 2;
5328
5329 if ( register_test(info->port_array[2]) &&
5330 register_test(info->port_array[3]) )
5331 info->port_array[0]->port_count += 2;
5332 }
5333 else {
5334 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5335 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5336 return -ENODEV;
5337 }
5338
5339 if ( !irq_test(info->port_array[0]) ||
5340 !irq_test(info->port_array[1]) ||
5341 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5342 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5343 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5344 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5345 return -ENODEV;
5346 }
5347
5348 if (!loopback_test(info->port_array[0]) ||
5349 !loopback_test(info->port_array[1]) ||
5350 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5351 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5352 printk( "%s(%d):DMA test failure for device %s\n",
5353 __FILE__,__LINE__,info->device_name);
5354 return -ENODEV;
5355 }
5356
5357 if ( debug_level >= DEBUG_LEVEL_INFO )
5358 printk( "%s(%d):device %s passed diagnostics\n",
5359 __FILE__,__LINE__,info->device_name );
5360
5361 info->port_array[0]->init_error = 0;
5362 info->port_array[1]->init_error = 0;
5363 if ( info->port_count > 2 ) {
5364 info->port_array[2]->init_error = 0;
5365 info->port_array[3]->init_error = 0;
5366 }
5367
5368 return 0;
5369 }
5370
5371 /* Test the shared memory on a PCI adapter.
5372 */
5373 static bool memory_test(SLMP_INFO *info)
5374 {
5375 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5376 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5377 unsigned long count = ARRAY_SIZE(testval);
5378 unsigned long i;
5379 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5380 unsigned long * addr = (unsigned long *)info->memory_base;
5381
5382 /* Test data lines with test pattern at one location. */
5383
5384 for ( i = 0 ; i < count ; i++ ) {
5385 *addr = testval[i];
5386 if ( *addr != testval[i] )
5387 return false;
5388 }
5389
5390 /* Test address lines with incrementing pattern over */
5391 /* entire address range. */
5392
5393 for ( i = 0 ; i < limit ; i++ ) {
5394 *addr = i * 4;
5395 addr++;
5396 }
5397
5398 addr = (unsigned long *)info->memory_base;
5399
5400 for ( i = 0 ; i < limit ; i++ ) {
5401 if ( *addr != i * 4 )
5402 return false;
5403 addr++;
5404 }
5405
5406 memset( info->memory_base, 0, SCA_MEM_SIZE );
5407 return true;
5408 }
5409
5410 /* Load data into PCI adapter shared memory.
5411 *
5412 * The PCI9050 releases control of the local bus
5413 * after completing the current read or write operation.
5414 *
5415 * While the PCI9050 write FIFO not empty, the
5416 * PCI9050 treats all of the writes as a single transaction
5417 * and does not release the bus. This causes DMA latency problems
5418 * at high speeds when copying large data blocks to the shared memory.
5419 *
5420 * This function breaks a write into multiple transations by
5421 * interleaving a read which flushes the write FIFO and 'completes'
5422 * the write transation. This allows any pending DMA request to gain control
5423 * of the local bus in a timely fasion.
5424 */
5425 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5426 {
5427 /* A load interval of 16 allows for 4 32-bit writes at */
5428 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5429
5430 unsigned short interval = count / sca_pci_load_interval;
5431 unsigned short i;
5432
5433 for ( i = 0 ; i < interval ; i++ )
5434 {
5435 memcpy(dest, src, sca_pci_load_interval);
5436 read_status_reg(info);
5437 dest += sca_pci_load_interval;
5438 src += sca_pci_load_interval;
5439 }
5440
5441 memcpy(dest, src, count % sca_pci_load_interval);
5442 }
5443
5444 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5445 {
5446 int i;
5447 int linecount;
5448 if (xmit)
5449 printk("%s tx data:\n",info->device_name);
5450 else
5451 printk("%s rx data:\n",info->device_name);
5452
5453 while(count) {
5454 if (count > 16)
5455 linecount = 16;
5456 else
5457 linecount = count;
5458
5459 for(i=0;i<linecount;i++)
5460 printk("%02X ",(unsigned char)data[i]);
5461 for(;i<17;i++)
5462 printk(" ");
5463 for(i=0;i<linecount;i++) {
5464 if (data[i]>=040 && data[i]<=0176)
5465 printk("%c",data[i]);
5466 else
5467 printk(".");
5468 }
5469 printk("\n");
5470
5471 data += linecount;
5472 count -= linecount;
5473 }
5474 } /* end of trace_block() */
5475
5476 /* called when HDLC frame times out
5477 * update stats and do tx completion processing
5478 */
5479 static void tx_timeout(unsigned long context)
5480 {
5481 SLMP_INFO *info = (SLMP_INFO*)context;
5482 unsigned long flags;
5483
5484 if ( debug_level >= DEBUG_LEVEL_INFO )
5485 printk( "%s(%d):%s tx_timeout()\n",
5486 __FILE__,__LINE__,info->device_name);
5487 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5488 info->icount.txtimeout++;
5489 }
5490 spin_lock_irqsave(&info->lock,flags);
5491 info->tx_active = false;
5492 info->tx_count = info->tx_put = info->tx_get = 0;
5493
5494 spin_unlock_irqrestore(&info->lock,flags);
5495
5496 #if SYNCLINK_GENERIC_HDLC
5497 if (info->netcount)
5498 hdlcdev_tx_done(info);
5499 else
5500 #endif
5501 bh_transmit(info);
5502 }
5503
5504 /* called to periodically check the DSR/RI modem signal input status
5505 */
5506 static void status_timeout(unsigned long context)
5507 {
5508 u16 status = 0;
5509 SLMP_INFO *info = (SLMP_INFO*)context;
5510 unsigned long flags;
5511 unsigned char delta;
5512
5513
5514 spin_lock_irqsave(&info->lock,flags);
5515 get_signals(info);
5516 spin_unlock_irqrestore(&info->lock,flags);
5517
5518 /* check for DSR/RI state change */
5519
5520 delta = info->old_signals ^ info->serial_signals;
5521 info->old_signals = info->serial_signals;
5522
5523 if (delta & SerialSignal_DSR)
5524 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5525
5526 if (delta & SerialSignal_RI)
5527 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5528
5529 if (delta & SerialSignal_DCD)
5530 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5531
5532 if (delta & SerialSignal_CTS)
5533 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5534
5535 if (status)
5536 isr_io_pin(info,status);
5537
5538 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5539 }
5540
5541
5542 /* Register Access Routines -
5543 * All registers are memory mapped
5544 */
5545 #define CALC_REGADDR() \
5546 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5547 if (info->port_num > 1) \
5548 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5549 if ( info->port_num & 1) { \
5550 if (Addr > 0x7f) \
5551 RegAddr += 0x40; /* DMA access */ \
5552 else if (Addr > 0x1f && Addr < 0x60) \
5553 RegAddr += 0x20; /* MSCI access */ \
5554 }
5555
5556
5557 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5558 {
5559 CALC_REGADDR();
5560 return *RegAddr;
5561 }
5562 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5563 {
5564 CALC_REGADDR();
5565 *RegAddr = Value;
5566 }
5567
5568 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5569 {
5570 CALC_REGADDR();
5571 return *((u16 *)RegAddr);
5572 }
5573
5574 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5575 {
5576 CALC_REGADDR();
5577 *((u16 *)RegAddr) = Value;
5578 }
5579
5580 static unsigned char read_status_reg(SLMP_INFO * info)
5581 {
5582 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5583 return *RegAddr;
5584 }
5585
5586 static void write_control_reg(SLMP_INFO * info)
5587 {
5588 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5589 *RegAddr = info->port_array[0]->ctrlreg_value;
5590 }
5591
5592
5593 static int synclinkmp_init_one (struct pci_dev *dev,
5594 const struct pci_device_id *ent)
5595 {
5596 if (pci_enable_device(dev)) {
5597 printk("error enabling pci device %p\n", dev);
5598 return -EIO;
5599 }
5600 return device_init( ++synclinkmp_adapter_count, dev );
5601 }
5602
5603 static void synclinkmp_remove_one (struct pci_dev *dev)
5604 {
5605 }
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