drivers/misc/mei/hw-me.c

   1 /*
   2  *
   3  * Intel Management Engine Interface (Intel MEI) Linux driver
   4  * Copyright (c) 2003-2012, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  */
  16
  17 #include <linux/pci.h>
  18
  19 #include <linux/kthread.h>
  20 #include <linux/interrupt.h>
  21
  22 #include "mei_dev.h"
  23 #include "hbm.h"
  24
  25 #include "hw-me.h"
  26 #include "hw-me-regs.h"
  27
  28 #include "mei-trace.h"
  29
  30 /**
  31  * mei_me_reg_read - Reads 32bit data from the mei device
  32  *
  33  * @hw: the me hardware structure
  34  * @offset: offset from which to read the data
  35  *
  36  * Return: register value (u32)
  37  */
  38 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
  39                                unsigned long offset)
  40 {
  41         return ioread32(hw->mem_addr + offset);
  42 }
  43
  44
  45 /**
  46  * mei_me_reg_write - Writes 32bit data to the mei device
  47  *
  48  * @hw: the me hardware structure
  49  * @offset: offset from which to write the data
  50  * @value: register value to write (u32)
  51  */
  52 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
  53                                  unsigned long offset, u32 value)
  54 {
  55         iowrite32(value, hw->mem_addr + offset);
  56 }
  57
  58 /**
  59  * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
  60  *  read window register
  61  *
  62  * @dev: the device structure
  63  *
  64  * Return: ME_CB_RW register value (u32)
  65  */
  66 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev)
  67 {
  68         return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
  69 }
  70
  71 /**
  72  * mei_me_hcbww_write - write 32bit data to the host circular buffer
  73  *
  74  * @dev: the device structure
  75  * @data: 32bit data to be written to the host circular buffer
  76  */
  77 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data)
  78 {
  79         mei_me_reg_write(to_me_hw(dev), H_CB_WW, data);
  80 }
  81
  82 /**
  83  * mei_me_mecsr_read - Reads 32bit data from the ME CSR
  84  *
  85  * @dev: the device structure
  86  *
  87  * Return: ME_CSR_HA register value (u32)
  88  */
  89 static inline u32 mei_me_mecsr_read(const struct mei_device *dev)
  90 {
  91         u32 reg;
  92
  93         reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA);
  94         trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg);
  95
  96         return reg;
  97 }
  98
  99 /**
 100  * mei_hcsr_read - Reads 32bit data from the host CSR
 101  *
 102  * @dev: the device structure
 103  *
 104  * Return: H_CSR register value (u32)
 105  */
 106 static inline u32 mei_hcsr_read(const struct mei_device *dev)
 107 {
 108         u32 reg;
 109
 110         reg = mei_me_reg_read(to_me_hw(dev), H_CSR);
 111         trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg);
 112
 113         return reg;
 114 }
 115
 116 /**
 117  * mei_hcsr_write - writes H_CSR register to the mei device
 118  *
 119  * @dev: the device structure
 120  * @reg: new register value
 121  */
 122 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg)
 123 {
 124         trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg);
 125         mei_me_reg_write(to_me_hw(dev), H_CSR, reg);
 126 }
 127
 128 /**
 129  * mei_hcsr_set - writes H_CSR register to the mei device,
 130  * and ignores the H_IS bit for it is write-one-to-zero.
 131  *
 132  * @dev: the device structure
 133  * @reg: new register value
 134  */
 135 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg)
 136 {
 137         reg &= ~H_CSR_IS_MASK;
 138         mei_hcsr_write(dev, reg);
 139 }
 140
 141 /**
 142  * mei_me_fw_status - read fw status register from pci config space
 143  *
 144  * @dev: mei device
 145  * @fw_status: fw status register values
 146  *
 147  * Return: 0 on success, error otherwise
 148  */
 149 static int mei_me_fw_status(struct mei_device *dev,
 150                             struct mei_fw_status *fw_status)
 151 {
 152         struct pci_dev *pdev = to_pci_dev(dev->dev);
 153         struct mei_me_hw *hw = to_me_hw(dev);
 154         const struct mei_fw_status *fw_src = &hw->cfg->fw_status;
 155         int ret;
 156         int i;
 157
 158         if (!fw_status)
 159                 return -EINVAL;
 160
 161         fw_status->count = fw_src->count;
 162         for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
 163                 ret = pci_read_config_dword(pdev,
 164                         fw_src->status[i], &fw_status->status[i]);
 165                 if (ret)
 166                         return ret;
 167         }
 168
 169         return 0;
 170 }
 171
 172 /**
 173  * mei_me_hw_config - configure hw dependent settings
 174  *
 175  * @dev: mei device
 176  */
 177 static void mei_me_hw_config(struct mei_device *dev)
 178 {
 179         struct pci_dev *pdev = to_pci_dev(dev->dev);
 180         struct mei_me_hw *hw = to_me_hw(dev);
 181         u32 hcsr, reg;
 182
 183         /* Doesn't change in runtime */
 184         hcsr = mei_hcsr_read(dev);
 185         dev->hbuf_depth = (hcsr & H_CBD) >> 24;
 186
 187         hw->pg_state = MEI_PG_OFF;
 188
 189         reg = 0;
 190         pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
 191         hw->d0i3_supported =
 192                 ((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK);
 193 }
 194
 195 /**
 196  * mei_me_pg_state  - translate internal pg state
 197  *   to the mei power gating state
 198  *
 199  * @dev:  mei device
 200  *
 201  * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
 202  */
 203 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
 204 {
 205         struct mei_me_hw *hw = to_me_hw(dev);
 206
 207         return hw->pg_state;
 208 }
 209
 210 /**
 211  * mei_me_intr_clear - clear and stop interrupts
 212  *
 213  * @dev: the device structure
 214  */
 215 static void mei_me_intr_clear(struct mei_device *dev)
 216 {
 217         u32 hcsr = mei_hcsr_read(dev);
 218
 219         if (hcsr & H_CSR_IS_MASK)
 220                 mei_hcsr_write(dev, hcsr);
 221 }
 222 /**
 223  * mei_me_intr_enable - enables mei device interrupts
 224  *
 225  * @dev: the device structure
 226  */
 227 static void mei_me_intr_enable(struct mei_device *dev)
 228 {
 229         u32 hcsr = mei_hcsr_read(dev);
 230
 231         hcsr |= H_CSR_IE_MASK;
 232         mei_hcsr_set(dev, hcsr);
 233 }
 234
 235 /**
 236  * mei_me_intr_disable - disables mei device interrupts
 237  *
 238  * @dev: the device structure
 239  */
 240 static void mei_me_intr_disable(struct mei_device *dev)
 241 {
 242         u32 hcsr = mei_hcsr_read(dev);
 243
 244         hcsr  &= ~H_CSR_IE_MASK;
 245         mei_hcsr_set(dev, hcsr);
 246 }
 247
 248 /**
 249  * mei_me_hw_reset_release - release device from the reset
 250  *
 251  * @dev: the device structure
 252  */
 253 static void mei_me_hw_reset_release(struct mei_device *dev)
 254 {
 255         u32 hcsr = mei_hcsr_read(dev);
 256
 257         hcsr |= H_IG;
 258         hcsr &= ~H_RST;
 259         mei_hcsr_set(dev, hcsr);
 260
 261         /* complete this write before we set host ready on another CPU */
 262         mmiowb();
 263 }
 264 /**
 265  * mei_me_hw_reset - resets fw via mei csr register.
 266  *
 267  * @dev: the device structure
 268  * @intr_enable: if interrupt should be enabled after reset.
 269  *
 270  * Return: always 0
 271  */
 272 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
 273 {
 274         u32 hcsr = mei_hcsr_read(dev);
 275
 276         /* H_RST may be found lit before reset is started,
 277          * for example if preceding reset flow hasn't completed.
 278          * In that case asserting H_RST will be ignored, therefore
 279          * we need to clean H_RST bit to start a successful reset sequence.
 280          */
 281         if ((hcsr & H_RST) == H_RST) {
 282                 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
 283                 hcsr &= ~H_RST;
 284                 mei_hcsr_set(dev, hcsr);
 285                 hcsr = mei_hcsr_read(dev);
 286         }
 287
 288         hcsr |= H_RST | H_IG | H_CSR_IS_MASK;
 289
 290         if (intr_enable)
 291                 hcsr |= H_CSR_IE_MASK;
 292         else
 293                 hcsr &= ~H_CSR_IE_MASK;
 294
 295         dev->recvd_hw_ready = false;
 296         mei_hcsr_write(dev, hcsr);
 297
 298         /*
 299          * Host reads the H_CSR once to ensure that the
 300          * posted write to H_CSR completes.
 301          */
 302         hcsr = mei_hcsr_read(dev);
 303
 304         if ((hcsr & H_RST) == 0)
 305                 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);
 306
 307         if ((hcsr & H_RDY) == H_RDY)
 308                 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);
 309
 310         if (intr_enable == false)
 311                 mei_me_hw_reset_release(dev);
 312
 313         return 0;
 314 }
 315
 316 /**
 317  * mei_me_host_set_ready - enable device
 318  *
 319  * @dev: mei device
 320  */
 321 static void mei_me_host_set_ready(struct mei_device *dev)
 322 {
 323         u32 hcsr = mei_hcsr_read(dev);
 324
 325         hcsr |= H_CSR_IE_MASK | H_IG | H_RDY;
 326         mei_hcsr_set(dev, hcsr);
 327 }
 328
 329 /**
 330  * mei_me_host_is_ready - check whether the host has turned ready
 331  *
 332  * @dev: mei device
 333  * Return: bool
 334  */
 335 static bool mei_me_host_is_ready(struct mei_device *dev)
 336 {
 337         u32 hcsr = mei_hcsr_read(dev);
 338
 339         return (hcsr & H_RDY) == H_RDY;
 340 }
 341
 342 /**
 343  * mei_me_hw_is_ready - check whether the me(hw) has turned ready
 344  *
 345  * @dev: mei device
 346  * Return: bool
 347  */
 348 static bool mei_me_hw_is_ready(struct mei_device *dev)
 349 {
 350         u32 mecsr = mei_me_mecsr_read(dev);
 351
 352         return (mecsr & ME_RDY_HRA) == ME_RDY_HRA;
 353 }
 354
 355 /**
 356  * mei_me_hw_ready_wait - wait until the me(hw) has turned ready
 357  *  or timeout is reached
 358  *
 359  * @dev: mei device
 360  * Return: 0 on success, error otherwise
 361  */
 362 static int mei_me_hw_ready_wait(struct mei_device *dev)
 363 {
 364         mutex_unlock(&dev->device_lock);
 365         wait_event_timeout(dev->wait_hw_ready,
 366                         dev->recvd_hw_ready,
 367                         mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
 368         mutex_lock(&dev->device_lock);
 369         if (!dev->recvd_hw_ready) {
 370                 dev_err(dev->dev, "wait hw ready failed\n");
 371                 return -ETIME;
 372         }
 373
 374         mei_me_hw_reset_release(dev);
 375         dev->recvd_hw_ready = false;
 376         return 0;
 377 }
 378
 379 /**
 380  * mei_me_hw_start - hw start routine
 381  *
 382  * @dev: mei device
 383  * Return: 0 on success, error otherwise
 384  */
 385 static int mei_me_hw_start(struct mei_device *dev)
 386 {
 387         int ret = mei_me_hw_ready_wait(dev);
 388
 389         if (ret)
 390                 return ret;
 391         dev_dbg(dev->dev, "hw is ready\n");
 392
 393         mei_me_host_set_ready(dev);
 394         return ret;
 395 }
 396
 397
 398 /**
 399  * mei_hbuf_filled_slots - gets number of device filled buffer slots
 400  *
 401  * @dev: the device structure
 402  *
 403  * Return: number of filled slots
 404  */
 405 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
 406 {
 407         u32 hcsr;
 408         char read_ptr, write_ptr;
 409
 410         hcsr = mei_hcsr_read(dev);
 411
 412         read_ptr = (char) ((hcsr & H_CBRP) >> 8);
 413         write_ptr = (char) ((hcsr & H_CBWP) >> 16);
 414
 415         return (unsigned char) (write_ptr - read_ptr);
 416 }
 417
 418 /**
 419  * mei_me_hbuf_is_empty - checks if host buffer is empty.
 420  *
 421  * @dev: the device structure
 422  *
 423  * Return: true if empty, false - otherwise.
 424  */
 425 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
 426 {
 427         return mei_hbuf_filled_slots(dev) == 0;
 428 }
 429
 430 /**
 431  * mei_me_hbuf_empty_slots - counts write empty slots.
 432  *
 433  * @dev: the device structure
 434  *
 435  * Return: -EOVERFLOW if overflow, otherwise empty slots count
 436  */
 437 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
 438 {
 439         unsigned char filled_slots, empty_slots;
 440
 441         filled_slots = mei_hbuf_filled_slots(dev);
 442         empty_slots = dev->hbuf_depth - filled_slots;
 443
 444         /* check for overflow */
 445         if (filled_slots > dev->hbuf_depth)
 446                 return -EOVERFLOW;
 447
 448         return empty_slots;
 449 }
 450
 451 /**
 452  * mei_me_hbuf_max_len - returns size of hw buffer.
 453  *
 454  * @dev: the device structure
 455  *
 456  * Return: size of hw buffer in bytes
 457  */
 458 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
 459 {
 460         return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
 461 }
 462
 463
 464 /**
 465  * mei_me_write_message - writes a message to mei device.
 466  *
 467  * @dev: the device structure
 468  * @header: mei HECI header of message
 469  * @buf: message payload will be written
 470  *
 471  * Return: -EIO if write has failed
 472  */
 473 static int mei_me_write_message(struct mei_device *dev,
 474                         struct mei_msg_hdr *header,
 475                         unsigned char *buf)
 476 {
 477         unsigned long rem;
 478         unsigned long length = header->length;
 479         u32 *reg_buf = (u32 *)buf;
 480         u32 hcsr;
 481         u32 dw_cnt;
 482         int i;
 483         int empty_slots;
 484
 485         dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
 486
 487         empty_slots = mei_hbuf_empty_slots(dev);
 488         dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots);
 489
 490         dw_cnt = mei_data2slots(length);
 491         if (empty_slots < 0 || dw_cnt > empty_slots)
 492                 return -EMSGSIZE;
 493
 494         mei_me_hcbww_write(dev, *((u32 *) header));
 495
 496         for (i = 0; i < length / 4; i++)
 497                 mei_me_hcbww_write(dev, reg_buf[i]);
 498
 499         rem = length & 0x3;
 500         if (rem > 0) {
 501                 u32 reg = 0;
 502
 503                 memcpy(&reg, &buf[length - rem], rem);
 504                 mei_me_hcbww_write(dev, reg);
 505         }
 506
 507         hcsr = mei_hcsr_read(dev) | H_IG;
 508         mei_hcsr_set(dev, hcsr);
 509         if (!mei_me_hw_is_ready(dev))
 510                 return -EIO;
 511
 512         return 0;
 513 }
 514
 515 /**
 516  * mei_me_count_full_read_slots - counts read full slots.
 517  *
 518  * @dev: the device structure
 519  *
 520  * Return: -EOVERFLOW if overflow, otherwise filled slots count
 521  */
 522 static int mei_me_count_full_read_slots(struct mei_device *dev)
 523 {
 524         u32 me_csr;
 525         char read_ptr, write_ptr;
 526         unsigned char buffer_depth, filled_slots;
 527
 528         me_csr = mei_me_mecsr_read(dev);
 529         buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24);
 530         read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8);
 531         write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16);
 532         filled_slots = (unsigned char) (write_ptr - read_ptr);
 533
 534         /* check for overflow */
 535         if (filled_slots > buffer_depth)
 536                 return -EOVERFLOW;
 537
 538         dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots);
 539         return (int)filled_slots;
 540 }
 541
 542 /**
 543  * mei_me_read_slots - reads a message from mei device.
 544  *
 545  * @dev: the device structure
 546  * @buffer: message buffer will be written
 547  * @buffer_length: message size will be read
 548  *
 549  * Return: always 0
 550  */
 551 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
 552                     unsigned long buffer_length)
 553 {
 554         u32 *reg_buf = (u32 *)buffer;
 555         u32 hcsr;
 556
 557         for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
 558                 *reg_buf++ = mei_me_mecbrw_read(dev);
 559
 560         if (buffer_length > 0) {
 561                 u32 reg = mei_me_mecbrw_read(dev);
 562
 563                 memcpy(reg_buf, &reg, buffer_length);
 564         }
 565
 566         hcsr = mei_hcsr_read(dev) | H_IG;
 567         mei_hcsr_set(dev, hcsr);
 568         return 0;
 569 }
 570
 571 /**
 572  * mei_me_pg_set - write pg enter register
 573  *
 574  * @dev: the device structure
 575  */
 576 static void mei_me_pg_set(struct mei_device *dev)
 577 {
 578         struct mei_me_hw *hw = to_me_hw(dev);
 579         u32 reg;
 580
 581         reg = mei_me_reg_read(hw, H_HPG_CSR);
 582         trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
 583
 584         reg |= H_HPG_CSR_PGI;
 585
 586         trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
 587         mei_me_reg_write(hw, H_HPG_CSR, reg);
 588 }
 589
 590 /**
 591  * mei_me_pg_unset - write pg exit register
 592  *
 593  * @dev: the device structure
 594  */
 595 static void mei_me_pg_unset(struct mei_device *dev)
 596 {
 597         struct mei_me_hw *hw = to_me_hw(dev);
 598         u32 reg;
 599
 600         reg = mei_me_reg_read(hw, H_HPG_CSR);
 601         trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
 602
 603         WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
 604
 605         reg |= H_HPG_CSR_PGIHEXR;
 606
 607         trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
 608         mei_me_reg_write(hw, H_HPG_CSR, reg);
 609 }
 610
 611 /**
 612  * mei_me_pg_enter_sync - perform pg entry procedure
 613  *
 614  * @dev: the device structure
 615  *
 616  * Return: 0 on success an error code otherwise
 617  */
 618 int mei_me_pg_enter_sync(struct mei_device *dev)
 619 {
 620         struct mei_me_hw *hw = to_me_hw(dev);
 621         unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
 622         int ret;
 623
 624         dev->pg_event = MEI_PG_EVENT_WAIT;
 625
 626         ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
 627         if (ret)
 628                 return ret;
 629
 630         mutex_unlock(&dev->device_lock);
 631         wait_event_timeout(dev->wait_pg,
 632                 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
 633         mutex_lock(&dev->device_lock);
 634
 635         if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
 636                 mei_me_pg_set(dev);
 637                 ret = 0;
 638         } else {
 639                 ret = -ETIME;
 640         }
 641
 642         dev->pg_event = MEI_PG_EVENT_IDLE;
 643         hw->pg_state = MEI_PG_ON;
 644
 645         return ret;
 646 }
 647
 648 /**
 649  * mei_me_pg_exit_sync - perform pg exit procedure
 650  *
 651  * @dev: the device structure
 652  *
 653  * Return: 0 on success an error code otherwise
 654  */
 655 int mei_me_pg_exit_sync(struct mei_device *dev)
 656 {
 657         struct mei_me_hw *hw = to_me_hw(dev);
 658         unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
 659         int ret;
 660
 661         if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
 662                 goto reply;
 663
 664         dev->pg_event = MEI_PG_EVENT_WAIT;
 665
 666         mei_me_pg_unset(dev);
 667
 668         mutex_unlock(&dev->device_lock);
 669         wait_event_timeout(dev->wait_pg,
 670                 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
 671         mutex_lock(&dev->device_lock);
 672
 673 reply:
 674         if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
 675                 ret = -ETIME;
 676                 goto out;
 677         }
 678
 679         dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
 680         ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
 681         if (ret)
 682                 return ret;
 683
 684         mutex_unlock(&dev->device_lock);
 685         wait_event_timeout(dev->wait_pg,
 686                 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
 687         mutex_lock(&dev->device_lock);
 688
 689         if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)
 690                 ret = 0;
 691         else
 692                 ret = -ETIME;
 693
 694 out:
 695         dev->pg_event = MEI_PG_EVENT_IDLE;
 696         hw->pg_state = MEI_PG_OFF;
 697
 698         return ret;
 699 }
 700
 701 /**
 702  * mei_me_pg_in_transition - is device now in pg transition
 703  *
 704  * @dev: the device structure
 705  *
 706  * Return: true if in pg transition, false otherwise
 707  */
 708 static bool mei_me_pg_in_transition(struct mei_device *dev)
 709 {
 710         return dev->pg_event >= MEI_PG_EVENT_WAIT &&
 711                dev->pg_event <= MEI_PG_EVENT_INTR_WAIT;
 712 }
 713
 714 /**
 715  * mei_me_pg_is_enabled - detect if PG is supported by HW
 716  *
 717  * @dev: the device structure
 718  *
 719  * Return: true is pg supported, false otherwise
 720  */
 721 static bool mei_me_pg_is_enabled(struct mei_device *dev)
 722 {
 723         u32 reg = mei_me_mecsr_read(dev);
 724
 725         if ((reg & ME_PGIC_HRA) == 0)
 726                 goto notsupported;
 727
 728         if (!dev->hbm_f_pg_supported)
 729                 goto notsupported;
 730
 731         return true;
 732
 733 notsupported:
 734         dev_dbg(dev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n",
 735                 !!(reg & ME_PGIC_HRA),
 736                 dev->version.major_version,
 737                 dev->version.minor_version,
 738                 HBM_MAJOR_VERSION_PGI,
 739                 HBM_MINOR_VERSION_PGI);
 740
 741         return false;
 742 }
 743
 744 /**
 745  * mei_me_pg_intr - perform pg processing in interrupt thread handler
 746  *
 747  * @dev: the device structure
 748  */
 749 static void mei_me_pg_intr(struct mei_device *dev)
 750 {
 751         struct mei_me_hw *hw = to_me_hw(dev);
 752
 753         if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT)
 754                 return;
 755
 756         dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
 757         hw->pg_state = MEI_PG_OFF;
 758         if (waitqueue_active(&dev->wait_pg))
 759                 wake_up(&dev->wait_pg);
 760 }
 761
 762 /**
 763  * mei_me_irq_quick_handler - The ISR of the MEI device
 764  *
 765  * @irq: The irq number
 766  * @dev_id: pointer to the device structure
 767  *
 768  * Return: irqreturn_t
 769  */
 770 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
 771 {
 772         struct mei_device *dev = (struct mei_device *)dev_id;
 773         struct mei_me_hw *hw = to_me_hw(dev);
 774         u32 hcsr;
 775
 776         hcsr = mei_hcsr_read(dev);
 777         if (!(hcsr & H_CSR_IS_MASK))
 778                 return IRQ_NONE;
 779
 780         hw->intr_source = hcsr & H_CSR_IS_MASK;
 781         dev_dbg(dev->dev, "interrupt source 0x%08X.\n", hw->intr_source);
 782
 783         /* clear H_IS and H_D0I3C_IS bits in H_CSR to clear the interrupts */
 784         mei_hcsr_write(dev, hcsr);
 785
 786         return IRQ_WAKE_THREAD;
 787 }
 788
 789 /**
 790  * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
 791  * processing.
 792  *
 793  * @irq: The irq number
 794  * @dev_id: pointer to the device structure
 795  *
 796  * Return: irqreturn_t
 797  *
 798  */
 799 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
 800 {
 801         struct mei_device *dev = (struct mei_device *) dev_id;
 802         struct mei_cl_cb complete_list;
 803         s32 slots;
 804         int rets = 0;
 805
 806         dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n");
 807         /* initialize our complete list */
 808         mutex_lock(&dev->device_lock);
 809         mei_io_list_init(&complete_list);
 810
 811         /* check if ME wants a reset */
 812         if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
 813                 dev_warn(dev->dev, "FW not ready: resetting.\n");
 814                 schedule_work(&dev->reset_work);
 815                 goto end;
 816         }
 817
 818         mei_me_pg_intr(dev);
 819
 820         /*  check if we need to start the dev */
 821         if (!mei_host_is_ready(dev)) {
 822                 if (mei_hw_is_ready(dev)) {
 823                         dev_dbg(dev->dev, "we need to start the dev.\n");
 824                         dev->recvd_hw_ready = true;
 825                         wake_up(&dev->wait_hw_ready);
 826                 } else {
 827                         dev_dbg(dev->dev, "Spurious Interrupt\n");
 828                 }
 829                 goto end;
 830         }
 831         /* check slots available for reading */
 832         slots = mei_count_full_read_slots(dev);
 833         while (slots > 0) {
 834                 dev_dbg(dev->dev, "slots to read = %08x\n", slots);
 835                 rets = mei_irq_read_handler(dev, &complete_list, &slots);
 836                 /* There is a race between ME write and interrupt delivery:
 837                  * Not all data is always available immediately after the
 838                  * interrupt, so try to read again on the next interrupt.
 839                  */
 840                 if (rets == -ENODATA)
 841                         break;
 842
 843                 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
 844                         dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n",
 845                                                 rets);
 846                         schedule_work(&dev->reset_work);
 847                         goto end;
 848                 }
 849         }
 850
 851         dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
 852
 853         /*
 854          * During PG handshake only allowed write is the replay to the
 855          * PG exit message, so block calling write function
 856          * if the pg event is in PG handshake
 857          */
 858         if (dev->pg_event != MEI_PG_EVENT_WAIT &&
 859             dev->pg_event != MEI_PG_EVENT_RECEIVED) {
 860                 rets = mei_irq_write_handler(dev, &complete_list);
 861                 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
 862         }
 863
 864         mei_irq_compl_handler(dev, &complete_list);
 865
 866 end:
 867         dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
 868         mutex_unlock(&dev->device_lock);
 869         return IRQ_HANDLED;
 870 }
 871
 872 static const struct mei_hw_ops mei_me_hw_ops = {
 873
 874         .fw_status = mei_me_fw_status,
 875         .pg_state  = mei_me_pg_state,
 876
 877         .host_is_ready = mei_me_host_is_ready,
 878
 879         .hw_is_ready = mei_me_hw_is_ready,
 880         .hw_reset = mei_me_hw_reset,
 881         .hw_config = mei_me_hw_config,
 882         .hw_start = mei_me_hw_start,
 883
 884         .pg_in_transition = mei_me_pg_in_transition,
 885         .pg_is_enabled = mei_me_pg_is_enabled,
 886
 887         .intr_clear = mei_me_intr_clear,
 888         .intr_enable = mei_me_intr_enable,
 889         .intr_disable = mei_me_intr_disable,
 890
 891         .hbuf_free_slots = mei_me_hbuf_empty_slots,
 892         .hbuf_is_ready = mei_me_hbuf_is_empty,
 893         .hbuf_max_len = mei_me_hbuf_max_len,
 894
 895         .write = mei_me_write_message,
 896
 897         .rdbuf_full_slots = mei_me_count_full_read_slots,
 898         .read_hdr = mei_me_mecbrw_read,
 899         .read = mei_me_read_slots
 900 };
 901
 902 static bool mei_me_fw_type_nm(struct pci_dev *pdev)
 903 {
 904         u32 reg;
 905
 906         pci_read_config_dword(pdev, PCI_CFG_HFS_2, &reg);
 907         /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
 908         return (reg & 0x600) == 0x200;
 909 }
 910
 911 #define MEI_CFG_FW_NM                           \
 912         .quirk_probe = mei_me_fw_type_nm
 913
 914 static bool mei_me_fw_type_sps(struct pci_dev *pdev)
 915 {
 916         u32 reg;
 917         /* Read ME FW Status check for SPS Firmware */
 918         pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
 919         /* if bits [19:16] = 15, running SPS Firmware */
 920         return (reg & 0xf0000) == 0xf0000;
 921 }
 922
 923 #define MEI_CFG_FW_SPS                           \
 924         .quirk_probe = mei_me_fw_type_sps
 925
 926
 927 #define MEI_CFG_LEGACY_HFS                      \
 928         .fw_status.count = 0
 929
 930 #define MEI_CFG_ICH_HFS                        \
 931         .fw_status.count = 1,                   \
 932         .fw_status.status[0] = PCI_CFG_HFS_1
 933
 934 #define MEI_CFG_PCH_HFS                         \
 935         .fw_status.count = 2,                   \
 936         .fw_status.status[0] = PCI_CFG_HFS_1,   \
 937         .fw_status.status[1] = PCI_CFG_HFS_2
 938
 939 #define MEI_CFG_PCH8_HFS                        \
 940         .fw_status.count = 6,                   \
 941         .fw_status.status[0] = PCI_CFG_HFS_1,   \
 942         .fw_status.status[1] = PCI_CFG_HFS_2,   \
 943         .fw_status.status[2] = PCI_CFG_HFS_3,   \
 944         .fw_status.status[3] = PCI_CFG_HFS_4,   \
 945         .fw_status.status[4] = PCI_CFG_HFS_5,   \
 946         .fw_status.status[5] = PCI_CFG_HFS_6
 947
 948 /* ICH Legacy devices */
 949 const struct mei_cfg mei_me_legacy_cfg = {
 950         MEI_CFG_LEGACY_HFS,
 951 };
 952
 953 /* ICH devices */
 954 const struct mei_cfg mei_me_ich_cfg = {
 955         MEI_CFG_ICH_HFS,
 956 };
 957
 958 /* PCH devices */
 959 const struct mei_cfg mei_me_pch_cfg = {
 960         MEI_CFG_PCH_HFS,
 961 };
 962
 963
 964 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
 965 const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
 966         MEI_CFG_PCH_HFS,
 967         MEI_CFG_FW_NM,
 968 };
 969
 970 /* PCH8 Lynx Point and newer devices */
 971 const struct mei_cfg mei_me_pch8_cfg = {
 972         MEI_CFG_PCH8_HFS,
 973 };
 974
 975 /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */
 976 const struct mei_cfg mei_me_pch8_sps_cfg = {
 977         MEI_CFG_PCH8_HFS,
 978         MEI_CFG_FW_SPS,
 979 };
 980
 981 /**
 982  * mei_me_dev_init - allocates and initializes the mei device structure
 983  *
 984  * @pdev: The pci device structure
 985  * @cfg: per device generation config
 986  *
 987  * Return: The mei_device_device pointer on success, NULL on failure.
 988  */
 989 struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
 990                                    const struct mei_cfg *cfg)
 991 {
 992         struct mei_device *dev;
 993         struct mei_me_hw *hw;
 994
 995         dev = kzalloc(sizeof(struct mei_device) +
 996                          sizeof(struct mei_me_hw), GFP_KERNEL);
 997         if (!dev)
 998                 return NULL;
 999         hw = to_me_hw(dev);
1000
1001         mei_device_init(dev, &pdev->dev, &mei_me_hw_ops);
1002         hw->cfg = cfg;
1003         return dev;
1004 }
1005