2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
4 * This driver is heavily based upon:
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
14 * Look into engine reset on timeout errors. Should not be required.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/blkdev.h>
22 #include <linux/delay.h>
23 #include <scsi/scsi_host.h>
24 #include <linux/libata.h>
26 #define DRV_NAME "pata_hpt37x"
27 #define DRV_VERSION "0.6.14"
37 struct hpt_clock
const *clocks
[4];
40 /* key for bus clock timings
42 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
43 * DMA. cycles = value + 1
44 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
45 * DMA. cycles = value + 1
46 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
48 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
50 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
51 * during task file register access.
52 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
54 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
58 * 30 PIO_MST enable. if set, the chip is in bus master mode during
63 static struct hpt_clock hpt37x_timings_33
[] = {
64 { XFER_UDMA_6
, 0x12446231 }, /* 0x12646231 ?? */
65 { XFER_UDMA_5
, 0x12446231 },
66 { XFER_UDMA_4
, 0x12446231 },
67 { XFER_UDMA_3
, 0x126c6231 },
68 { XFER_UDMA_2
, 0x12486231 },
69 { XFER_UDMA_1
, 0x124c6233 },
70 { XFER_UDMA_0
, 0x12506297 },
72 { XFER_MW_DMA_2
, 0x22406c31 },
73 { XFER_MW_DMA_1
, 0x22406c33 },
74 { XFER_MW_DMA_0
, 0x22406c97 },
76 { XFER_PIO_4
, 0x06414e31 },
77 { XFER_PIO_3
, 0x06414e42 },
78 { XFER_PIO_2
, 0x06414e53 },
79 { XFER_PIO_1
, 0x06814e93 },
80 { XFER_PIO_0
, 0x06814ea7 }
83 static struct hpt_clock hpt37x_timings_50
[] = {
84 { XFER_UDMA_6
, 0x12848242 },
85 { XFER_UDMA_5
, 0x12848242 },
86 { XFER_UDMA_4
, 0x12ac8242 },
87 { XFER_UDMA_3
, 0x128c8242 },
88 { XFER_UDMA_2
, 0x120c8242 },
89 { XFER_UDMA_1
, 0x12148254 },
90 { XFER_UDMA_0
, 0x121882ea },
92 { XFER_MW_DMA_2
, 0x22808242 },
93 { XFER_MW_DMA_1
, 0x22808254 },
94 { XFER_MW_DMA_0
, 0x228082ea },
96 { XFER_PIO_4
, 0x0a81f442 },
97 { XFER_PIO_3
, 0x0a81f443 },
98 { XFER_PIO_2
, 0x0a81f454 },
99 { XFER_PIO_1
, 0x0ac1f465 },
100 { XFER_PIO_0
, 0x0ac1f48a }
103 static struct hpt_clock hpt37x_timings_66
[] = {
104 { XFER_UDMA_6
, 0x1c869c62 },
105 { XFER_UDMA_5
, 0x1cae9c62 }, /* 0x1c8a9c62 */
106 { XFER_UDMA_4
, 0x1c8a9c62 },
107 { XFER_UDMA_3
, 0x1c8e9c62 },
108 { XFER_UDMA_2
, 0x1c929c62 },
109 { XFER_UDMA_1
, 0x1c9a9c62 },
110 { XFER_UDMA_0
, 0x1c829c62 },
112 { XFER_MW_DMA_2
, 0x2c829c62 },
113 { XFER_MW_DMA_1
, 0x2c829c66 },
114 { XFER_MW_DMA_0
, 0x2c829d2e },
116 { XFER_PIO_4
, 0x0c829c62 },
117 { XFER_PIO_3
, 0x0c829c84 },
118 { XFER_PIO_2
, 0x0c829ca6 },
119 { XFER_PIO_1
, 0x0d029d26 },
120 { XFER_PIO_0
, 0x0d029d5e }
124 static const struct hpt_chip hpt370
= {
135 static const struct hpt_chip hpt370a
= {
146 static const struct hpt_chip hpt372
= {
157 static const struct hpt_chip hpt302
= {
168 static const struct hpt_chip hpt371
= {
179 static const struct hpt_chip hpt372a
= {
190 static const struct hpt_chip hpt374
= {
202 * hpt37x_find_mode - reset the hpt37x bus
204 * @speed: transfer mode
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
210 static u32
hpt37x_find_mode(struct ata_port
*ap
, int speed
)
212 struct hpt_clock
*clocks
= ap
->host
->private_data
;
214 while(clocks
->xfer_speed
) {
215 if (clocks
->xfer_speed
== speed
)
216 return clocks
->timing
;
220 return 0xffffffffU
; /* silence compiler warning */
223 static int hpt_dma_blacklisted(const struct ata_device
*dev
, char *modestr
, const char *list
[])
225 unsigned char model_num
[ATA_ID_PROD_LEN
+ 1];
228 ata_id_c_string(dev
->id
, model_num
, ATA_ID_PROD
, sizeof(model_num
));
230 while (list
[i
] != NULL
) {
231 if (!strcmp(list
[i
], model_num
)) {
232 printk(KERN_WARNING DRV_NAME
": %s is not supported for %s.\n",
241 static const char *bad_ata33
[] = {
242 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
243 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
244 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
248 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
252 static const char *bad_ata100_5
[] = {
272 * hpt370_filter - mode selection filter
275 * Block UDMA on devices that cause trouble with this controller.
278 static unsigned long hpt370_filter(struct ata_device
*adev
, unsigned long mask
)
280 if (adev
->class == ATA_DEV_ATA
) {
281 if (hpt_dma_blacklisted(adev
, "UDMA", bad_ata33
))
282 mask
&= ~ATA_MASK_UDMA
;
283 if (hpt_dma_blacklisted(adev
, "UDMA100", bad_ata100_5
))
284 mask
&= ~(0xE0 << ATA_SHIFT_UDMA
);
286 return ata_bmdma_mode_filter(adev
, mask
);
290 * hpt370a_filter - mode selection filter
293 * Block UDMA on devices that cause trouble with this controller.
296 static unsigned long hpt370a_filter(struct ata_device
*adev
, unsigned long mask
)
298 if (adev
->class == ATA_DEV_ATA
) {
299 if (hpt_dma_blacklisted(adev
, "UDMA100", bad_ata100_5
))
300 mask
&= ~(0xE0 << ATA_SHIFT_UDMA
);
302 return ata_bmdma_mode_filter(adev
, mask
);
306 * hpt37x_cable_detect - Detect the cable type
307 * @ap: ATA port to detect on
309 * Return the cable type attached to this port
312 static int hpt37x_cable_detect(struct ata_port
*ap
)
314 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
317 pci_read_config_byte(pdev
, 0x5B, &scr2
);
318 pci_write_config_byte(pdev
, 0x5B, scr2
& ~0x01);
320 udelay(10); /* debounce */
322 /* Cable register now active */
323 pci_read_config_byte(pdev
, 0x5A, &ata66
);
325 pci_write_config_byte(pdev
, 0x5B, scr2
);
327 if (ata66
& (2 >> ap
->port_no
))
328 return ATA_CBL_PATA40
;
330 return ATA_CBL_PATA80
;
334 * hpt374_fn1_cable_detect - Detect the cable type
335 * @ap: ATA port to detect on
337 * Return the cable type attached to this port
340 static int hpt374_fn1_cable_detect(struct ata_port
*ap
)
342 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
343 unsigned int mcrbase
= 0x50 + 4 * ap
->port_no
;
347 /* Do the extra channel work */
348 pci_read_config_word(pdev
, mcrbase
+ 2, &mcr3
);
349 /* Set bit 15 of 0x52 to enable TCBLID as input */
350 pci_write_config_word(pdev
, mcrbase
+ 2, mcr3
| 0x8000);
351 pci_read_config_byte(pdev
, 0x5A, &ata66
);
352 /* Reset TCBLID/FCBLID to output */
353 pci_write_config_word(pdev
, mcrbase
+ 2, mcr3
);
355 if (ata66
& (2 >> ap
->port_no
))
356 return ATA_CBL_PATA40
;
358 return ATA_CBL_PATA80
;
362 * hpt37x_pre_reset - reset the hpt37x bus
363 * @link: ATA link to reset
364 * @deadline: deadline jiffies for the operation
366 * Perform the initial reset handling for the HPT37x.
369 static int hpt37x_pre_reset(struct ata_link
*link
, unsigned long deadline
)
371 struct ata_port
*ap
= link
->ap
;
372 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
373 static const struct pci_bits hpt37x_enable_bits
[] = {
374 { 0x50, 1, 0x04, 0x04 },
375 { 0x54, 1, 0x04, 0x04 }
377 if (!pci_test_config_bits(pdev
, &hpt37x_enable_bits
[ap
->port_no
]))
380 /* Reset the state machine */
381 pci_write_config_byte(pdev
, 0x50 + 4 * ap
->port_no
, 0x37);
384 return ata_sff_prereset(link
, deadline
);
388 * hpt370_set_piomode - PIO setup
390 * @adev: device on the interface
392 * Perform PIO mode setup.
395 static void hpt370_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
397 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
403 addr1
= 0x40 + 4 * (adev
->devno
+ 2 * ap
->port_no
);
404 addr2
= 0x51 + 4 * ap
->port_no
;
406 /* Fast interrupt prediction disable, hold off interrupt disable */
407 pci_read_config_byte(pdev
, addr2
, &fast
);
410 pci_write_config_byte(pdev
, addr2
, fast
);
412 pci_read_config_dword(pdev
, addr1
, ®
);
413 mode
= hpt37x_find_mode(ap
, adev
->pio_mode
);
414 mode
&= 0xCFC3FFFF; /* Leave DMA bits alone */
415 reg
&= ~0xCFC3FFFF; /* Strip timing bits */
416 pci_write_config_dword(pdev
, addr1
, reg
| mode
);
420 * hpt370_set_dmamode - DMA timing setup
422 * @adev: Device being configured
424 * Set up the channel for MWDMA or UDMA modes. Much the same as with
425 * PIO, load the mode number and then set MWDMA or UDMA flag.
428 static void hpt370_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
430 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
435 addr1
= 0x40 + 4 * (adev
->devno
+ 2 * ap
->port_no
);
436 addr2
= 0x51 + 4 * ap
->port_no
;
438 /* Fast interrupt prediction disable, hold off interrupt disable */
439 pci_read_config_byte(pdev
, addr2
, &fast
);
442 pci_write_config_byte(pdev
, addr2
, fast
);
444 mask
= adev
->dma_mode
< XFER_UDMA_0
? 0x31C001FF : 0x303C0000;
446 pci_read_config_dword(pdev
, addr1
, ®
);
447 mode
= hpt37x_find_mode(ap
, adev
->dma_mode
);
450 pci_write_config_dword(pdev
, addr1
, reg
| mode
);
454 * hpt370_bmdma_end - DMA engine stop
457 * Work around the HPT370 DMA engine.
460 static void hpt370_bmdma_stop(struct ata_queued_cmd
*qc
)
462 struct ata_port
*ap
= qc
->ap
;
463 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
464 u8 dma_stat
= ioread8(ap
->ioaddr
.bmdma_addr
+ 2);
466 void __iomem
*bmdma
= ap
->ioaddr
.bmdma_addr
;
468 if (dma_stat
& 0x01) {
470 dma_stat
= ioread8(bmdma
+ 2);
472 if (dma_stat
& 0x01) {
473 /* Clear the engine */
474 pci_write_config_byte(pdev
, 0x50 + 4 * ap
->port_no
, 0x37);
477 dma_cmd
= ioread8(bmdma
);
478 iowrite8(dma_cmd
& 0xFE, bmdma
);
480 dma_stat
= ioread8(bmdma
+ 2);
481 iowrite8(dma_stat
| 0x06 , bmdma
+ 2);
482 /* Clear the engine */
483 pci_write_config_byte(pdev
, 0x50 + 4 * ap
->port_no
, 0x37);
490 * hpt372_set_piomode - PIO setup
492 * @adev: device on the interface
494 * Perform PIO mode setup.
497 static void hpt372_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
499 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
505 addr1
= 0x40 + 4 * (adev
->devno
+ 2 * ap
->port_no
);
506 addr2
= 0x51 + 4 * ap
->port_no
;
508 /* Fast interrupt prediction disable, hold off interrupt disable */
509 pci_read_config_byte(pdev
, addr2
, &fast
);
511 pci_write_config_byte(pdev
, addr2
, fast
);
513 pci_read_config_dword(pdev
, addr1
, ®
);
514 mode
= hpt37x_find_mode(ap
, adev
->pio_mode
);
516 printk("Find mode for %d reports %X\n", adev
->pio_mode
, mode
);
517 mode
&= 0xCFC3FFFF; /* Leave DMA bits alone */
518 reg
&= ~0xCFC3FFFF; /* Strip timing bits */
519 pci_write_config_dword(pdev
, addr1
, reg
| mode
);
523 * hpt372_set_dmamode - DMA timing setup
525 * @adev: Device being configured
527 * Set up the channel for MWDMA or UDMA modes. Much the same as with
528 * PIO, load the mode number and then set MWDMA or UDMA flag.
531 static void hpt372_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
533 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
538 addr1
= 0x40 + 4 * (adev
->devno
+ 2 * ap
->port_no
);
539 addr2
= 0x51 + 4 * ap
->port_no
;
541 /* Fast interrupt prediction disable, hold off interrupt disable */
542 pci_read_config_byte(pdev
, addr2
, &fast
);
544 pci_write_config_byte(pdev
, addr2
, fast
);
546 mask
= adev
->dma_mode
< XFER_UDMA_0
? 0x31C001FF : 0x303C0000;
548 pci_read_config_dword(pdev
, addr1
, ®
);
549 mode
= hpt37x_find_mode(ap
, adev
->dma_mode
);
550 printk("Find mode for DMA %d reports %X\n", adev
->dma_mode
, mode
);
553 pci_write_config_dword(pdev
, addr1
, reg
| mode
);
557 * hpt37x_bmdma_end - DMA engine stop
560 * Clean up after the HPT372 and later DMA engine
563 static void hpt37x_bmdma_stop(struct ata_queued_cmd
*qc
)
565 struct ata_port
*ap
= qc
->ap
;
566 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
567 int mscreg
= 0x50 + 4 * ap
->port_no
;
568 u8 bwsr_stat
, msc_stat
;
570 pci_read_config_byte(pdev
, 0x6A, &bwsr_stat
);
571 pci_read_config_byte(pdev
, mscreg
, &msc_stat
);
572 if (bwsr_stat
& (1 << ap
->port_no
))
573 pci_write_config_byte(pdev
, mscreg
, msc_stat
| 0x30);
578 static struct scsi_host_template hpt37x_sht
= {
579 ATA_BMDMA_SHT(DRV_NAME
),
583 * Configuration for HPT370
586 static struct ata_port_operations hpt370_port_ops
= {
587 .inherits
= &ata_bmdma_port_ops
,
589 .bmdma_stop
= hpt370_bmdma_stop
,
591 .mode_filter
= hpt370_filter
,
592 .cable_detect
= hpt37x_cable_detect
,
593 .set_piomode
= hpt370_set_piomode
,
594 .set_dmamode
= hpt370_set_dmamode
,
595 .prereset
= hpt37x_pre_reset
,
599 * Configuration for HPT370A. Close to 370 but less filters
602 static struct ata_port_operations hpt370a_port_ops
= {
603 .inherits
= &hpt370_port_ops
,
604 .mode_filter
= hpt370a_filter
,
608 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
609 * and DMA mode setting functionality.
612 static struct ata_port_operations hpt372_port_ops
= {
613 .inherits
= &ata_bmdma_port_ops
,
615 .bmdma_stop
= hpt37x_bmdma_stop
,
617 .cable_detect
= hpt37x_cable_detect
,
618 .set_piomode
= hpt372_set_piomode
,
619 .set_dmamode
= hpt372_set_dmamode
,
620 .prereset
= hpt37x_pre_reset
,
624 * Configuration for HPT374. Mode setting works like 372 and friends
625 * but we have a different cable detection procedure for function 1.
628 static struct ata_port_operations hpt374_fn1_port_ops
= {
629 .inherits
= &hpt372_port_ops
,
630 .cable_detect
= hpt374_fn1_cable_detect
,
631 .prereset
= hpt37x_pre_reset
,
635 * hpt37x_clock_slot - Turn timing to PC clock entry
636 * @freq: Reported frequency timing
639 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
643 static int hpt37x_clock_slot(unsigned int freq
, unsigned int base
)
645 unsigned int f
= (base
* freq
) / 192; /* Mhz */
647 return 0; /* 33Mhz slot */
649 return 1; /* 40Mhz slot */
651 return 2; /* 50Mhz slot */
652 return 3; /* 60Mhz slot */
656 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
659 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
663 static int hpt37x_calibrate_dpll(struct pci_dev
*dev
)
669 for(tries
= 0; tries
< 0x5000; tries
++) {
671 pci_read_config_byte(dev
, 0x5b, ®5b
);
673 /* See if it stays set */
674 for(tries
= 0; tries
< 0x1000; tries
++) {
675 pci_read_config_byte(dev
, 0x5b, ®5b
);
677 if ((reg5b
& 0x80) == 0)
680 /* Turn off tuning, we have the DPLL set */
681 pci_read_config_dword(dev
, 0x5c, ®5c
);
682 pci_write_config_dword(dev
, 0x5c, reg5c
& ~ 0x100);
686 /* Never went stable */
690 static u32
hpt374_read_freq(struct pci_dev
*pdev
)
693 unsigned long io_base
= pci_resource_start(pdev
, 4);
694 if (PCI_FUNC(pdev
->devfn
) & 1) {
695 struct pci_dev
*pdev_0
;
697 pdev_0
= pci_get_slot(pdev
->bus
, pdev
->devfn
- 1);
698 /* Someone hot plugged the controller on us ? */
701 io_base
= pci_resource_start(pdev_0
, 4);
702 freq
= inl(io_base
+ 0x90);
705 freq
= inl(io_base
+ 0x90);
710 * hpt37x_init_one - Initialise an HPT37X/302
712 * @id: Entry in match table
714 * Initialise an HPT37x device. There are some interesting complications
715 * here. Firstly the chip may report 366 and be one of several variants.
716 * Secondly all the timings depend on the clock for the chip which we must
719 * This is the known chip mappings. It may be missing a couple of later
722 * Chip version PCI Rev Notes
723 * HPT366 4 (HPT366) 0 Other driver
724 * HPT366 4 (HPT366) 1 Other driver
725 * HPT368 4 (HPT366) 2 Other driver
726 * HPT370 4 (HPT366) 3 UDMA100
727 * HPT370A 4 (HPT366) 4 UDMA100
728 * HPT372 4 (HPT366) 5 UDMA133 (1)
729 * HPT372N 4 (HPT366) 6 Other driver
730 * HPT372A 5 (HPT372) 1 UDMA133 (1)
731 * HPT372N 5 (HPT372) 2 Other driver
732 * HPT302 6 (HPT302) 1 UDMA133
733 * HPT302N 6 (HPT302) 2 Other driver
734 * HPT371 7 (HPT371) * UDMA133
735 * HPT374 8 (HPT374) * UDMA133 4 channel
736 * HPT372N 9 (HPT372N) * Other driver
738 * (1) UDMA133 support depends on the bus clock
741 static int hpt37x_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
743 /* HPT370 - UDMA100 */
744 static const struct ata_port_info info_hpt370
= {
745 .flags
= ATA_FLAG_SLAVE_POSS
,
746 .pio_mask
= ATA_PIO4
,
747 .mwdma_mask
= ATA_MWDMA2
,
748 .udma_mask
= ATA_UDMA5
,
749 .port_ops
= &hpt370_port_ops
751 /* HPT370A - UDMA100 */
752 static const struct ata_port_info info_hpt370a
= {
753 .flags
= ATA_FLAG_SLAVE_POSS
,
754 .pio_mask
= ATA_PIO4
,
755 .mwdma_mask
= ATA_MWDMA2
,
756 .udma_mask
= ATA_UDMA5
,
757 .port_ops
= &hpt370a_port_ops
759 /* HPT370 - UDMA100 */
760 static const struct ata_port_info info_hpt370_33
= {
761 .flags
= ATA_FLAG_SLAVE_POSS
,
762 .pio_mask
= ATA_PIO4
,
763 .mwdma_mask
= ATA_MWDMA2
,
764 .udma_mask
= ATA_UDMA5
,
765 .port_ops
= &hpt370_port_ops
767 /* HPT370A - UDMA100 */
768 static const struct ata_port_info info_hpt370a_33
= {
769 .flags
= ATA_FLAG_SLAVE_POSS
,
770 .pio_mask
= ATA_PIO4
,
771 .mwdma_mask
= ATA_MWDMA2
,
772 .udma_mask
= ATA_UDMA5
,
773 .port_ops
= &hpt370a_port_ops
775 /* HPT371, 372 and friends - UDMA133 */
776 static const struct ata_port_info info_hpt372
= {
777 .flags
= ATA_FLAG_SLAVE_POSS
,
778 .pio_mask
= ATA_PIO4
,
779 .mwdma_mask
= ATA_MWDMA2
,
780 .udma_mask
= ATA_UDMA6
,
781 .port_ops
= &hpt372_port_ops
783 /* HPT374 - UDMA100, function 1 uses different prereset method */
784 static const struct ata_port_info info_hpt374_fn0
= {
785 .flags
= ATA_FLAG_SLAVE_POSS
,
786 .pio_mask
= ATA_PIO4
,
787 .mwdma_mask
= ATA_MWDMA2
,
788 .udma_mask
= ATA_UDMA5
,
789 .port_ops
= &hpt372_port_ops
791 static const struct ata_port_info info_hpt374_fn1
= {
792 .flags
= ATA_FLAG_SLAVE_POSS
,
793 .pio_mask
= ATA_PIO4
,
794 .mwdma_mask
= ATA_MWDMA2
,
795 .udma_mask
= ATA_UDMA5
,
796 .port_ops
= &hpt374_fn1_port_ops
799 static const int MHz
[4] = { 33, 40, 50, 66 };
800 void *private_data
= NULL
;
801 const struct ata_port_info
*ppi
[] = { NULL
, NULL
};
802 u8 rev
= dev
->revision
;
808 unsigned long iobase
= pci_resource_start(dev
, 4);
810 const struct hpt_chip
*chip_table
;
814 rc
= pcim_enable_device(dev
);
818 if (dev
->device
== PCI_DEVICE_ID_TTI_HPT366
) {
819 /* May be a later chip in disguise. Check */
820 /* Older chips are in the HPT366 driver. Ignore them */
823 /* N series chips have their own driver. Ignore */
829 ppi
[0] = &info_hpt370
;
830 chip_table
= &hpt370
;
834 ppi
[0] = &info_hpt370a
;
835 chip_table
= &hpt370a
;
839 ppi
[0] = &info_hpt372
;
840 chip_table
= &hpt372
;
843 printk(KERN_ERR
"pata_hpt37x: Unknown HPT366 "
844 "subtype, please report (%d).\n", rev
);
848 switch(dev
->device
) {
849 case PCI_DEVICE_ID_TTI_HPT372
:
850 /* 372N if rev >= 2*/
853 ppi
[0] = &info_hpt372
;
854 chip_table
= &hpt372a
;
856 case PCI_DEVICE_ID_TTI_HPT302
:
857 /* 302N if rev > 1 */
860 ppi
[0] = &info_hpt372
;
862 chip_table
= &hpt302
;
864 case PCI_DEVICE_ID_TTI_HPT371
:
867 ppi
[0] = &info_hpt372
;
868 chip_table
= &hpt371
;
869 /* Single channel device, master is not present
870 but the BIOS (or us for non x86) must mark it
872 pci_read_config_byte(dev
, 0x50, &mcr1
);
874 pci_write_config_byte(dev
, 0x50, mcr1
);
876 case PCI_DEVICE_ID_TTI_HPT374
:
877 chip_table
= &hpt374
;
878 if (!(PCI_FUNC(dev
->devfn
) & 1))
879 *ppi
= &info_hpt374_fn0
;
881 *ppi
= &info_hpt374_fn1
;
884 printk(KERN_ERR
"pata_hpt37x: PCI table is bogus please report (%d).\n", dev
->device
);
888 /* Ok so this is a chip we support */
890 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, (L1_CACHE_BYTES
/ 4));
891 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x78);
892 pci_write_config_byte(dev
, PCI_MIN_GNT
, 0x08);
893 pci_write_config_byte(dev
, PCI_MAX_LAT
, 0x08);
895 pci_read_config_byte(dev
, 0x5A, &irqmask
);
897 pci_write_config_byte(dev
, 0x5a, irqmask
);
900 * default to pci clock. make sure MA15/16 are set to output
901 * to prevent drives having problems with 40-pin cables. Needed
902 * for some drives such as IBM-DTLA which will not enter ready
903 * state on reset when PDIAG is a input.
906 pci_write_config_byte(dev
, 0x5b, 0x23);
909 * HighPoint does this for HPT372A.
910 * NOTE: This register is only writeable via I/O space.
912 if (chip_table
== &hpt372a
)
913 outb(0x0e, iobase
+ 0x9c);
915 /* Some devices do not let this value be accessed via PCI space
916 according to the old driver. In addition we must use the value
917 from FN 0 on the HPT374 */
919 if (chip_table
== &hpt374
) {
920 freq
= hpt374_read_freq(dev
);
924 freq
= inl(iobase
+ 0x90);
926 if ((freq
>> 12) != 0xABCDE) {
931 printk(KERN_WARNING
"pata_hpt37x: BIOS has not set timing clocks.\n");
933 /* This is the process the HPT371 BIOS is reported to use */
934 for(i
= 0; i
< 128; i
++) {
935 pci_read_config_byte(dev
, 0x78, &sr
);
944 * Turn the frequency check into a band and then find a timing
948 clock_slot
= hpt37x_clock_slot(freq
, chip_table
->base
);
949 if (chip_table
->clocks
[clock_slot
] == NULL
|| prefer_dpll
) {
951 * We need to try PLL mode instead
953 * For non UDMA133 capable devices we should
954 * use a 50MHz DPLL by choice
956 unsigned int f_low
, f_high
;
960 dpll
= (ppi
[0]->udma_mask
& 0xC0) ? 3 : 2;
962 f_low
= (MHz
[clock_slot
] * 48) / MHz
[dpll
];
967 /* Select the DPLL clock. */
968 pci_write_config_byte(dev
, 0x5b, 0x21);
969 pci_write_config_dword(dev
, 0x5C, (f_high
<< 16) | f_low
| 0x100);
971 for(adjust
= 0; adjust
< 8; adjust
++) {
972 if (hpt37x_calibrate_dpll(dev
))
974 /* See if it'll settle at a fractionally different clock */
976 f_low
-= adjust
>> 1;
978 f_high
+= adjust
>> 1;
979 pci_write_config_dword(dev
, 0x5C, (f_high
<< 16) | f_low
| 0x100);
982 printk(KERN_ERR
"pata_hpt37x: DPLL did not stabilize!\n");
986 private_data
= (void *)hpt37x_timings_66
;
988 private_data
= (void *)hpt37x_timings_50
;
990 printk(KERN_INFO
"pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
991 MHz
[clock_slot
], MHz
[dpll
]);
993 private_data
= (void *)chip_table
->clocks
[clock_slot
];
995 * Perform a final fixup. Note that we will have used the
996 * DPLL on the HPT372 which means we don't have to worry
997 * about lack of UDMA133 support on lower clocks
1000 if (clock_slot
< 2 && ppi
[0] == &info_hpt370
)
1001 ppi
[0] = &info_hpt370_33
;
1002 if (clock_slot
< 2 && ppi
[0] == &info_hpt370a
)
1003 ppi
[0] = &info_hpt370a_33
;
1004 printk(KERN_INFO
"pata_hpt37x: %s using %dMHz bus clock.\n",
1005 chip_table
->name
, MHz
[clock_slot
]);
1008 /* Now kick off ATA set up */
1009 return ata_pci_sff_init_one(dev
, ppi
, &hpt37x_sht
, private_data
);
1012 static const struct pci_device_id hpt37x
[] = {
1013 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT366
), },
1014 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT371
), },
1015 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT372
), },
1016 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT374
), },
1017 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT302
), },
1022 static struct pci_driver hpt37x_pci_driver
= {
1025 .probe
= hpt37x_init_one
,
1026 .remove
= ata_pci_remove_one
1029 static int __init
hpt37x_init(void)
1031 return pci_register_driver(&hpt37x_pci_driver
);
1034 static void __exit
hpt37x_exit(void)
1036 pci_unregister_driver(&hpt37x_pci_driver
);
1039 MODULE_AUTHOR("Alan Cox");
1040 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1041 MODULE_LICENSE("GPL");
1042 MODULE_DEVICE_TABLE(pci
, hpt37x
);
1043 MODULE_VERSION(DRV_VERSION
);
1045 module_init(hpt37x_init
);
1046 module_exit(hpt37x_exit
);