arch/arm/mach-sa1100/irq.c

   1 /*
   2  * linux/arch/arm/mach-sa1100/irq.c
   3  *
   4  * Copyright (C) 1999-2001 Nicolas Pitre
   5  *
   6  * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/ioport.h>
  19 #include <linux/syscore_ops.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/irqs.h>
  23 #include <asm/mach/irq.h>
  24 #include <asm/exception.h>
  25
  26 #include "generic.h"
  27
  28
  29 /*
  30  * SA1100 GPIO edge detection for IRQs:
  31  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
  32  * Use this instead of directly setting GRER/GFER.
  33  */
  34 static int GPIO_IRQ_rising_edge;
  35 static int GPIO_IRQ_falling_edge;
  36 static int GPIO_IRQ_mask = (1 << 11) - 1;
  37
  38 /*
  39  * To get the GPIO number from an IRQ number
  40  */
  41 #define GPIO_11_27_IRQ(i)       ((i) + 11 - IRQ_GPIO11)
  42 #define GPIO11_27_MASK(irq)     (1 << GPIO_11_27_IRQ(irq))
  43
  44 static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
  45 {
  46         unsigned int mask;
  47
  48         if (d->irq <= IRQ_GPIO10)
  49                 mask = 1 << d->irq;
  50         else
  51                 mask = GPIO11_27_MASK(d->irq);
  52
  53         if (type == IRQ_TYPE_PROBE) {
  54                 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
  55                         return 0;
  56                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  57         }
  58
  59         if (type & IRQ_TYPE_EDGE_RISING) {
  60                 GPIO_IRQ_rising_edge |= mask;
  61         } else
  62                 GPIO_IRQ_rising_edge &= ~mask;
  63         if (type & IRQ_TYPE_EDGE_FALLING) {
  64                 GPIO_IRQ_falling_edge |= mask;
  65         } else
  66                 GPIO_IRQ_falling_edge &= ~mask;
  67
  68         GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
  69         GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
  70
  71         return 0;
  72 }
  73
  74 /*
  75  * GPIO IRQs must be acknowledged.  This is for IRQs from GPIO0 to 10.
  76  */
  77 static void sa1100_low_gpio_ack(struct irq_data *d)
  78 {
  79         GEDR = (1 << d->irq);
  80 }
  81
  82 static void sa1100_low_gpio_mask(struct irq_data *d)
  83 {
  84         ICMR &= ~(1 << d->irq);
  85 }
  86
  87 static void sa1100_low_gpio_unmask(struct irq_data *d)
  88 {
  89         ICMR |= 1 << d->irq;
  90 }
  91
  92 static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
  93 {
  94         if (on)
  95                 PWER |= 1 << d->irq;
  96         else
  97                 PWER &= ~(1 << d->irq);
  98         return 0;
  99 }
 100
 101 static struct irq_chip sa1100_low_gpio_chip = {
 102         .name           = "GPIO-l",
 103         .irq_ack        = sa1100_low_gpio_ack,
 104         .irq_mask       = sa1100_low_gpio_mask,
 105         .irq_unmask     = sa1100_low_gpio_unmask,
 106         .irq_set_type   = sa1100_gpio_type,
 107         .irq_set_wake   = sa1100_low_gpio_wake,
 108 };
 109
 110 static int sa1100_low_gpio_irqdomain_map(struct irq_domain *d,
 111                 unsigned int irq, irq_hw_number_t hwirq)
 112 {
 113         irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
 114                                  handle_edge_irq);
 115         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 116
 117         return 0;
 118 }
 119
 120 static struct irq_domain_ops sa1100_low_gpio_irqdomain_ops = {
 121         .map = sa1100_low_gpio_irqdomain_map,
 122         .xlate = irq_domain_xlate_onetwocell,
 123 };
 124
 125 static struct irq_domain *sa1100_low_gpio_irqdomain;
 126
 127 /*
 128  * IRQ11 (GPIO11 through 27) handler.  We enter here with the
 129  * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
 130  * and call the handler.
 131  */
 132 static void
 133 sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
 134 {
 135         unsigned int mask;
 136
 137         mask = GEDR & 0xfffff800;
 138         do {
 139                 /*
 140                  * clear down all currently active IRQ sources.
 141                  * We will be processing them all.
 142                  */
 143                 GEDR = mask;
 144
 145                 irq = IRQ_GPIO11;
 146                 mask >>= 11;
 147                 do {
 148                         if (mask & 1)
 149                                 generic_handle_irq(irq);
 150                         mask >>= 1;
 151                         irq++;
 152                 } while (mask);
 153
 154                 mask = GEDR & 0xfffff800;
 155         } while (mask);
 156 }
 157
 158 /*
 159  * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
 160  * In addition, the IRQs are all collected up into one bit in the
 161  * interrupt controller registers.
 162  */
 163 static void sa1100_high_gpio_ack(struct irq_data *d)
 164 {
 165         unsigned int mask = GPIO11_27_MASK(d->irq);
 166
 167         GEDR = mask;
 168 }
 169
 170 static void sa1100_high_gpio_mask(struct irq_data *d)
 171 {
 172         unsigned int mask = GPIO11_27_MASK(d->irq);
 173
 174         GPIO_IRQ_mask &= ~mask;
 175
 176         GRER &= ~mask;
 177         GFER &= ~mask;
 178 }
 179
 180 static void sa1100_high_gpio_unmask(struct irq_data *d)
 181 {
 182         unsigned int mask = GPIO11_27_MASK(d->irq);
 183
 184         GPIO_IRQ_mask |= mask;
 185
 186         GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
 187         GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
 188 }
 189
 190 static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
 191 {
 192         if (on)
 193                 PWER |= GPIO11_27_MASK(d->irq);
 194         else
 195                 PWER &= ~GPIO11_27_MASK(d->irq);
 196         return 0;
 197 }
 198
 199 static struct irq_chip sa1100_high_gpio_chip = {
 200         .name           = "GPIO-h",
 201         .irq_ack        = sa1100_high_gpio_ack,
 202         .irq_mask       = sa1100_high_gpio_mask,
 203         .irq_unmask     = sa1100_high_gpio_unmask,
 204         .irq_set_type   = sa1100_gpio_type,
 205         .irq_set_wake   = sa1100_high_gpio_wake,
 206 };
 207
 208 static int sa1100_high_gpio_irqdomain_map(struct irq_domain *d,
 209                 unsigned int irq, irq_hw_number_t hwirq)
 210 {
 211         irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
 212                                  handle_edge_irq);
 213         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 214
 215         return 0;
 216 }
 217
 218 static struct irq_domain_ops sa1100_high_gpio_irqdomain_ops = {
 219         .map = sa1100_high_gpio_irqdomain_map,
 220         .xlate = irq_domain_xlate_onetwocell,
 221 };
 222
 223 static struct irq_domain *sa1100_high_gpio_irqdomain;
 224
 225 /*
 226  * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
 227  * this is for internal IRQs i.e. from IRQ LCD to RTCAlrm.
 228  */
 229 static void sa1100_mask_irq(struct irq_data *d)
 230 {
 231         ICMR &= ~(1 << d->irq);
 232 }
 233
 234 static void sa1100_unmask_irq(struct irq_data *d)
 235 {
 236         ICMR |= (1 << d->irq);
 237 }
 238
 239 /*
 240  * Apart form GPIOs, only the RTC alarm can be a wakeup event.
 241  */
 242 static int sa1100_set_wake(struct irq_data *d, unsigned int on)
 243 {
 244         if (d->irq == IRQ_RTCAlrm) {
 245                 if (on)
 246                         PWER |= PWER_RTC;
 247                 else
 248                         PWER &= ~PWER_RTC;
 249                 return 0;
 250         }
 251         return -EINVAL;
 252 }
 253
 254 static struct irq_chip sa1100_normal_chip = {
 255         .name           = "SC",
 256         .irq_ack        = sa1100_mask_irq,
 257         .irq_mask       = sa1100_mask_irq,
 258         .irq_unmask     = sa1100_unmask_irq,
 259         .irq_set_wake   = sa1100_set_wake,
 260 };
 261
 262 static int sa1100_normal_irqdomain_map(struct irq_domain *d,
 263                 unsigned int irq, irq_hw_number_t hwirq)
 264 {
 265         irq_set_chip_and_handler(irq, &sa1100_normal_chip,
 266                                  handle_level_irq);
 267         set_irq_flags(irq, IRQF_VALID);
 268
 269         return 0;
 270 }
 271
 272 static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
 273         .map = sa1100_normal_irqdomain_map,
 274         .xlate = irq_domain_xlate_onetwocell,
 275 };
 276
 277 static struct irq_domain *sa1100_normal_irqdomain;
 278
 279 static struct resource irq_resource =
 280         DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
 281
 282 static struct sa1100irq_state {
 283         unsigned int    saved;
 284         unsigned int    icmr;
 285         unsigned int    iclr;
 286         unsigned int    iccr;
 287 } sa1100irq_state;
 288
 289 static int sa1100irq_suspend(void)
 290 {
 291         struct sa1100irq_state *st = &sa1100irq_state;
 292
 293         st->saved = 1;
 294         st->icmr = ICMR;
 295         st->iclr = ICLR;
 296         st->iccr = ICCR;
 297
 298         /*
 299          * Disable all GPIO-based interrupts.
 300          */
 301         ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
 302                   IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
 303                   IC_GPIO1|IC_GPIO0);
 304
 305         /*
 306          * Set the appropriate edges for wakeup.
 307          */
 308         GRER = PWER & GPIO_IRQ_rising_edge;
 309         GFER = PWER & GPIO_IRQ_falling_edge;
 310
 311         /*
 312          * Clear any pending GPIO interrupts.
 313          */
 314         GEDR = GEDR;
 315
 316         return 0;
 317 }
 318
 319 static void sa1100irq_resume(void)
 320 {
 321         struct sa1100irq_state *st = &sa1100irq_state;
 322
 323         if (st->saved) {
 324                 ICCR = st->iccr;
 325                 ICLR = st->iclr;
 326
 327                 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
 328                 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
 329
 330                 ICMR = st->icmr;
 331         }
 332 }
 333
 334 static struct syscore_ops sa1100irq_syscore_ops = {
 335         .suspend        = sa1100irq_suspend,
 336         .resume         = sa1100irq_resume,
 337 };
 338
 339 static int __init sa1100irq_init_devicefs(void)
 340 {
 341         register_syscore_ops(&sa1100irq_syscore_ops);
 342         return 0;
 343 }
 344
 345 device_initcall(sa1100irq_init_devicefs);
 346
 347 static asmlinkage void __exception_irq_entry
 348 sa1100_handle_irq(struct pt_regs *regs)
 349 {
 350         uint32_t icip, icmr, mask;
 351
 352         do {
 353                 icip = (ICIP);
 354                 icmr = (ICMR);
 355                 mask = icip & icmr;
 356
 357                 if (mask == 0)
 358                         break;
 359
 360                 handle_IRQ(ffs(mask) - 1 + IRQ_GPIO0, regs);
 361         } while (1);
 362 }
 363
 364 void __init sa1100_init_irq(void)
 365 {
 366         request_resource(&iomem_resource, &irq_resource);
 367
 368         /* disable all IRQs */
 369         ICMR = 0;
 370
 371         /* all IRQs are IRQ, not FIQ */
 372         ICLR = 0;
 373
 374         /* clear all GPIO edge detects */
 375         GFER = 0;
 376         GRER = 0;
 377         GEDR = -1;
 378
 379         /*
 380          * Whatever the doc says, this has to be set for the wait-on-irq
 381          * instruction to work... on a SA1100 rev 9 at least.
 382          */
 383         ICCR = 1;
 384
 385         sa1100_low_gpio_irqdomain = irq_domain_add_legacy(NULL,
 386                         11, IRQ_GPIO0, 0,
 387                         &sa1100_low_gpio_irqdomain_ops, NULL);
 388
 389         sa1100_normal_irqdomain = irq_domain_add_legacy(NULL,
 390                         20, IRQ_LCD, 12,
 391                         &sa1100_normal_irqdomain_ops, NULL);
 392
 393         sa1100_high_gpio_irqdomain = irq_domain_add_legacy(NULL,
 394                         17, IRQ_GPIO11, 11,
 395                         &sa1100_high_gpio_irqdomain_ops, NULL);
 396
 397         /*
 398          * Install handler for GPIO 11-27 edge detect interrupts
 399          */
 400         irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
 401         irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
 402
 403         set_handle_irq(sa1100_handle_irq);
 404
 405         sa1100_init_gpio();
 406 }