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mlx4_en: Use netif_set_real_num_{rx, tx}_queues()
[linux-2.6/btrfs-unstable.git] / drivers / net / jme.h
blob1360f68861b8c6d22205c7a16019e8723ff322be
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24 #ifndef __JME_H_INCLUDED__
25 #define __JME_H_INCLUDED__
26
27 #define DRV_NAME "jme"
28 #define DRV_VERSION "1.0.6"
29 #define PFX DRV_NAME ": "
30
31 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
32 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
33
34 /*
35 * Message related definitions
36 */
37 #define JME_DEF_MSG_ENABLE \
38 (NETIF_MSG_PROBE | \
39 NETIF_MSG_LINK | \
40 NETIF_MSG_RX_ERR | \
41 NETIF_MSG_TX_ERR | \
42 NETIF_MSG_HW)
43
44 #ifdef TX_DEBUG
45 #define tx_dbg(priv, fmt, args...) \
46 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
47 #else
48 #define tx_dbg(priv, fmt, args...) \
49 do { \
50 if (0) \
51 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
52 } while (0)
53 #endif
54
55 /*
56 * Extra PCI Configuration space interface
57 */
58 #define PCI_DCSR_MRRS 0x59
59 #define PCI_DCSR_MRRS_MASK 0x70
60
61 enum pci_dcsr_mrrs_vals {
62 MRRS_128B = 0x00,
63 MRRS_256B = 0x10,
64 MRRS_512B = 0x20,
65 MRRS_1024B = 0x30,
66 MRRS_2048B = 0x40,
67 MRRS_4096B = 0x50,
68 };
69
70 #define PCI_SPI 0xB0
71
72 enum pci_spi_bits {
73 SPI_EN = 0x10,
74 SPI_MISO = 0x08,
75 SPI_MOSI = 0x04,
76 SPI_SCLK = 0x02,
77 SPI_CS = 0x01,
78 };
79
80 struct jme_spi_op {
81 void __user *uwbuf;
82 void __user *urbuf;
83 __u8 wn; /* Number of write actions */
84 __u8 rn; /* Number of read actions */
85 __u8 bitn; /* Number of bits per action */
86 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
87 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
88
89 /* Internal use only */
90 u8 *kwbuf;
91 u8 *krbuf;
92 u8 sr;
93 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
94 };
95
96 enum jme_spi_op_bits {
97 SPI_MODE_CPHA = 0x01,
98 SPI_MODE_CPOL = 0x02,
99 SPI_MODE_DUP = 0x80,
100 };
101
102 #define HALF_US 500 /* 500 ns */
103 #define JMESPIIOCTL SIOCDEVPRIVATE
104
105 /*
106 * Dynamic(adaptive)/Static PCC values
107 */
108 enum dynamic_pcc_values {
109 PCC_OFF = 0,
110 PCC_P1 = 1,
111 PCC_P2 = 2,
112 PCC_P3 = 3,
113
114 PCC_OFF_TO = 0,
115 PCC_P1_TO = 1,
116 PCC_P2_TO = 64,
117 PCC_P3_TO = 128,
118
119 PCC_OFF_CNT = 0,
120 PCC_P1_CNT = 1,
121 PCC_P2_CNT = 16,
122 PCC_P3_CNT = 32,
123 };
124 struct dynpcc_info {
125 unsigned long last_bytes;
126 unsigned long last_pkts;
127 unsigned long intr_cnt;
128 unsigned char cur;
129 unsigned char attempt;
130 unsigned char cnt;
131 };
132 #define PCC_INTERVAL_US 100000
133 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
134 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
135 #define PCC_P2_THRESHOLD 800
136 #define PCC_INTR_THRESHOLD 800
137 #define PCC_TX_TO 1000
138 #define PCC_TX_CNT 8
139
140 /*
141 * TX/RX Descriptors
142 *
143 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
144 */
145 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
146 #define TX_DESC_SIZE 16
147 #define TX_RING_NR 8
148 #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
149
150 struct txdesc {
151 union {
152 __u8 all[16];
153 __le32 dw[4];
154 struct {
155 /* DW0 */
156 __le16 vlan;
157 __u8 rsv1;
158 __u8 flags;
159
160 /* DW1 */
161 __le16 datalen;
162 __le16 mss;
163
164 /* DW2 */
165 __le16 pktsize;
166 __le16 rsv2;
167
168 /* DW3 */
169 __le32 bufaddr;
170 } desc1;
171 struct {
172 /* DW0 */
173 __le16 rsv1;
174 __u8 rsv2;
175 __u8 flags;
176
177 /* DW1 */
178 __le16 datalen;
179 __le16 rsv3;
180
181 /* DW2 */
182 __le32 bufaddrh;
183
184 /* DW3 */
185 __le32 bufaddrl;
186 } desc2;
187 struct {
188 /* DW0 */
189 __u8 ehdrsz;
190 __u8 rsv1;
191 __u8 rsv2;
192 __u8 flags;
193
194 /* DW1 */
195 __le16 trycnt;
196 __le16 segcnt;
197
198 /* DW2 */
199 __le16 pktsz;
200 __le16 rsv3;
201
202 /* DW3 */
203 __le32 bufaddrl;
204 } descwb;
205 };
206 };
207
208 enum jme_txdesc_flags_bits {
209 TXFLAG_OWN = 0x80,
210 TXFLAG_INT = 0x40,
211 TXFLAG_64BIT = 0x20,
212 TXFLAG_TCPCS = 0x10,
213 TXFLAG_UDPCS = 0x08,
214 TXFLAG_IPCS = 0x04,
215 TXFLAG_LSEN = 0x02,
216 TXFLAG_TAGON = 0x01,
217 };
218
219 #define TXDESC_MSS_SHIFT 2
220 enum jme_txwbdesc_flags_bits {
221 TXWBFLAG_OWN = 0x80,
222 TXWBFLAG_INT = 0x40,
223 TXWBFLAG_TMOUT = 0x20,
224 TXWBFLAG_TRYOUT = 0x10,
225 TXWBFLAG_COL = 0x08,
226
227 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
228 TXWBFLAG_TRYOUT |
229 TXWBFLAG_COL,
230 };
231
232 #define RX_DESC_SIZE 16
233 #define RX_RING_NR 4
234 #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
235 #define RX_BUF_DMA_ALIGN 8
236 #define RX_PREPAD_SIZE 10
237 #define ETH_CRC_LEN 2
238 #define RX_VLANHDR_LEN 2
239 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
240 ETH_HLEN + \
241 ETH_CRC_LEN + \
242 RX_VLANHDR_LEN + \
243 RX_BUF_DMA_ALIGN)
244
245 struct rxdesc {
246 union {
247 __u8 all[16];
248 __le32 dw[4];
249 struct {
250 /* DW0 */
251 __le16 rsv2;
252 __u8 rsv1;
253 __u8 flags;
254
255 /* DW1 */
256 __le16 datalen;
257 __le16 wbcpl;
258
259 /* DW2 */
260 __le32 bufaddrh;
261
262 /* DW3 */
263 __le32 bufaddrl;
264 } desc1;
265 struct {
266 /* DW0 */
267 __le16 vlan;
268 __le16 flags;
269
270 /* DW1 */
271 __le16 framesize;
272 __u8 errstat;
273 __u8 desccnt;
274
275 /* DW2 */
276 __le32 rsshash;
277
278 /* DW3 */
279 __u8 hashfun;
280 __u8 hashtype;
281 __le16 resrv;
282 } descwb;
283 };
284 };
285
286 enum jme_rxdesc_flags_bits {
287 RXFLAG_OWN = 0x80,
288 RXFLAG_INT = 0x40,
289 RXFLAG_64BIT = 0x20,
290 };
291
292 enum jme_rxwbdesc_flags_bits {
293 RXWBFLAG_OWN = 0x8000,
294 RXWBFLAG_INT = 0x4000,
295 RXWBFLAG_MF = 0x2000,
296 RXWBFLAG_64BIT = 0x2000,
297 RXWBFLAG_TCPON = 0x1000,
298 RXWBFLAG_UDPON = 0x0800,
299 RXWBFLAG_IPCS = 0x0400,
300 RXWBFLAG_TCPCS = 0x0200,
301 RXWBFLAG_UDPCS = 0x0100,
302 RXWBFLAG_TAGON = 0x0080,
303 RXWBFLAG_IPV4 = 0x0040,
304 RXWBFLAG_IPV6 = 0x0020,
305 RXWBFLAG_PAUSE = 0x0010,
306 RXWBFLAG_MAGIC = 0x0008,
307 RXWBFLAG_WAKEUP = 0x0004,
308 RXWBFLAG_DEST = 0x0003,
309 RXWBFLAG_DEST_UNI = 0x0001,
310 RXWBFLAG_DEST_MUL = 0x0002,
311 RXWBFLAG_DEST_BRO = 0x0003,
312 };
313
314 enum jme_rxwbdesc_desccnt_mask {
315 RXWBDCNT_WBCPL = 0x80,
316 RXWBDCNT_DCNT = 0x7F,
317 };
318
319 enum jme_rxwbdesc_errstat_bits {
320 RXWBERR_LIMIT = 0x80,
321 RXWBERR_MIIER = 0x40,
322 RXWBERR_NIBON = 0x20,
323 RXWBERR_COLON = 0x10,
324 RXWBERR_ABORT = 0x08,
325 RXWBERR_SHORT = 0x04,
326 RXWBERR_OVERUN = 0x02,
327 RXWBERR_CRCERR = 0x01,
328 RXWBERR_ALLERR = 0xFF,
329 };
330
331 /*
332 * Buffer information corresponding to ring descriptors.
333 */
334 struct jme_buffer_info {
335 struct sk_buff *skb;
336 dma_addr_t mapping;
337 int len;
338 int nr_desc;
339 unsigned long start_xmit;
340 };
341
342 /*
343 * The structure holding buffer information and ring descriptors all together.
344 */
345 struct jme_ring {
346 void *alloc; /* pointer to allocated memory */
347 void *desc; /* pointer to ring memory */
348 dma_addr_t dmaalloc; /* phys address of ring alloc */
349 dma_addr_t dma; /* phys address for ring dma */
350
351 /* Buffer information corresponding to each descriptor */
352 struct jme_buffer_info *bufinf;
353
354 int next_to_use;
355 atomic_t next_to_clean;
356 atomic_t nr_free;
357 };
358
359 #define NET_STAT(priv) (priv->dev->stats)
360 #define NETDEV_GET_STATS(netdev, fun_ptr)
361 #define DECLARE_NET_DEVICE_STATS
362
363 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
364 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
365 netif_napi_add(dev, napis, pollfn, q);
366 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
367 #define JME_NAPI_WEIGHT(w) int w
368 #define JME_NAPI_WEIGHT_VAL(w) w
369 #define JME_NAPI_WEIGHT_SET(w, r)
370 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
371 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
372 #define JME_NAPI_DISABLE(priv) \
373 if (!napi_disable_pending(&priv->napi)) \
374 napi_disable(&priv->napi);
375 #define JME_RX_SCHEDULE_PREP(priv) \
376 napi_schedule_prep(&priv->napi)
377 #define JME_RX_SCHEDULE(priv) \
378 __napi_schedule(&priv->napi);
379
380 /*
381 * Jmac Adapter Private data
382 */
383 struct jme_adapter {
384 struct pci_dev *pdev;
385 struct net_device *dev;
386 void __iomem *regs;
387 struct mii_if_info mii_if;
388 struct jme_ring rxring[RX_RING_NR];
389 struct jme_ring txring[TX_RING_NR];
390 spinlock_t phy_lock;
391 spinlock_t macaddr_lock;
392 spinlock_t rxmcs_lock;
393 struct tasklet_struct rxempty_task;
394 struct tasklet_struct rxclean_task;
395 struct tasklet_struct txclean_task;
396 struct tasklet_struct linkch_task;
397 struct tasklet_struct pcc_task;
398 unsigned long flags;
399 u32 reg_txcs;
400 u32 reg_txpfc;
401 u32 reg_rxcs;
402 u32 reg_rxmcs;
403 u32 reg_ghc;
404 u32 reg_pmcs;
405 u32 phylink;
406 u32 tx_ring_size;
407 u32 tx_ring_mask;
408 u32 tx_wake_threshold;
409 u32 rx_ring_size;
410 u32 rx_ring_mask;
411 u8 mrrs;
412 unsigned int fpgaver;
413 unsigned int chiprev;
414 u8 rev;
415 u32 msg_enable;
416 struct ethtool_cmd old_ecmd;
417 unsigned int old_mtu;
418 struct vlan_group *vlgrp;
419 struct dynpcc_info dpi;
420 atomic_t intr_sem;
421 atomic_t link_changing;
422 atomic_t tx_cleaning;
423 atomic_t rx_cleaning;
424 atomic_t rx_empty;
425 int (*jme_rx)(struct sk_buff *skb);
426 int (*jme_vlan_rx)(struct sk_buff *skb,
427 struct vlan_group *grp,
428 unsigned short vlan_tag);
429 DECLARE_NAPI_STRUCT
430 DECLARE_NET_DEVICE_STATS
431 };
432
433 enum jme_flags_bits {
434 JME_FLAG_MSI = 1,
435 JME_FLAG_SSET = 2,
436 JME_FLAG_TXCSUM = 3,
437 JME_FLAG_TSO = 4,
438 JME_FLAG_POLL = 5,
439 JME_FLAG_SHUTDOWN = 6,
440 };
441
442 #define TX_TIMEOUT (5 * HZ)
443 #define JME_REG_LEN 0x500
444 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
445
446 static inline struct jme_adapter*
447 jme_napi_priv(struct napi_struct *napi)
448 {
449 struct jme_adapter *jme;
450 jme = container_of(napi, struct jme_adapter, napi);
451 return jme;
452 }
453
454 /*
455 * MMaped I/O Resters
456 */
457 enum jme_iomap_offsets {
458 JME_MAC = 0x0000,
459 JME_PHY = 0x0400,
460 JME_MISC = 0x0800,
461 JME_RSS = 0x0C00,
462 };
463
464 enum jme_iomap_lens {
465 JME_MAC_LEN = 0x80,
466 JME_PHY_LEN = 0x58,
467 JME_MISC_LEN = 0x98,
468 JME_RSS_LEN = 0xFF,
469 };
470
471 enum jme_iomap_regs {
472 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
473 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
474 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
475 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
476 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
477 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
478 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
479 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
480
481 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
482 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
483 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
484 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
485 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
486 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
487 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
488 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
489 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
490 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
491 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
492 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
493
494 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
495 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
496 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
497
498
499 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
500 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
501 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
502 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
503
504
505 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
506 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
507 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
508 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
509 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
510 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
511 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
512 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
513 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
514 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
515 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
516 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
517 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
518 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
519 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
520 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
521 };
522
523 /*
524 * TX Control/Status Bits
525 */
526 enum jme_txcs_bits {
527 TXCS_QUEUE7S = 0x00008000,
528 TXCS_QUEUE6S = 0x00004000,
529 TXCS_QUEUE5S = 0x00002000,
530 TXCS_QUEUE4S = 0x00001000,
531 TXCS_QUEUE3S = 0x00000800,
532 TXCS_QUEUE2S = 0x00000400,
533 TXCS_QUEUE1S = 0x00000200,
534 TXCS_QUEUE0S = 0x00000100,
535 TXCS_FIFOTH = 0x000000C0,
536 TXCS_DMASIZE = 0x00000030,
537 TXCS_BURST = 0x00000004,
538 TXCS_ENABLE = 0x00000001,
539 };
540
541 enum jme_txcs_value {
542 TXCS_FIFOTH_16QW = 0x000000C0,
543 TXCS_FIFOTH_12QW = 0x00000080,
544 TXCS_FIFOTH_8QW = 0x00000040,
545 TXCS_FIFOTH_4QW = 0x00000000,
546
547 TXCS_DMASIZE_64B = 0x00000000,
548 TXCS_DMASIZE_128B = 0x00000010,
549 TXCS_DMASIZE_256B = 0x00000020,
550 TXCS_DMASIZE_512B = 0x00000030,
551
552 TXCS_SELECT_QUEUE0 = 0x00000000,
553 TXCS_SELECT_QUEUE1 = 0x00010000,
554 TXCS_SELECT_QUEUE2 = 0x00020000,
555 TXCS_SELECT_QUEUE3 = 0x00030000,
556 TXCS_SELECT_QUEUE4 = 0x00040000,
557 TXCS_SELECT_QUEUE5 = 0x00050000,
558 TXCS_SELECT_QUEUE6 = 0x00060000,
559 TXCS_SELECT_QUEUE7 = 0x00070000,
560
561 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
562 TXCS_BURST,
563 };
564
565 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
566
567 /*
568 * TX MAC Control/Status Bits
569 */
570 enum jme_txmcs_bit_masks {
571 TXMCS_IFG2 = 0xC0000000,
572 TXMCS_IFG1 = 0x30000000,
573 TXMCS_TTHOLD = 0x00000300,
574 TXMCS_FBURST = 0x00000080,
575 TXMCS_CARRIEREXT = 0x00000040,
576 TXMCS_DEFER = 0x00000020,
577 TXMCS_BACKOFF = 0x00000010,
578 TXMCS_CARRIERSENSE = 0x00000008,
579 TXMCS_COLLISION = 0x00000004,
580 TXMCS_CRC = 0x00000002,
581 TXMCS_PADDING = 0x00000001,
582 };
583
584 enum jme_txmcs_values {
585 TXMCS_IFG2_6_4 = 0x00000000,
586 TXMCS_IFG2_8_5 = 0x40000000,
587 TXMCS_IFG2_10_6 = 0x80000000,
588 TXMCS_IFG2_12_7 = 0xC0000000,
589
590 TXMCS_IFG1_8_4 = 0x00000000,
591 TXMCS_IFG1_12_6 = 0x10000000,
592 TXMCS_IFG1_16_8 = 0x20000000,
593 TXMCS_IFG1_20_10 = 0x30000000,
594
595 TXMCS_TTHOLD_1_8 = 0x00000000,
596 TXMCS_TTHOLD_1_4 = 0x00000100,
597 TXMCS_TTHOLD_1_2 = 0x00000200,
598 TXMCS_TTHOLD_FULL = 0x00000300,
599
600 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
601 TXMCS_IFG1_16_8 |
602 TXMCS_TTHOLD_FULL |
603 TXMCS_DEFER |
604 TXMCS_CRC |
605 TXMCS_PADDING,
606 };
607
608 enum jme_txpfc_bits_masks {
609 TXPFC_VLAN_TAG = 0xFFFF0000,
610 TXPFC_VLAN_EN = 0x00008000,
611 TXPFC_PF_EN = 0x00000001,
612 };
613
614 enum jme_txtrhd_bits_masks {
615 TXTRHD_TXPEN = 0x80000000,
616 TXTRHD_TXP = 0x7FFFFF00,
617 TXTRHD_TXREN = 0x00000080,
618 TXTRHD_TXRL = 0x0000007F,
619 };
620
621 enum jme_txtrhd_shifts {
622 TXTRHD_TXP_SHIFT = 8,
623 TXTRHD_TXRL_SHIFT = 0,
624 };
625
626 /*
627 * RX Control/Status Bits
628 */
629 enum jme_rxcs_bit_masks {
630 /* FIFO full threshold for transmitting Tx Pause Packet */
631 RXCS_FIFOTHTP = 0x30000000,
632 /* FIFO threshold for processing next packet */
633 RXCS_FIFOTHNP = 0x0C000000,
634 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
635 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
636 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
637 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
638 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
639 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
640 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
641 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
642 RXCS_QST = 0x00000004, /* Receive queue start */
643 RXCS_SUSPEND = 0x00000002,
644 RXCS_ENABLE = 0x00000001,
645 };
646
647 enum jme_rxcs_values {
648 RXCS_FIFOTHTP_16T = 0x00000000,
649 RXCS_FIFOTHTP_32T = 0x10000000,
650 RXCS_FIFOTHTP_64T = 0x20000000,
651 RXCS_FIFOTHTP_128T = 0x30000000,
652
653 RXCS_FIFOTHNP_16QW = 0x00000000,
654 RXCS_FIFOTHNP_32QW = 0x04000000,
655 RXCS_FIFOTHNP_64QW = 0x08000000,
656 RXCS_FIFOTHNP_128QW = 0x0C000000,
657
658 RXCS_DMAREQSZ_16B = 0x00000000,
659 RXCS_DMAREQSZ_32B = 0x01000000,
660 RXCS_DMAREQSZ_64B = 0x02000000,
661 RXCS_DMAREQSZ_128B = 0x03000000,
662
663 RXCS_QUEUESEL_Q0 = 0x00000000,
664 RXCS_QUEUESEL_Q1 = 0x00010000,
665 RXCS_QUEUESEL_Q2 = 0x00020000,
666 RXCS_QUEUESEL_Q3 = 0x00030000,
667
668 RXCS_RETRYGAP_256ns = 0x00000000,
669 RXCS_RETRYGAP_512ns = 0x00001000,
670 RXCS_RETRYGAP_1024ns = 0x00002000,
671 RXCS_RETRYGAP_2048ns = 0x00003000,
672 RXCS_RETRYGAP_4096ns = 0x00004000,
673 RXCS_RETRYGAP_8192ns = 0x00005000,
674 RXCS_RETRYGAP_16384ns = 0x00006000,
675 RXCS_RETRYGAP_32768ns = 0x00007000,
676
677 RXCS_RETRYCNT_0 = 0x00000000,
678 RXCS_RETRYCNT_4 = 0x00000100,
679 RXCS_RETRYCNT_8 = 0x00000200,
680 RXCS_RETRYCNT_12 = 0x00000300,
681 RXCS_RETRYCNT_16 = 0x00000400,
682 RXCS_RETRYCNT_20 = 0x00000500,
683 RXCS_RETRYCNT_24 = 0x00000600,
684 RXCS_RETRYCNT_28 = 0x00000700,
685 RXCS_RETRYCNT_32 = 0x00000800,
686 RXCS_RETRYCNT_36 = 0x00000900,
687 RXCS_RETRYCNT_40 = 0x00000A00,
688 RXCS_RETRYCNT_44 = 0x00000B00,
689 RXCS_RETRYCNT_48 = 0x00000C00,
690 RXCS_RETRYCNT_52 = 0x00000D00,
691 RXCS_RETRYCNT_56 = 0x00000E00,
692 RXCS_RETRYCNT_60 = 0x00000F00,
693
694 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
695 RXCS_FIFOTHNP_128QW |
696 RXCS_DMAREQSZ_128B |
697 RXCS_RETRYGAP_256ns |
698 RXCS_RETRYCNT_32,
699 };
700
701 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
702
703 /*
704 * RX MAC Control/Status Bits
705 */
706 enum jme_rxmcs_bits {
707 RXMCS_ALLFRAME = 0x00000800,
708 RXMCS_BRDFRAME = 0x00000400,
709 RXMCS_MULFRAME = 0x00000200,
710 RXMCS_UNIFRAME = 0x00000100,
711 RXMCS_ALLMULFRAME = 0x00000080,
712 RXMCS_MULFILTERED = 0x00000040,
713 RXMCS_RXCOLLDEC = 0x00000020,
714 RXMCS_FLOWCTRL = 0x00000008,
715 RXMCS_VTAGRM = 0x00000004,
716 RXMCS_PREPAD = 0x00000002,
717 RXMCS_CHECKSUM = 0x00000001,
718
719 RXMCS_DEFAULT = RXMCS_VTAGRM |
720 RXMCS_PREPAD |
721 RXMCS_FLOWCTRL |
722 RXMCS_CHECKSUM,
723 };
724
725 /*
726 * Wakeup Frame setup interface registers
727 */
728 #define WAKEUP_FRAME_NR 8
729 #define WAKEUP_FRAME_MASK_DWNR 4
730
731 enum jme_wfoi_bit_masks {
732 WFOI_MASK_SEL = 0x00000070,
733 WFOI_CRC_SEL = 0x00000008,
734 WFOI_FRAME_SEL = 0x00000007,
735 };
736
737 enum jme_wfoi_shifts {
738 WFOI_MASK_SHIFT = 4,
739 };
740
741 /*
742 * SMI Related definitions
743 */
744 enum jme_smi_bit_mask {
745 SMI_DATA_MASK = 0xFFFF0000,
746 SMI_REG_ADDR_MASK = 0x0000F800,
747 SMI_PHY_ADDR_MASK = 0x000007C0,
748 SMI_OP_WRITE = 0x00000020,
749 /* Set to 1, after req done it'll be cleared to 0 */
750 SMI_OP_REQ = 0x00000010,
751 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
752 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
753 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
754 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
755 };
756
757 enum jme_smi_bit_shift {
758 SMI_DATA_SHIFT = 16,
759 SMI_REG_ADDR_SHIFT = 11,
760 SMI_PHY_ADDR_SHIFT = 6,
761 };
762
763 static inline u32 smi_reg_addr(int x)
764 {
765 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
766 }
767
768 static inline u32 smi_phy_addr(int x)
769 {
770 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
771 }
772
773 #define JME_PHY_TIMEOUT 100 /* 100 msec */
774 #define JME_PHY_REG_NR 32
775
776 /*
777 * Global Host Control
778 */
779 enum jme_ghc_bit_mask {
780 GHC_SWRST = 0x40000000,
781 GHC_DPX = 0x00000040,
782 GHC_SPEED = 0x00000030,
783 GHC_LINK_POLL = 0x00000001,
784 };
785
786 enum jme_ghc_speed_val {
787 GHC_SPEED_10M = 0x00000010,
788 GHC_SPEED_100M = 0x00000020,
789 GHC_SPEED_1000M = 0x00000030,
790 };
791
792 enum jme_ghc_to_clk {
793 GHC_TO_CLK_OFF = 0x00000000,
794 GHC_TO_CLK_GPHY = 0x00400000,
795 GHC_TO_CLK_PCIE = 0x00800000,
796 GHC_TO_CLK_INVALID = 0x00C00000,
797 };
798
799 enum jme_ghc_txmac_clk {
800 GHC_TXMAC_CLK_OFF = 0x00000000,
801 GHC_TXMAC_CLK_GPHY = 0x00100000,
802 GHC_TXMAC_CLK_PCIE = 0x00200000,
803 GHC_TXMAC_CLK_INVALID = 0x00300000,
804 };
805
806 /*
807 * Power management control and status register
808 */
809 enum jme_pmcs_bit_masks {
810 PMCS_WF7DET = 0x80000000,
811 PMCS_WF6DET = 0x40000000,
812 PMCS_WF5DET = 0x20000000,
813 PMCS_WF4DET = 0x10000000,
814 PMCS_WF3DET = 0x08000000,
815 PMCS_WF2DET = 0x04000000,
816 PMCS_WF1DET = 0x02000000,
817 PMCS_WF0DET = 0x01000000,
818 PMCS_LFDET = 0x00040000,
819 PMCS_LRDET = 0x00020000,
820 PMCS_MFDET = 0x00010000,
821 PMCS_WF7EN = 0x00008000,
822 PMCS_WF6EN = 0x00004000,
823 PMCS_WF5EN = 0x00002000,
824 PMCS_WF4EN = 0x00001000,
825 PMCS_WF3EN = 0x00000800,
826 PMCS_WF2EN = 0x00000400,
827 PMCS_WF1EN = 0x00000200,
828 PMCS_WF0EN = 0x00000100,
829 PMCS_LFEN = 0x00000004,
830 PMCS_LREN = 0x00000002,
831 PMCS_MFEN = 0x00000001,
832 };
833
834 /*
835 * Giga PHY Status Registers
836 */
837 enum jme_phy_link_bit_mask {
838 PHY_LINK_SPEED_MASK = 0x0000C000,
839 PHY_LINK_DUPLEX = 0x00002000,
840 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
841 PHY_LINK_UP = 0x00000400,
842 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
843 PHY_LINK_MDI_STAT = 0x00000040,
844 };
845
846 enum jme_phy_link_speed_val {
847 PHY_LINK_SPEED_10M = 0x00000000,
848 PHY_LINK_SPEED_100M = 0x00004000,
849 PHY_LINK_SPEED_1000M = 0x00008000,
850 };
851
852 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
853
854 /*
855 * SMB Control and Status
856 */
857 enum jme_smbcsr_bit_mask {
858 SMBCSR_CNACK = 0x00020000,
859 SMBCSR_RELOAD = 0x00010000,
860 SMBCSR_EEPROMD = 0x00000020,
861 SMBCSR_INITDONE = 0x00000010,
862 SMBCSR_BUSY = 0x0000000F,
863 };
864
865 enum jme_smbintf_bit_mask {
866 SMBINTF_HWDATR = 0xFF000000,
867 SMBINTF_HWDATW = 0x00FF0000,
868 SMBINTF_HWADDR = 0x0000FF00,
869 SMBINTF_HWRWN = 0x00000020,
870 SMBINTF_HWCMD = 0x00000010,
871 SMBINTF_FASTM = 0x00000008,
872 SMBINTF_GPIOSCL = 0x00000004,
873 SMBINTF_GPIOSDA = 0x00000002,
874 SMBINTF_GPIOEN = 0x00000001,
875 };
876
877 enum jme_smbintf_vals {
878 SMBINTF_HWRWN_READ = 0x00000020,
879 SMBINTF_HWRWN_WRITE = 0x00000000,
880 };
881
882 enum jme_smbintf_shifts {
883 SMBINTF_HWDATR_SHIFT = 24,
884 SMBINTF_HWDATW_SHIFT = 16,
885 SMBINTF_HWADDR_SHIFT = 8,
886 };
887
888 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
889 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
890 #define JME_SMB_LEN 256
891 #define JME_EEPROM_MAGIC 0x250
892
893 /*
894 * Timer Control/Status Register
895 */
896 enum jme_tmcsr_bit_masks {
897 TMCSR_SWIT = 0x80000000,
898 TMCSR_EN = 0x01000000,
899 TMCSR_CNT = 0x00FFFFFF,
900 };
901
902 /*
903 * General Purpose REG-0
904 */
905 enum jme_gpreg0_masks {
906 GPREG0_DISSH = 0xFF000000,
907 GPREG0_PCIRLMT = 0x00300000,
908 GPREG0_PCCNOMUTCLR = 0x00040000,
909 GPREG0_LNKINTPOLL = 0x00001000,
910 GPREG0_PCCTMR = 0x00000300,
911 GPREG0_PHYADDR = 0x0000001F,
912 };
913
914 enum jme_gpreg0_vals {
915 GPREG0_DISSH_DW7 = 0x80000000,
916 GPREG0_DISSH_DW6 = 0x40000000,
917 GPREG0_DISSH_DW5 = 0x20000000,
918 GPREG0_DISSH_DW4 = 0x10000000,
919 GPREG0_DISSH_DW3 = 0x08000000,
920 GPREG0_DISSH_DW2 = 0x04000000,
921 GPREG0_DISSH_DW1 = 0x02000000,
922 GPREG0_DISSH_DW0 = 0x01000000,
923 GPREG0_DISSH_ALL = 0xFF000000,
924
925 GPREG0_PCIRLMT_8 = 0x00000000,
926 GPREG0_PCIRLMT_6 = 0x00100000,
927 GPREG0_PCIRLMT_5 = 0x00200000,
928 GPREG0_PCIRLMT_4 = 0x00300000,
929
930 GPREG0_PCCTMR_16ns = 0x00000000,
931 GPREG0_PCCTMR_256ns = 0x00000100,
932 GPREG0_PCCTMR_1us = 0x00000200,
933 GPREG0_PCCTMR_1ms = 0x00000300,
934
935 GPREG0_PHYADDR_1 = 0x00000001,
936
937 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
938 GPREG0_PCCTMR_1us |
939 GPREG0_PHYADDR_1,
940 };
941
942 /*
943 * General Purpose REG-1
944 * Note: All theses bits defined here are for
945 * Chip mode revision 0x11 only
946 */
947 enum jme_gpreg1_masks {
948 GPREG1_INTRDELAYUNIT = 0x00000018,
949 GPREG1_INTRDELAYENABLE = 0x00000007,
950 };
951
952 enum jme_gpreg1_vals {
953 GPREG1_RSSPATCH = 0x00000040,
954 GPREG1_HALFMODEPATCH = 0x00000020,
955
956 GPREG1_INTDLYUNIT_16NS = 0x00000000,
957 GPREG1_INTDLYUNIT_256NS = 0x00000008,
958 GPREG1_INTDLYUNIT_1US = 0x00000010,
959 GPREG1_INTDLYUNIT_16US = 0x00000018,
960
961 GPREG1_INTDLYEN_1U = 0x00000001,
962 GPREG1_INTDLYEN_2U = 0x00000002,
963 GPREG1_INTDLYEN_3U = 0x00000003,
964 GPREG1_INTDLYEN_4U = 0x00000004,
965 GPREG1_INTDLYEN_5U = 0x00000005,
966 GPREG1_INTDLYEN_6U = 0x00000006,
967 GPREG1_INTDLYEN_7U = 0x00000007,
968
969 GPREG1_DEFAULT = 0x00000000,
970 };
971
972 /*
973 * Interrupt Status Bits
974 */
975 enum jme_interrupt_bits {
976 INTR_SWINTR = 0x80000000,
977 INTR_TMINTR = 0x40000000,
978 INTR_LINKCH = 0x20000000,
979 INTR_PAUSERCV = 0x10000000,
980 INTR_MAGICRCV = 0x08000000,
981 INTR_WAKERCV = 0x04000000,
982 INTR_PCCRX0TO = 0x02000000,
983 INTR_PCCRX1TO = 0x01000000,
984 INTR_PCCRX2TO = 0x00800000,
985 INTR_PCCRX3TO = 0x00400000,
986 INTR_PCCTXTO = 0x00200000,
987 INTR_PCCRX0 = 0x00100000,
988 INTR_PCCRX1 = 0x00080000,
989 INTR_PCCRX2 = 0x00040000,
990 INTR_PCCRX3 = 0x00020000,
991 INTR_PCCTX = 0x00010000,
992 INTR_RX3EMP = 0x00008000,
993 INTR_RX2EMP = 0x00004000,
994 INTR_RX1EMP = 0x00002000,
995 INTR_RX0EMP = 0x00001000,
996 INTR_RX3 = 0x00000800,
997 INTR_RX2 = 0x00000400,
998 INTR_RX1 = 0x00000200,
999 INTR_RX0 = 0x00000100,
1000 INTR_TX7 = 0x00000080,
1001 INTR_TX6 = 0x00000040,
1002 INTR_TX5 = 0x00000020,
1003 INTR_TX4 = 0x00000010,
1004 INTR_TX3 = 0x00000008,
1005 INTR_TX2 = 0x00000004,
1006 INTR_TX1 = 0x00000002,
1007 INTR_TX0 = 0x00000001,
1008 };
1009
1010 static const u32 INTR_ENABLE = INTR_SWINTR |
1011 INTR_TMINTR |
1012 INTR_LINKCH |
1013 INTR_PCCRX0TO |
1014 INTR_PCCRX0 |
1015 INTR_PCCTXTO |
1016 INTR_PCCTX |
1017 INTR_RX0EMP;
1018
1019 /*
1020 * PCC Control Registers
1021 */
1022 enum jme_pccrx_masks {
1023 PCCRXTO_MASK = 0xFFFF0000,
1024 PCCRX_MASK = 0x0000FF00,
1025 };
1026
1027 enum jme_pcctx_masks {
1028 PCCTXTO_MASK = 0xFFFF0000,
1029 PCCTX_MASK = 0x0000FF00,
1030 PCCTX_QS_MASK = 0x000000FF,
1031 };
1032
1033 enum jme_pccrx_shifts {
1034 PCCRXTO_SHIFT = 16,
1035 PCCRX_SHIFT = 8,
1036 };
1037
1038 enum jme_pcctx_shifts {
1039 PCCTXTO_SHIFT = 16,
1040 PCCTX_SHIFT = 8,
1041 };
1042
1043 enum jme_pcctx_bits {
1044 PCCTXQ0_EN = 0x00000001,
1045 PCCTXQ1_EN = 0x00000002,
1046 PCCTXQ2_EN = 0x00000004,
1047 PCCTXQ3_EN = 0x00000008,
1048 PCCTXQ4_EN = 0x00000010,
1049 PCCTXQ5_EN = 0x00000020,
1050 PCCTXQ6_EN = 0x00000040,
1051 PCCTXQ7_EN = 0x00000080,
1052 };
1053
1054 /*
1055 * Chip Mode Register
1056 */
1057 enum jme_chipmode_bit_masks {
1058 CM_FPGAVER_MASK = 0xFFFF0000,
1059 CM_CHIPREV_MASK = 0x0000FF00,
1060 CM_CHIPMODE_MASK = 0x0000000F,
1061 };
1062
1063 enum jme_chipmode_shifts {
1064 CM_FPGAVER_SHIFT = 16,
1065 CM_CHIPREV_SHIFT = 8,
1066 };
1067
1068 /*
1069 * Aggressive Power Mode Control
1070 */
1071 enum jme_apmc_bits {
1072 JME_APMC_PCIE_SD_EN = 0x40000000,
1073 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1074 JME_APMC_EPIEN = 0x04000000,
1075 JME_APMC_EPIEN_CTRL = 0x03000000,
1076 };
1077
1078 enum jme_apmc_values {
1079 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1080 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1081 };
1082
1083 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1084
1085 #ifdef REG_DEBUG
1086 static char *MAC_REG_NAME[] = {
1087 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1088 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1089 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1090 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1091 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1092 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1093 "JME_PMCS"};
1094
1095 static char *PE_REG_NAME[] = {
1096 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1097 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1098 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1099 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1100 "JME_SMBCSR", "JME_SMBINTF"};
1101
1102 static char *MISC_REG_NAME[] = {
1103 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1104 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1105 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1106 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1107 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1108 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1109 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1110 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1111 "JME_PCCSRX0"};
1112
1113 static inline void reg_dbg(const struct jme_adapter *jme,
1114 const char *msg, u32 val, u32 reg)
1115 {
1116 const char *regname;
1117 switch (reg & 0xF00) {
1118 case 0x000:
1119 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1120 break;
1121 case 0x400:
1122 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1123 break;
1124 case 0x800:
1125 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1126 break;
1127 default:
1128 regname = PE_REG_NAME[0];
1129 }
1130 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1131 msg, val, regname);
1132 }
1133 #else
1134 static inline void reg_dbg(const struct jme_adapter *jme,
1135 const char *msg, u32 val, u32 reg) {}
1136 #endif
1137
1138 /*
1139 * Read/Write MMaped I/O Registers
1140 */
1141 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1142 {
1143 return readl(jme->regs + reg);
1144 }
1145
1146 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1147 {
1148 reg_dbg(jme, "REG WRITE", val, reg);
1149 writel(val, jme->regs + reg);
1150 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1151 }
1152
1153 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1154 {
1155 /*
1156 * Read after write should cause flush
1157 */
1158 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1159 writel(val, jme->regs + reg);
1160 readl(jme->regs + reg);
1161 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1162 }
1163
1164 /*
1165 * PHY Regs
1166 */
1167 enum jme_phy_reg17_bit_masks {
1168 PREG17_SPEED = 0xC000,
1169 PREG17_DUPLEX = 0x2000,
1170 PREG17_SPDRSV = 0x0800,
1171 PREG17_LNKUP = 0x0400,
1172 PREG17_MDI = 0x0040,
1173 };
1174
1175 enum jme_phy_reg17_vals {
1176 PREG17_SPEED_10M = 0x0000,
1177 PREG17_SPEED_100M = 0x4000,
1178 PREG17_SPEED_1000M = 0x8000,
1179 };
1180
1181 #define BMSR_ANCOMP 0x0020
1182
1183 /*
1184 * Workaround
1185 */
1186 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1187 {
1188 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1189 }
1190
1191 /*
1192 * Function prototypes
1193 */
1194 static int jme_set_settings(struct net_device *netdev,
1195 struct ethtool_cmd *ecmd);
1196 static void jme_set_multi(struct net_device *netdev);
1197
1198 #endif
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