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mlx4_en: Use netif_set_real_num_{rx, tx}_queues()
[linux-2.6/btrfs-unstable.git] / drivers / net / jme.c
blobc04c096bc6a90b4734237d5ada679db4c8af60d0
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/pci.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/mii.h>
33 #include <linux/crc32.h>
34 #include <linux/delay.h>
35 #include <linux/spinlock.h>
36 #include <linux/in.h>
37 #include <linux/ip.h>
38 #include <linux/ipv6.h>
39 #include <linux/tcp.h>
40 #include <linux/udp.h>
41 #include <linux/if_vlan.h>
42 #include <linux/slab.h>
43 #include <net/ip6_checksum.h>
44 #include "jme.h"
45
46 static int force_pseudohp = -1;
47 static int no_pseudohp = -1;
48 static int no_extplug = -1;
49 module_param(force_pseudohp, int, 0);
50 MODULE_PARM_DESC(force_pseudohp,
51 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
52 module_param(no_pseudohp, int, 0);
53 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
54 module_param(no_extplug, int, 0);
55 MODULE_PARM_DESC(no_extplug,
56 "Do not use external plug signal for pseudo hot-plug.");
57
58 static int
59 jme_mdio_read(struct net_device *netdev, int phy, int reg)
60 {
61 struct jme_adapter *jme = netdev_priv(netdev);
62 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
63
64 read_again:
65 jwrite32(jme, JME_SMI, SMI_OP_REQ |
66 smi_phy_addr(phy) |
67 smi_reg_addr(reg));
68
69 wmb();
70 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
71 udelay(20);
72 val = jread32(jme, JME_SMI);
73 if ((val & SMI_OP_REQ) == 0)
74 break;
75 }
76
77 if (i == 0) {
78 pr_err("phy(%d) read timeout : %d\n", phy, reg);
79 return 0;
80 }
81
82 if (again--)
83 goto read_again;
84
85 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
86 }
87
88 static void
89 jme_mdio_write(struct net_device *netdev,
90 int phy, int reg, int val)
91 {
92 struct jme_adapter *jme = netdev_priv(netdev);
93 int i;
94
95 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
96 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
97 smi_phy_addr(phy) | smi_reg_addr(reg));
98
99 wmb();
100 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
101 udelay(20);
102 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
103 break;
104 }
105
106 if (i == 0)
107 pr_err("phy(%d) write timeout : %d\n", phy, reg);
108 }
109
110 static inline void
111 jme_reset_phy_processor(struct jme_adapter *jme)
112 {
113 u32 val;
114
115 jme_mdio_write(jme->dev,
116 jme->mii_if.phy_id,
117 MII_ADVERTISE, ADVERTISE_ALL |
118 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
119
120 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
121 jme_mdio_write(jme->dev,
122 jme->mii_if.phy_id,
123 MII_CTRL1000,
124 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
125
126 val = jme_mdio_read(jme->dev,
127 jme->mii_if.phy_id,
128 MII_BMCR);
129
130 jme_mdio_write(jme->dev,
131 jme->mii_if.phy_id,
132 MII_BMCR, val | BMCR_RESET);
133 }
134
135 static void
136 jme_setup_wakeup_frame(struct jme_adapter *jme,
137 u32 *mask, u32 crc, int fnr)
138 {
139 int i;
140
141 /*
142 * Setup CRC pattern
143 */
144 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
145 wmb();
146 jwrite32(jme, JME_WFODP, crc);
147 wmb();
148
149 /*
150 * Setup Mask
151 */
152 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
153 jwrite32(jme, JME_WFOI,
154 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
155 (fnr & WFOI_FRAME_SEL));
156 wmb();
157 jwrite32(jme, JME_WFODP, mask[i]);
158 wmb();
159 }
160 }
161
162 static inline void
163 jme_reset_mac_processor(struct jme_adapter *jme)
164 {
165 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
166 u32 crc = 0xCDCDCDCD;
167 u32 gpreg0;
168 int i;
169
170 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
171 udelay(2);
172 jwrite32(jme, JME_GHC, jme->reg_ghc);
173
174 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
175 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
176 jwrite32(jme, JME_RXQDC, 0x00000000);
177 jwrite32(jme, JME_RXNDA, 0x00000000);
178 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
179 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
180 jwrite32(jme, JME_TXQDC, 0x00000000);
181 jwrite32(jme, JME_TXNDA, 0x00000000);
182
183 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
184 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
185 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
186 jme_setup_wakeup_frame(jme, mask, crc, i);
187 if (jme->fpgaver)
188 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
189 else
190 gpreg0 = GPREG0_DEFAULT;
191 jwrite32(jme, JME_GPREG0, gpreg0);
192 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
193 }
194
195 static inline void
196 jme_reset_ghc_speed(struct jme_adapter *jme)
197 {
198 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
199 jwrite32(jme, JME_GHC, jme->reg_ghc);
200 }
201
202 static inline void
203 jme_clear_pm(struct jme_adapter *jme)
204 {
205 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
206 pci_set_power_state(jme->pdev, PCI_D0);
207 pci_enable_wake(jme->pdev, PCI_D0, false);
208 }
209
210 static int
211 jme_reload_eeprom(struct jme_adapter *jme)
212 {
213 u32 val;
214 int i;
215
216 val = jread32(jme, JME_SMBCSR);
217
218 if (val & SMBCSR_EEPROMD) {
219 val |= SMBCSR_CNACK;
220 jwrite32(jme, JME_SMBCSR, val);
221 val |= SMBCSR_RELOAD;
222 jwrite32(jme, JME_SMBCSR, val);
223 mdelay(12);
224
225 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
226 mdelay(1);
227 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
228 break;
229 }
230
231 if (i == 0) {
232 pr_err("eeprom reload timeout\n");
233 return -EIO;
234 }
235 }
236
237 return 0;
238 }
239
240 static void
241 jme_load_macaddr(struct net_device *netdev)
242 {
243 struct jme_adapter *jme = netdev_priv(netdev);
244 unsigned char macaddr[6];
245 u32 val;
246
247 spin_lock_bh(&jme->macaddr_lock);
248 val = jread32(jme, JME_RXUMA_LO);
249 macaddr[0] = (val >> 0) & 0xFF;
250 macaddr[1] = (val >> 8) & 0xFF;
251 macaddr[2] = (val >> 16) & 0xFF;
252 macaddr[3] = (val >> 24) & 0xFF;
253 val = jread32(jme, JME_RXUMA_HI);
254 macaddr[4] = (val >> 0) & 0xFF;
255 macaddr[5] = (val >> 8) & 0xFF;
256 memcpy(netdev->dev_addr, macaddr, 6);
257 spin_unlock_bh(&jme->macaddr_lock);
258 }
259
260 static inline void
261 jme_set_rx_pcc(struct jme_adapter *jme, int p)
262 {
263 switch (p) {
264 case PCC_OFF:
265 jwrite32(jme, JME_PCCRX0,
266 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
267 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
268 break;
269 case PCC_P1:
270 jwrite32(jme, JME_PCCRX0,
271 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
272 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
273 break;
274 case PCC_P2:
275 jwrite32(jme, JME_PCCRX0,
276 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
277 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
278 break;
279 case PCC_P3:
280 jwrite32(jme, JME_PCCRX0,
281 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
282 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
283 break;
284 default:
285 break;
286 }
287 wmb();
288
289 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
290 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
291 }
292
293 static void
294 jme_start_irq(struct jme_adapter *jme)
295 {
296 register struct dynpcc_info *dpi = &(jme->dpi);
297
298 jme_set_rx_pcc(jme, PCC_P1);
299 dpi->cur = PCC_P1;
300 dpi->attempt = PCC_P1;
301 dpi->cnt = 0;
302
303 jwrite32(jme, JME_PCCTX,
304 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
305 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
306 PCCTXQ0_EN
307 );
308
309 /*
310 * Enable Interrupts
311 */
312 jwrite32(jme, JME_IENS, INTR_ENABLE);
313 }
314
315 static inline void
316 jme_stop_irq(struct jme_adapter *jme)
317 {
318 /*
319 * Disable Interrupts
320 */
321 jwrite32f(jme, JME_IENC, INTR_ENABLE);
322 }
323
324 static u32
325 jme_linkstat_from_phy(struct jme_adapter *jme)
326 {
327 u32 phylink, bmsr;
328
329 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
330 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
331 if (bmsr & BMSR_ANCOMP)
332 phylink |= PHY_LINK_AUTONEG_COMPLETE;
333
334 return phylink;
335 }
336
337 static inline void
338 jme_set_phyfifoa(struct jme_adapter *jme)
339 {
340 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
341 }
342
343 static inline void
344 jme_set_phyfifob(struct jme_adapter *jme)
345 {
346 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
347 }
348
349 static int
350 jme_check_link(struct net_device *netdev, int testonly)
351 {
352 struct jme_adapter *jme = netdev_priv(netdev);
353 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
354 char linkmsg[64];
355 int rc = 0;
356
357 linkmsg[0] = '\0';
358
359 if (jme->fpgaver)
360 phylink = jme_linkstat_from_phy(jme);
361 else
362 phylink = jread32(jme, JME_PHY_LINK);
363
364 if (phylink & PHY_LINK_UP) {
365 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
366 /*
367 * If we did not enable AN
368 * Speed/Duplex Info should be obtained from SMI
369 */
370 phylink = PHY_LINK_UP;
371
372 bmcr = jme_mdio_read(jme->dev,
373 jme->mii_if.phy_id,
374 MII_BMCR);
375
376 phylink |= ((bmcr & BMCR_SPEED1000) &&
377 (bmcr & BMCR_SPEED100) == 0) ?
378 PHY_LINK_SPEED_1000M :
379 (bmcr & BMCR_SPEED100) ?
380 PHY_LINK_SPEED_100M :
381 PHY_LINK_SPEED_10M;
382
383 phylink |= (bmcr & BMCR_FULLDPLX) ?
384 PHY_LINK_DUPLEX : 0;
385
386 strcat(linkmsg, "Forced: ");
387 } else {
388 /*
389 * Keep polling for speed/duplex resolve complete
390 */
391 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
392 --cnt) {
393
394 udelay(1);
395
396 if (jme->fpgaver)
397 phylink = jme_linkstat_from_phy(jme);
398 else
399 phylink = jread32(jme, JME_PHY_LINK);
400 }
401 if (!cnt)
402 pr_err("Waiting speed resolve timeout\n");
403
404 strcat(linkmsg, "ANed: ");
405 }
406
407 if (jme->phylink == phylink) {
408 rc = 1;
409 goto out;
410 }
411 if (testonly)
412 goto out;
413
414 jme->phylink = phylink;
415
416 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
417 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
418 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
419 switch (phylink & PHY_LINK_SPEED_MASK) {
420 case PHY_LINK_SPEED_10M:
421 ghc |= GHC_SPEED_10M |
422 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
423 strcat(linkmsg, "10 Mbps, ");
424 break;
425 case PHY_LINK_SPEED_100M:
426 ghc |= GHC_SPEED_100M |
427 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
428 strcat(linkmsg, "100 Mbps, ");
429 break;
430 case PHY_LINK_SPEED_1000M:
431 ghc |= GHC_SPEED_1000M |
432 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
433 strcat(linkmsg, "1000 Mbps, ");
434 break;
435 default:
436 break;
437 }
438
439 if (phylink & PHY_LINK_DUPLEX) {
440 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
441 ghc |= GHC_DPX;
442 } else {
443 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
444 TXMCS_BACKOFF |
445 TXMCS_CARRIERSENSE |
446 TXMCS_COLLISION);
447 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
448 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
449 TXTRHD_TXREN |
450 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
451 }
452
453 gpreg1 = GPREG1_DEFAULT;
454 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
455 if (!(phylink & PHY_LINK_DUPLEX))
456 gpreg1 |= GPREG1_HALFMODEPATCH;
457 switch (phylink & PHY_LINK_SPEED_MASK) {
458 case PHY_LINK_SPEED_10M:
459 jme_set_phyfifoa(jme);
460 gpreg1 |= GPREG1_RSSPATCH;
461 break;
462 case PHY_LINK_SPEED_100M:
463 jme_set_phyfifob(jme);
464 gpreg1 |= GPREG1_RSSPATCH;
465 break;
466 case PHY_LINK_SPEED_1000M:
467 jme_set_phyfifoa(jme);
468 break;
469 default:
470 break;
471 }
472 }
473
474 jwrite32(jme, JME_GPREG1, gpreg1);
475 jwrite32(jme, JME_GHC, ghc);
476 jme->reg_ghc = ghc;
477
478 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
479 "Full-Duplex, " :
480 "Half-Duplex, ");
481 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
482 "MDI-X" :
483 "MDI");
484 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
485 netif_carrier_on(netdev);
486 } else {
487 if (testonly)
488 goto out;
489
490 netif_info(jme, link, jme->dev, "Link is down\n");
491 jme->phylink = 0;
492 netif_carrier_off(netdev);
493 }
494
495 out:
496 return rc;
497 }
498
499 static int
500 jme_setup_tx_resources(struct jme_adapter *jme)
501 {
502 struct jme_ring *txring = &(jme->txring[0]);
503
504 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
505 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
506 &(txring->dmaalloc),
507 GFP_ATOMIC);
508
509 if (!txring->alloc)
510 goto err_set_null;
511
512 /*
513 * 16 Bytes align
514 */
515 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
516 RING_DESC_ALIGN);
517 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
518 txring->next_to_use = 0;
519 atomic_set(&txring->next_to_clean, 0);
520 atomic_set(&txring->nr_free, jme->tx_ring_size);
521
522 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
523 jme->tx_ring_size, GFP_ATOMIC);
524 if (unlikely(!(txring->bufinf)))
525 goto err_free_txring;
526
527 /*
528 * Initialize Transmit Descriptors
529 */
530 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
531 memset(txring->bufinf, 0,
532 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
533
534 return 0;
535
536 err_free_txring:
537 dma_free_coherent(&(jme->pdev->dev),
538 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
539 txring->alloc,
540 txring->dmaalloc);
541
542 err_set_null:
543 txring->desc = NULL;
544 txring->dmaalloc = 0;
545 txring->dma = 0;
546 txring->bufinf = NULL;
547
548 return -ENOMEM;
549 }
550
551 static void
552 jme_free_tx_resources(struct jme_adapter *jme)
553 {
554 int i;
555 struct jme_ring *txring = &(jme->txring[0]);
556 struct jme_buffer_info *txbi;
557
558 if (txring->alloc) {
559 if (txring->bufinf) {
560 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
561 txbi = txring->bufinf + i;
562 if (txbi->skb) {
563 dev_kfree_skb(txbi->skb);
564 txbi->skb = NULL;
565 }
566 txbi->mapping = 0;
567 txbi->len = 0;
568 txbi->nr_desc = 0;
569 txbi->start_xmit = 0;
570 }
571 kfree(txring->bufinf);
572 }
573
574 dma_free_coherent(&(jme->pdev->dev),
575 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
576 txring->alloc,
577 txring->dmaalloc);
578
579 txring->alloc = NULL;
580 txring->desc = NULL;
581 txring->dmaalloc = 0;
582 txring->dma = 0;
583 txring->bufinf = NULL;
584 }
585 txring->next_to_use = 0;
586 atomic_set(&txring->next_to_clean, 0);
587 atomic_set(&txring->nr_free, 0);
588 }
589
590 static inline void
591 jme_enable_tx_engine(struct jme_adapter *jme)
592 {
593 /*
594 * Select Queue 0
595 */
596 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
597 wmb();
598
599 /*
600 * Setup TX Queue 0 DMA Bass Address
601 */
602 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
603 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
604 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
605
606 /*
607 * Setup TX Descptor Count
608 */
609 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
610
611 /*
612 * Enable TX Engine
613 */
614 wmb();
615 jwrite32(jme, JME_TXCS, jme->reg_txcs |
616 TXCS_SELECT_QUEUE0 |
617 TXCS_ENABLE);
618
619 }
620
621 static inline void
622 jme_restart_tx_engine(struct jme_adapter *jme)
623 {
624 /*
625 * Restart TX Engine
626 */
627 jwrite32(jme, JME_TXCS, jme->reg_txcs |
628 TXCS_SELECT_QUEUE0 |
629 TXCS_ENABLE);
630 }
631
632 static inline void
633 jme_disable_tx_engine(struct jme_adapter *jme)
634 {
635 int i;
636 u32 val;
637
638 /*
639 * Disable TX Engine
640 */
641 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
642 wmb();
643
644 val = jread32(jme, JME_TXCS);
645 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
646 mdelay(1);
647 val = jread32(jme, JME_TXCS);
648 rmb();
649 }
650
651 if (!i)
652 pr_err("Disable TX engine timeout\n");
653 }
654
655 static void
656 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
657 {
658 struct jme_ring *rxring = &(jme->rxring[0]);
659 register struct rxdesc *rxdesc = rxring->desc;
660 struct jme_buffer_info *rxbi = rxring->bufinf;
661 rxdesc += i;
662 rxbi += i;
663
664 rxdesc->dw[0] = 0;
665 rxdesc->dw[1] = 0;
666 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
667 rxdesc->desc1.bufaddrl = cpu_to_le32(
668 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
669 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
670 if (jme->dev->features & NETIF_F_HIGHDMA)
671 rxdesc->desc1.flags = RXFLAG_64BIT;
672 wmb();
673 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
674 }
675
676 static int
677 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
678 {
679 struct jme_ring *rxring = &(jme->rxring[0]);
680 struct jme_buffer_info *rxbi = rxring->bufinf + i;
681 struct sk_buff *skb;
682
683 skb = netdev_alloc_skb(jme->dev,
684 jme->dev->mtu + RX_EXTRA_LEN);
685 if (unlikely(!skb))
686 return -ENOMEM;
687
688 rxbi->skb = skb;
689 rxbi->len = skb_tailroom(skb);
690 rxbi->mapping = pci_map_page(jme->pdev,
691 virt_to_page(skb->data),
692 offset_in_page(skb->data),
693 rxbi->len,
694 PCI_DMA_FROMDEVICE);
695
696 return 0;
697 }
698
699 static void
700 jme_free_rx_buf(struct jme_adapter *jme, int i)
701 {
702 struct jme_ring *rxring = &(jme->rxring[0]);
703 struct jme_buffer_info *rxbi = rxring->bufinf;
704 rxbi += i;
705
706 if (rxbi->skb) {
707 pci_unmap_page(jme->pdev,
708 rxbi->mapping,
709 rxbi->len,
710 PCI_DMA_FROMDEVICE);
711 dev_kfree_skb(rxbi->skb);
712 rxbi->skb = NULL;
713 rxbi->mapping = 0;
714 rxbi->len = 0;
715 }
716 }
717
718 static void
719 jme_free_rx_resources(struct jme_adapter *jme)
720 {
721 int i;
722 struct jme_ring *rxring = &(jme->rxring[0]);
723
724 if (rxring->alloc) {
725 if (rxring->bufinf) {
726 for (i = 0 ; i < jme->rx_ring_size ; ++i)
727 jme_free_rx_buf(jme, i);
728 kfree(rxring->bufinf);
729 }
730
731 dma_free_coherent(&(jme->pdev->dev),
732 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
733 rxring->alloc,
734 rxring->dmaalloc);
735 rxring->alloc = NULL;
736 rxring->desc = NULL;
737 rxring->dmaalloc = 0;
738 rxring->dma = 0;
739 rxring->bufinf = NULL;
740 }
741 rxring->next_to_use = 0;
742 atomic_set(&rxring->next_to_clean, 0);
743 }
744
745 static int
746 jme_setup_rx_resources(struct jme_adapter *jme)
747 {
748 int i;
749 struct jme_ring *rxring = &(jme->rxring[0]);
750
751 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
752 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
753 &(rxring->dmaalloc),
754 GFP_ATOMIC);
755 if (!rxring->alloc)
756 goto err_set_null;
757
758 /*
759 * 16 Bytes align
760 */
761 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
762 RING_DESC_ALIGN);
763 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
764 rxring->next_to_use = 0;
765 atomic_set(&rxring->next_to_clean, 0);
766
767 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
768 jme->rx_ring_size, GFP_ATOMIC);
769 if (unlikely(!(rxring->bufinf)))
770 goto err_free_rxring;
771
772 /*
773 * Initiallize Receive Descriptors
774 */
775 memset(rxring->bufinf, 0,
776 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
777 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
778 if (unlikely(jme_make_new_rx_buf(jme, i))) {
779 jme_free_rx_resources(jme);
780 return -ENOMEM;
781 }
782
783 jme_set_clean_rxdesc(jme, i);
784 }
785
786 return 0;
787
788 err_free_rxring:
789 dma_free_coherent(&(jme->pdev->dev),
790 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
791 rxring->alloc,
792 rxring->dmaalloc);
793 err_set_null:
794 rxring->desc = NULL;
795 rxring->dmaalloc = 0;
796 rxring->dma = 0;
797 rxring->bufinf = NULL;
798
799 return -ENOMEM;
800 }
801
802 static inline void
803 jme_enable_rx_engine(struct jme_adapter *jme)
804 {
805 /*
806 * Select Queue 0
807 */
808 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
809 RXCS_QUEUESEL_Q0);
810 wmb();
811
812 /*
813 * Setup RX DMA Bass Address
814 */
815 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
816 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
817 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
818
819 /*
820 * Setup RX Descriptor Count
821 */
822 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
823
824 /*
825 * Setup Unicast Filter
826 */
827 jme_set_multi(jme->dev);
828
829 /*
830 * Enable RX Engine
831 */
832 wmb();
833 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
834 RXCS_QUEUESEL_Q0 |
835 RXCS_ENABLE |
836 RXCS_QST);
837 }
838
839 static inline void
840 jme_restart_rx_engine(struct jme_adapter *jme)
841 {
842 /*
843 * Start RX Engine
844 */
845 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
846 RXCS_QUEUESEL_Q0 |
847 RXCS_ENABLE |
848 RXCS_QST);
849 }
850
851 static inline void
852 jme_disable_rx_engine(struct jme_adapter *jme)
853 {
854 int i;
855 u32 val;
856
857 /*
858 * Disable RX Engine
859 */
860 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
861 wmb();
862
863 val = jread32(jme, JME_RXCS);
864 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
865 mdelay(1);
866 val = jread32(jme, JME_RXCS);
867 rmb();
868 }
869
870 if (!i)
871 pr_err("Disable RX engine timeout\n");
872
873 }
874
875 static int
876 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
877 {
878 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
879 return false;
880
881 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
882 == RXWBFLAG_TCPON)) {
883 if (flags & RXWBFLAG_IPV4)
884 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
885 return false;
886 }
887
888 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
889 == RXWBFLAG_UDPON)) {
890 if (flags & RXWBFLAG_IPV4)
891 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
892 return false;
893 }
894
895 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
896 == RXWBFLAG_IPV4)) {
897 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
898 return false;
899 }
900
901 return true;
902 }
903
904 static void
905 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
906 {
907 struct jme_ring *rxring = &(jme->rxring[0]);
908 struct rxdesc *rxdesc = rxring->desc;
909 struct jme_buffer_info *rxbi = rxring->bufinf;
910 struct sk_buff *skb;
911 int framesize;
912
913 rxdesc += idx;
914 rxbi += idx;
915
916 skb = rxbi->skb;
917 pci_dma_sync_single_for_cpu(jme->pdev,
918 rxbi->mapping,
919 rxbi->len,
920 PCI_DMA_FROMDEVICE);
921
922 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
923 pci_dma_sync_single_for_device(jme->pdev,
924 rxbi->mapping,
925 rxbi->len,
926 PCI_DMA_FROMDEVICE);
927
928 ++(NET_STAT(jme).rx_dropped);
929 } else {
930 framesize = le16_to_cpu(rxdesc->descwb.framesize)
931 - RX_PREPAD_SIZE;
932
933 skb_reserve(skb, RX_PREPAD_SIZE);
934 skb_put(skb, framesize);
935 skb->protocol = eth_type_trans(skb, jme->dev);
936
937 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
938 skb->ip_summed = CHECKSUM_UNNECESSARY;
939 else
940 skb_checksum_none_assert(skb);
941
942 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
943 if (jme->vlgrp) {
944 jme->jme_vlan_rx(skb, jme->vlgrp,
945 le16_to_cpu(rxdesc->descwb.vlan));
946 NET_STAT(jme).rx_bytes += 4;
947 } else {
948 dev_kfree_skb(skb);
949 }
950 } else {
951 jme->jme_rx(skb);
952 }
953
954 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
955 cpu_to_le16(RXWBFLAG_DEST_MUL))
956 ++(NET_STAT(jme).multicast);
957
958 NET_STAT(jme).rx_bytes += framesize;
959 ++(NET_STAT(jme).rx_packets);
960 }
961
962 jme_set_clean_rxdesc(jme, idx);
963
964 }
965
966 static int
967 jme_process_receive(struct jme_adapter *jme, int limit)
968 {
969 struct jme_ring *rxring = &(jme->rxring[0]);
970 struct rxdesc *rxdesc = rxring->desc;
971 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
972
973 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
974 goto out_inc;
975
976 if (unlikely(atomic_read(&jme->link_changing) != 1))
977 goto out_inc;
978
979 if (unlikely(!netif_carrier_ok(jme->dev)))
980 goto out_inc;
981
982 i = atomic_read(&rxring->next_to_clean);
983 while (limit > 0) {
984 rxdesc = rxring->desc;
985 rxdesc += i;
986
987 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
988 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
989 goto out;
990 --limit;
991
992 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
993
994 if (unlikely(desccnt > 1 ||
995 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
996
997 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
998 ++(NET_STAT(jme).rx_crc_errors);
999 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1000 ++(NET_STAT(jme).rx_fifo_errors);
1001 else
1002 ++(NET_STAT(jme).rx_errors);
1003
1004 if (desccnt > 1)
1005 limit -= desccnt - 1;
1006
1007 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1008 jme_set_clean_rxdesc(jme, j);
1009 j = (j + 1) & (mask);
1010 }
1011
1012 } else {
1013 jme_alloc_and_feed_skb(jme, i);
1014 }
1015
1016 i = (i + desccnt) & (mask);
1017 }
1018
1019 out:
1020 atomic_set(&rxring->next_to_clean, i);
1021
1022 out_inc:
1023 atomic_inc(&jme->rx_cleaning);
1024
1025 return limit > 0 ? limit : 0;
1026
1027 }
1028
1029 static void
1030 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1031 {
1032 if (likely(atmp == dpi->cur)) {
1033 dpi->cnt = 0;
1034 return;
1035 }
1036
1037 if (dpi->attempt == atmp) {
1038 ++(dpi->cnt);
1039 } else {
1040 dpi->attempt = atmp;
1041 dpi->cnt = 0;
1042 }
1043
1044 }
1045
1046 static void
1047 jme_dynamic_pcc(struct jme_adapter *jme)
1048 {
1049 register struct dynpcc_info *dpi = &(jme->dpi);
1050
1051 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1052 jme_attempt_pcc(dpi, PCC_P3);
1053 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1054 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1055 jme_attempt_pcc(dpi, PCC_P2);
1056 else
1057 jme_attempt_pcc(dpi, PCC_P1);
1058
1059 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1060 if (dpi->attempt < dpi->cur)
1061 tasklet_schedule(&jme->rxclean_task);
1062 jme_set_rx_pcc(jme, dpi->attempt);
1063 dpi->cur = dpi->attempt;
1064 dpi->cnt = 0;
1065 }
1066 }
1067
1068 static void
1069 jme_start_pcc_timer(struct jme_adapter *jme)
1070 {
1071 struct dynpcc_info *dpi = &(jme->dpi);
1072 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1073 dpi->last_pkts = NET_STAT(jme).rx_packets;
1074 dpi->intr_cnt = 0;
1075 jwrite32(jme, JME_TMCSR,
1076 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1077 }
1078
1079 static inline void
1080 jme_stop_pcc_timer(struct jme_adapter *jme)
1081 {
1082 jwrite32(jme, JME_TMCSR, 0);
1083 }
1084
1085 static void
1086 jme_shutdown_nic(struct jme_adapter *jme)
1087 {
1088 u32 phylink;
1089
1090 phylink = jme_linkstat_from_phy(jme);
1091
1092 if (!(phylink & PHY_LINK_UP)) {
1093 /*
1094 * Disable all interrupt before issue timer
1095 */
1096 jme_stop_irq(jme);
1097 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1098 }
1099 }
1100
1101 static void
1102 jme_pcc_tasklet(unsigned long arg)
1103 {
1104 struct jme_adapter *jme = (struct jme_adapter *)arg;
1105 struct net_device *netdev = jme->dev;
1106
1107 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1108 jme_shutdown_nic(jme);
1109 return;
1110 }
1111
1112 if (unlikely(!netif_carrier_ok(netdev) ||
1113 (atomic_read(&jme->link_changing) != 1)
1114 )) {
1115 jme_stop_pcc_timer(jme);
1116 return;
1117 }
1118
1119 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1120 jme_dynamic_pcc(jme);
1121
1122 jme_start_pcc_timer(jme);
1123 }
1124
1125 static inline void
1126 jme_polling_mode(struct jme_adapter *jme)
1127 {
1128 jme_set_rx_pcc(jme, PCC_OFF);
1129 }
1130
1131 static inline void
1132 jme_interrupt_mode(struct jme_adapter *jme)
1133 {
1134 jme_set_rx_pcc(jme, PCC_P1);
1135 }
1136
1137 static inline int
1138 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1139 {
1140 u32 apmc;
1141 apmc = jread32(jme, JME_APMC);
1142 return apmc & JME_APMC_PSEUDO_HP_EN;
1143 }
1144
1145 static void
1146 jme_start_shutdown_timer(struct jme_adapter *jme)
1147 {
1148 u32 apmc;
1149
1150 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1151 apmc &= ~JME_APMC_EPIEN_CTRL;
1152 if (!no_extplug) {
1153 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1154 wmb();
1155 }
1156 jwrite32f(jme, JME_APMC, apmc);
1157
1158 jwrite32f(jme, JME_TIMER2, 0);
1159 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1160 jwrite32(jme, JME_TMCSR,
1161 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1162 }
1163
1164 static void
1165 jme_stop_shutdown_timer(struct jme_adapter *jme)
1166 {
1167 u32 apmc;
1168
1169 jwrite32f(jme, JME_TMCSR, 0);
1170 jwrite32f(jme, JME_TIMER2, 0);
1171 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1172
1173 apmc = jread32(jme, JME_APMC);
1174 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1175 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1176 wmb();
1177 jwrite32f(jme, JME_APMC, apmc);
1178 }
1179
1180 static void
1181 jme_link_change_tasklet(unsigned long arg)
1182 {
1183 struct jme_adapter *jme = (struct jme_adapter *)arg;
1184 struct net_device *netdev = jme->dev;
1185 int rc;
1186
1187 while (!atomic_dec_and_test(&jme->link_changing)) {
1188 atomic_inc(&jme->link_changing);
1189 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1190 while (atomic_read(&jme->link_changing) != 1)
1191 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1192 }
1193
1194 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1195 goto out;
1196
1197 jme->old_mtu = netdev->mtu;
1198 netif_stop_queue(netdev);
1199 if (jme_pseudo_hotplug_enabled(jme))
1200 jme_stop_shutdown_timer(jme);
1201
1202 jme_stop_pcc_timer(jme);
1203 tasklet_disable(&jme->txclean_task);
1204 tasklet_disable(&jme->rxclean_task);
1205 tasklet_disable(&jme->rxempty_task);
1206
1207 if (netif_carrier_ok(netdev)) {
1208 jme_reset_ghc_speed(jme);
1209 jme_disable_rx_engine(jme);
1210 jme_disable_tx_engine(jme);
1211 jme_reset_mac_processor(jme);
1212 jme_free_rx_resources(jme);
1213 jme_free_tx_resources(jme);
1214
1215 if (test_bit(JME_FLAG_POLL, &jme->flags))
1216 jme_polling_mode(jme);
1217
1218 netif_carrier_off(netdev);
1219 }
1220
1221 jme_check_link(netdev, 0);
1222 if (netif_carrier_ok(netdev)) {
1223 rc = jme_setup_rx_resources(jme);
1224 if (rc) {
1225 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1226 goto out_enable_tasklet;
1227 }
1228
1229 rc = jme_setup_tx_resources(jme);
1230 if (rc) {
1231 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1232 goto err_out_free_rx_resources;
1233 }
1234
1235 jme_enable_rx_engine(jme);
1236 jme_enable_tx_engine(jme);
1237
1238 netif_start_queue(netdev);
1239
1240 if (test_bit(JME_FLAG_POLL, &jme->flags))
1241 jme_interrupt_mode(jme);
1242
1243 jme_start_pcc_timer(jme);
1244 } else if (jme_pseudo_hotplug_enabled(jme)) {
1245 jme_start_shutdown_timer(jme);
1246 }
1247
1248 goto out_enable_tasklet;
1249
1250 err_out_free_rx_resources:
1251 jme_free_rx_resources(jme);
1252 out_enable_tasklet:
1253 tasklet_enable(&jme->txclean_task);
1254 tasklet_hi_enable(&jme->rxclean_task);
1255 tasklet_hi_enable(&jme->rxempty_task);
1256 out:
1257 atomic_inc(&jme->link_changing);
1258 }
1259
1260 static void
1261 jme_rx_clean_tasklet(unsigned long arg)
1262 {
1263 struct jme_adapter *jme = (struct jme_adapter *)arg;
1264 struct dynpcc_info *dpi = &(jme->dpi);
1265
1266 jme_process_receive(jme, jme->rx_ring_size);
1267 ++(dpi->intr_cnt);
1268
1269 }
1270
1271 static int
1272 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1273 {
1274 struct jme_adapter *jme = jme_napi_priv(holder);
1275 int rest;
1276
1277 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1278
1279 while (atomic_read(&jme->rx_empty) > 0) {
1280 atomic_dec(&jme->rx_empty);
1281 ++(NET_STAT(jme).rx_dropped);
1282 jme_restart_rx_engine(jme);
1283 }
1284 atomic_inc(&jme->rx_empty);
1285
1286 if (rest) {
1287 JME_RX_COMPLETE(netdev, holder);
1288 jme_interrupt_mode(jme);
1289 }
1290
1291 JME_NAPI_WEIGHT_SET(budget, rest);
1292 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1293 }
1294
1295 static void
1296 jme_rx_empty_tasklet(unsigned long arg)
1297 {
1298 struct jme_adapter *jme = (struct jme_adapter *)arg;
1299
1300 if (unlikely(atomic_read(&jme->link_changing) != 1))
1301 return;
1302
1303 if (unlikely(!netif_carrier_ok(jme->dev)))
1304 return;
1305
1306 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1307
1308 jme_rx_clean_tasklet(arg);
1309
1310 while (atomic_read(&jme->rx_empty) > 0) {
1311 atomic_dec(&jme->rx_empty);
1312 ++(NET_STAT(jme).rx_dropped);
1313 jme_restart_rx_engine(jme);
1314 }
1315 atomic_inc(&jme->rx_empty);
1316 }
1317
1318 static void
1319 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1320 {
1321 struct jme_ring *txring = &(jme->txring[0]);
1322
1323 smp_wmb();
1324 if (unlikely(netif_queue_stopped(jme->dev) &&
1325 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1326 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1327 netif_wake_queue(jme->dev);
1328 }
1329
1330 }
1331
1332 static void
1333 jme_tx_clean_tasklet(unsigned long arg)
1334 {
1335 struct jme_adapter *jme = (struct jme_adapter *)arg;
1336 struct jme_ring *txring = &(jme->txring[0]);
1337 struct txdesc *txdesc = txring->desc;
1338 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1339 int i, j, cnt = 0, max, err, mask;
1340
1341 tx_dbg(jme, "Into txclean\n");
1342
1343 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1344 goto out;
1345
1346 if (unlikely(atomic_read(&jme->link_changing) != 1))
1347 goto out;
1348
1349 if (unlikely(!netif_carrier_ok(jme->dev)))
1350 goto out;
1351
1352 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1353 mask = jme->tx_ring_mask;
1354
1355 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1356
1357 ctxbi = txbi + i;
1358
1359 if (likely(ctxbi->skb &&
1360 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1361
1362 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1363 i, ctxbi->nr_desc, jiffies);
1364
1365 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1366
1367 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1368 ttxbi = txbi + ((i + j) & (mask));
1369 txdesc[(i + j) & (mask)].dw[0] = 0;
1370
1371 pci_unmap_page(jme->pdev,
1372 ttxbi->mapping,
1373 ttxbi->len,
1374 PCI_DMA_TODEVICE);
1375
1376 ttxbi->mapping = 0;
1377 ttxbi->len = 0;
1378 }
1379
1380 dev_kfree_skb(ctxbi->skb);
1381
1382 cnt += ctxbi->nr_desc;
1383
1384 if (unlikely(err)) {
1385 ++(NET_STAT(jme).tx_carrier_errors);
1386 } else {
1387 ++(NET_STAT(jme).tx_packets);
1388 NET_STAT(jme).tx_bytes += ctxbi->len;
1389 }
1390
1391 ctxbi->skb = NULL;
1392 ctxbi->len = 0;
1393 ctxbi->start_xmit = 0;
1394
1395 } else {
1396 break;
1397 }
1398
1399 i = (i + ctxbi->nr_desc) & mask;
1400
1401 ctxbi->nr_desc = 0;
1402 }
1403
1404 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1405 atomic_set(&txring->next_to_clean, i);
1406 atomic_add(cnt, &txring->nr_free);
1407
1408 jme_wake_queue_if_stopped(jme);
1409
1410 out:
1411 atomic_inc(&jme->tx_cleaning);
1412 }
1413
1414 static void
1415 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1416 {
1417 /*
1418 * Disable interrupt
1419 */
1420 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1421
1422 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1423 /*
1424 * Link change event is critical
1425 * all other events are ignored
1426 */
1427 jwrite32(jme, JME_IEVE, intrstat);
1428 tasklet_schedule(&jme->linkch_task);
1429 goto out_reenable;
1430 }
1431
1432 if (intrstat & INTR_TMINTR) {
1433 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1434 tasklet_schedule(&jme->pcc_task);
1435 }
1436
1437 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1438 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1439 tasklet_schedule(&jme->txclean_task);
1440 }
1441
1442 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1443 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1444 INTR_PCCRX0 |
1445 INTR_RX0EMP)) |
1446 INTR_RX0);
1447 }
1448
1449 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1450 if (intrstat & INTR_RX0EMP)
1451 atomic_inc(&jme->rx_empty);
1452
1453 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1454 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1455 jme_polling_mode(jme);
1456 JME_RX_SCHEDULE(jme);
1457 }
1458 }
1459 } else {
1460 if (intrstat & INTR_RX0EMP) {
1461 atomic_inc(&jme->rx_empty);
1462 tasklet_hi_schedule(&jme->rxempty_task);
1463 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1464 tasklet_hi_schedule(&jme->rxclean_task);
1465 }
1466 }
1467
1468 out_reenable:
1469 /*
1470 * Re-enable interrupt
1471 */
1472 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1473 }
1474
1475 static irqreturn_t
1476 jme_intr(int irq, void *dev_id)
1477 {
1478 struct net_device *netdev = dev_id;
1479 struct jme_adapter *jme = netdev_priv(netdev);
1480 u32 intrstat;
1481
1482 intrstat = jread32(jme, JME_IEVE);
1483
1484 /*
1485 * Check if it's really an interrupt for us
1486 */
1487 if (unlikely((intrstat & INTR_ENABLE) == 0))
1488 return IRQ_NONE;
1489
1490 /*
1491 * Check if the device still exist
1492 */
1493 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1494 return IRQ_NONE;
1495
1496 jme_intr_msi(jme, intrstat);
1497
1498 return IRQ_HANDLED;
1499 }
1500
1501 static irqreturn_t
1502 jme_msi(int irq, void *dev_id)
1503 {
1504 struct net_device *netdev = dev_id;
1505 struct jme_adapter *jme = netdev_priv(netdev);
1506 u32 intrstat;
1507
1508 intrstat = jread32(jme, JME_IEVE);
1509
1510 jme_intr_msi(jme, intrstat);
1511
1512 return IRQ_HANDLED;
1513 }
1514
1515 static void
1516 jme_reset_link(struct jme_adapter *jme)
1517 {
1518 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1519 }
1520
1521 static void
1522 jme_restart_an(struct jme_adapter *jme)
1523 {
1524 u32 bmcr;
1525
1526 spin_lock_bh(&jme->phy_lock);
1527 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1528 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1529 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1530 spin_unlock_bh(&jme->phy_lock);
1531 }
1532
1533 static int
1534 jme_request_irq(struct jme_adapter *jme)
1535 {
1536 int rc;
1537 struct net_device *netdev = jme->dev;
1538 irq_handler_t handler = jme_intr;
1539 int irq_flags = IRQF_SHARED;
1540
1541 if (!pci_enable_msi(jme->pdev)) {
1542 set_bit(JME_FLAG_MSI, &jme->flags);
1543 handler = jme_msi;
1544 irq_flags = 0;
1545 }
1546
1547 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1548 netdev);
1549 if (rc) {
1550 netdev_err(netdev,
1551 "Unable to request %s interrupt (return: %d)\n",
1552 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1553 rc);
1554
1555 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1556 pci_disable_msi(jme->pdev);
1557 clear_bit(JME_FLAG_MSI, &jme->flags);
1558 }
1559 } else {
1560 netdev->irq = jme->pdev->irq;
1561 }
1562
1563 return rc;
1564 }
1565
1566 static void
1567 jme_free_irq(struct jme_adapter *jme)
1568 {
1569 free_irq(jme->pdev->irq, jme->dev);
1570 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1571 pci_disable_msi(jme->pdev);
1572 clear_bit(JME_FLAG_MSI, &jme->flags);
1573 jme->dev->irq = jme->pdev->irq;
1574 }
1575 }
1576
1577 static int
1578 jme_open(struct net_device *netdev)
1579 {
1580 struct jme_adapter *jme = netdev_priv(netdev);
1581 int rc;
1582
1583 jme_clear_pm(jme);
1584 JME_NAPI_ENABLE(jme);
1585
1586 tasklet_enable(&jme->linkch_task);
1587 tasklet_enable(&jme->txclean_task);
1588 tasklet_hi_enable(&jme->rxclean_task);
1589 tasklet_hi_enable(&jme->rxempty_task);
1590
1591 rc = jme_request_irq(jme);
1592 if (rc)
1593 goto err_out;
1594
1595 jme_start_irq(jme);
1596
1597 if (test_bit(JME_FLAG_SSET, &jme->flags))
1598 jme_set_settings(netdev, &jme->old_ecmd);
1599 else
1600 jme_reset_phy_processor(jme);
1601
1602 jme_reset_link(jme);
1603
1604 return 0;
1605
1606 err_out:
1607 netif_stop_queue(netdev);
1608 netif_carrier_off(netdev);
1609 return rc;
1610 }
1611
1612 #ifdef CONFIG_PM
1613 static void
1614 jme_set_100m_half(struct jme_adapter *jme)
1615 {
1616 u32 bmcr, tmp;
1617
1618 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1619 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1620 BMCR_SPEED1000 | BMCR_FULLDPLX);
1621 tmp |= BMCR_SPEED100;
1622
1623 if (bmcr != tmp)
1624 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1625
1626 if (jme->fpgaver)
1627 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1628 else
1629 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1630 }
1631
1632 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1633 static void
1634 jme_wait_link(struct jme_adapter *jme)
1635 {
1636 u32 phylink, to = JME_WAIT_LINK_TIME;
1637
1638 mdelay(1000);
1639 phylink = jme_linkstat_from_phy(jme);
1640 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1641 mdelay(10);
1642 phylink = jme_linkstat_from_phy(jme);
1643 }
1644 }
1645 #endif
1646
1647 static inline void
1648 jme_phy_off(struct jme_adapter *jme)
1649 {
1650 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1651 }
1652
1653 static int
1654 jme_close(struct net_device *netdev)
1655 {
1656 struct jme_adapter *jme = netdev_priv(netdev);
1657
1658 netif_stop_queue(netdev);
1659 netif_carrier_off(netdev);
1660
1661 jme_stop_irq(jme);
1662 jme_free_irq(jme);
1663
1664 JME_NAPI_DISABLE(jme);
1665
1666 tasklet_disable(&jme->linkch_task);
1667 tasklet_disable(&jme->txclean_task);
1668 tasklet_disable(&jme->rxclean_task);
1669 tasklet_disable(&jme->rxempty_task);
1670
1671 jme_reset_ghc_speed(jme);
1672 jme_disable_rx_engine(jme);
1673 jme_disable_tx_engine(jme);
1674 jme_reset_mac_processor(jme);
1675 jme_free_rx_resources(jme);
1676 jme_free_tx_resources(jme);
1677 jme->phylink = 0;
1678 jme_phy_off(jme);
1679
1680 return 0;
1681 }
1682
1683 static int
1684 jme_alloc_txdesc(struct jme_adapter *jme,
1685 struct sk_buff *skb)
1686 {
1687 struct jme_ring *txring = &(jme->txring[0]);
1688 int idx, nr_alloc, mask = jme->tx_ring_mask;
1689
1690 idx = txring->next_to_use;
1691 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1692
1693 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1694 return -1;
1695
1696 atomic_sub(nr_alloc, &txring->nr_free);
1697
1698 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1699
1700 return idx;
1701 }
1702
1703 static void
1704 jme_fill_tx_map(struct pci_dev *pdev,
1705 struct txdesc *txdesc,
1706 struct jme_buffer_info *txbi,
1707 struct page *page,
1708 u32 page_offset,
1709 u32 len,
1710 u8 hidma)
1711 {
1712 dma_addr_t dmaaddr;
1713
1714 dmaaddr = pci_map_page(pdev,
1715 page,
1716 page_offset,
1717 len,
1718 PCI_DMA_TODEVICE);
1719
1720 pci_dma_sync_single_for_device(pdev,
1721 dmaaddr,
1722 len,
1723 PCI_DMA_TODEVICE);
1724
1725 txdesc->dw[0] = 0;
1726 txdesc->dw[1] = 0;
1727 txdesc->desc2.flags = TXFLAG_OWN;
1728 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1729 txdesc->desc2.datalen = cpu_to_le16(len);
1730 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1731 txdesc->desc2.bufaddrl = cpu_to_le32(
1732 (__u64)dmaaddr & 0xFFFFFFFFUL);
1733
1734 txbi->mapping = dmaaddr;
1735 txbi->len = len;
1736 }
1737
1738 static void
1739 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1740 {
1741 struct jme_ring *txring = &(jme->txring[0]);
1742 struct txdesc *txdesc = txring->desc, *ctxdesc;
1743 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1744 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1745 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1746 int mask = jme->tx_ring_mask;
1747 struct skb_frag_struct *frag;
1748 u32 len;
1749
1750 for (i = 0 ; i < nr_frags ; ++i) {
1751 frag = &skb_shinfo(skb)->frags[i];
1752 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1753 ctxbi = txbi + ((idx + i + 2) & (mask));
1754
1755 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1756 frag->page_offset, frag->size, hidma);
1757 }
1758
1759 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1760 ctxdesc = txdesc + ((idx + 1) & (mask));
1761 ctxbi = txbi + ((idx + 1) & (mask));
1762 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1763 offset_in_page(skb->data), len, hidma);
1764
1765 }
1766
1767 static int
1768 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1769 {
1770 if (unlikely(skb_shinfo(skb)->gso_size &&
1771 skb_header_cloned(skb) &&
1772 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1773 dev_kfree_skb(skb);
1774 return -1;
1775 }
1776
1777 return 0;
1778 }
1779
1780 static int
1781 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1782 {
1783 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1784 if (*mss) {
1785 *flags |= TXFLAG_LSEN;
1786
1787 if (skb->protocol == htons(ETH_P_IP)) {
1788 struct iphdr *iph = ip_hdr(skb);
1789
1790 iph->check = 0;
1791 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1792 iph->daddr, 0,
1793 IPPROTO_TCP,
1794 0);
1795 } else {
1796 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1797
1798 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1799 &ip6h->daddr, 0,
1800 IPPROTO_TCP,
1801 0);
1802 }
1803
1804 return 0;
1805 }
1806
1807 return 1;
1808 }
1809
1810 static void
1811 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1812 {
1813 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1814 u8 ip_proto;
1815
1816 switch (skb->protocol) {
1817 case htons(ETH_P_IP):
1818 ip_proto = ip_hdr(skb)->protocol;
1819 break;
1820 case htons(ETH_P_IPV6):
1821 ip_proto = ipv6_hdr(skb)->nexthdr;
1822 break;
1823 default:
1824 ip_proto = 0;
1825 break;
1826 }
1827
1828 switch (ip_proto) {
1829 case IPPROTO_TCP:
1830 *flags |= TXFLAG_TCPCS;
1831 break;
1832 case IPPROTO_UDP:
1833 *flags |= TXFLAG_UDPCS;
1834 break;
1835 default:
1836 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1837 break;
1838 }
1839 }
1840 }
1841
1842 static inline void
1843 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1844 {
1845 if (vlan_tx_tag_present(skb)) {
1846 *flags |= TXFLAG_TAGON;
1847 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1848 }
1849 }
1850
1851 static int
1852 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1853 {
1854 struct jme_ring *txring = &(jme->txring[0]);
1855 struct txdesc *txdesc;
1856 struct jme_buffer_info *txbi;
1857 u8 flags;
1858
1859 txdesc = (struct txdesc *)txring->desc + idx;
1860 txbi = txring->bufinf + idx;
1861
1862 txdesc->dw[0] = 0;
1863 txdesc->dw[1] = 0;
1864 txdesc->dw[2] = 0;
1865 txdesc->dw[3] = 0;
1866 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1867 /*
1868 * Set OWN bit at final.
1869 * When kernel transmit faster than NIC.
1870 * And NIC trying to send this descriptor before we tell
1871 * it to start sending this TX queue.
1872 * Other fields are already filled correctly.
1873 */
1874 wmb();
1875 flags = TXFLAG_OWN | TXFLAG_INT;
1876 /*
1877 * Set checksum flags while not tso
1878 */
1879 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1880 jme_tx_csum(jme, skb, &flags);
1881 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1882 jme_map_tx_skb(jme, skb, idx);
1883 txdesc->desc1.flags = flags;
1884 /*
1885 * Set tx buffer info after telling NIC to send
1886 * For better tx_clean timing
1887 */
1888 wmb();
1889 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1890 txbi->skb = skb;
1891 txbi->len = skb->len;
1892 txbi->start_xmit = jiffies;
1893 if (!txbi->start_xmit)
1894 txbi->start_xmit = (0UL-1);
1895
1896 return 0;
1897 }
1898
1899 static void
1900 jme_stop_queue_if_full(struct jme_adapter *jme)
1901 {
1902 struct jme_ring *txring = &(jme->txring[0]);
1903 struct jme_buffer_info *txbi = txring->bufinf;
1904 int idx = atomic_read(&txring->next_to_clean);
1905
1906 txbi += idx;
1907
1908 smp_wmb();
1909 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1910 netif_stop_queue(jme->dev);
1911 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
1912 smp_wmb();
1913 if (atomic_read(&txring->nr_free)
1914 >= (jme->tx_wake_threshold)) {
1915 netif_wake_queue(jme->dev);
1916 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
1917 }
1918 }
1919
1920 if (unlikely(txbi->start_xmit &&
1921 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1922 txbi->skb)) {
1923 netif_stop_queue(jme->dev);
1924 netif_info(jme, tx_queued, jme->dev,
1925 "TX Queue Stopped %d@%lu\n", idx, jiffies);
1926 }
1927 }
1928
1929 /*
1930 * This function is already protected by netif_tx_lock()
1931 */
1932
1933 static netdev_tx_t
1934 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1935 {
1936 struct jme_adapter *jme = netdev_priv(netdev);
1937 int idx;
1938
1939 if (unlikely(jme_expand_header(jme, skb))) {
1940 ++(NET_STAT(jme).tx_dropped);
1941 return NETDEV_TX_OK;
1942 }
1943
1944 idx = jme_alloc_txdesc(jme, skb);
1945
1946 if (unlikely(idx < 0)) {
1947 netif_stop_queue(netdev);
1948 netif_err(jme, tx_err, jme->dev,
1949 "BUG! Tx ring full when queue awake!\n");
1950
1951 return NETDEV_TX_BUSY;
1952 }
1953
1954 jme_fill_tx_desc(jme, skb, idx);
1955
1956 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1957 TXCS_SELECT_QUEUE0 |
1958 TXCS_QUEUE0S |
1959 TXCS_ENABLE);
1960
1961 tx_dbg(jme, "xmit: %d+%d@%lu\n",
1962 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
1963 jme_stop_queue_if_full(jme);
1964
1965 return NETDEV_TX_OK;
1966 }
1967
1968 static int
1969 jme_set_macaddr(struct net_device *netdev, void *p)
1970 {
1971 struct jme_adapter *jme = netdev_priv(netdev);
1972 struct sockaddr *addr = p;
1973 u32 val;
1974
1975 if (netif_running(netdev))
1976 return -EBUSY;
1977
1978 spin_lock_bh(&jme->macaddr_lock);
1979 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1980
1981 val = (addr->sa_data[3] & 0xff) << 24 |
1982 (addr->sa_data[2] & 0xff) << 16 |
1983 (addr->sa_data[1] & 0xff) << 8 |
1984 (addr->sa_data[0] & 0xff);
1985 jwrite32(jme, JME_RXUMA_LO, val);
1986 val = (addr->sa_data[5] & 0xff) << 8 |
1987 (addr->sa_data[4] & 0xff);
1988 jwrite32(jme, JME_RXUMA_HI, val);
1989 spin_unlock_bh(&jme->macaddr_lock);
1990
1991 return 0;
1992 }
1993
1994 static void
1995 jme_set_multi(struct net_device *netdev)
1996 {
1997 struct jme_adapter *jme = netdev_priv(netdev);
1998 u32 mc_hash[2] = {};
1999
2000 spin_lock_bh(&jme->rxmcs_lock);
2001
2002 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2003
2004 if (netdev->flags & IFF_PROMISC) {
2005 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2006 } else if (netdev->flags & IFF_ALLMULTI) {
2007 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2008 } else if (netdev->flags & IFF_MULTICAST) {
2009 struct netdev_hw_addr *ha;
2010 int bit_nr;
2011
2012 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2013 netdev_for_each_mc_addr(ha, netdev) {
2014 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2015 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2016 }
2017
2018 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2019 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2020 }
2021
2022 wmb();
2023 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2024
2025 spin_unlock_bh(&jme->rxmcs_lock);
2026 }
2027
2028 static int
2029 jme_change_mtu(struct net_device *netdev, int new_mtu)
2030 {
2031 struct jme_adapter *jme = netdev_priv(netdev);
2032
2033 if (new_mtu == jme->old_mtu)
2034 return 0;
2035
2036 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2037 ((new_mtu) < IPV6_MIN_MTU))
2038 return -EINVAL;
2039
2040 if (new_mtu > 4000) {
2041 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2042 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2043 jme_restart_rx_engine(jme);
2044 } else {
2045 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2046 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2047 jme_restart_rx_engine(jme);
2048 }
2049
2050 if (new_mtu > 1900) {
2051 netdev->features &= ~(NETIF_F_HW_CSUM |
2052 NETIF_F_TSO |
2053 NETIF_F_TSO6);
2054 } else {
2055 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2056 netdev->features |= NETIF_F_HW_CSUM;
2057 if (test_bit(JME_FLAG_TSO, &jme->flags))
2058 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2059 }
2060
2061 netdev->mtu = new_mtu;
2062 jme_reset_link(jme);
2063
2064 return 0;
2065 }
2066
2067 static void
2068 jme_tx_timeout(struct net_device *netdev)
2069 {
2070 struct jme_adapter *jme = netdev_priv(netdev);
2071
2072 jme->phylink = 0;
2073 jme_reset_phy_processor(jme);
2074 if (test_bit(JME_FLAG_SSET, &jme->flags))
2075 jme_set_settings(netdev, &jme->old_ecmd);
2076
2077 /*
2078 * Force to Reset the link again
2079 */
2080 jme_reset_link(jme);
2081 }
2082
2083 static inline void jme_pause_rx(struct jme_adapter *jme)
2084 {
2085 atomic_dec(&jme->link_changing);
2086
2087 jme_set_rx_pcc(jme, PCC_OFF);
2088 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2089 JME_NAPI_DISABLE(jme);
2090 } else {
2091 tasklet_disable(&jme->rxclean_task);
2092 tasklet_disable(&jme->rxempty_task);
2093 }
2094 }
2095
2096 static inline void jme_resume_rx(struct jme_adapter *jme)
2097 {
2098 struct dynpcc_info *dpi = &(jme->dpi);
2099
2100 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2101 JME_NAPI_ENABLE(jme);
2102 } else {
2103 tasklet_hi_enable(&jme->rxclean_task);
2104 tasklet_hi_enable(&jme->rxempty_task);
2105 }
2106 dpi->cur = PCC_P1;
2107 dpi->attempt = PCC_P1;
2108 dpi->cnt = 0;
2109 jme_set_rx_pcc(jme, PCC_P1);
2110
2111 atomic_inc(&jme->link_changing);
2112 }
2113
2114 static void
2115 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2116 {
2117 struct jme_adapter *jme = netdev_priv(netdev);
2118
2119 jme_pause_rx(jme);
2120 jme->vlgrp = grp;
2121 jme_resume_rx(jme);
2122 }
2123
2124 static void
2125 jme_get_drvinfo(struct net_device *netdev,
2126 struct ethtool_drvinfo *info)
2127 {
2128 struct jme_adapter *jme = netdev_priv(netdev);
2129
2130 strcpy(info->driver, DRV_NAME);
2131 strcpy(info->version, DRV_VERSION);
2132 strcpy(info->bus_info, pci_name(jme->pdev));
2133 }
2134
2135 static int
2136 jme_get_regs_len(struct net_device *netdev)
2137 {
2138 return JME_REG_LEN;
2139 }
2140
2141 static void
2142 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2143 {
2144 int i;
2145
2146 for (i = 0 ; i < len ; i += 4)
2147 p[i >> 2] = jread32(jme, reg + i);
2148 }
2149
2150 static void
2151 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2152 {
2153 int i;
2154 u16 *p16 = (u16 *)p;
2155
2156 for (i = 0 ; i < reg_nr ; ++i)
2157 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2158 }
2159
2160 static void
2161 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2162 {
2163 struct jme_adapter *jme = netdev_priv(netdev);
2164 u32 *p32 = (u32 *)p;
2165
2166 memset(p, 0xFF, JME_REG_LEN);
2167
2168 regs->version = 1;
2169 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2170
2171 p32 += 0x100 >> 2;
2172 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2173
2174 p32 += 0x100 >> 2;
2175 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2176
2177 p32 += 0x100 >> 2;
2178 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2179
2180 p32 += 0x100 >> 2;
2181 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2182 }
2183
2184 static int
2185 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2186 {
2187 struct jme_adapter *jme = netdev_priv(netdev);
2188
2189 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2190 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2191
2192 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2193 ecmd->use_adaptive_rx_coalesce = false;
2194 ecmd->rx_coalesce_usecs = 0;
2195 ecmd->rx_max_coalesced_frames = 0;
2196 return 0;
2197 }
2198
2199 ecmd->use_adaptive_rx_coalesce = true;
2200
2201 switch (jme->dpi.cur) {
2202 case PCC_P1:
2203 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2204 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2205 break;
2206 case PCC_P2:
2207 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2208 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2209 break;
2210 case PCC_P3:
2211 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2212 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2213 break;
2214 default:
2215 break;
2216 }
2217
2218 return 0;
2219 }
2220
2221 static int
2222 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2223 {
2224 struct jme_adapter *jme = netdev_priv(netdev);
2225 struct dynpcc_info *dpi = &(jme->dpi);
2226
2227 if (netif_running(netdev))
2228 return -EBUSY;
2229
2230 if (ecmd->use_adaptive_rx_coalesce &&
2231 test_bit(JME_FLAG_POLL, &jme->flags)) {
2232 clear_bit(JME_FLAG_POLL, &jme->flags);
2233 jme->jme_rx = netif_rx;
2234 jme->jme_vlan_rx = vlan_hwaccel_rx;
2235 dpi->cur = PCC_P1;
2236 dpi->attempt = PCC_P1;
2237 dpi->cnt = 0;
2238 jme_set_rx_pcc(jme, PCC_P1);
2239 jme_interrupt_mode(jme);
2240 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2241 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2242 set_bit(JME_FLAG_POLL, &jme->flags);
2243 jme->jme_rx = netif_receive_skb;
2244 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2245 jme_interrupt_mode(jme);
2246 }
2247
2248 return 0;
2249 }
2250
2251 static void
2252 jme_get_pauseparam(struct net_device *netdev,
2253 struct ethtool_pauseparam *ecmd)
2254 {
2255 struct jme_adapter *jme = netdev_priv(netdev);
2256 u32 val;
2257
2258 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2259 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2260
2261 spin_lock_bh(&jme->phy_lock);
2262 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2263 spin_unlock_bh(&jme->phy_lock);
2264
2265 ecmd->autoneg =
2266 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2267 }
2268
2269 static int
2270 jme_set_pauseparam(struct net_device *netdev,
2271 struct ethtool_pauseparam *ecmd)
2272 {
2273 struct jme_adapter *jme = netdev_priv(netdev);
2274 u32 val;
2275
2276 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2277 (ecmd->tx_pause != 0)) {
2278
2279 if (ecmd->tx_pause)
2280 jme->reg_txpfc |= TXPFC_PF_EN;
2281 else
2282 jme->reg_txpfc &= ~TXPFC_PF_EN;
2283
2284 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2285 }
2286
2287 spin_lock_bh(&jme->rxmcs_lock);
2288 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2289 (ecmd->rx_pause != 0)) {
2290
2291 if (ecmd->rx_pause)
2292 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2293 else
2294 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2295
2296 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2297 }
2298 spin_unlock_bh(&jme->rxmcs_lock);
2299
2300 spin_lock_bh(&jme->phy_lock);
2301 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2302 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2303 (ecmd->autoneg != 0)) {
2304
2305 if (ecmd->autoneg)
2306 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2307 else
2308 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2309
2310 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2311 MII_ADVERTISE, val);
2312 }
2313 spin_unlock_bh(&jme->phy_lock);
2314
2315 return 0;
2316 }
2317
2318 static void
2319 jme_get_wol(struct net_device *netdev,
2320 struct ethtool_wolinfo *wol)
2321 {
2322 struct jme_adapter *jme = netdev_priv(netdev);
2323
2324 wol->supported = WAKE_MAGIC | WAKE_PHY;
2325
2326 wol->wolopts = 0;
2327
2328 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2329 wol->wolopts |= WAKE_PHY;
2330
2331 if (jme->reg_pmcs & PMCS_MFEN)
2332 wol->wolopts |= WAKE_MAGIC;
2333
2334 }
2335
2336 static int
2337 jme_set_wol(struct net_device *netdev,
2338 struct ethtool_wolinfo *wol)
2339 {
2340 struct jme_adapter *jme = netdev_priv(netdev);
2341
2342 if (wol->wolopts & (WAKE_MAGICSECURE |
2343 WAKE_UCAST |
2344 WAKE_MCAST |
2345 WAKE_BCAST |
2346 WAKE_ARP))
2347 return -EOPNOTSUPP;
2348
2349 jme->reg_pmcs = 0;
2350
2351 if (wol->wolopts & WAKE_PHY)
2352 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2353
2354 if (wol->wolopts & WAKE_MAGIC)
2355 jme->reg_pmcs |= PMCS_MFEN;
2356
2357 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2358
2359 return 0;
2360 }
2361
2362 static int
2363 jme_get_settings(struct net_device *netdev,
2364 struct ethtool_cmd *ecmd)
2365 {
2366 struct jme_adapter *jme = netdev_priv(netdev);
2367 int rc;
2368
2369 spin_lock_bh(&jme->phy_lock);
2370 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2371 spin_unlock_bh(&jme->phy_lock);
2372 return rc;
2373 }
2374
2375 static int
2376 jme_set_settings(struct net_device *netdev,
2377 struct ethtool_cmd *ecmd)
2378 {
2379 struct jme_adapter *jme = netdev_priv(netdev);
2380 int rc, fdc = 0;
2381
2382 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2383 return -EINVAL;
2384
2385 if (jme->mii_if.force_media &&
2386 ecmd->autoneg != AUTONEG_ENABLE &&
2387 (jme->mii_if.full_duplex != ecmd->duplex))
2388 fdc = 1;
2389
2390 spin_lock_bh(&jme->phy_lock);
2391 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2392 spin_unlock_bh(&jme->phy_lock);
2393
2394 if (!rc && fdc)
2395 jme_reset_link(jme);
2396
2397 if (!rc) {
2398 set_bit(JME_FLAG_SSET, &jme->flags);
2399 jme->old_ecmd = *ecmd;
2400 }
2401
2402 return rc;
2403 }
2404
2405 static u32
2406 jme_get_link(struct net_device *netdev)
2407 {
2408 struct jme_adapter *jme = netdev_priv(netdev);
2409 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2410 }
2411
2412 static u32
2413 jme_get_msglevel(struct net_device *netdev)
2414 {
2415 struct jme_adapter *jme = netdev_priv(netdev);
2416 return jme->msg_enable;
2417 }
2418
2419 static void
2420 jme_set_msglevel(struct net_device *netdev, u32 value)
2421 {
2422 struct jme_adapter *jme = netdev_priv(netdev);
2423 jme->msg_enable = value;
2424 }
2425
2426 static u32
2427 jme_get_rx_csum(struct net_device *netdev)
2428 {
2429 struct jme_adapter *jme = netdev_priv(netdev);
2430 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2431 }
2432
2433 static int
2434 jme_set_rx_csum(struct net_device *netdev, u32 on)
2435 {
2436 struct jme_adapter *jme = netdev_priv(netdev);
2437
2438 spin_lock_bh(&jme->rxmcs_lock);
2439 if (on)
2440 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2441 else
2442 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2443 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2444 spin_unlock_bh(&jme->rxmcs_lock);
2445
2446 return 0;
2447 }
2448
2449 static int
2450 jme_set_tx_csum(struct net_device *netdev, u32 on)
2451 {
2452 struct jme_adapter *jme = netdev_priv(netdev);
2453
2454 if (on) {
2455 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2456 if (netdev->mtu <= 1900)
2457 netdev->features |= NETIF_F_HW_CSUM;
2458 } else {
2459 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2460 netdev->features &= ~NETIF_F_HW_CSUM;
2461 }
2462
2463 return 0;
2464 }
2465
2466 static int
2467 jme_set_tso(struct net_device *netdev, u32 on)
2468 {
2469 struct jme_adapter *jme = netdev_priv(netdev);
2470
2471 if (on) {
2472 set_bit(JME_FLAG_TSO, &jme->flags);
2473 if (netdev->mtu <= 1900)
2474 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2475 } else {
2476 clear_bit(JME_FLAG_TSO, &jme->flags);
2477 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2478 }
2479
2480 return 0;
2481 }
2482
2483 static int
2484 jme_nway_reset(struct net_device *netdev)
2485 {
2486 struct jme_adapter *jme = netdev_priv(netdev);
2487 jme_restart_an(jme);
2488 return 0;
2489 }
2490
2491 static u8
2492 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2493 {
2494 u32 val;
2495 int to;
2496
2497 val = jread32(jme, JME_SMBCSR);
2498 to = JME_SMB_BUSY_TIMEOUT;
2499 while ((val & SMBCSR_BUSY) && --to) {
2500 msleep(1);
2501 val = jread32(jme, JME_SMBCSR);
2502 }
2503 if (!to) {
2504 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2505 return 0xFF;
2506 }
2507
2508 jwrite32(jme, JME_SMBINTF,
2509 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2510 SMBINTF_HWRWN_READ |
2511 SMBINTF_HWCMD);
2512
2513 val = jread32(jme, JME_SMBINTF);
2514 to = JME_SMB_BUSY_TIMEOUT;
2515 while ((val & SMBINTF_HWCMD) && --to) {
2516 msleep(1);
2517 val = jread32(jme, JME_SMBINTF);
2518 }
2519 if (!to) {
2520 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2521 return 0xFF;
2522 }
2523
2524 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2525 }
2526
2527 static void
2528 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2529 {
2530 u32 val;
2531 int to;
2532
2533 val = jread32(jme, JME_SMBCSR);
2534 to = JME_SMB_BUSY_TIMEOUT;
2535 while ((val & SMBCSR_BUSY) && --to) {
2536 msleep(1);
2537 val = jread32(jme, JME_SMBCSR);
2538 }
2539 if (!to) {
2540 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2541 return;
2542 }
2543
2544 jwrite32(jme, JME_SMBINTF,
2545 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2546 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2547 SMBINTF_HWRWN_WRITE |
2548 SMBINTF_HWCMD);
2549
2550 val = jread32(jme, JME_SMBINTF);
2551 to = JME_SMB_BUSY_TIMEOUT;
2552 while ((val & SMBINTF_HWCMD) && --to) {
2553 msleep(1);
2554 val = jread32(jme, JME_SMBINTF);
2555 }
2556 if (!to) {
2557 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2558 return;
2559 }
2560
2561 mdelay(2);
2562 }
2563
2564 static int
2565 jme_get_eeprom_len(struct net_device *netdev)
2566 {
2567 struct jme_adapter *jme = netdev_priv(netdev);
2568 u32 val;
2569 val = jread32(jme, JME_SMBCSR);
2570 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2571 }
2572
2573 static int
2574 jme_get_eeprom(struct net_device *netdev,
2575 struct ethtool_eeprom *eeprom, u8 *data)
2576 {
2577 struct jme_adapter *jme = netdev_priv(netdev);
2578 int i, offset = eeprom->offset, len = eeprom->len;
2579
2580 /*
2581 * ethtool will check the boundary for us
2582 */
2583 eeprom->magic = JME_EEPROM_MAGIC;
2584 for (i = 0 ; i < len ; ++i)
2585 data[i] = jme_smb_read(jme, i + offset);
2586
2587 return 0;
2588 }
2589
2590 static int
2591 jme_set_eeprom(struct net_device *netdev,
2592 struct ethtool_eeprom *eeprom, u8 *data)
2593 {
2594 struct jme_adapter *jme = netdev_priv(netdev);
2595 int i, offset = eeprom->offset, len = eeprom->len;
2596
2597 if (eeprom->magic != JME_EEPROM_MAGIC)
2598 return -EINVAL;
2599
2600 /*
2601 * ethtool will check the boundary for us
2602 */
2603 for (i = 0 ; i < len ; ++i)
2604 jme_smb_write(jme, i + offset, data[i]);
2605
2606 return 0;
2607 }
2608
2609 static const struct ethtool_ops jme_ethtool_ops = {
2610 .get_drvinfo = jme_get_drvinfo,
2611 .get_regs_len = jme_get_regs_len,
2612 .get_regs = jme_get_regs,
2613 .get_coalesce = jme_get_coalesce,
2614 .set_coalesce = jme_set_coalesce,
2615 .get_pauseparam = jme_get_pauseparam,
2616 .set_pauseparam = jme_set_pauseparam,
2617 .get_wol = jme_get_wol,
2618 .set_wol = jme_set_wol,
2619 .get_settings = jme_get_settings,
2620 .set_settings = jme_set_settings,
2621 .get_link = jme_get_link,
2622 .get_msglevel = jme_get_msglevel,
2623 .set_msglevel = jme_set_msglevel,
2624 .get_rx_csum = jme_get_rx_csum,
2625 .set_rx_csum = jme_set_rx_csum,
2626 .set_tx_csum = jme_set_tx_csum,
2627 .set_tso = jme_set_tso,
2628 .set_sg = ethtool_op_set_sg,
2629 .nway_reset = jme_nway_reset,
2630 .get_eeprom_len = jme_get_eeprom_len,
2631 .get_eeprom = jme_get_eeprom,
2632 .set_eeprom = jme_set_eeprom,
2633 };
2634
2635 static int
2636 jme_pci_dma64(struct pci_dev *pdev)
2637 {
2638 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2639 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2640 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2641 return 1;
2642
2643 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2644 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2645 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2646 return 1;
2647
2648 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2649 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2650 return 0;
2651
2652 return -1;
2653 }
2654
2655 static inline void
2656 jme_phy_init(struct jme_adapter *jme)
2657 {
2658 u16 reg26;
2659
2660 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2661 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2662 }
2663
2664 static inline void
2665 jme_check_hw_ver(struct jme_adapter *jme)
2666 {
2667 u32 chipmode;
2668
2669 chipmode = jread32(jme, JME_CHIPMODE);
2670
2671 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2672 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2673 }
2674
2675 static const struct net_device_ops jme_netdev_ops = {
2676 .ndo_open = jme_open,
2677 .ndo_stop = jme_close,
2678 .ndo_validate_addr = eth_validate_addr,
2679 .ndo_start_xmit = jme_start_xmit,
2680 .ndo_set_mac_address = jme_set_macaddr,
2681 .ndo_set_multicast_list = jme_set_multi,
2682 .ndo_change_mtu = jme_change_mtu,
2683 .ndo_tx_timeout = jme_tx_timeout,
2684 .ndo_vlan_rx_register = jme_vlan_rx_register,
2685 };
2686
2687 static int __devinit
2688 jme_init_one(struct pci_dev *pdev,
2689 const struct pci_device_id *ent)
2690 {
2691 int rc = 0, using_dac, i;
2692 struct net_device *netdev;
2693 struct jme_adapter *jme;
2694 u16 bmcr, bmsr;
2695 u32 apmc;
2696
2697 /*
2698 * set up PCI device basics
2699 */
2700 rc = pci_enable_device(pdev);
2701 if (rc) {
2702 pr_err("Cannot enable PCI device\n");
2703 goto err_out;
2704 }
2705
2706 using_dac = jme_pci_dma64(pdev);
2707 if (using_dac < 0) {
2708 pr_err("Cannot set PCI DMA Mask\n");
2709 rc = -EIO;
2710 goto err_out_disable_pdev;
2711 }
2712
2713 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2714 pr_err("No PCI resource region found\n");
2715 rc = -ENOMEM;
2716 goto err_out_disable_pdev;
2717 }
2718
2719 rc = pci_request_regions(pdev, DRV_NAME);
2720 if (rc) {
2721 pr_err("Cannot obtain PCI resource region\n");
2722 goto err_out_disable_pdev;
2723 }
2724
2725 pci_set_master(pdev);
2726
2727 /*
2728 * alloc and init net device
2729 */
2730 netdev = alloc_etherdev(sizeof(*jme));
2731 if (!netdev) {
2732 pr_err("Cannot allocate netdev structure\n");
2733 rc = -ENOMEM;
2734 goto err_out_release_regions;
2735 }
2736 netdev->netdev_ops = &jme_netdev_ops;
2737 netdev->ethtool_ops = &jme_ethtool_ops;
2738 netdev->watchdog_timeo = TX_TIMEOUT;
2739 netdev->features = NETIF_F_HW_CSUM |
2740 NETIF_F_SG |
2741 NETIF_F_TSO |
2742 NETIF_F_TSO6 |
2743 NETIF_F_HW_VLAN_TX |
2744 NETIF_F_HW_VLAN_RX;
2745 if (using_dac)
2746 netdev->features |= NETIF_F_HIGHDMA;
2747
2748 SET_NETDEV_DEV(netdev, &pdev->dev);
2749 pci_set_drvdata(pdev, netdev);
2750
2751 /*
2752 * init adapter info
2753 */
2754 jme = netdev_priv(netdev);
2755 jme->pdev = pdev;
2756 jme->dev = netdev;
2757 jme->jme_rx = netif_rx;
2758 jme->jme_vlan_rx = vlan_hwaccel_rx;
2759 jme->old_mtu = netdev->mtu = 1500;
2760 jme->phylink = 0;
2761 jme->tx_ring_size = 1 << 10;
2762 jme->tx_ring_mask = jme->tx_ring_size - 1;
2763 jme->tx_wake_threshold = 1 << 9;
2764 jme->rx_ring_size = 1 << 9;
2765 jme->rx_ring_mask = jme->rx_ring_size - 1;
2766 jme->msg_enable = JME_DEF_MSG_ENABLE;
2767 jme->regs = ioremap(pci_resource_start(pdev, 0),
2768 pci_resource_len(pdev, 0));
2769 if (!(jme->regs)) {
2770 pr_err("Mapping PCI resource region error\n");
2771 rc = -ENOMEM;
2772 goto err_out_free_netdev;
2773 }
2774
2775 if (no_pseudohp) {
2776 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2777 jwrite32(jme, JME_APMC, apmc);
2778 } else if (force_pseudohp) {
2779 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2780 jwrite32(jme, JME_APMC, apmc);
2781 }
2782
2783 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2784
2785 spin_lock_init(&jme->phy_lock);
2786 spin_lock_init(&jme->macaddr_lock);
2787 spin_lock_init(&jme->rxmcs_lock);
2788
2789 atomic_set(&jme->link_changing, 1);
2790 atomic_set(&jme->rx_cleaning, 1);
2791 atomic_set(&jme->tx_cleaning, 1);
2792 atomic_set(&jme->rx_empty, 1);
2793
2794 tasklet_init(&jme->pcc_task,
2795 jme_pcc_tasklet,
2796 (unsigned long) jme);
2797 tasklet_init(&jme->linkch_task,
2798 jme_link_change_tasklet,
2799 (unsigned long) jme);
2800 tasklet_init(&jme->txclean_task,
2801 jme_tx_clean_tasklet,
2802 (unsigned long) jme);
2803 tasklet_init(&jme->rxclean_task,
2804 jme_rx_clean_tasklet,
2805 (unsigned long) jme);
2806 tasklet_init(&jme->rxempty_task,
2807 jme_rx_empty_tasklet,
2808 (unsigned long) jme);
2809 tasklet_disable_nosync(&jme->linkch_task);
2810 tasklet_disable_nosync(&jme->txclean_task);
2811 tasklet_disable_nosync(&jme->rxclean_task);
2812 tasklet_disable_nosync(&jme->rxempty_task);
2813 jme->dpi.cur = PCC_P1;
2814
2815 jme->reg_ghc = 0;
2816 jme->reg_rxcs = RXCS_DEFAULT;
2817 jme->reg_rxmcs = RXMCS_DEFAULT;
2818 jme->reg_txpfc = 0;
2819 jme->reg_pmcs = PMCS_MFEN;
2820 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2821 set_bit(JME_FLAG_TSO, &jme->flags);
2822
2823 /*
2824 * Get Max Read Req Size from PCI Config Space
2825 */
2826 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2827 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2828 switch (jme->mrrs) {
2829 case MRRS_128B:
2830 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2831 break;
2832 case MRRS_256B:
2833 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2834 break;
2835 default:
2836 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2837 break;
2838 }
2839
2840 /*
2841 * Must check before reset_mac_processor
2842 */
2843 jme_check_hw_ver(jme);
2844 jme->mii_if.dev = netdev;
2845 if (jme->fpgaver) {
2846 jme->mii_if.phy_id = 0;
2847 for (i = 1 ; i < 32 ; ++i) {
2848 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2849 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2850 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2851 jme->mii_if.phy_id = i;
2852 break;
2853 }
2854 }
2855
2856 if (!jme->mii_if.phy_id) {
2857 rc = -EIO;
2858 pr_err("Can not find phy_id\n");
2859 goto err_out_unmap;
2860 }
2861
2862 jme->reg_ghc |= GHC_LINK_POLL;
2863 } else {
2864 jme->mii_if.phy_id = 1;
2865 }
2866 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2867 jme->mii_if.supports_gmii = true;
2868 else
2869 jme->mii_if.supports_gmii = false;
2870 jme->mii_if.mdio_read = jme_mdio_read;
2871 jme->mii_if.mdio_write = jme_mdio_write;
2872
2873 jme_clear_pm(jme);
2874 jme_set_phyfifoa(jme);
2875 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2876 if (!jme->fpgaver)
2877 jme_phy_init(jme);
2878 jme_phy_off(jme);
2879
2880 /*
2881 * Reset MAC processor and reload EEPROM for MAC Address
2882 */
2883 jme_reset_mac_processor(jme);
2884 rc = jme_reload_eeprom(jme);
2885 if (rc) {
2886 pr_err("Reload eeprom for reading MAC Address error\n");
2887 goto err_out_unmap;
2888 }
2889 jme_load_macaddr(netdev);
2890
2891 /*
2892 * Tell stack that we are not ready to work until open()
2893 */
2894 netif_carrier_off(netdev);
2895 netif_stop_queue(netdev);
2896
2897 /*
2898 * Register netdev
2899 */
2900 rc = register_netdev(netdev);
2901 if (rc) {
2902 pr_err("Cannot register net device\n");
2903 goto err_out_unmap;
2904 }
2905
2906 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2907 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2908 "JMC250 Gigabit Ethernet" :
2909 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2910 "JMC260 Fast Ethernet" : "Unknown",
2911 (jme->fpgaver != 0) ? " (FPGA)" : "",
2912 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2913 jme->rev, netdev->dev_addr);
2914
2915 return 0;
2916
2917 err_out_unmap:
2918 iounmap(jme->regs);
2919 err_out_free_netdev:
2920 pci_set_drvdata(pdev, NULL);
2921 free_netdev(netdev);
2922 err_out_release_regions:
2923 pci_release_regions(pdev);
2924 err_out_disable_pdev:
2925 pci_disable_device(pdev);
2926 err_out:
2927 return rc;
2928 }
2929
2930 static void __devexit
2931 jme_remove_one(struct pci_dev *pdev)
2932 {
2933 struct net_device *netdev = pci_get_drvdata(pdev);
2934 struct jme_adapter *jme = netdev_priv(netdev);
2935
2936 unregister_netdev(netdev);
2937 iounmap(jme->regs);
2938 pci_set_drvdata(pdev, NULL);
2939 free_netdev(netdev);
2940 pci_release_regions(pdev);
2941 pci_disable_device(pdev);
2942
2943 }
2944
2945 #ifdef CONFIG_PM
2946 static int
2947 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2948 {
2949 struct net_device *netdev = pci_get_drvdata(pdev);
2950 struct jme_adapter *jme = netdev_priv(netdev);
2951
2952 atomic_dec(&jme->link_changing);
2953
2954 netif_device_detach(netdev);
2955 netif_stop_queue(netdev);
2956 jme_stop_irq(jme);
2957
2958 tasklet_disable(&jme->txclean_task);
2959 tasklet_disable(&jme->rxclean_task);
2960 tasklet_disable(&jme->rxempty_task);
2961
2962 if (netif_carrier_ok(netdev)) {
2963 if (test_bit(JME_FLAG_POLL, &jme->flags))
2964 jme_polling_mode(jme);
2965
2966 jme_stop_pcc_timer(jme);
2967 jme_reset_ghc_speed(jme);
2968 jme_disable_rx_engine(jme);
2969 jme_disable_tx_engine(jme);
2970 jme_reset_mac_processor(jme);
2971 jme_free_rx_resources(jme);
2972 jme_free_tx_resources(jme);
2973 netif_carrier_off(netdev);
2974 jme->phylink = 0;
2975 }
2976
2977 tasklet_enable(&jme->txclean_task);
2978 tasklet_hi_enable(&jme->rxclean_task);
2979 tasklet_hi_enable(&jme->rxempty_task);
2980
2981 pci_save_state(pdev);
2982 if (jme->reg_pmcs) {
2983 jme_set_100m_half(jme);
2984
2985 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2986 jme_wait_link(jme);
2987
2988 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2989
2990 pci_enable_wake(pdev, PCI_D3cold, true);
2991 } else {
2992 jme_phy_off(jme);
2993 }
2994 pci_set_power_state(pdev, PCI_D3cold);
2995
2996 return 0;
2997 }
2998
2999 static int
3000 jme_resume(struct pci_dev *pdev)
3001 {
3002 struct net_device *netdev = pci_get_drvdata(pdev);
3003 struct jme_adapter *jme = netdev_priv(netdev);
3004
3005 jme_clear_pm(jme);
3006 pci_restore_state(pdev);
3007
3008 if (test_bit(JME_FLAG_SSET, &jme->flags))
3009 jme_set_settings(netdev, &jme->old_ecmd);
3010 else
3011 jme_reset_phy_processor(jme);
3012
3013 jme_start_irq(jme);
3014 netif_device_attach(netdev);
3015
3016 atomic_inc(&jme->link_changing);
3017
3018 jme_reset_link(jme);
3019
3020 return 0;
3021 }
3022 #endif
3023
3024 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3025 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3026 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3027 { }
3028 };
3029
3030 static struct pci_driver jme_driver = {
3031 .name = DRV_NAME,
3032 .id_table = jme_pci_tbl,
3033 .probe = jme_init_one,
3034 .remove = __devexit_p(jme_remove_one),
3035 #ifdef CONFIG_PM
3036 .suspend = jme_suspend,
3037 .resume = jme_resume,
3038 #endif /* CONFIG_PM */
3039 };
3040
3041 static int __init
3042 jme_init_module(void)
3043 {
3044 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3045 return pci_register_driver(&jme_driver);
3046 }
3047
3048 static void __exit
3049 jme_cleanup_module(void)
3050 {
3051 pci_unregister_driver(&jme_driver);
3052 }
3053
3054 module_init(jme_init_module);
3055 module_exit(jme_cleanup_module);
3056
3057 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3058 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3059 MODULE_LICENSE("GPL");
3060 MODULE_VERSION(DRV_VERSION);
3061 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3062
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