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Merge tag 'renesas-dt-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6/btrfs-unstable.git] / arch / arm / mach-shmobile / clock-r8a7790.c
blob312376d2cfd14572d60753118d3c375797423ed0
1 /*
2 * r8a7790 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/sh_clk.h>
24 #include <linux/clkdev.h>
25 #include <mach/clock.h>
26 #include <mach/common.h>
27 #include <mach/r8a7790.h>
28
29 /*
30 * MD EXTAL PLL0 PLL1 PLL3
31 * 14 13 19 (MHz) *1 *1
32 *---------------------------------------------------
33 * 0 0 0 15 x 1 x172/2 x208/2 x106
34 * 0 0 1 15 x 1 x172/2 x208/2 x88
35 * 0 1 0 20 x 1 x130/2 x156/2 x80
36 * 0 1 1 20 x 1 x130/2 x156/2 x66
37 * 1 0 0 26 / 2 x200/2 x240/2 x122
38 * 1 0 1 26 / 2 x200/2 x240/2 x102
39 * 1 1 0 30 / 2 x172/2 x208/2 x106
40 * 1 1 1 30 / 2 x172/2 x208/2 x88
41 *
42 * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
43 * see "p1 / 2" on R8A7790_CLOCK_ROOT() below
44 */
45
46 #define CPG_BASE 0xe6150000
47 #define CPG_LEN 0x1000
48
49 #define SMSTPCR1 0xe6150134
50 #define SMSTPCR2 0xe6150138
51 #define SMSTPCR3 0xe615013c
52 #define SMSTPCR5 0xe6150144
53 #define SMSTPCR7 0xe615014c
54 #define SMSTPCR8 0xe6150990
55 #define SMSTPCR9 0xe6150994
56 #define SMSTPCR10 0xe6150998
57
58 #define SDCKCR 0xE6150074
59 #define SD2CKCR 0xE6150078
60 #define SD3CKCR 0xE615007C
61 #define MMC0CKCR 0xE6150240
62 #define MMC1CKCR 0xE6150244
63 #define SSPCKCR 0xE6150248
64 #define SSPRSCKCR 0xE615024C
65
66 static struct clk_mapping cpg_mapping = {
67 .phys = CPG_BASE,
68 .len = CPG_LEN,
69 };
70
71 static struct clk extal_clk = {
72 /* .rate will be updated on r8a7790_clock_init() */
73 .mapping = &cpg_mapping,
74 };
75
76 static struct sh_clk_ops followparent_clk_ops = {
77 .recalc = followparent_recalc,
78 };
79
80 static struct clk main_clk = {
81 /* .parent will be set r8a7790_clock_init */
82 .ops = &followparent_clk_ops,
83 };
84
85 /*
86 * clock ratio of these clock will be updated
87 * on r8a7790_clock_init()
88 */
89 SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
90 SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
91 SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1);
92 SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
93
94 /* fixed ratio clock */
95 SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
96 SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
97
98 SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
99 SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
100 SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
101 SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
102 SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
103 SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2);
104 SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12);
105 SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
106 SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48);
107 SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8);
108 SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4);
109 SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
110 SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024));
111
112 SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4);
113 SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8);
114 SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8);
115 SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
116
117 static struct clk *main_clks[] = {
118 &extal_clk,
119 &extal_div2_clk,
120 &main_clk,
121 &pll1_clk,
122 &pll1_div2_clk,
123 &pll3_clk,
124 &lb_clk,
125 &qspi_clk,
126 &zg_clk,
127 &zx_clk,
128 &zs_clk,
129 &hp_clk,
130 &i_clk,
131 &b_clk,
132 &p_clk,
133 &cl_clk,
134 &m2_clk,
135 &imp_clk,
136 &rclk_clk,
137 &oscclk_clk,
138 &zb3_clk,
139 &zb3d2_clk,
140 &ddr_clk,
141 &mp_clk,
142 &cp_clk,
143 };
144
145 /* SDHI (DIV4) clock */
146 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
147
148 static struct clk_div_mult_table div4_div_mult_table = {
149 .divisors = divisors,
150 .nr_divisors = ARRAY_SIZE(divisors),
151 };
152
153 static struct clk_div4_table div4_table = {
154 .div_mult_table = &div4_div_mult_table,
155 };
156
157 enum {
158 DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
159 };
160
161 static struct clk div4_clks[DIV4_NR] = {
162 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
163 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
164 [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
165 };
166
167 /* DIV6 clocks */
168 enum {
169 DIV6_SD2, DIV6_SD3,
170 DIV6_MMC0, DIV6_MMC1,
171 DIV6_SSP, DIV6_SSPRS,
172 DIV6_NR
173 };
174
175 static struct clk div6_clks[DIV6_NR] = {
176 [DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
177 [DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
178 [DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
179 [DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
180 [DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
181 [DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
182 };
183
184 /* MSTP */
185 enum {
186 MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
187 MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
188 MSTP931, MSTP930, MSTP929, MSTP928,
189 MSTP917,
190 MSTP813,
191 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
192 MSTP717, MSTP716,
193 MSTP704,
194 MSTP522,
195 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
196 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
197 MSTP124,
198 MSTP_NR
199 };
200
201 static struct clk mstp_clks[MSTP_NR] = {
202 [MSTP1015] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 15, 0), /* SSI0 */
203 [MSTP1014] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 14, 0), /* SSI1 */
204 [MSTP1013] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 13, 0), /* SSI2 */
205 [MSTP1012] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 12, 0), /* SSI3 */
206 [MSTP1011] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 11, 0), /* SSI4 */
207 [MSTP1010] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 10, 0), /* SSI5 */
208 [MSTP1009] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 9, 0), /* SSI6 */
209 [MSTP1008] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 8, 0), /* SSI7 */
210 [MSTP1007] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 7, 0), /* SSI8 */
211 [MSTP1006] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 6, 0), /* SSI9 */
212 [MSTP1005] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 5, 0), /* SSI ALL */
213 [MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */
214 [MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */
215 [MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */
216 [MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */
217 [MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
218 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
219 [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
220 [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
221 [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
222 [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
223 [MSTP722] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 22, 0), /* DU2 */
224 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
225 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
226 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
227 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
228 [MSTP704] = SH_CLK_MSTP32(&mp_clk, SMSTPCR7, 4, 0), /* HSUSB */
229 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
230 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
231 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
232 [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */
233 [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SD2], SMSTPCR3, 12, 0), /* SDHI2 */
234 [MSTP311] = SH_CLK_MSTP32(&div6_clks[DIV6_SD3], SMSTPCR3, 11, 0), /* SDHI3 */
235 [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, 0), /* MMC1 */
236 [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
237 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
238 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
239 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
240 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
241 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
242 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
243 [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
244 };
245
246 static struct clk_lookup lookups[] = {
247
248 /* main clocks */
249 CLKDEV_CON_ID("extal", &extal_clk),
250 CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
251 CLKDEV_CON_ID("main", &main_clk),
252 CLKDEV_CON_ID("pll1", &pll1_clk),
253 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
254 CLKDEV_CON_ID("pll3", &pll3_clk),
255 CLKDEV_CON_ID("zg", &zg_clk),
256 CLKDEV_CON_ID("zx", &zx_clk),
257 CLKDEV_CON_ID("zs", &zs_clk),
258 CLKDEV_CON_ID("hp", &hp_clk),
259 CLKDEV_CON_ID("i", &i_clk),
260 CLKDEV_CON_ID("b", &b_clk),
261 CLKDEV_CON_ID("lb", &lb_clk),
262 CLKDEV_CON_ID("p", &p_clk),
263 CLKDEV_CON_ID("cl", &cl_clk),
264 CLKDEV_CON_ID("m2", &m2_clk),
265 CLKDEV_CON_ID("imp", &imp_clk),
266 CLKDEV_CON_ID("rclk", &rclk_clk),
267 CLKDEV_CON_ID("oscclk", &oscclk_clk),
268 CLKDEV_CON_ID("zb3", &zb3_clk),
269 CLKDEV_CON_ID("zb3d2", &zb3d2_clk),
270 CLKDEV_CON_ID("ddr", &ddr_clk),
271 CLKDEV_CON_ID("mp", &mp_clk),
272 CLKDEV_CON_ID("qspi", &qspi_clk),
273 CLKDEV_CON_ID("cp", &cp_clk),
274
275 /* DIV4 */
276 CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]),
277
278 /* DIV6 */
279 CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]),
280 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
281
282 /* MSTP */
283 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
284 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
285 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
286 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
287 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
288 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
289 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
290 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
291 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
292 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
293 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
294 CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
295 CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
296 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
297 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
298 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
299 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
300 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
301 CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
302 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
303 CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
304 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
305 CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
306 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
307 CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
308 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
309 CLKDEV_DEV_ID("ee160000.sd", &mstp_clks[MSTP311]),
310 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
311 CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
312 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
313 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
314 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
315 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
316
317 /* ICK */
318 CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
319 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
320 CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
321 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
322 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
323 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
324 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
325 CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
326 CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
327 CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
328 CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
329 CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
330 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
331 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
332 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
333 CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
334
335 };
336
337 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
338 extal_clk.rate = e * 1000 * 1000; \
339 main_clk.parent = m; \
340 SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
341 if (mode & MD(19)) \
342 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
343 else \
344 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
345
346
347 void __init r8a7790_clock_init(void)
348 {
349 u32 mode = rcar_gen2_read_mode_pins();
350 int k, ret = 0;
351
352 switch (mode & (MD(14) | MD(13))) {
353 case 0:
354 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
355 break;
356 case MD(13):
357 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
358 break;
359 case MD(14):
360 R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
361 break;
362 case MD(13) | MD(14):
363 R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
364 break;
365 }
366
367 if (mode & (MD(18)))
368 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
369 else
370 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
371
372 if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
373 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
374 else
375 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
376
377 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
378 ret = clk_register(main_clks[k]);
379
380 if (!ret)
381 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
382
383 if (!ret)
384 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
385
386 if (!ret)
387 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
388
389 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
390
391 if (!ret)
392 shmobile_clk_init();
393 else
394 panic("failed to setup r8a7790 clocks\n");
395 }
(deprecated) Btrfs devel tree