2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
42 struct mlx5e_rq_param
{
43 u32 rqc
[MLX5_ST_SZ_DW(rqc
)];
44 struct mlx5_wq_param wq
;
47 struct mlx5e_sq_param
{
48 u32 sqc
[MLX5_ST_SZ_DW(sqc
)];
49 struct mlx5_wq_param wq
;
54 struct mlx5e_cq_param
{
55 u32 cqc
[MLX5_ST_SZ_DW(cqc
)];
56 struct mlx5_wq_param wq
;
60 struct mlx5e_channel_param
{
61 struct mlx5e_rq_param rq
;
62 struct mlx5e_sq_param sq
;
63 struct mlx5e_sq_param icosq
;
64 struct mlx5e_cq_param rx_cq
;
65 struct mlx5e_cq_param tx_cq
;
66 struct mlx5e_cq_param icosq_cq
;
69 static void mlx5e_update_carrier(struct mlx5e_priv
*priv
)
71 struct mlx5_core_dev
*mdev
= priv
->mdev
;
74 port_state
= mlx5_query_vport_state(mdev
,
75 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT
, 0);
77 if (port_state
== VPORT_STATE_UP
)
78 netif_carrier_on(priv
->netdev
);
80 netif_carrier_off(priv
->netdev
);
83 static void mlx5e_update_carrier_work(struct work_struct
*work
)
85 struct mlx5e_priv
*priv
= container_of(work
, struct mlx5e_priv
,
88 mutex_lock(&priv
->state_lock
);
89 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
90 mlx5e_update_carrier(priv
);
91 mutex_unlock(&priv
->state_lock
);
94 static void mlx5e_update_sw_counters(struct mlx5e_priv
*priv
)
96 struct mlx5e_sw_stats
*s
= &priv
->stats
.sw
;
97 struct mlx5e_rq_stats
*rq_stats
;
98 struct mlx5e_sq_stats
*sq_stats
;
99 u64 tx_offload_none
= 0;
102 memset(s
, 0, sizeof(*s
));
103 for (i
= 0; i
< priv
->params
.num_channels
; i
++) {
104 rq_stats
= &priv
->channel
[i
]->rq
.stats
;
106 s
->rx_packets
+= rq_stats
->packets
;
107 s
->rx_bytes
+= rq_stats
->bytes
;
108 s
->lro_packets
+= rq_stats
->lro_packets
;
109 s
->lro_bytes
+= rq_stats
->lro_bytes
;
110 s
->rx_csum_none
+= rq_stats
->csum_none
;
111 s
->rx_csum_sw
+= rq_stats
->csum_sw
;
112 s
->rx_csum_inner
+= rq_stats
->csum_inner
;
113 s
->rx_wqe_err
+= rq_stats
->wqe_err
;
114 s
->rx_mpwqe_filler
+= rq_stats
->mpwqe_filler
;
115 s
->rx_mpwqe_frag
+= rq_stats
->mpwqe_frag
;
116 s
->rx_buff_alloc_err
+= rq_stats
->buff_alloc_err
;
118 for (j
= 0; j
< priv
->params
.num_tc
; j
++) {
119 sq_stats
= &priv
->channel
[i
]->sq
[j
].stats
;
121 s
->tx_packets
+= sq_stats
->packets
;
122 s
->tx_bytes
+= sq_stats
->bytes
;
123 s
->tso_packets
+= sq_stats
->tso_packets
;
124 s
->tso_bytes
+= sq_stats
->tso_bytes
;
125 s
->tso_inner_packets
+= sq_stats
->tso_inner_packets
;
126 s
->tso_inner_bytes
+= sq_stats
->tso_inner_bytes
;
127 s
->tx_queue_stopped
+= sq_stats
->stopped
;
128 s
->tx_queue_wake
+= sq_stats
->wake
;
129 s
->tx_queue_dropped
+= sq_stats
->dropped
;
130 s
->tx_csum_inner
+= sq_stats
->csum_offload_inner
;
131 tx_offload_none
+= sq_stats
->csum_offload_none
;
135 /* Update calculated offload counters */
136 s
->tx_csum_offload
= s
->tx_packets
- tx_offload_none
- s
->tx_csum_inner
;
137 s
->rx_csum_good
= s
->rx_packets
- s
->rx_csum_none
-
140 s
->link_down_events
= MLX5_GET(ppcnt_reg
,
141 priv
->stats
.pport
.phy_counters
,
142 counter_set
.phys_layer_cntrs
.link_down_events
);
145 static void mlx5e_update_vport_counters(struct mlx5e_priv
*priv
)
147 int outlen
= MLX5_ST_SZ_BYTES(query_vport_counter_out
);
148 u32
*out
= (u32
*)priv
->stats
.vport
.query_vport_out
;
149 u32 in
[MLX5_ST_SZ_DW(query_vport_counter_in
)];
150 struct mlx5_core_dev
*mdev
= priv
->mdev
;
152 memset(in
, 0, sizeof(in
));
154 MLX5_SET(query_vport_counter_in
, in
, opcode
,
155 MLX5_CMD_OP_QUERY_VPORT_COUNTER
);
156 MLX5_SET(query_vport_counter_in
, in
, op_mod
, 0);
157 MLX5_SET(query_vport_counter_in
, in
, other_vport
, 0);
159 memset(out
, 0, outlen
);
161 mlx5_cmd_exec(mdev
, in
, sizeof(in
), out
, outlen
);
164 static void mlx5e_update_pport_counters(struct mlx5e_priv
*priv
)
166 struct mlx5e_pport_stats
*pstats
= &priv
->stats
.pport
;
167 struct mlx5_core_dev
*mdev
= priv
->mdev
;
168 int sz
= MLX5_ST_SZ_BYTES(ppcnt_reg
);
173 in
= mlx5_vzalloc(sz
);
177 MLX5_SET(ppcnt_reg
, in
, local_port
, 1);
179 out
= pstats
->IEEE_802_3_counters
;
180 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_IEEE_802_3_COUNTERS_GROUP
);
181 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
183 out
= pstats
->RFC_2863_counters
;
184 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2863_COUNTERS_GROUP
);
185 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
187 out
= pstats
->RFC_2819_counters
;
188 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2819_COUNTERS_GROUP
);
189 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
191 out
= pstats
->phy_counters
;
192 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP
);
193 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
195 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PER_PRIORITY_COUNTERS_GROUP
);
196 for (prio
= 0; prio
< NUM_PPORT_PRIO
; prio
++) {
197 out
= pstats
->per_prio_counters
[prio
];
198 MLX5_SET(ppcnt_reg
, in
, prio_tc
, prio
);
199 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
,
200 MLX5_REG_PPCNT
, 0, 0);
207 static void mlx5e_update_q_counter(struct mlx5e_priv
*priv
)
209 struct mlx5e_qcounter_stats
*qcnt
= &priv
->stats
.qcnt
;
211 if (!priv
->q_counter
)
214 mlx5_core_query_out_of_buffer(priv
->mdev
, priv
->q_counter
,
215 &qcnt
->rx_out_of_buffer
);
218 void mlx5e_update_stats(struct mlx5e_priv
*priv
)
220 mlx5e_update_q_counter(priv
);
221 mlx5e_update_vport_counters(priv
);
222 mlx5e_update_pport_counters(priv
);
223 mlx5e_update_sw_counters(priv
);
226 static void mlx5e_update_stats_work(struct work_struct
*work
)
228 struct delayed_work
*dwork
= to_delayed_work(work
);
229 struct mlx5e_priv
*priv
= container_of(dwork
, struct mlx5e_priv
,
231 mutex_lock(&priv
->state_lock
);
232 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
)) {
233 mlx5e_update_stats(priv
);
234 schedule_delayed_work(dwork
,
236 MLX5E_UPDATE_STATS_INTERVAL
));
238 mutex_unlock(&priv
->state_lock
);
241 static void mlx5e_async_event(struct mlx5_core_dev
*mdev
, void *vpriv
,
242 enum mlx5_dev_event event
, unsigned long param
)
244 struct mlx5e_priv
*priv
= vpriv
;
246 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE
, &priv
->state
))
250 case MLX5_DEV_EVENT_PORT_UP
:
251 case MLX5_DEV_EVENT_PORT_DOWN
:
252 schedule_work(&priv
->update_carrier_work
);
260 static void mlx5e_enable_async_events(struct mlx5e_priv
*priv
)
262 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE
, &priv
->state
);
265 static void mlx5e_disable_async_events(struct mlx5e_priv
*priv
)
267 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE
, &priv
->state
);
268 synchronize_irq(mlx5_get_msix_vec(priv
->mdev
, MLX5_EQ_VEC_ASYNC
));
271 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
272 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
274 static int mlx5e_create_rq(struct mlx5e_channel
*c
,
275 struct mlx5e_rq_param
*param
,
278 struct mlx5e_priv
*priv
= c
->priv
;
279 struct mlx5_core_dev
*mdev
= priv
->mdev
;
280 void *rqc
= param
->rqc
;
281 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
287 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
289 err
= mlx5_wq_ll_create(mdev
, ¶m
->wq
, rqc_wq
, &rq
->wq
,
294 rq
->wq
.db
= &rq
->wq
.db
[MLX5_RCV_DBR
];
296 wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
298 switch (priv
->params
.rq_wq_type
) {
299 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
300 rq
->wqe_info
= kzalloc_node(wq_sz
* sizeof(*rq
->wqe_info
),
301 GFP_KERNEL
, cpu_to_node(c
->cpu
));
304 goto err_rq_wq_destroy
;
306 rq
->handle_rx_cqe
= mlx5e_handle_rx_cqe_mpwrq
;
307 rq
->alloc_wqe
= mlx5e_alloc_rx_mpwqe
;
309 rq
->wqe_sz
= MLX5_MPWRQ_NUM_STRIDES
* MLX5_MPWRQ_STRIDE_SIZE
;
310 byte_count
= rq
->wqe_sz
;
312 default: /* MLX5_WQ_TYPE_LINKED_LIST */
313 rq
->skb
= kzalloc_node(wq_sz
* sizeof(*rq
->skb
), GFP_KERNEL
,
314 cpu_to_node(c
->cpu
));
317 goto err_rq_wq_destroy
;
319 rq
->handle_rx_cqe
= mlx5e_handle_rx_cqe
;
320 rq
->alloc_wqe
= mlx5e_alloc_rx_wqe
;
322 rq
->wqe_sz
= (priv
->params
.lro_en
) ?
323 priv
->params
.lro_wqe_sz
:
324 MLX5E_SW2HW_MTU(priv
->netdev
->mtu
);
325 rq
->wqe_sz
= SKB_DATA_ALIGN(rq
->wqe_sz
);
326 byte_count
= rq
->wqe_sz
;
327 byte_count
|= MLX5_HW_START_PADDING
;
330 for (i
= 0; i
< wq_sz
; i
++) {
331 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, i
);
333 wqe
->data
.byte_count
= cpu_to_be32(byte_count
);
336 rq
->wq_type
= priv
->params
.rq_wq_type
;
338 rq
->netdev
= c
->netdev
;
339 rq
->tstamp
= &priv
->tstamp
;
343 rq
->mkey_be
= c
->mkey_be
;
344 rq
->umr_mkey_be
= cpu_to_be32(c
->priv
->umr_mkey
.key
);
349 mlx5_wq_destroy(&rq
->wq_ctrl
);
354 static void mlx5e_destroy_rq(struct mlx5e_rq
*rq
)
356 switch (rq
->wq_type
) {
357 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
360 default: /* MLX5_WQ_TYPE_LINKED_LIST */
364 mlx5_wq_destroy(&rq
->wq_ctrl
);
367 static int mlx5e_enable_rq(struct mlx5e_rq
*rq
, struct mlx5e_rq_param
*param
)
369 struct mlx5e_priv
*priv
= rq
->priv
;
370 struct mlx5_core_dev
*mdev
= priv
->mdev
;
378 inlen
= MLX5_ST_SZ_BYTES(create_rq_in
) +
379 sizeof(u64
) * rq
->wq_ctrl
.buf
.npages
;
380 in
= mlx5_vzalloc(inlen
);
384 rqc
= MLX5_ADDR_OF(create_rq_in
, in
, ctx
);
385 wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
387 memcpy(rqc
, param
->rqc
, sizeof(param
->rqc
));
389 MLX5_SET(rqc
, rqc
, cqn
, rq
->cq
.mcq
.cqn
);
390 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RST
);
391 MLX5_SET(rqc
, rqc
, flush_in_error_en
, 1);
392 MLX5_SET(rqc
, rqc
, vsd
, priv
->params
.vlan_strip_disable
);
393 MLX5_SET(wq
, wq
, log_wq_pg_sz
, rq
->wq_ctrl
.buf
.page_shift
-
394 MLX5_ADAPTER_PAGE_SHIFT
);
395 MLX5_SET64(wq
, wq
, dbr_addr
, rq
->wq_ctrl
.db
.dma
);
397 mlx5_fill_page_array(&rq
->wq_ctrl
.buf
,
398 (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
400 err
= mlx5_core_create_rq(mdev
, in
, inlen
, &rq
->rqn
);
407 static int mlx5e_modify_rq_state(struct mlx5e_rq
*rq
, int curr_state
,
410 struct mlx5e_channel
*c
= rq
->channel
;
411 struct mlx5e_priv
*priv
= c
->priv
;
412 struct mlx5_core_dev
*mdev
= priv
->mdev
;
419 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
420 in
= mlx5_vzalloc(inlen
);
424 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
426 MLX5_SET(modify_rq_in
, in
, rq_state
, curr_state
);
427 MLX5_SET(rqc
, rqc
, state
, next_state
);
429 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
436 static int mlx5e_modify_rq_vsd(struct mlx5e_rq
*rq
, bool vsd
)
438 struct mlx5e_channel
*c
= rq
->channel
;
439 struct mlx5e_priv
*priv
= c
->priv
;
440 struct mlx5_core_dev
*mdev
= priv
->mdev
;
447 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
448 in
= mlx5_vzalloc(inlen
);
452 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
454 MLX5_SET(modify_rq_in
, in
, rq_state
, MLX5_RQC_STATE_RDY
);
455 MLX5_SET64(modify_rq_in
, in
, modify_bitmask
, MLX5_RQ_BITMASK_VSD
);
456 MLX5_SET(rqc
, rqc
, vsd
, vsd
);
457 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RDY
);
459 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
466 static void mlx5e_disable_rq(struct mlx5e_rq
*rq
)
468 mlx5_core_destroy_rq(rq
->priv
->mdev
, rq
->rqn
);
471 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq
*rq
)
473 unsigned long exp_time
= jiffies
+ msecs_to_jiffies(20000);
474 struct mlx5e_channel
*c
= rq
->channel
;
475 struct mlx5e_priv
*priv
= c
->priv
;
476 struct mlx5_wq_ll
*wq
= &rq
->wq
;
478 while (time_before(jiffies
, exp_time
)) {
479 if (wq
->cur_sz
>= priv
->params
.min_rx_wqes
)
488 static int mlx5e_open_rq(struct mlx5e_channel
*c
,
489 struct mlx5e_rq_param
*param
,
492 struct mlx5e_sq
*sq
= &c
->icosq
;
493 u16 pi
= sq
->pc
& sq
->wq
.sz_m1
;
496 err
= mlx5e_create_rq(c
, param
, rq
);
500 err
= mlx5e_enable_rq(rq
, param
);
504 err
= mlx5e_modify_rq_state(rq
, MLX5_RQC_STATE_RST
, MLX5_RQC_STATE_RDY
);
508 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE
, &rq
->state
);
510 sq
->ico_wqe_info
[pi
].opcode
= MLX5_OPCODE_NOP
;
511 sq
->ico_wqe_info
[pi
].num_wqebbs
= 1;
512 mlx5e_send_nop(sq
, true); /* trigger mlx5e_post_rx_wqes() */
517 mlx5e_disable_rq(rq
);
519 mlx5e_destroy_rq(rq
);
524 static void mlx5e_close_rq(struct mlx5e_rq
*rq
)
526 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE
, &rq
->state
);
527 napi_synchronize(&rq
->channel
->napi
); /* prevent mlx5e_post_rx_wqes */
529 mlx5e_modify_rq_state(rq
, MLX5_RQC_STATE_RDY
, MLX5_RQC_STATE_ERR
);
530 while (!mlx5_wq_ll_is_empty(&rq
->wq
))
533 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
534 napi_synchronize(&rq
->channel
->napi
);
536 mlx5e_disable_rq(rq
);
537 mlx5e_destroy_rq(rq
);
540 static void mlx5e_free_sq_db(struct mlx5e_sq
*sq
)
547 static int mlx5e_alloc_sq_db(struct mlx5e_sq
*sq
, int numa
)
549 int wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
550 int df_sz
= wq_sz
* MLX5_SEND_WQEBB_NUM_DS
;
552 sq
->skb
= kzalloc_node(wq_sz
* sizeof(*sq
->skb
), GFP_KERNEL
, numa
);
553 sq
->dma_fifo
= kzalloc_node(df_sz
* sizeof(*sq
->dma_fifo
), GFP_KERNEL
,
555 sq
->wqe_info
= kzalloc_node(wq_sz
* sizeof(*sq
->wqe_info
), GFP_KERNEL
,
558 if (!sq
->skb
|| !sq
->dma_fifo
|| !sq
->wqe_info
) {
559 mlx5e_free_sq_db(sq
);
563 sq
->dma_fifo_mask
= df_sz
- 1;
568 static int mlx5e_create_sq(struct mlx5e_channel
*c
,
570 struct mlx5e_sq_param
*param
,
573 struct mlx5e_priv
*priv
= c
->priv
;
574 struct mlx5_core_dev
*mdev
= priv
->mdev
;
576 void *sqc
= param
->sqc
;
577 void *sqc_wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
580 err
= mlx5_alloc_map_uar(mdev
, &sq
->uar
, true);
584 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
586 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
,
589 goto err_unmap_free_uar
;
591 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
592 if (sq
->uar
.bf_map
) {
593 set_bit(MLX5E_SQ_STATE_BF_ENABLE
, &sq
->state
);
594 sq
->uar_map
= sq
->uar
.bf_map
;
596 sq
->uar_map
= sq
->uar
.map
;
598 sq
->bf_buf_size
= (1 << MLX5_CAP_GEN(mdev
, log_bf_reg_size
)) / 2;
599 sq
->max_inline
= param
->max_inline
;
601 err
= mlx5e_alloc_sq_db(sq
, cpu_to_node(c
->cpu
));
603 goto err_sq_wq_destroy
;
606 u8 wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
608 sq
->ico_wqe_info
= kzalloc_node(sizeof(*sq
->ico_wqe_info
) *
611 cpu_to_node(c
->cpu
));
612 if (!sq
->ico_wqe_info
) {
619 txq_ix
= c
->ix
+ tc
* priv
->params
.num_channels
;
620 sq
->txq
= netdev_get_tx_queue(priv
->netdev
, txq_ix
);
621 priv
->txq_to_sq_map
[txq_ix
] = sq
;
625 sq
->tstamp
= &priv
->tstamp
;
626 sq
->mkey_be
= c
->mkey_be
;
629 sq
->edge
= (sq
->wq
.sz_m1
+ 1) - MLX5_SEND_WQE_MAX_WQEBBS
;
630 sq
->bf_budget
= MLX5E_SQ_BF_BUDGET
;
635 mlx5e_free_sq_db(sq
);
638 mlx5_wq_destroy(&sq
->wq_ctrl
);
641 mlx5_unmap_free_uar(mdev
, &sq
->uar
);
646 static void mlx5e_destroy_sq(struct mlx5e_sq
*sq
)
648 struct mlx5e_channel
*c
= sq
->channel
;
649 struct mlx5e_priv
*priv
= c
->priv
;
651 kfree(sq
->ico_wqe_info
);
652 mlx5e_free_sq_db(sq
);
653 mlx5_wq_destroy(&sq
->wq_ctrl
);
654 mlx5_unmap_free_uar(priv
->mdev
, &sq
->uar
);
657 static int mlx5e_enable_sq(struct mlx5e_sq
*sq
, struct mlx5e_sq_param
*param
)
659 struct mlx5e_channel
*c
= sq
->channel
;
660 struct mlx5e_priv
*priv
= c
->priv
;
661 struct mlx5_core_dev
*mdev
= priv
->mdev
;
669 inlen
= MLX5_ST_SZ_BYTES(create_sq_in
) +
670 sizeof(u64
) * sq
->wq_ctrl
.buf
.npages
;
671 in
= mlx5_vzalloc(inlen
);
675 sqc
= MLX5_ADDR_OF(create_sq_in
, in
, ctx
);
676 wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
678 memcpy(sqc
, param
->sqc
, sizeof(param
->sqc
));
680 MLX5_SET(sqc
, sqc
, tis_num_0
, param
->icosq
? 0 : priv
->tisn
[sq
->tc
]);
681 MLX5_SET(sqc
, sqc
, cqn
, sq
->cq
.mcq
.cqn
);
682 MLX5_SET(sqc
, sqc
, state
, MLX5_SQC_STATE_RST
);
683 MLX5_SET(sqc
, sqc
, tis_lst_sz
, param
->icosq
? 0 : 1);
684 MLX5_SET(sqc
, sqc
, flush_in_error_en
, 1);
686 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
687 MLX5_SET(wq
, wq
, uar_page
, sq
->uar
.index
);
688 MLX5_SET(wq
, wq
, log_wq_pg_sz
, sq
->wq_ctrl
.buf
.page_shift
-
689 MLX5_ADAPTER_PAGE_SHIFT
);
690 MLX5_SET64(wq
, wq
, dbr_addr
, sq
->wq_ctrl
.db
.dma
);
692 mlx5_fill_page_array(&sq
->wq_ctrl
.buf
,
693 (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
695 err
= mlx5_core_create_sq(mdev
, in
, inlen
, &sq
->sqn
);
702 static int mlx5e_modify_sq(struct mlx5e_sq
*sq
, int curr_state
, int next_state
)
704 struct mlx5e_channel
*c
= sq
->channel
;
705 struct mlx5e_priv
*priv
= c
->priv
;
706 struct mlx5_core_dev
*mdev
= priv
->mdev
;
713 inlen
= MLX5_ST_SZ_BYTES(modify_sq_in
);
714 in
= mlx5_vzalloc(inlen
);
718 sqc
= MLX5_ADDR_OF(modify_sq_in
, in
, ctx
);
720 MLX5_SET(modify_sq_in
, in
, sq_state
, curr_state
);
721 MLX5_SET(sqc
, sqc
, state
, next_state
);
723 err
= mlx5_core_modify_sq(mdev
, sq
->sqn
, in
, inlen
);
730 static void mlx5e_disable_sq(struct mlx5e_sq
*sq
)
732 struct mlx5e_channel
*c
= sq
->channel
;
733 struct mlx5e_priv
*priv
= c
->priv
;
734 struct mlx5_core_dev
*mdev
= priv
->mdev
;
736 mlx5_core_destroy_sq(mdev
, sq
->sqn
);
739 static int mlx5e_open_sq(struct mlx5e_channel
*c
,
741 struct mlx5e_sq_param
*param
,
746 err
= mlx5e_create_sq(c
, tc
, param
, sq
);
750 err
= mlx5e_enable_sq(sq
, param
);
754 err
= mlx5e_modify_sq(sq
, MLX5_SQC_STATE_RST
, MLX5_SQC_STATE_RDY
);
759 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE
, &sq
->state
);
760 netdev_tx_reset_queue(sq
->txq
);
761 netif_tx_start_queue(sq
->txq
);
767 mlx5e_disable_sq(sq
);
769 mlx5e_destroy_sq(sq
);
774 static inline void netif_tx_disable_queue(struct netdev_queue
*txq
)
776 __netif_tx_lock_bh(txq
);
777 netif_tx_stop_queue(txq
);
778 __netif_tx_unlock_bh(txq
);
781 static void mlx5e_close_sq(struct mlx5e_sq
*sq
)
784 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE
, &sq
->state
);
785 /* prevent netif_tx_wake_queue */
786 napi_synchronize(&sq
->channel
->napi
);
787 netif_tx_disable_queue(sq
->txq
);
789 /* ensure hw is notified of all pending wqes */
790 if (mlx5e_sq_has_room_for(sq
, 1))
791 mlx5e_send_nop(sq
, true);
793 mlx5e_modify_sq(sq
, MLX5_SQC_STATE_RDY
, MLX5_SQC_STATE_ERR
);
796 while (sq
->cc
!= sq
->pc
) /* wait till sq is empty */
799 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
800 napi_synchronize(&sq
->channel
->napi
);
802 mlx5e_disable_sq(sq
);
803 mlx5e_destroy_sq(sq
);
806 static int mlx5e_create_cq(struct mlx5e_channel
*c
,
807 struct mlx5e_cq_param
*param
,
810 struct mlx5e_priv
*priv
= c
->priv
;
811 struct mlx5_core_dev
*mdev
= priv
->mdev
;
812 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
818 param
->wq
.buf_numa_node
= cpu_to_node(c
->cpu
);
819 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
820 param
->eq_ix
= c
->ix
;
822 err
= mlx5_cqwq_create(mdev
, ¶m
->wq
, param
->cqc
, &cq
->wq
,
827 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn_not_used
, &irqn
);
832 mcq
->set_ci_db
= cq
->wq_ctrl
.db
.db
;
833 mcq
->arm_db
= cq
->wq_ctrl
.db
.db
+ 1;
836 mcq
->vector
= param
->eq_ix
;
837 mcq
->comp
= mlx5e_completion_event
;
838 mcq
->event
= mlx5e_cq_error_event
;
840 mcq
->uar
= &priv
->cq_uar
;
842 for (i
= 0; i
< mlx5_cqwq_get_size(&cq
->wq
); i
++) {
843 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, i
);
854 static void mlx5e_destroy_cq(struct mlx5e_cq
*cq
)
856 mlx5_wq_destroy(&cq
->wq_ctrl
);
859 static int mlx5e_enable_cq(struct mlx5e_cq
*cq
, struct mlx5e_cq_param
*param
)
861 struct mlx5e_priv
*priv
= cq
->priv
;
862 struct mlx5_core_dev
*mdev
= priv
->mdev
;
863 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
868 unsigned int irqn_not_used
;
872 inlen
= MLX5_ST_SZ_BYTES(create_cq_in
) +
873 sizeof(u64
) * cq
->wq_ctrl
.buf
.npages
;
874 in
= mlx5_vzalloc(inlen
);
878 cqc
= MLX5_ADDR_OF(create_cq_in
, in
, cq_context
);
880 memcpy(cqc
, param
->cqc
, sizeof(param
->cqc
));
882 mlx5_fill_page_array(&cq
->wq_ctrl
.buf
,
883 (__be64
*)MLX5_ADDR_OF(create_cq_in
, in
, pas
));
885 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn
, &irqn_not_used
);
887 MLX5_SET(cqc
, cqc
, c_eqn
, eqn
);
888 MLX5_SET(cqc
, cqc
, uar_page
, mcq
->uar
->index
);
889 MLX5_SET(cqc
, cqc
, log_page_size
, cq
->wq_ctrl
.buf
.page_shift
-
890 MLX5_ADAPTER_PAGE_SHIFT
);
891 MLX5_SET64(cqc
, cqc
, dbr_addr
, cq
->wq_ctrl
.db
.dma
);
893 err
= mlx5_core_create_cq(mdev
, mcq
, in
, inlen
);
905 static void mlx5e_disable_cq(struct mlx5e_cq
*cq
)
907 struct mlx5e_priv
*priv
= cq
->priv
;
908 struct mlx5_core_dev
*mdev
= priv
->mdev
;
910 mlx5_core_destroy_cq(mdev
, &cq
->mcq
);
913 static int mlx5e_open_cq(struct mlx5e_channel
*c
,
914 struct mlx5e_cq_param
*param
,
916 u16 moderation_usecs
,
917 u16 moderation_frames
)
920 struct mlx5e_priv
*priv
= c
->priv
;
921 struct mlx5_core_dev
*mdev
= priv
->mdev
;
923 err
= mlx5e_create_cq(c
, param
, cq
);
927 err
= mlx5e_enable_cq(cq
, param
);
931 if (MLX5_CAP_GEN(mdev
, cq_moderation
))
932 mlx5_core_modify_cq_moderation(mdev
, &cq
->mcq
,
938 mlx5e_destroy_cq(cq
);
943 static void mlx5e_close_cq(struct mlx5e_cq
*cq
)
945 mlx5e_disable_cq(cq
);
946 mlx5e_destroy_cq(cq
);
949 static int mlx5e_get_cpu(struct mlx5e_priv
*priv
, int ix
)
951 return cpumask_first(priv
->mdev
->priv
.irq_info
[ix
].mask
);
954 static int mlx5e_open_tx_cqs(struct mlx5e_channel
*c
,
955 struct mlx5e_channel_param
*cparam
)
957 struct mlx5e_priv
*priv
= c
->priv
;
961 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
962 err
= mlx5e_open_cq(c
, &cparam
->tx_cq
, &c
->sq
[tc
].cq
,
963 priv
->params
.tx_cq_moderation_usec
,
964 priv
->params
.tx_cq_moderation_pkts
);
966 goto err_close_tx_cqs
;
972 for (tc
--; tc
>= 0; tc
--)
973 mlx5e_close_cq(&c
->sq
[tc
].cq
);
978 static void mlx5e_close_tx_cqs(struct mlx5e_channel
*c
)
982 for (tc
= 0; tc
< c
->num_tc
; tc
++)
983 mlx5e_close_cq(&c
->sq
[tc
].cq
);
986 static int mlx5e_open_sqs(struct mlx5e_channel
*c
,
987 struct mlx5e_channel_param
*cparam
)
992 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
993 err
= mlx5e_open_sq(c
, tc
, &cparam
->sq
, &c
->sq
[tc
]);
1001 for (tc
--; tc
>= 0; tc
--)
1002 mlx5e_close_sq(&c
->sq
[tc
]);
1007 static void mlx5e_close_sqs(struct mlx5e_channel
*c
)
1011 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1012 mlx5e_close_sq(&c
->sq
[tc
]);
1015 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv
*priv
, int ix
)
1019 for (i
= 0; i
< MLX5E_MAX_NUM_TC
; i
++)
1020 priv
->channeltc_to_txq_map
[ix
][i
] =
1021 ix
+ i
* priv
->params
.num_channels
;
1024 static int mlx5e_open_channel(struct mlx5e_priv
*priv
, int ix
,
1025 struct mlx5e_channel_param
*cparam
,
1026 struct mlx5e_channel
**cp
)
1028 struct net_device
*netdev
= priv
->netdev
;
1029 int cpu
= mlx5e_get_cpu(priv
, ix
);
1030 struct mlx5e_channel
*c
;
1033 c
= kzalloc_node(sizeof(*c
), GFP_KERNEL
, cpu_to_node(cpu
));
1040 c
->pdev
= &priv
->mdev
->pdev
->dev
;
1041 c
->netdev
= priv
->netdev
;
1042 c
->mkey_be
= cpu_to_be32(priv
->mkey
.key
);
1043 c
->num_tc
= priv
->params
.num_tc
;
1045 mlx5e_build_channeltc_to_txq_map(priv
, ix
);
1047 netif_napi_add(netdev
, &c
->napi
, mlx5e_napi_poll
, 64);
1049 err
= mlx5e_open_cq(c
, &cparam
->icosq_cq
, &c
->icosq
.cq
, 0, 0);
1053 err
= mlx5e_open_tx_cqs(c
, cparam
);
1055 goto err_close_icosq_cq
;
1057 err
= mlx5e_open_cq(c
, &cparam
->rx_cq
, &c
->rq
.cq
,
1058 priv
->params
.rx_cq_moderation_usec
,
1059 priv
->params
.rx_cq_moderation_pkts
);
1061 goto err_close_tx_cqs
;
1063 napi_enable(&c
->napi
);
1065 err
= mlx5e_open_sq(c
, 0, &cparam
->icosq
, &c
->icosq
);
1067 goto err_disable_napi
;
1069 err
= mlx5e_open_sqs(c
, cparam
);
1071 goto err_close_icosq
;
1073 err
= mlx5e_open_rq(c
, &cparam
->rq
, &c
->rq
);
1077 netif_set_xps_queue(netdev
, get_cpu_mask(c
->cpu
), ix
);
1086 mlx5e_close_sq(&c
->icosq
);
1089 napi_disable(&c
->napi
);
1090 mlx5e_close_cq(&c
->rq
.cq
);
1093 mlx5e_close_tx_cqs(c
);
1096 mlx5e_close_cq(&c
->icosq
.cq
);
1099 netif_napi_del(&c
->napi
);
1100 napi_hash_del(&c
->napi
);
1106 static void mlx5e_close_channel(struct mlx5e_channel
*c
)
1108 mlx5e_close_rq(&c
->rq
);
1110 mlx5e_close_sq(&c
->icosq
);
1111 napi_disable(&c
->napi
);
1112 mlx5e_close_cq(&c
->rq
.cq
);
1113 mlx5e_close_tx_cqs(c
);
1114 mlx5e_close_cq(&c
->icosq
.cq
);
1115 netif_napi_del(&c
->napi
);
1117 napi_hash_del(&c
->napi
);
1123 static void mlx5e_build_rq_param(struct mlx5e_priv
*priv
,
1124 struct mlx5e_rq_param
*param
)
1126 void *rqc
= param
->rqc
;
1127 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1129 switch (priv
->params
.rq_wq_type
) {
1130 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
1131 MLX5_SET(wq
, wq
, log_wqe_num_of_strides
,
1132 MLX5_MPWRQ_LOG_NUM_STRIDES
- 9);
1133 MLX5_SET(wq
, wq
, log_wqe_stride_size
,
1134 MLX5_MPWRQ_LOG_STRIDE_SIZE
- 6);
1135 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
);
1137 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1138 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1141 MLX5_SET(wq
, wq
, end_padding_mode
, MLX5_WQ_END_PAD_MODE_ALIGN
);
1142 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1143 MLX5_SET(wq
, wq
, log_wq_sz
, priv
->params
.log_rq_size
);
1144 MLX5_SET(wq
, wq
, pd
, priv
->pdn
);
1145 MLX5_SET(rqc
, rqc
, counter_set_id
, priv
->q_counter
);
1147 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1148 param
->wq
.linear
= 1;
1151 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param
*param
)
1153 void *rqc
= param
->rqc
;
1154 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1156 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1157 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1160 static void mlx5e_build_sq_param_common(struct mlx5e_priv
*priv
,
1161 struct mlx5e_sq_param
*param
)
1163 void *sqc
= param
->sqc
;
1164 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1166 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(MLX5_SEND_WQE_BB
));
1167 MLX5_SET(wq
, wq
, pd
, priv
->pdn
);
1169 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1172 static void mlx5e_build_sq_param(struct mlx5e_priv
*priv
,
1173 struct mlx5e_sq_param
*param
)
1175 void *sqc
= param
->sqc
;
1176 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1178 mlx5e_build_sq_param_common(priv
, param
);
1179 MLX5_SET(wq
, wq
, log_wq_sz
, priv
->params
.log_sq_size
);
1181 param
->max_inline
= priv
->params
.tx_max_inline
;
1184 static void mlx5e_build_common_cq_param(struct mlx5e_priv
*priv
,
1185 struct mlx5e_cq_param
*param
)
1187 void *cqc
= param
->cqc
;
1189 MLX5_SET(cqc
, cqc
, uar_page
, priv
->cq_uar
.index
);
1192 static void mlx5e_build_rx_cq_param(struct mlx5e_priv
*priv
,
1193 struct mlx5e_cq_param
*param
)
1195 void *cqc
= param
->cqc
;
1198 switch (priv
->params
.rq_wq_type
) {
1199 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
1200 log_cq_size
= priv
->params
.log_rq_size
+
1201 MLX5_MPWRQ_LOG_NUM_STRIDES
;
1203 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1204 log_cq_size
= priv
->params
.log_rq_size
;
1207 MLX5_SET(cqc
, cqc
, log_cq_size
, log_cq_size
);
1209 mlx5e_build_common_cq_param(priv
, param
);
1212 static void mlx5e_build_tx_cq_param(struct mlx5e_priv
*priv
,
1213 struct mlx5e_cq_param
*param
)
1215 void *cqc
= param
->cqc
;
1217 MLX5_SET(cqc
, cqc
, log_cq_size
, priv
->params
.log_sq_size
);
1219 mlx5e_build_common_cq_param(priv
, param
);
1222 static void mlx5e_build_ico_cq_param(struct mlx5e_priv
*priv
,
1223 struct mlx5e_cq_param
*param
,
1226 void *cqc
= param
->cqc
;
1228 MLX5_SET(cqc
, cqc
, log_cq_size
, log_wq_size
);
1230 mlx5e_build_common_cq_param(priv
, param
);
1233 static void mlx5e_build_icosq_param(struct mlx5e_priv
*priv
,
1234 struct mlx5e_sq_param
*param
,
1237 void *sqc
= param
->sqc
;
1238 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1240 mlx5e_build_sq_param_common(priv
, param
);
1242 MLX5_SET(wq
, wq
, log_wq_sz
, log_wq_size
);
1243 MLX5_SET(sqc
, sqc
, reg_umr
, MLX5_CAP_ETH(priv
->mdev
, reg_umr_sq
));
1245 param
->icosq
= true;
1248 static void mlx5e_build_channel_param(struct mlx5e_priv
*priv
,
1249 struct mlx5e_channel_param
*cparam
)
1251 u8 icosq_log_wq_sz
= MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE
;
1253 memset(cparam
, 0, sizeof(*cparam
));
1255 mlx5e_build_rq_param(priv
, &cparam
->rq
);
1256 mlx5e_build_sq_param(priv
, &cparam
->sq
);
1257 mlx5e_build_icosq_param(priv
, &cparam
->icosq
, icosq_log_wq_sz
);
1258 mlx5e_build_rx_cq_param(priv
, &cparam
->rx_cq
);
1259 mlx5e_build_tx_cq_param(priv
, &cparam
->tx_cq
);
1260 mlx5e_build_ico_cq_param(priv
, &cparam
->icosq_cq
, icosq_log_wq_sz
);
1263 static int mlx5e_open_channels(struct mlx5e_priv
*priv
)
1265 struct mlx5e_channel_param cparam
;
1266 int nch
= priv
->params
.num_channels
;
1271 priv
->channel
= kcalloc(nch
, sizeof(struct mlx5e_channel
*),
1274 priv
->txq_to_sq_map
= kcalloc(nch
* priv
->params
.num_tc
,
1275 sizeof(struct mlx5e_sq
*), GFP_KERNEL
);
1277 if (!priv
->channel
|| !priv
->txq_to_sq_map
)
1278 goto err_free_txq_to_sq_map
;
1280 mlx5e_build_channel_param(priv
, &cparam
);
1281 for (i
= 0; i
< nch
; i
++) {
1282 err
= mlx5e_open_channel(priv
, i
, &cparam
, &priv
->channel
[i
]);
1284 goto err_close_channels
;
1287 for (j
= 0; j
< nch
; j
++) {
1288 err
= mlx5e_wait_for_min_rx_wqes(&priv
->channel
[j
]->rq
);
1290 goto err_close_channels
;
1296 for (i
--; i
>= 0; i
--)
1297 mlx5e_close_channel(priv
->channel
[i
]);
1299 err_free_txq_to_sq_map
:
1300 kfree(priv
->txq_to_sq_map
);
1301 kfree(priv
->channel
);
1306 static void mlx5e_close_channels(struct mlx5e_priv
*priv
)
1310 for (i
= 0; i
< priv
->params
.num_channels
; i
++)
1311 mlx5e_close_channel(priv
->channel
[i
]);
1313 kfree(priv
->txq_to_sq_map
);
1314 kfree(priv
->channel
);
1317 static int mlx5e_rx_hash_fn(int hfunc
)
1319 return (hfunc
== ETH_RSS_HASH_TOP
) ?
1320 MLX5_RX_HASH_FN_TOEPLITZ
:
1321 MLX5_RX_HASH_FN_INVERTED_XOR8
;
1324 static int mlx5e_bits_invert(unsigned long a
, int size
)
1329 for (i
= 0; i
< size
; i
++)
1330 inv
|= (test_bit(size
- i
- 1, &a
) ? 1 : 0) << i
;
1335 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv
*priv
, void *rqtc
)
1339 for (i
= 0; i
< MLX5E_INDIR_RQT_SIZE
; i
++) {
1342 if (priv
->params
.rss_hfunc
== ETH_RSS_HASH_XOR
)
1343 ix
= mlx5e_bits_invert(i
, MLX5E_LOG_INDIR_RQT_SIZE
);
1345 ix
= priv
->params
.indirection_rqt
[ix
];
1346 MLX5_SET(rqtc
, rqtc
, rq_num
[i
],
1347 test_bit(MLX5E_STATE_OPENED
, &priv
->state
) ?
1348 priv
->channel
[ix
]->rq
.rqn
:
1353 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv
*priv
, void *rqtc
,
1354 enum mlx5e_rqt_ix rqt_ix
)
1358 case MLX5E_INDIRECTION_RQT
:
1359 mlx5e_fill_indir_rqt_rqns(priv
, rqtc
);
1363 default: /* MLX5E_SINGLE_RQ_RQT */
1364 MLX5_SET(rqtc
, rqtc
, rq_num
[0],
1365 test_bit(MLX5E_STATE_OPENED
, &priv
->state
) ?
1366 priv
->channel
[0]->rq
.rqn
:
1373 static int mlx5e_create_rqt(struct mlx5e_priv
*priv
, enum mlx5e_rqt_ix rqt_ix
)
1375 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1382 sz
= (rqt_ix
== MLX5E_SINGLE_RQ_RQT
) ? 1 : MLX5E_INDIR_RQT_SIZE
;
1384 inlen
= MLX5_ST_SZ_BYTES(create_rqt_in
) + sizeof(u32
) * sz
;
1385 in
= mlx5_vzalloc(inlen
);
1389 rqtc
= MLX5_ADDR_OF(create_rqt_in
, in
, rqt_context
);
1391 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
1392 MLX5_SET(rqtc
, rqtc
, rqt_max_size
, sz
);
1394 mlx5e_fill_rqt_rqns(priv
, rqtc
, rqt_ix
);
1396 err
= mlx5_core_create_rqt(mdev
, in
, inlen
, &priv
->rqtn
[rqt_ix
]);
1403 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, enum mlx5e_rqt_ix rqt_ix
)
1405 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1412 sz
= (rqt_ix
== MLX5E_SINGLE_RQ_RQT
) ? 1 : MLX5E_INDIR_RQT_SIZE
;
1414 inlen
= MLX5_ST_SZ_BYTES(modify_rqt_in
) + sizeof(u32
) * sz
;
1415 in
= mlx5_vzalloc(inlen
);
1419 rqtc
= MLX5_ADDR_OF(modify_rqt_in
, in
, ctx
);
1421 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
1423 mlx5e_fill_rqt_rqns(priv
, rqtc
, rqt_ix
);
1425 MLX5_SET(modify_rqt_in
, in
, bitmask
.rqn_list
, 1);
1427 err
= mlx5_core_modify_rqt(mdev
, priv
->rqtn
[rqt_ix
], in
, inlen
);
1434 static void mlx5e_destroy_rqt(struct mlx5e_priv
*priv
, enum mlx5e_rqt_ix rqt_ix
)
1436 mlx5_core_destroy_rqt(priv
->mdev
, priv
->rqtn
[rqt_ix
]);
1439 static void mlx5e_redirect_rqts(struct mlx5e_priv
*priv
)
1441 mlx5e_redirect_rqt(priv
, MLX5E_INDIRECTION_RQT
);
1442 mlx5e_redirect_rqt(priv
, MLX5E_SINGLE_RQ_RQT
);
1445 static void mlx5e_build_tir_ctx_lro(void *tirc
, struct mlx5e_priv
*priv
)
1447 if (!priv
->params
.lro_en
)
1450 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1452 MLX5_SET(tirc
, tirc
, lro_enable_mask
,
1453 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
|
1454 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
);
1455 MLX5_SET(tirc
, tirc
, lro_max_ip_payload_size
,
1456 (priv
->params
.lro_wqe_sz
-
1457 ROUGH_MAX_L2_L3_HDR_SZ
) >> 8);
1458 MLX5_SET(tirc
, tirc
, lro_timeout_period_usecs
,
1459 MLX5_CAP_ETH(priv
->mdev
,
1460 lro_timer_supported_periods
[2]));
1463 void mlx5e_build_tir_ctx_hash(void *tirc
, struct mlx5e_priv
*priv
)
1465 MLX5_SET(tirc
, tirc
, rx_hash_fn
,
1466 mlx5e_rx_hash_fn(priv
->params
.rss_hfunc
));
1467 if (priv
->params
.rss_hfunc
== ETH_RSS_HASH_TOP
) {
1468 void *rss_key
= MLX5_ADDR_OF(tirc
, tirc
,
1469 rx_hash_toeplitz_key
);
1470 size_t len
= MLX5_FLD_SZ_BYTES(tirc
,
1471 rx_hash_toeplitz_key
);
1473 MLX5_SET(tirc
, tirc
, rx_hash_symmetric
, 1);
1474 memcpy(rss_key
, priv
->params
.toeplitz_hash_key
, len
);
1478 static int mlx5e_modify_tirs_lro(struct mlx5e_priv
*priv
)
1480 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1488 inlen
= MLX5_ST_SZ_BYTES(modify_tir_in
);
1489 in
= mlx5_vzalloc(inlen
);
1493 MLX5_SET(modify_tir_in
, in
, bitmask
.lro
, 1);
1494 tirc
= MLX5_ADDR_OF(modify_tir_in
, in
, ctx
);
1496 mlx5e_build_tir_ctx_lro(tirc
, priv
);
1498 for (tt
= 0; tt
< MLX5E_NUM_TT
; tt
++) {
1499 err
= mlx5_core_modify_tir(mdev
, priv
->tirn
[tt
], in
, inlen
);
1509 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev
*mdev
,
1516 inlen
= MLX5_ST_SZ_BYTES(modify_tir_in
);
1517 in
= mlx5_vzalloc(inlen
);
1521 MLX5_SET(modify_tir_in
, in
, bitmask
.self_lb_en
, 1);
1523 err
= mlx5_core_modify_tir(mdev
, tirn
, in
, inlen
);
1530 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv
*priv
)
1535 for (i
= 0; i
< MLX5E_NUM_TT
; i
++) {
1536 err
= mlx5e_refresh_tir_self_loopback_enable(priv
->mdev
,
1545 static int mlx5e_set_dev_port_mtu(struct net_device
*netdev
)
1547 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1548 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1552 err
= mlx5_set_port_mtu(mdev
, MLX5E_SW2HW_MTU(netdev
->mtu
), 1);
1556 mlx5_query_port_oper_mtu(mdev
, &hw_mtu
, 1);
1558 if (MLX5E_HW2SW_MTU(hw_mtu
) != netdev
->mtu
)
1559 netdev_warn(netdev
, "%s: Port MTU %d is different than netdev mtu %d\n",
1560 __func__
, MLX5E_HW2SW_MTU(hw_mtu
), netdev
->mtu
);
1562 netdev
->mtu
= MLX5E_HW2SW_MTU(hw_mtu
);
1566 static void mlx5e_netdev_set_tcs(struct net_device
*netdev
)
1568 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1569 int nch
= priv
->params
.num_channels
;
1570 int ntc
= priv
->params
.num_tc
;
1573 netdev_reset_tc(netdev
);
1578 netdev_set_num_tc(netdev
, ntc
);
1580 for (tc
= 0; tc
< ntc
; tc
++)
1581 netdev_set_tc_queue(netdev
, tc
, nch
, tc
* nch
);
1584 int mlx5e_open_locked(struct net_device
*netdev
)
1586 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1590 set_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1592 mlx5e_netdev_set_tcs(netdev
);
1594 num_txqs
= priv
->params
.num_channels
* priv
->params
.num_tc
;
1595 netif_set_real_num_tx_queues(netdev
, num_txqs
);
1596 netif_set_real_num_rx_queues(netdev
, priv
->params
.num_channels
);
1598 err
= mlx5e_set_dev_port_mtu(netdev
);
1600 goto err_clear_state_opened_flag
;
1602 err
= mlx5e_open_channels(priv
);
1604 netdev_err(netdev
, "%s: mlx5e_open_channels failed, %d\n",
1606 goto err_clear_state_opened_flag
;
1609 err
= mlx5e_refresh_tirs_self_loopback_enable(priv
);
1611 netdev_err(netdev
, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1613 goto err_close_channels
;
1616 mlx5e_redirect_rqts(priv
);
1617 mlx5e_update_carrier(priv
);
1618 mlx5e_timestamp_init(priv
);
1620 schedule_delayed_work(&priv
->update_stats_work
, 0);
1625 mlx5e_close_channels(priv
);
1626 err_clear_state_opened_flag
:
1627 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1631 static int mlx5e_open(struct net_device
*netdev
)
1633 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1636 mutex_lock(&priv
->state_lock
);
1637 err
= mlx5e_open_locked(netdev
);
1638 mutex_unlock(&priv
->state_lock
);
1643 int mlx5e_close_locked(struct net_device
*netdev
)
1645 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1647 /* May already be CLOSED in case a previous configuration operation
1648 * (e.g RX/TX queue size change) that involves close&open failed.
1650 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
1653 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1655 mlx5e_timestamp_cleanup(priv
);
1656 netif_carrier_off(priv
->netdev
);
1657 mlx5e_redirect_rqts(priv
);
1658 mlx5e_close_channels(priv
);
1663 static int mlx5e_close(struct net_device
*netdev
)
1665 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1668 mutex_lock(&priv
->state_lock
);
1669 err
= mlx5e_close_locked(netdev
);
1670 mutex_unlock(&priv
->state_lock
);
1675 static int mlx5e_create_drop_rq(struct mlx5e_priv
*priv
,
1676 struct mlx5e_rq
*rq
,
1677 struct mlx5e_rq_param
*param
)
1679 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1680 void *rqc
= param
->rqc
;
1681 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1684 param
->wq
.db_numa_node
= param
->wq
.buf_numa_node
;
1686 err
= mlx5_wq_ll_create(mdev
, ¶m
->wq
, rqc_wq
, &rq
->wq
,
1696 static int mlx5e_create_drop_cq(struct mlx5e_priv
*priv
,
1697 struct mlx5e_cq
*cq
,
1698 struct mlx5e_cq_param
*param
)
1700 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1701 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
1706 err
= mlx5_cqwq_create(mdev
, ¶m
->wq
, param
->cqc
, &cq
->wq
,
1711 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn_not_used
, &irqn
);
1714 mcq
->set_ci_db
= cq
->wq_ctrl
.db
.db
;
1715 mcq
->arm_db
= cq
->wq_ctrl
.db
.db
+ 1;
1716 *mcq
->set_ci_db
= 0;
1718 mcq
->vector
= param
->eq_ix
;
1719 mcq
->comp
= mlx5e_completion_event
;
1720 mcq
->event
= mlx5e_cq_error_event
;
1722 mcq
->uar
= &priv
->cq_uar
;
1729 static int mlx5e_open_drop_rq(struct mlx5e_priv
*priv
)
1731 struct mlx5e_cq_param cq_param
;
1732 struct mlx5e_rq_param rq_param
;
1733 struct mlx5e_rq
*rq
= &priv
->drop_rq
;
1734 struct mlx5e_cq
*cq
= &priv
->drop_rq
.cq
;
1737 memset(&cq_param
, 0, sizeof(cq_param
));
1738 memset(&rq_param
, 0, sizeof(rq_param
));
1739 mlx5e_build_drop_rq_param(&rq_param
);
1741 err
= mlx5e_create_drop_cq(priv
, cq
, &cq_param
);
1745 err
= mlx5e_enable_cq(cq
, &cq_param
);
1747 goto err_destroy_cq
;
1749 err
= mlx5e_create_drop_rq(priv
, rq
, &rq_param
);
1751 goto err_disable_cq
;
1753 err
= mlx5e_enable_rq(rq
, &rq_param
);
1755 goto err_destroy_rq
;
1760 mlx5e_destroy_rq(&priv
->drop_rq
);
1763 mlx5e_disable_cq(&priv
->drop_rq
.cq
);
1766 mlx5e_destroy_cq(&priv
->drop_rq
.cq
);
1771 static void mlx5e_close_drop_rq(struct mlx5e_priv
*priv
)
1773 mlx5e_disable_rq(&priv
->drop_rq
);
1774 mlx5e_destroy_rq(&priv
->drop_rq
);
1775 mlx5e_disable_cq(&priv
->drop_rq
.cq
);
1776 mlx5e_destroy_cq(&priv
->drop_rq
.cq
);
1779 static int mlx5e_create_tis(struct mlx5e_priv
*priv
, int tc
)
1781 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1782 u32 in
[MLX5_ST_SZ_DW(create_tis_in
)];
1783 void *tisc
= MLX5_ADDR_OF(create_tis_in
, in
, ctx
);
1785 memset(in
, 0, sizeof(in
));
1787 MLX5_SET(tisc
, tisc
, prio
, tc
<< 1);
1788 MLX5_SET(tisc
, tisc
, transport_domain
, priv
->tdn
);
1790 return mlx5_core_create_tis(mdev
, in
, sizeof(in
), &priv
->tisn
[tc
]);
1793 static void mlx5e_destroy_tis(struct mlx5e_priv
*priv
, int tc
)
1795 mlx5_core_destroy_tis(priv
->mdev
, priv
->tisn
[tc
]);
1798 static int mlx5e_create_tises(struct mlx5e_priv
*priv
)
1803 for (tc
= 0; tc
< MLX5E_MAX_NUM_TC
; tc
++) {
1804 err
= mlx5e_create_tis(priv
, tc
);
1806 goto err_close_tises
;
1812 for (tc
--; tc
>= 0; tc
--)
1813 mlx5e_destroy_tis(priv
, tc
);
1818 static void mlx5e_destroy_tises(struct mlx5e_priv
*priv
)
1822 for (tc
= 0; tc
< MLX5E_MAX_NUM_TC
; tc
++)
1823 mlx5e_destroy_tis(priv
, tc
);
1826 static void mlx5e_build_tir_ctx(struct mlx5e_priv
*priv
, u32
*tirc
, int tt
)
1828 void *hfso
= MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_outer
);
1830 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->tdn
);
1832 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1833 MLX5_HASH_FIELD_SEL_DST_IP)
1835 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1836 MLX5_HASH_FIELD_SEL_DST_IP |\
1837 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1838 MLX5_HASH_FIELD_SEL_L4_DPORT)
1840 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1841 MLX5_HASH_FIELD_SEL_DST_IP |\
1842 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1844 mlx5e_build_tir_ctx_lro(tirc
, priv
);
1846 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
1850 MLX5_SET(tirc
, tirc
, indirect_table
,
1851 priv
->rqtn
[MLX5E_SINGLE_RQ_RQT
]);
1852 MLX5_SET(tirc
, tirc
, rx_hash_fn
, MLX5_RX_HASH_FN_INVERTED_XOR8
);
1855 MLX5_SET(tirc
, tirc
, indirect_table
,
1856 priv
->rqtn
[MLX5E_INDIRECTION_RQT
]);
1857 mlx5e_build_tir_ctx_hash(tirc
, priv
);
1862 case MLX5E_TT_IPV4_TCP
:
1863 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1864 MLX5_L3_PROT_TYPE_IPV4
);
1865 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1866 MLX5_L4_PROT_TYPE_TCP
);
1867 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1868 MLX5_HASH_IP_L4PORTS
);
1871 case MLX5E_TT_IPV6_TCP
:
1872 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1873 MLX5_L3_PROT_TYPE_IPV6
);
1874 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1875 MLX5_L4_PROT_TYPE_TCP
);
1876 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1877 MLX5_HASH_IP_L4PORTS
);
1880 case MLX5E_TT_IPV4_UDP
:
1881 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1882 MLX5_L3_PROT_TYPE_IPV4
);
1883 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1884 MLX5_L4_PROT_TYPE_UDP
);
1885 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1886 MLX5_HASH_IP_L4PORTS
);
1889 case MLX5E_TT_IPV6_UDP
:
1890 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1891 MLX5_L3_PROT_TYPE_IPV6
);
1892 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1893 MLX5_L4_PROT_TYPE_UDP
);
1894 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1895 MLX5_HASH_IP_L4PORTS
);
1898 case MLX5E_TT_IPV4_IPSEC_AH
:
1899 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1900 MLX5_L3_PROT_TYPE_IPV4
);
1901 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1902 MLX5_HASH_IP_IPSEC_SPI
);
1905 case MLX5E_TT_IPV6_IPSEC_AH
:
1906 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1907 MLX5_L3_PROT_TYPE_IPV6
);
1908 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1909 MLX5_HASH_IP_IPSEC_SPI
);
1912 case MLX5E_TT_IPV4_IPSEC_ESP
:
1913 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1914 MLX5_L3_PROT_TYPE_IPV4
);
1915 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1916 MLX5_HASH_IP_IPSEC_SPI
);
1919 case MLX5E_TT_IPV6_IPSEC_ESP
:
1920 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1921 MLX5_L3_PROT_TYPE_IPV6
);
1922 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1923 MLX5_HASH_IP_IPSEC_SPI
);
1927 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1928 MLX5_L3_PROT_TYPE_IPV4
);
1929 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1934 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1935 MLX5_L3_PROT_TYPE_IPV6
);
1936 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1942 static int mlx5e_create_tir(struct mlx5e_priv
*priv
, int tt
)
1944 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1950 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
1951 in
= mlx5_vzalloc(inlen
);
1955 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
1957 mlx5e_build_tir_ctx(priv
, tirc
, tt
);
1959 err
= mlx5_core_create_tir(mdev
, in
, inlen
, &priv
->tirn
[tt
]);
1966 static void mlx5e_destroy_tir(struct mlx5e_priv
*priv
, int tt
)
1968 mlx5_core_destroy_tir(priv
->mdev
, priv
->tirn
[tt
]);
1971 static int mlx5e_create_tirs(struct mlx5e_priv
*priv
)
1976 for (i
= 0; i
< MLX5E_NUM_TT
; i
++) {
1977 err
= mlx5e_create_tir(priv
, i
);
1979 goto err_destroy_tirs
;
1985 for (i
--; i
>= 0; i
--)
1986 mlx5e_destroy_tir(priv
, i
);
1991 static void mlx5e_destroy_tirs(struct mlx5e_priv
*priv
)
1995 for (i
= 0; i
< MLX5E_NUM_TT
; i
++)
1996 mlx5e_destroy_tir(priv
, i
);
1999 int mlx5e_modify_rqs_vsd(struct mlx5e_priv
*priv
, bool vsd
)
2004 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
2007 for (i
= 0; i
< priv
->params
.num_channels
; i
++) {
2008 err
= mlx5e_modify_rq_vsd(&priv
->channel
[i
]->rq
, vsd
);
2016 static int mlx5e_setup_tc(struct net_device
*netdev
, u8 tc
)
2018 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2022 if (tc
&& tc
!= MLX5E_MAX_NUM_TC
)
2025 mutex_lock(&priv
->state_lock
);
2027 was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2029 mlx5e_close_locked(priv
->netdev
);
2031 priv
->params
.num_tc
= tc
? tc
: 1;
2034 err
= mlx5e_open_locked(priv
->netdev
);
2036 mutex_unlock(&priv
->state_lock
);
2041 static int mlx5e_ndo_setup_tc(struct net_device
*dev
, u32 handle
,
2042 __be16 proto
, struct tc_to_netdev
*tc
)
2044 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2046 if (TC_H_MAJ(handle
) != TC_H_MAJ(TC_H_INGRESS
))
2050 case TC_SETUP_CLSFLOWER
:
2051 switch (tc
->cls_flower
->command
) {
2052 case TC_CLSFLOWER_REPLACE
:
2053 return mlx5e_configure_flower(priv
, proto
, tc
->cls_flower
);
2054 case TC_CLSFLOWER_DESTROY
:
2055 return mlx5e_delete_flower(priv
, tc
->cls_flower
);
2062 if (tc
->type
!= TC_SETUP_MQPRIO
)
2065 return mlx5e_setup_tc(dev
, tc
->tc
);
2068 static struct rtnl_link_stats64
*
2069 mlx5e_get_stats(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
2071 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2072 struct mlx5e_sw_stats
*sstats
= &priv
->stats
.sw
;
2073 struct mlx5e_vport_stats
*vstats
= &priv
->stats
.vport
;
2074 struct mlx5e_pport_stats
*pstats
= &priv
->stats
.pport
;
2076 stats
->rx_packets
= sstats
->rx_packets
;
2077 stats
->rx_bytes
= sstats
->rx_bytes
;
2078 stats
->tx_packets
= sstats
->tx_packets
;
2079 stats
->tx_bytes
= sstats
->tx_bytes
;
2081 stats
->rx_dropped
= priv
->stats
.qcnt
.rx_out_of_buffer
;
2082 stats
->tx_dropped
= sstats
->tx_queue_dropped
;
2084 stats
->rx_length_errors
=
2085 PPORT_802_3_GET(pstats
, a_in_range_length_errors
) +
2086 PPORT_802_3_GET(pstats
, a_out_of_range_length_field
) +
2087 PPORT_802_3_GET(pstats
, a_frame_too_long_errors
);
2088 stats
->rx_crc_errors
=
2089 PPORT_802_3_GET(pstats
, a_frame_check_sequence_errors
);
2090 stats
->rx_frame_errors
= PPORT_802_3_GET(pstats
, a_alignment_errors
);
2091 stats
->tx_aborted_errors
= PPORT_2863_GET(pstats
, if_out_discards
);
2092 stats
->tx_carrier_errors
=
2093 PPORT_802_3_GET(pstats
, a_symbol_error_during_carrier
);
2094 stats
->rx_errors
= stats
->rx_length_errors
+ stats
->rx_crc_errors
+
2095 stats
->rx_frame_errors
;
2096 stats
->tx_errors
= stats
->tx_aborted_errors
+ stats
->tx_carrier_errors
;
2098 /* vport multicast also counts packets that are dropped due to steering
2099 * or rx out of buffer
2102 VPORT_COUNTER_GET(vstats
, received_eth_multicast
.packets
);
2107 static void mlx5e_set_rx_mode(struct net_device
*dev
)
2109 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2111 schedule_work(&priv
->set_rx_mode_work
);
2114 static int mlx5e_set_mac(struct net_device
*netdev
, void *addr
)
2116 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2117 struct sockaddr
*saddr
= addr
;
2119 if (!is_valid_ether_addr(saddr
->sa_data
))
2120 return -EADDRNOTAVAIL
;
2122 netif_addr_lock_bh(netdev
);
2123 ether_addr_copy(netdev
->dev_addr
, saddr
->sa_data
);
2124 netif_addr_unlock_bh(netdev
);
2126 schedule_work(&priv
->set_rx_mode_work
);
2131 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2134 netdev->features |= feature; \
2136 netdev->features &= ~feature; \
2139 typedef int (*mlx5e_feature_handler
)(struct net_device
*netdev
, bool enable
);
2141 static int set_feature_lro(struct net_device
*netdev
, bool enable
)
2143 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2144 bool was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2147 mutex_lock(&priv
->state_lock
);
2149 if (was_opened
&& (priv
->params
.rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST
))
2150 mlx5e_close_locked(priv
->netdev
);
2152 priv
->params
.lro_en
= enable
;
2153 err
= mlx5e_modify_tirs_lro(priv
);
2155 netdev_err(netdev
, "lro modify failed, %d\n", err
);
2156 priv
->params
.lro_en
= !enable
;
2159 if (was_opened
&& (priv
->params
.rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST
))
2160 mlx5e_open_locked(priv
->netdev
);
2162 mutex_unlock(&priv
->state_lock
);
2167 static int set_feature_vlan_filter(struct net_device
*netdev
, bool enable
)
2169 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2172 mlx5e_enable_vlan_filter(priv
);
2174 mlx5e_disable_vlan_filter(priv
);
2179 static int set_feature_tc_num_filters(struct net_device
*netdev
, bool enable
)
2181 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2183 if (!enable
&& mlx5e_tc_num_filters(priv
)) {
2185 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2192 static int set_feature_rx_all(struct net_device
*netdev
, bool enable
)
2194 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2195 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2197 return mlx5_set_port_fcs(mdev
, !enable
);
2200 static int set_feature_rx_vlan(struct net_device
*netdev
, bool enable
)
2202 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2205 mutex_lock(&priv
->state_lock
);
2207 priv
->params
.vlan_strip_disable
= !enable
;
2208 err
= mlx5e_modify_rqs_vsd(priv
, !enable
);
2210 priv
->params
.vlan_strip_disable
= enable
;
2212 mutex_unlock(&priv
->state_lock
);
2217 static int mlx5e_handle_feature(struct net_device
*netdev
,
2218 netdev_features_t wanted_features
,
2219 netdev_features_t feature
,
2220 mlx5e_feature_handler feature_handler
)
2222 netdev_features_t changes
= wanted_features
^ netdev
->features
;
2223 bool enable
= !!(wanted_features
& feature
);
2226 if (!(changes
& feature
))
2229 err
= feature_handler(netdev
, enable
);
2231 netdev_err(netdev
, "%s feature 0x%llx failed err %d\n",
2232 enable
? "Enable" : "Disable", feature
, err
);
2236 MLX5E_SET_FEATURE(netdev
, feature
, enable
);
2240 static int mlx5e_set_features(struct net_device
*netdev
,
2241 netdev_features_t features
)
2245 err
= mlx5e_handle_feature(netdev
, features
, NETIF_F_LRO
,
2247 err
|= mlx5e_handle_feature(netdev
, features
,
2248 NETIF_F_HW_VLAN_CTAG_FILTER
,
2249 set_feature_vlan_filter
);
2250 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_HW_TC
,
2251 set_feature_tc_num_filters
);
2252 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_RXALL
,
2253 set_feature_rx_all
);
2254 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_HW_VLAN_CTAG_RX
,
2255 set_feature_rx_vlan
);
2257 return err
? -EINVAL
: 0;
2260 static int mlx5e_change_mtu(struct net_device
*netdev
, int new_mtu
)
2262 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2263 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2268 mlx5_query_port_max_mtu(mdev
, &max_mtu
, 1);
2270 max_mtu
= MLX5E_HW2SW_MTU(max_mtu
);
2272 if (new_mtu
> max_mtu
) {
2274 "%s: Bad MTU (%d) > (%d) Max\n",
2275 __func__
, new_mtu
, max_mtu
);
2279 mutex_lock(&priv
->state_lock
);
2281 was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2283 mlx5e_close_locked(netdev
);
2285 netdev
->mtu
= new_mtu
;
2288 err
= mlx5e_open_locked(netdev
);
2290 mutex_unlock(&priv
->state_lock
);
2295 static int mlx5e_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2299 return mlx5e_hwstamp_set(dev
, ifr
);
2301 return mlx5e_hwstamp_get(dev
, ifr
);
2307 static int mlx5e_set_vf_mac(struct net_device
*dev
, int vf
, u8
*mac
)
2309 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2310 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2312 return mlx5_eswitch_set_vport_mac(mdev
->priv
.eswitch
, vf
+ 1, mac
);
2315 static int mlx5e_set_vf_vlan(struct net_device
*dev
, int vf
, u16 vlan
, u8 qos
)
2317 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2318 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2320 return mlx5_eswitch_set_vport_vlan(mdev
->priv
.eswitch
, vf
+ 1,
2324 static int mlx5_vport_link2ifla(u8 esw_link
)
2327 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN
:
2328 return IFLA_VF_LINK_STATE_DISABLE
;
2329 case MLX5_ESW_VPORT_ADMIN_STATE_UP
:
2330 return IFLA_VF_LINK_STATE_ENABLE
;
2332 return IFLA_VF_LINK_STATE_AUTO
;
2335 static int mlx5_ifla_link2vport(u8 ifla_link
)
2337 switch (ifla_link
) {
2338 case IFLA_VF_LINK_STATE_DISABLE
:
2339 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN
;
2340 case IFLA_VF_LINK_STATE_ENABLE
:
2341 return MLX5_ESW_VPORT_ADMIN_STATE_UP
;
2343 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO
;
2346 static int mlx5e_set_vf_link_state(struct net_device
*dev
, int vf
,
2349 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2350 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2352 return mlx5_eswitch_set_vport_state(mdev
->priv
.eswitch
, vf
+ 1,
2353 mlx5_ifla_link2vport(link_state
));
2356 static int mlx5e_get_vf_config(struct net_device
*dev
,
2357 int vf
, struct ifla_vf_info
*ivi
)
2359 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2360 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2363 err
= mlx5_eswitch_get_vport_config(mdev
->priv
.eswitch
, vf
+ 1, ivi
);
2366 ivi
->linkstate
= mlx5_vport_link2ifla(ivi
->linkstate
);
2370 static int mlx5e_get_vf_stats(struct net_device
*dev
,
2371 int vf
, struct ifla_vf_stats
*vf_stats
)
2373 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2374 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2376 return mlx5_eswitch_get_vport_stats(mdev
->priv
.eswitch
, vf
+ 1,
2380 static void mlx5e_add_vxlan_port(struct net_device
*netdev
,
2381 sa_family_t sa_family
, __be16 port
)
2383 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2385 if (!mlx5e_vxlan_allowed(priv
->mdev
))
2388 mlx5e_vxlan_add_port(priv
, be16_to_cpu(port
));
2391 static void mlx5e_del_vxlan_port(struct net_device
*netdev
,
2392 sa_family_t sa_family
, __be16 port
)
2394 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2396 if (!mlx5e_vxlan_allowed(priv
->mdev
))
2399 mlx5e_vxlan_del_port(priv
, be16_to_cpu(port
));
2402 static netdev_features_t
mlx5e_vxlan_features_check(struct mlx5e_priv
*priv
,
2403 struct sk_buff
*skb
,
2404 netdev_features_t features
)
2406 struct udphdr
*udph
;
2410 switch (vlan_get_protocol(skb
)) {
2411 case htons(ETH_P_IP
):
2412 proto
= ip_hdr(skb
)->protocol
;
2414 case htons(ETH_P_IPV6
):
2415 proto
= ipv6_hdr(skb
)->nexthdr
;
2421 if (proto
== IPPROTO_UDP
) {
2422 udph
= udp_hdr(skb
);
2423 port
= be16_to_cpu(udph
->dest
);
2426 /* Verify if UDP port is being offloaded by HW */
2427 if (port
&& mlx5e_vxlan_lookup_port(priv
, port
))
2431 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2432 return features
& ~(NETIF_F_CSUM_MASK
| NETIF_F_GSO_MASK
);
2435 static netdev_features_t
mlx5e_features_check(struct sk_buff
*skb
,
2436 struct net_device
*netdev
,
2437 netdev_features_t features
)
2439 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2441 features
= vlan_features_check(skb
, features
);
2442 features
= vxlan_features_check(skb
, features
);
2444 /* Validate if the tunneled packet is being offloaded by HW */
2445 if (skb
->encapsulation
&&
2446 (features
& NETIF_F_CSUM_MASK
|| features
& NETIF_F_GSO_MASK
))
2447 return mlx5e_vxlan_features_check(priv
, skb
, features
);
2452 static const struct net_device_ops mlx5e_netdev_ops_basic
= {
2453 .ndo_open
= mlx5e_open
,
2454 .ndo_stop
= mlx5e_close
,
2455 .ndo_start_xmit
= mlx5e_xmit
,
2456 .ndo_setup_tc
= mlx5e_ndo_setup_tc
,
2457 .ndo_select_queue
= mlx5e_select_queue
,
2458 .ndo_get_stats64
= mlx5e_get_stats
,
2459 .ndo_set_rx_mode
= mlx5e_set_rx_mode
,
2460 .ndo_set_mac_address
= mlx5e_set_mac
,
2461 .ndo_vlan_rx_add_vid
= mlx5e_vlan_rx_add_vid
,
2462 .ndo_vlan_rx_kill_vid
= mlx5e_vlan_rx_kill_vid
,
2463 .ndo_set_features
= mlx5e_set_features
,
2464 .ndo_change_mtu
= mlx5e_change_mtu
,
2465 .ndo_do_ioctl
= mlx5e_ioctl
,
2468 static const struct net_device_ops mlx5e_netdev_ops_sriov
= {
2469 .ndo_open
= mlx5e_open
,
2470 .ndo_stop
= mlx5e_close
,
2471 .ndo_start_xmit
= mlx5e_xmit
,
2472 .ndo_setup_tc
= mlx5e_ndo_setup_tc
,
2473 .ndo_select_queue
= mlx5e_select_queue
,
2474 .ndo_get_stats64
= mlx5e_get_stats
,
2475 .ndo_set_rx_mode
= mlx5e_set_rx_mode
,
2476 .ndo_set_mac_address
= mlx5e_set_mac
,
2477 .ndo_vlan_rx_add_vid
= mlx5e_vlan_rx_add_vid
,
2478 .ndo_vlan_rx_kill_vid
= mlx5e_vlan_rx_kill_vid
,
2479 .ndo_set_features
= mlx5e_set_features
,
2480 .ndo_change_mtu
= mlx5e_change_mtu
,
2481 .ndo_do_ioctl
= mlx5e_ioctl
,
2482 .ndo_add_vxlan_port
= mlx5e_add_vxlan_port
,
2483 .ndo_del_vxlan_port
= mlx5e_del_vxlan_port
,
2484 .ndo_features_check
= mlx5e_features_check
,
2485 .ndo_set_vf_mac
= mlx5e_set_vf_mac
,
2486 .ndo_set_vf_vlan
= mlx5e_set_vf_vlan
,
2487 .ndo_get_vf_config
= mlx5e_get_vf_config
,
2488 .ndo_set_vf_link_state
= mlx5e_set_vf_link_state
,
2489 .ndo_get_vf_stats
= mlx5e_get_vf_stats
,
2492 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev
*mdev
)
2494 if (MLX5_CAP_GEN(mdev
, port_type
) != MLX5_CAP_PORT_TYPE_ETH
)
2496 if (!MLX5_CAP_GEN(mdev
, eth_net_offloads
) ||
2497 !MLX5_CAP_GEN(mdev
, nic_flow_table
) ||
2498 !MLX5_CAP_ETH(mdev
, csum_cap
) ||
2499 !MLX5_CAP_ETH(mdev
, max_lso_cap
) ||
2500 !MLX5_CAP_ETH(mdev
, vlan_cap
) ||
2501 !MLX5_CAP_ETH(mdev
, rss_ind_tbl_cap
) ||
2502 MLX5_CAP_FLOWTABLE(mdev
,
2503 flow_table_properties_nic_receive
.max_ft_level
)
2505 mlx5_core_warn(mdev
,
2506 "Not creating net device, some required device capabilities are missing\n");
2509 if (!MLX5_CAP_ETH(mdev
, self_lb_en_modifiable
))
2510 mlx5_core_warn(mdev
, "Self loop back prevention is not supported\n");
2511 if (!MLX5_CAP_GEN(mdev
, cq_moderation
))
2512 mlx5_core_warn(mdev
, "CQ modiration is not supported\n");
2517 u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev
*mdev
)
2519 int bf_buf_size
= (1 << MLX5_CAP_GEN(mdev
, log_bf_reg_size
)) / 2;
2521 return bf_buf_size
-
2522 sizeof(struct mlx5e_tx_wqe
) +
2523 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2526 #ifdef CONFIG_MLX5_CORE_EN_DCB
2527 static void mlx5e_ets_init(struct mlx5e_priv
*priv
)
2531 priv
->params
.ets
.ets_cap
= mlx5_max_tc(priv
->mdev
) + 1;
2532 for (i
= 0; i
< priv
->params
.ets
.ets_cap
; i
++) {
2533 priv
->params
.ets
.tc_tx_bw
[i
] = MLX5E_MAX_BW_ALLOC
;
2534 priv
->params
.ets
.tc_tsa
[i
] = IEEE_8021QAZ_TSA_VENDOR
;
2535 priv
->params
.ets
.prio_tc
[i
] = i
;
2538 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2539 priv
->params
.ets
.prio_tc
[0] = 1;
2540 priv
->params
.ets
.prio_tc
[1] = 0;
2544 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev
*mdev
,
2545 u32
*indirection_rqt
, int len
,
2548 int node
= mdev
->priv
.numa_node
;
2549 int node_num_of_cores
;
2553 node
= first_online_node
;
2555 node_num_of_cores
= cpumask_weight(cpumask_of_node(node
));
2557 if (node_num_of_cores
)
2558 num_channels
= min_t(int, num_channels
, node_num_of_cores
);
2560 for (i
= 0; i
< len
; i
++)
2561 indirection_rqt
[i
] = i
% num_channels
;
2564 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev
*mdev
)
2566 return MLX5_CAP_GEN(mdev
, striding_rq
) &&
2567 MLX5_CAP_GEN(mdev
, umr_ptr_rlky
) &&
2568 MLX5_CAP_ETH(mdev
, reg_umr_sq
);
2571 static void mlx5e_build_netdev_priv(struct mlx5_core_dev
*mdev
,
2572 struct net_device
*netdev
,
2575 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2577 priv
->params
.log_sq_size
=
2578 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE
;
2579 priv
->params
.rq_wq_type
= mlx5e_check_fragmented_striding_rq_cap(mdev
) ?
2580 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
2581 MLX5_WQ_TYPE_LINKED_LIST
;
2583 switch (priv
->params
.rq_wq_type
) {
2584 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
2585 priv
->params
.log_rq_size
= MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW
;
2586 priv
->params
.lro_en
= true;
2588 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2589 priv
->params
.log_rq_size
= MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE
;
2592 priv
->params
.min_rx_wqes
= mlx5_min_rx_wqes(priv
->params
.rq_wq_type
,
2593 BIT(priv
->params
.log_rq_size
));
2594 priv
->params
.rx_cq_moderation_usec
=
2595 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC
;
2596 priv
->params
.rx_cq_moderation_pkts
=
2597 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS
;
2598 priv
->params
.tx_cq_moderation_usec
=
2599 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC
;
2600 priv
->params
.tx_cq_moderation_pkts
=
2601 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS
;
2602 priv
->params
.tx_max_inline
= mlx5e_get_max_inline_cap(mdev
);
2603 priv
->params
.num_tc
= 1;
2604 priv
->params
.rss_hfunc
= ETH_RSS_HASH_XOR
;
2606 netdev_rss_key_fill(priv
->params
.toeplitz_hash_key
,
2607 sizeof(priv
->params
.toeplitz_hash_key
));
2609 mlx5e_build_default_indir_rqt(mdev
, priv
->params
.indirection_rqt
,
2610 MLX5E_INDIR_RQT_SIZE
, num_channels
);
2612 priv
->params
.lro_wqe_sz
=
2613 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ
;
2616 priv
->netdev
= netdev
;
2617 priv
->params
.num_channels
= num_channels
;
2619 #ifdef CONFIG_MLX5_CORE_EN_DCB
2620 mlx5e_ets_init(priv
);
2623 mutex_init(&priv
->state_lock
);
2625 INIT_WORK(&priv
->update_carrier_work
, mlx5e_update_carrier_work
);
2626 INIT_WORK(&priv
->set_rx_mode_work
, mlx5e_set_rx_mode_work
);
2627 INIT_DELAYED_WORK(&priv
->update_stats_work
, mlx5e_update_stats_work
);
2630 static void mlx5e_set_netdev_dev_addr(struct net_device
*netdev
)
2632 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2634 mlx5_query_nic_vport_mac_address(priv
->mdev
, 0, netdev
->dev_addr
);
2635 if (is_zero_ether_addr(netdev
->dev_addr
) &&
2636 !MLX5_CAP_GEN(priv
->mdev
, vport_group_manager
)) {
2637 eth_hw_addr_random(netdev
);
2638 mlx5_core_info(priv
->mdev
, "Assigned random MAC address %pM\n", netdev
->dev_addr
);
2642 static void mlx5e_build_netdev(struct net_device
*netdev
)
2644 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2645 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2649 SET_NETDEV_DEV(netdev
, &mdev
->pdev
->dev
);
2651 if (MLX5_CAP_GEN(mdev
, vport_group_manager
)) {
2652 netdev
->netdev_ops
= &mlx5e_netdev_ops_sriov
;
2653 #ifdef CONFIG_MLX5_CORE_EN_DCB
2654 netdev
->dcbnl_ops
= &mlx5e_dcbnl_ops
;
2657 netdev
->netdev_ops
= &mlx5e_netdev_ops_basic
;
2660 netdev
->watchdog_timeo
= 15 * HZ
;
2662 netdev
->ethtool_ops
= &mlx5e_ethtool_ops
;
2664 netdev
->vlan_features
|= NETIF_F_SG
;
2665 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
2666 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
2667 netdev
->vlan_features
|= NETIF_F_GRO
;
2668 netdev
->vlan_features
|= NETIF_F_TSO
;
2669 netdev
->vlan_features
|= NETIF_F_TSO6
;
2670 netdev
->vlan_features
|= NETIF_F_RXCSUM
;
2671 netdev
->vlan_features
|= NETIF_F_RXHASH
;
2673 if (!!MLX5_CAP_ETH(mdev
, lro_cap
))
2674 netdev
->vlan_features
|= NETIF_F_LRO
;
2676 netdev
->hw_features
= netdev
->vlan_features
;
2677 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_TX
;
2678 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
;
2679 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
2681 if (mlx5e_vxlan_allowed(mdev
)) {
2682 netdev
->hw_features
|= NETIF_F_GSO_UDP_TUNNEL
;
2683 netdev
->hw_enc_features
|= NETIF_F_IP_CSUM
;
2684 netdev
->hw_enc_features
|= NETIF_F_RXCSUM
;
2685 netdev
->hw_enc_features
|= NETIF_F_TSO
;
2686 netdev
->hw_enc_features
|= NETIF_F_TSO6
;
2687 netdev
->hw_enc_features
|= NETIF_F_RXHASH
;
2688 netdev
->hw_enc_features
|= NETIF_F_GSO_UDP_TUNNEL
;
2691 mlx5_query_port_fcs(mdev
, &fcs_supported
, &fcs_enabled
);
2694 netdev
->hw_features
|= NETIF_F_RXALL
;
2696 netdev
->features
= netdev
->hw_features
;
2697 if (!priv
->params
.lro_en
)
2698 netdev
->features
&= ~NETIF_F_LRO
;
2701 netdev
->features
&= ~NETIF_F_RXALL
;
2703 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2704 if (FT_CAP(flow_modify_en
) &&
2705 FT_CAP(modify_root
) &&
2706 FT_CAP(identified_miss_table_mode
) &&
2707 FT_CAP(flow_table_modify
))
2708 priv
->netdev
->hw_features
|= NETIF_F_HW_TC
;
2710 netdev
->features
|= NETIF_F_HIGHDMA
;
2712 netdev
->priv_flags
|= IFF_UNICAST_FLT
;
2714 mlx5e_set_netdev_dev_addr(netdev
);
2717 static int mlx5e_create_mkey(struct mlx5e_priv
*priv
, u32 pdn
,
2718 struct mlx5_core_mkey
*mkey
)
2720 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2721 struct mlx5_create_mkey_mbox_in
*in
;
2724 in
= mlx5_vzalloc(sizeof(*in
));
2728 in
->seg
.flags
= MLX5_PERM_LOCAL_WRITE
|
2729 MLX5_PERM_LOCAL_READ
|
2730 MLX5_ACCESS_MODE_PA
;
2731 in
->seg
.flags_pd
= cpu_to_be32(pdn
| MLX5_MKEY_LEN64
);
2732 in
->seg
.qpn_mkey7_0
= cpu_to_be32(0xffffff << 8);
2734 err
= mlx5_core_create_mkey(mdev
, mkey
, in
, sizeof(*in
), NULL
, NULL
,
2742 static void mlx5e_create_q_counter(struct mlx5e_priv
*priv
)
2744 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2747 err
= mlx5_core_alloc_q_counter(mdev
, &priv
->q_counter
);
2749 mlx5_core_warn(mdev
, "alloc queue counter failed, %d\n", err
);
2750 priv
->q_counter
= 0;
2754 static void mlx5e_destroy_q_counter(struct mlx5e_priv
*priv
)
2756 if (!priv
->q_counter
)
2759 mlx5_core_dealloc_q_counter(priv
->mdev
, priv
->q_counter
);
2762 static int mlx5e_create_umr_mkey(struct mlx5e_priv
*priv
)
2764 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2765 struct mlx5_create_mkey_mbox_in
*in
;
2766 struct mlx5_mkey_seg
*mkc
;
2767 int inlen
= sizeof(*in
);
2769 mlx5e_get_max_num_channels(mdev
) * MLX5_CHANNEL_MAX_NUM_MTTS
;
2772 in
= mlx5_vzalloc(inlen
);
2777 mkc
->status
= MLX5_MKEY_STATUS_FREE
;
2778 mkc
->flags
= MLX5_PERM_UMR_EN
|
2779 MLX5_PERM_LOCAL_READ
|
2780 MLX5_PERM_LOCAL_WRITE
|
2781 MLX5_ACCESS_MODE_MTT
;
2783 mkc
->qpn_mkey7_0
= cpu_to_be32(0xffffff << 8);
2784 mkc
->flags_pd
= cpu_to_be32(priv
->pdn
);
2785 mkc
->len
= cpu_to_be64(npages
<< PAGE_SHIFT
);
2786 mkc
->xlt_oct_size
= cpu_to_be32(mlx5e_get_mtt_octw(npages
));
2787 mkc
->log2_page_size
= PAGE_SHIFT
;
2789 err
= mlx5_core_create_mkey(mdev
, &priv
->umr_mkey
, in
, inlen
, NULL
,
2797 static void *mlx5e_create_netdev(struct mlx5_core_dev
*mdev
)
2799 struct net_device
*netdev
;
2800 struct mlx5e_priv
*priv
;
2801 int nch
= mlx5e_get_max_num_channels(mdev
);
2804 if (mlx5e_check_required_hca_cap(mdev
))
2807 netdev
= alloc_etherdev_mqs(sizeof(struct mlx5e_priv
),
2808 nch
* MLX5E_MAX_NUM_TC
,
2811 mlx5_core_err(mdev
, "alloc_etherdev_mqs() failed\n");
2815 mlx5e_build_netdev_priv(mdev
, netdev
, nch
);
2816 mlx5e_build_netdev(netdev
);
2818 netif_carrier_off(netdev
);
2820 priv
= netdev_priv(netdev
);
2822 err
= mlx5_alloc_map_uar(mdev
, &priv
->cq_uar
, false);
2824 mlx5_core_err(mdev
, "alloc_map uar failed, %d\n", err
);
2825 goto err_free_netdev
;
2828 err
= mlx5_core_alloc_pd(mdev
, &priv
->pdn
);
2830 mlx5_core_err(mdev
, "alloc pd failed, %d\n", err
);
2831 goto err_unmap_free_uar
;
2834 err
= mlx5_core_alloc_transport_domain(mdev
, &priv
->tdn
);
2836 mlx5_core_err(mdev
, "alloc td failed, %d\n", err
);
2837 goto err_dealloc_pd
;
2840 err
= mlx5e_create_mkey(priv
, priv
->pdn
, &priv
->mkey
);
2842 mlx5_core_err(mdev
, "create mkey failed, %d\n", err
);
2843 goto err_dealloc_transport_domain
;
2846 err
= mlx5e_create_umr_mkey(priv
);
2848 mlx5_core_err(mdev
, "create umr mkey failed, %d\n", err
);
2849 goto err_destroy_mkey
;
2852 err
= mlx5e_create_tises(priv
);
2854 mlx5_core_warn(mdev
, "create tises failed, %d\n", err
);
2855 goto err_destroy_umr_mkey
;
2858 err
= mlx5e_open_drop_rq(priv
);
2860 mlx5_core_err(mdev
, "open drop rq failed, %d\n", err
);
2861 goto err_destroy_tises
;
2864 err
= mlx5e_create_rqt(priv
, MLX5E_INDIRECTION_RQT
);
2866 mlx5_core_warn(mdev
, "create rqt(INDIR) failed, %d\n", err
);
2867 goto err_close_drop_rq
;
2870 err
= mlx5e_create_rqt(priv
, MLX5E_SINGLE_RQ_RQT
);
2872 mlx5_core_warn(mdev
, "create rqt(SINGLE) failed, %d\n", err
);
2873 goto err_destroy_rqt_indir
;
2876 err
= mlx5e_create_tirs(priv
);
2878 mlx5_core_warn(mdev
, "create tirs failed, %d\n", err
);
2879 goto err_destroy_rqt_single
;
2882 err
= mlx5e_create_flow_tables(priv
);
2884 mlx5_core_warn(mdev
, "create flow tables failed, %d\n", err
);
2885 goto err_destroy_tirs
;
2888 mlx5e_create_q_counter(priv
);
2890 mlx5e_init_eth_addr(priv
);
2892 mlx5e_vxlan_init(priv
);
2894 err
= mlx5e_tc_init(priv
);
2896 goto err_dealloc_q_counters
;
2898 #ifdef CONFIG_MLX5_CORE_EN_DCB
2899 mlx5e_dcbnl_ieee_setets_core(priv
, &priv
->params
.ets
);
2902 err
= register_netdev(netdev
);
2904 mlx5_core_err(mdev
, "register_netdev failed, %d\n", err
);
2905 goto err_tc_cleanup
;
2908 if (mlx5e_vxlan_allowed(mdev
))
2909 vxlan_get_rx_port(netdev
);
2911 mlx5e_enable_async_events(priv
);
2912 schedule_work(&priv
->set_rx_mode_work
);
2917 mlx5e_tc_cleanup(priv
);
2919 err_dealloc_q_counters
:
2920 mlx5e_destroy_q_counter(priv
);
2921 mlx5e_destroy_flow_tables(priv
);
2924 mlx5e_destroy_tirs(priv
);
2926 err_destroy_rqt_single
:
2927 mlx5e_destroy_rqt(priv
, MLX5E_SINGLE_RQ_RQT
);
2929 err_destroy_rqt_indir
:
2930 mlx5e_destroy_rqt(priv
, MLX5E_INDIRECTION_RQT
);
2933 mlx5e_close_drop_rq(priv
);
2936 mlx5e_destroy_tises(priv
);
2938 err_destroy_umr_mkey
:
2939 mlx5_core_destroy_mkey(mdev
, &priv
->umr_mkey
);
2942 mlx5_core_destroy_mkey(mdev
, &priv
->mkey
);
2944 err_dealloc_transport_domain
:
2945 mlx5_core_dealloc_transport_domain(mdev
, priv
->tdn
);
2948 mlx5_core_dealloc_pd(mdev
, priv
->pdn
);
2951 mlx5_unmap_free_uar(mdev
, &priv
->cq_uar
);
2954 free_netdev(netdev
);
2959 static void mlx5e_destroy_netdev(struct mlx5_core_dev
*mdev
, void *vpriv
)
2961 struct mlx5e_priv
*priv
= vpriv
;
2962 struct net_device
*netdev
= priv
->netdev
;
2964 set_bit(MLX5E_STATE_DESTROYING
, &priv
->state
);
2966 schedule_work(&priv
->set_rx_mode_work
);
2967 mlx5e_disable_async_events(priv
);
2968 flush_scheduled_work();
2969 unregister_netdev(netdev
);
2970 mlx5e_tc_cleanup(priv
);
2971 mlx5e_vxlan_cleanup(priv
);
2972 mlx5e_destroy_q_counter(priv
);
2973 mlx5e_destroy_flow_tables(priv
);
2974 mlx5e_destroy_tirs(priv
);
2975 mlx5e_destroy_rqt(priv
, MLX5E_SINGLE_RQ_RQT
);
2976 mlx5e_destroy_rqt(priv
, MLX5E_INDIRECTION_RQT
);
2977 mlx5e_close_drop_rq(priv
);
2978 mlx5e_destroy_tises(priv
);
2979 mlx5_core_destroy_mkey(priv
->mdev
, &priv
->umr_mkey
);
2980 mlx5_core_destroy_mkey(priv
->mdev
, &priv
->mkey
);
2981 mlx5_core_dealloc_transport_domain(priv
->mdev
, priv
->tdn
);
2982 mlx5_core_dealloc_pd(priv
->mdev
, priv
->pdn
);
2983 mlx5_unmap_free_uar(priv
->mdev
, &priv
->cq_uar
);
2984 free_netdev(netdev
);
2987 static void *mlx5e_get_netdev(void *vpriv
)
2989 struct mlx5e_priv
*priv
= vpriv
;
2991 return priv
->netdev
;
2994 static struct mlx5_interface mlx5e_interface
= {
2995 .add
= mlx5e_create_netdev
,
2996 .remove
= mlx5e_destroy_netdev
,
2997 .event
= mlx5e_async_event
,
2998 .protocol
= MLX5_INTERFACE_PROTOCOL_ETH
,
2999 .get_dev
= mlx5e_get_netdev
,
3002 void mlx5e_init(void)
3004 mlx5_register_interface(&mlx5e_interface
);
3007 void mlx5e_cleanup(void)
3009 mlx5_unregister_interface(&mlx5e_interface
);