sound/soc/intel/sst-dsp.h

   1 /*
   2  * Intel Smart Sound Technology (SST) Core
   3  *
   4  * Copyright (C) 2013, Intel Corporation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License version
   8  * 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #ifndef __SOUND_SOC_SST_DSP_H
  18 #define __SOUND_SOC_SST_DSP_H
  19
  20 #include <linux/kernel.h>
  21 #include <linux/types.h>
  22 #include <linux/interrupt.h>
  23
  24 /* SST Device IDs  */
  25 #define SST_DEV_ID_LYNX_POINT           0x33C8
  26 #define SST_DEV_ID_WILDCAT_POINT        0x3438
  27 #define SST_DEV_ID_BYT                  0x0F28
  28
  29 /* Supported SST DMA Devices */
  30 #define SST_DMA_TYPE_DW         1
  31 #define SST_DMA_TYPE_MID        2
  32
  33 /* SST Shim register map
  34  * The register naming can differ between products. Some products also
  35  * contain extra functionality.
  36  */
  37 #define SST_CSR                 0x00
  38 #define SST_PISR                0x08
  39 #define SST_PIMR                0x10
  40 #define SST_ISRX                0x18
  41 #define SST_ISRD                0x20
  42 #define SST_IMRX                0x28
  43 #define SST_IMRD                0x30
  44 #define SST_IPCX                0x38 /* IPC IA -> SST */
  45 #define SST_IPCD                0x40 /* IPC SST -> IA */
  46 #define SST_ISRSC               0x48
  47 #define SST_ISRLPESC            0x50
  48 #define SST_IMRSC               0x58
  49 #define SST_IMRLPESC            0x60
  50 #define SST_IPCSC               0x68
  51 #define SST_IPCLPESC            0x70
  52 #define SST_CLKCTL              0x78
  53 #define SST_CSR2                0x80
  54 #define SST_LTRC                0xE0
  55 #define SST_HDMC                0xE8
  56
  57 #define SST_SHIM_BEGIN          SST_CSR
  58 #define SST_SHIM_END            SST_HDMC
  59
  60 #define SST_DBGO                0xF0
  61
  62 #define SST_SHIM_SIZE           0x100
  63 #define SST_PWMCTRL             0x1000
  64
  65 /* SST Shim Register bits
  66  * The register bit naming can differ between products. Some products also
  67  * contain extra functionality.
  68  */
  69
  70 /* CSR / CS */
  71 #define SST_CSR_RST             (0x1 << 1)
  72 #define SST_CSR_SBCS0           (0x1 << 2)
  73 #define SST_CSR_SBCS1           (0x1 << 3)
  74 #define SST_CSR_DCS(x)          (x << 4)
  75 #define SST_CSR_DCS_MASK        (0x7 << 4)
  76 #define SST_CSR_STALL           (0x1 << 10)
  77 #define SST_CSR_S0IOCS          (0x1 << 21)
  78 #define SST_CSR_S1IOCS          (0x1 << 23)
  79 #define SST_CSR_LPCS            (0x1 << 31)
  80 #define SST_BYT_CSR_RST         (0x1 << 0)
  81 #define SST_BYT_CSR_VECTOR_SEL  (0x1 << 1)
  82 #define SST_BYT_CSR_STALL       (0x1 << 2)
  83 #define SST_BYT_CSR_PWAITMODE   (0x1 << 3)
  84
  85 /*  ISRX / ISC */
  86 #define SST_ISRX_BUSY           (0x1 << 1)
  87 #define SST_ISRX_DONE           (0x1 << 0)
  88 #define SST_BYT_ISRX_REQUEST    (0x1 << 1)
  89
  90 /*  ISRD / ISD */
  91 #define SST_ISRD_BUSY           (0x1 << 1)
  92 #define SST_ISRD_DONE           (0x1 << 0)
  93
  94 /* IMRX / IMC */
  95 #define SST_IMRX_BUSY           (0x1 << 1)
  96 #define SST_IMRX_DONE           (0x1 << 0)
  97 #define SST_BYT_IMRX_REQUEST    (0x1 << 1)
  98
  99 /*  IPCX / IPCC */
 100 #define SST_IPCX_DONE           (0x1 << 30)
 101 #define SST_IPCX_BUSY           (0x1 << 31)
 102 #define SST_BYT_IPCX_DONE       ((u64)0x1 << 62)
 103 #define SST_BYT_IPCX_BUSY       ((u64)0x1 << 63)
 104
 105 /*  IPCD */
 106 #define SST_IPCD_DONE           (0x1 << 30)
 107 #define SST_IPCD_BUSY           (0x1 << 31)
 108 #define SST_BYT_IPCD_DONE       ((u64)0x1 << 62)
 109 #define SST_BYT_IPCD_BUSY       ((u64)0x1 << 63)
 110
 111 /* CLKCTL */
 112 #define SST_CLKCTL_SMOS(x)      (x << 24)
 113 #define SST_CLKCTL_MASK         (3 << 24)
 114 #define SST_CLKCTL_DCPLCG       (1 << 18)
 115 #define SST_CLKCTL_SCOE1        (1 << 17)
 116 #define SST_CLKCTL_SCOE0        (1 << 16)
 117
 118 /* CSR2 / CS2 */
 119 #define SST_CSR2_SDFD_SSP0      (1 << 1)
 120 #define SST_CSR2_SDFD_SSP1      (1 << 2)
 121
 122 /* LTRC */
 123 #define SST_LTRC_VAL(x)         (x << 0)
 124
 125 /* HDMC */
 126 #define SST_HDMC_HDDA0(x)       (x << 0)
 127 #define SST_HDMC_HDDA1(x)       (x << 7)
 128
 129
 130 /* SST Vendor Defined Registers and bits */
 131 #define SST_VDRTCTL0            0xa0
 132 #define SST_VDRTCTL1            0xa4
 133 #define SST_VDRTCTL2            0xa8
 134 #define SST_VDRTCTL3            0xaC
 135
 136 /* VDRTCTL0 */
 137 #define SST_VDRTCL0_DSRAMPGE_SHIFT      16
 138 #define SST_VDRTCL0_DSRAMPGE_MASK       (0xffff << SST_VDRTCL0_DSRAMPGE_SHIFT)
 139 #define SST_VDRTCL0_ISRAMPGE_SHIFT      6
 140 #define SST_VDRTCL0_ISRAMPGE_MASK       (0x3ff << SST_VDRTCL0_ISRAMPGE_SHIFT)
 141
 142 struct sst_dsp;
 143
 144 /*
 145  * SST Device.
 146  *
 147  * This structure is populated by the SST core driver.
 148  */
 149 struct sst_dsp_device {
 150         /* Mandatory fields */
 151         struct sst_ops *ops;
 152         irqreturn_t (*thread)(int irq, void *context);
 153         void *thread_context;
 154 };
 155
 156 /*
 157  * SST Platform Data.
 158  */
 159 struct sst_pdata {
 160         /* ACPI data */
 161         u32 lpe_base;
 162         u32 lpe_size;
 163         u32 pcicfg_base;
 164         u32 pcicfg_size;
 165         u32 fw_base;
 166         u32 fw_size;
 167         int irq;
 168
 169         /* Firmware */
 170         const struct firmware *fw;
 171
 172         /* DMA */
 173         u32 dma_base;
 174         u32 dma_size;
 175         int dma_engine;
 176         struct device *dma_dev;
 177
 178         /* DSP */
 179         u32 id;
 180         void *dsp;
 181 };
 182
 183 /* Initialization */
 184 struct sst_dsp *sst_dsp_new(struct device *dev,
 185         struct sst_dsp_device *sst_dev, struct sst_pdata *pdata);
 186 void sst_dsp_free(struct sst_dsp *sst);
 187
 188 /* SHIM Read / Write */
 189 void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value);
 190 u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset);
 191 int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
 192                                 u32 mask, u32 value);
 193 void sst_dsp_shim_write64(struct sst_dsp *sst, u32 offset, u64 value);
 194 u64 sst_dsp_shim_read64(struct sst_dsp *sst, u32 offset);
 195 int sst_dsp_shim_update_bits64(struct sst_dsp *sst, u32 offset,
 196                                 u64 mask, u64 value);
 197
 198 /* SHIM Read / Write Unlocked for callers already holding sst lock */
 199 void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value);
 200 u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset);
 201 int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
 202                                 u32 mask, u32 value);
 203 void sst_dsp_shim_write64_unlocked(struct sst_dsp *sst, u32 offset, u64 value);
 204 u64 sst_dsp_shim_read64_unlocked(struct sst_dsp *sst, u32 offset);
 205 int sst_dsp_shim_update_bits64_unlocked(struct sst_dsp *sst, u32 offset,
 206                                         u64 mask, u64 value);
 207
 208 /* Internal generic low-level SST IO functions - can be overidden */
 209 void sst_shim32_write(void __iomem *addr, u32 offset, u32 value);
 210 u32 sst_shim32_read(void __iomem *addr, u32 offset);
 211 void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value);
 212 u64 sst_shim32_read64(void __iomem *addr, u32 offset);
 213 void sst_memcpy_toio_32(struct sst_dsp *sst,
 214                         void __iomem *dest, void *src, size_t bytes);
 215 void sst_memcpy_fromio_32(struct sst_dsp *sst,
 216                           void *dest, void __iomem *src, size_t bytes);
 217
 218 /* DSP reset & boot */
 219 void sst_dsp_reset(struct sst_dsp *sst);
 220 int sst_dsp_boot(struct sst_dsp *sst);
 221
 222 /* Msg IO */
 223 void sst_dsp_ipc_msg_tx(struct sst_dsp *dsp, u32 msg);
 224 u32 sst_dsp_ipc_msg_rx(struct sst_dsp *dsp);
 225
 226 /* Mailbox management */
 227 int sst_dsp_mailbox_init(struct sst_dsp *dsp, u32 inbox_offset,
 228         size_t inbox_size, u32 outbox_offset, size_t outbox_size);
 229 void sst_dsp_inbox_write(struct sst_dsp *dsp, void *message, size_t bytes);
 230 void sst_dsp_inbox_read(struct sst_dsp *dsp, void *message, size_t bytes);
 231 void sst_dsp_outbox_write(struct sst_dsp *dsp, void *message, size_t bytes);
 232 void sst_dsp_outbox_read(struct sst_dsp *dsp, void *message, size_t bytes);
 233 void sst_dsp_mailbox_dump(struct sst_dsp *dsp, size_t bytes);
 234
 235 /* Debug */
 236 void sst_dsp_dump(struct sst_dsp *sst);
 237
 238 #endif