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[SCSI] bfa: Add support to configure min/max bandwidth for a pcifn
[linux-2.6/btrfs-unstable.git] / drivers / scsi / bfa / bfa_core.c
blob89ebd4459bfc037472cfa5d5b5de7901ec25d0c2
1 /*
2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
3 * All rights reserved
4 * www.brocade.com
5 *
6 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License (GPL) Version 2 as
10 * published by the Free Software Foundation
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 */
17
18 #include "bfad_drv.h"
19 #include "bfa_modules.h"
20 #include "bfi_reg.h"
21
22 BFA_TRC_FILE(HAL, CORE);
23
24 /*
25 * BFA module list terminated by NULL
26 */
27 static struct bfa_module_s *hal_mods[] = {
28 &hal_mod_fcdiag,
29 &hal_mod_sgpg,
30 &hal_mod_fcport,
31 &hal_mod_fcxp,
32 &hal_mod_lps,
33 &hal_mod_uf,
34 &hal_mod_rport,
35 &hal_mod_fcp,
36 &hal_mod_dconf,
37 NULL
38 };
39
40 /*
41 * Message handlers for various modules.
42 */
43 static bfa_isr_func_t bfa_isrs[BFI_MC_MAX] = {
44 bfa_isr_unhandled, /* NONE */
45 bfa_isr_unhandled, /* BFI_MC_IOC */
46 bfa_fcdiag_intr, /* BFI_MC_DIAG */
47 bfa_isr_unhandled, /* BFI_MC_FLASH */
48 bfa_isr_unhandled, /* BFI_MC_CEE */
49 bfa_fcport_isr, /* BFI_MC_FCPORT */
50 bfa_isr_unhandled, /* BFI_MC_IOCFC */
51 bfa_isr_unhandled, /* BFI_MC_LL */
52 bfa_uf_isr, /* BFI_MC_UF */
53 bfa_fcxp_isr, /* BFI_MC_FCXP */
54 bfa_lps_isr, /* BFI_MC_LPS */
55 bfa_rport_isr, /* BFI_MC_RPORT */
56 bfa_itn_isr, /* BFI_MC_ITN */
57 bfa_isr_unhandled, /* BFI_MC_IOIM_READ */
58 bfa_isr_unhandled, /* BFI_MC_IOIM_WRITE */
59 bfa_isr_unhandled, /* BFI_MC_IOIM_IO */
60 bfa_ioim_isr, /* BFI_MC_IOIM */
61 bfa_ioim_good_comp_isr, /* BFI_MC_IOIM_IOCOM */
62 bfa_tskim_isr, /* BFI_MC_TSKIM */
63 bfa_isr_unhandled, /* BFI_MC_SBOOT */
64 bfa_isr_unhandled, /* BFI_MC_IPFC */
65 bfa_isr_unhandled, /* BFI_MC_PORT */
66 bfa_isr_unhandled, /* --------- */
67 bfa_isr_unhandled, /* --------- */
68 bfa_isr_unhandled, /* --------- */
69 bfa_isr_unhandled, /* --------- */
70 bfa_isr_unhandled, /* --------- */
71 bfa_isr_unhandled, /* --------- */
72 bfa_isr_unhandled, /* --------- */
73 bfa_isr_unhandled, /* --------- */
74 bfa_isr_unhandled, /* --------- */
75 bfa_isr_unhandled, /* --------- */
76 };
77 /*
78 * Message handlers for mailbox command classes
79 */
80 static bfa_ioc_mbox_mcfunc_t bfa_mbox_isrs[BFI_MC_MAX] = {
81 NULL,
82 NULL, /* BFI_MC_IOC */
83 NULL, /* BFI_MC_DIAG */
84 NULL, /* BFI_MC_FLASH */
85 NULL, /* BFI_MC_CEE */
86 NULL, /* BFI_MC_PORT */
87 bfa_iocfc_isr, /* BFI_MC_IOCFC */
88 NULL,
89 };
90
91
92
93 static void
94 bfa_com_port_attach(struct bfa_s *bfa)
95 {
96 struct bfa_port_s *port = &bfa->modules.port;
97 struct bfa_mem_dma_s *port_dma = BFA_MEM_PORT_DMA(bfa);
98
99 bfa_port_attach(port, &bfa->ioc, bfa, bfa->trcmod);
100 bfa_port_mem_claim(port, port_dma->kva_curp, port_dma->dma_curp);
101 }
102
103 /*
104 * ablk module attach
105 */
106 static void
107 bfa_com_ablk_attach(struct bfa_s *bfa)
108 {
109 struct bfa_ablk_s *ablk = &bfa->modules.ablk;
110 struct bfa_mem_dma_s *ablk_dma = BFA_MEM_ABLK_DMA(bfa);
111
112 bfa_ablk_attach(ablk, &bfa->ioc);
113 bfa_ablk_memclaim(ablk, ablk_dma->kva_curp, ablk_dma->dma_curp);
114 }
115
116 static void
117 bfa_com_cee_attach(struct bfa_s *bfa)
118 {
119 struct bfa_cee_s *cee = &bfa->modules.cee;
120 struct bfa_mem_dma_s *cee_dma = BFA_MEM_CEE_DMA(bfa);
121
122 cee->trcmod = bfa->trcmod;
123 bfa_cee_attach(cee, &bfa->ioc, bfa);
124 bfa_cee_mem_claim(cee, cee_dma->kva_curp, cee_dma->dma_curp);
125 }
126
127 static void
128 bfa_com_sfp_attach(struct bfa_s *bfa)
129 {
130 struct bfa_sfp_s *sfp = BFA_SFP_MOD(bfa);
131 struct bfa_mem_dma_s *sfp_dma = BFA_MEM_SFP_DMA(bfa);
132
133 bfa_sfp_attach(sfp, &bfa->ioc, bfa, bfa->trcmod);
134 bfa_sfp_memclaim(sfp, sfp_dma->kva_curp, sfp_dma->dma_curp);
135 }
136
137 static void
138 bfa_com_flash_attach(struct bfa_s *bfa, bfa_boolean_t mincfg)
139 {
140 struct bfa_flash_s *flash = BFA_FLASH(bfa);
141 struct bfa_mem_dma_s *flash_dma = BFA_MEM_FLASH_DMA(bfa);
142
143 bfa_flash_attach(flash, &bfa->ioc, bfa, bfa->trcmod, mincfg);
144 bfa_flash_memclaim(flash, flash_dma->kva_curp,
145 flash_dma->dma_curp, mincfg);
146 }
147
148 static void
149 bfa_com_diag_attach(struct bfa_s *bfa)
150 {
151 struct bfa_diag_s *diag = BFA_DIAG_MOD(bfa);
152 struct bfa_mem_dma_s *diag_dma = BFA_MEM_DIAG_DMA(bfa);
153
154 bfa_diag_attach(diag, &bfa->ioc, bfa, bfa_fcport_beacon, bfa->trcmod);
155 bfa_diag_memclaim(diag, diag_dma->kva_curp, diag_dma->dma_curp);
156 }
157
158 static void
159 bfa_com_phy_attach(struct bfa_s *bfa, bfa_boolean_t mincfg)
160 {
161 struct bfa_phy_s *phy = BFA_PHY(bfa);
162 struct bfa_mem_dma_s *phy_dma = BFA_MEM_PHY_DMA(bfa);
163
164 bfa_phy_attach(phy, &bfa->ioc, bfa, bfa->trcmod, mincfg);
165 bfa_phy_memclaim(phy, phy_dma->kva_curp, phy_dma->dma_curp, mincfg);
166 }
167
168 /*
169 * BFA IOC FC related definitions
170 */
171
172 /*
173 * IOC local definitions
174 */
175 #define BFA_IOCFC_TOV 5000 /* msecs */
176
177 enum {
178 BFA_IOCFC_ACT_NONE = 0,
179 BFA_IOCFC_ACT_INIT = 1,
180 BFA_IOCFC_ACT_STOP = 2,
181 BFA_IOCFC_ACT_DISABLE = 3,
182 BFA_IOCFC_ACT_ENABLE = 4,
183 };
184
185 #define DEF_CFG_NUM_FABRICS 1
186 #define DEF_CFG_NUM_LPORTS 256
187 #define DEF_CFG_NUM_CQS 4
188 #define DEF_CFG_NUM_IOIM_REQS (BFA_IOIM_MAX)
189 #define DEF_CFG_NUM_TSKIM_REQS 128
190 #define DEF_CFG_NUM_FCXP_REQS 64
191 #define DEF_CFG_NUM_UF_BUFS 64
192 #define DEF_CFG_NUM_RPORTS 1024
193 #define DEF_CFG_NUM_ITNIMS (DEF_CFG_NUM_RPORTS)
194 #define DEF_CFG_NUM_TINS 256
195
196 #define DEF_CFG_NUM_SGPGS 2048
197 #define DEF_CFG_NUM_REQQ_ELEMS 256
198 #define DEF_CFG_NUM_RSPQ_ELEMS 64
199 #define DEF_CFG_NUM_SBOOT_TGTS 16
200 #define DEF_CFG_NUM_SBOOT_LUNS 16
201
202 /*
203 * IOCFC state machine definitions/declarations
204 */
205 bfa_fsm_state_decl(bfa_iocfc, stopped, struct bfa_iocfc_s, enum iocfc_event);
206 bfa_fsm_state_decl(bfa_iocfc, initing, struct bfa_iocfc_s, enum iocfc_event);
207 bfa_fsm_state_decl(bfa_iocfc, dconf_read, struct bfa_iocfc_s, enum iocfc_event);
208 bfa_fsm_state_decl(bfa_iocfc, init_cfg_wait,
209 struct bfa_iocfc_s, enum iocfc_event);
210 bfa_fsm_state_decl(bfa_iocfc, init_cfg_done,
211 struct bfa_iocfc_s, enum iocfc_event);
212 bfa_fsm_state_decl(bfa_iocfc, operational,
213 struct bfa_iocfc_s, enum iocfc_event);
214 bfa_fsm_state_decl(bfa_iocfc, dconf_write,
215 struct bfa_iocfc_s, enum iocfc_event);
216 bfa_fsm_state_decl(bfa_iocfc, stopping, struct bfa_iocfc_s, enum iocfc_event);
217 bfa_fsm_state_decl(bfa_iocfc, enabling, struct bfa_iocfc_s, enum iocfc_event);
218 bfa_fsm_state_decl(bfa_iocfc, cfg_wait, struct bfa_iocfc_s, enum iocfc_event);
219 bfa_fsm_state_decl(bfa_iocfc, disabling, struct bfa_iocfc_s, enum iocfc_event);
220 bfa_fsm_state_decl(bfa_iocfc, disabled, struct bfa_iocfc_s, enum iocfc_event);
221 bfa_fsm_state_decl(bfa_iocfc, failed, struct bfa_iocfc_s, enum iocfc_event);
222 bfa_fsm_state_decl(bfa_iocfc, init_failed,
223 struct bfa_iocfc_s, enum iocfc_event);
224
225 /*
226 * forward declaration for IOC FC functions
227 */
228 static void bfa_iocfc_start_submod(struct bfa_s *bfa);
229 static void bfa_iocfc_disable_submod(struct bfa_s *bfa);
230 static void bfa_iocfc_send_cfg(void *bfa_arg);
231 static void bfa_iocfc_enable_cbfn(void *bfa_arg, enum bfa_status status);
232 static void bfa_iocfc_disable_cbfn(void *bfa_arg);
233 static void bfa_iocfc_hbfail_cbfn(void *bfa_arg);
234 static void bfa_iocfc_reset_cbfn(void *bfa_arg);
235 static struct bfa_ioc_cbfn_s bfa_iocfc_cbfn;
236 static void bfa_iocfc_init_cb(void *bfa_arg, bfa_boolean_t complete);
237 static void bfa_iocfc_stop_cb(void *bfa_arg, bfa_boolean_t compl);
238 static void bfa_iocfc_enable_cb(void *bfa_arg, bfa_boolean_t compl);
239 static void bfa_iocfc_disable_cb(void *bfa_arg, bfa_boolean_t compl);
240
241 static void
242 bfa_iocfc_sm_stopped_entry(struct bfa_iocfc_s *iocfc)
243 {
244 }
245
246 static void
247 bfa_iocfc_sm_stopped(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
248 {
249 bfa_trc(iocfc->bfa, event);
250
251 switch (event) {
252 case IOCFC_E_INIT:
253 case IOCFC_E_ENABLE:
254 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_initing);
255 break;
256 default:
257 bfa_sm_fault(iocfc->bfa, event);
258 break;
259 }
260 }
261
262 static void
263 bfa_iocfc_sm_initing_entry(struct bfa_iocfc_s *iocfc)
264 {
265 bfa_ioc_enable(&iocfc->bfa->ioc);
266 }
267
268 static void
269 bfa_iocfc_sm_initing(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
270 {
271 bfa_trc(iocfc->bfa, event);
272
273 switch (event) {
274 case IOCFC_E_IOC_ENABLED:
275 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_read);
276 break;
277
278 case IOCFC_E_DISABLE:
279 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling);
280 break;
281
282 case IOCFC_E_STOP:
283 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping);
284 break;
285
286 case IOCFC_E_IOC_FAILED:
287 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_failed);
288 break;
289 default:
290 bfa_sm_fault(iocfc->bfa, event);
291 break;
292 }
293 }
294
295 static void
296 bfa_iocfc_sm_dconf_read_entry(struct bfa_iocfc_s *iocfc)
297 {
298 bfa_dconf_modinit(iocfc->bfa);
299 }
300
301 static void
302 bfa_iocfc_sm_dconf_read(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
303 {
304 bfa_trc(iocfc->bfa, event);
305
306 switch (event) {
307 case IOCFC_E_DCONF_DONE:
308 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_cfg_wait);
309 break;
310
311 case IOCFC_E_DISABLE:
312 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling);
313 break;
314
315 case IOCFC_E_STOP:
316 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping);
317 break;
318
319 case IOCFC_E_IOC_FAILED:
320 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_failed);
321 break;
322 default:
323 bfa_sm_fault(iocfc->bfa, event);
324 break;
325 }
326 }
327
328 static void
329 bfa_iocfc_sm_init_cfg_wait_entry(struct bfa_iocfc_s *iocfc)
330 {
331 bfa_iocfc_send_cfg(iocfc->bfa);
332 }
333
334 static void
335 bfa_iocfc_sm_init_cfg_wait(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
336 {
337 bfa_trc(iocfc->bfa, event);
338
339 switch (event) {
340 case IOCFC_E_CFG_DONE:
341 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_cfg_done);
342 break;
343
344 case IOCFC_E_DISABLE:
345 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling);
346 break;
347
348 case IOCFC_E_STOP:
349 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping);
350 break;
351
352 case IOCFC_E_IOC_FAILED:
353 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_failed);
354 break;
355 default:
356 bfa_sm_fault(iocfc->bfa, event);
357 break;
358 }
359 }
360
361 static void
362 bfa_iocfc_sm_init_cfg_done_entry(struct bfa_iocfc_s *iocfc)
363 {
364 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK;
365 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.init_hcb_qe,
366 bfa_iocfc_init_cb, iocfc->bfa);
367 }
368
369 static void
370 bfa_iocfc_sm_init_cfg_done(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
371 {
372 bfa_trc(iocfc->bfa, event);
373
374 switch (event) {
375 case IOCFC_E_START:
376 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_operational);
377 break;
378 case IOCFC_E_STOP:
379 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping);
380 break;
381 case IOCFC_E_DISABLE:
382 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling);
383 break;
384 case IOCFC_E_IOC_FAILED:
385 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed);
386 break;
387 default:
388 bfa_sm_fault(iocfc->bfa, event);
389 break;
390 }
391 }
392
393 static void
394 bfa_iocfc_sm_operational_entry(struct bfa_iocfc_s *iocfc)
395 {
396 bfa_fcport_init(iocfc->bfa);
397 bfa_iocfc_start_submod(iocfc->bfa);
398 }
399
400 static void
401 bfa_iocfc_sm_operational(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
402 {
403 bfa_trc(iocfc->bfa, event);
404
405 switch (event) {
406 case IOCFC_E_STOP:
407 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write);
408 break;
409 case IOCFC_E_DISABLE:
410 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling);
411 break;
412 case IOCFC_E_IOC_FAILED:
413 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed);
414 break;
415 default:
416 bfa_sm_fault(iocfc->bfa, event);
417 break;
418 }
419 }
420
421 static void
422 bfa_iocfc_sm_dconf_write_entry(struct bfa_iocfc_s *iocfc)
423 {
424 bfa_dconf_modexit(iocfc->bfa);
425 }
426
427 static void
428 bfa_iocfc_sm_dconf_write(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
429 {
430 bfa_trc(iocfc->bfa, event);
431
432 switch (event) {
433 case IOCFC_E_DCONF_DONE:
434 case IOCFC_E_IOC_FAILED:
435 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping);
436 break;
437 default:
438 bfa_sm_fault(iocfc->bfa, event);
439 break;
440 }
441 }
442
443 static void
444 bfa_iocfc_sm_stopping_entry(struct bfa_iocfc_s *iocfc)
445 {
446 bfa_ioc_disable(&iocfc->bfa->ioc);
447 }
448
449 static void
450 bfa_iocfc_sm_stopping(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
451 {
452 bfa_trc(iocfc->bfa, event);
453
454 switch (event) {
455 case IOCFC_E_IOC_DISABLED:
456 bfa_isr_disable(iocfc->bfa);
457 bfa_iocfc_disable_submod(iocfc->bfa);
458 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopped);
459 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK;
460 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.stop_hcb_qe,
461 bfa_iocfc_stop_cb, iocfc->bfa);
462 break;
463
464 case IOCFC_E_IOC_ENABLED:
465 case IOCFC_E_DCONF_DONE:
466 case IOCFC_E_CFG_DONE:
467 break;
468
469 default:
470 bfa_sm_fault(iocfc->bfa, event);
471 break;
472 }
473 }
474
475 static void
476 bfa_iocfc_sm_enabling_entry(struct bfa_iocfc_s *iocfc)
477 {
478 bfa_ioc_enable(&iocfc->bfa->ioc);
479 }
480
481 static void
482 bfa_iocfc_sm_enabling(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
483 {
484 bfa_trc(iocfc->bfa, event);
485
486 switch (event) {
487 case IOCFC_E_IOC_ENABLED:
488 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_cfg_wait);
489 break;
490
491 case IOCFC_E_DISABLE:
492 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling);
493 break;
494
495 case IOCFC_E_STOP:
496 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write);
497 break;
498
499 case IOCFC_E_IOC_FAILED:
500 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed);
501
502 if (iocfc->bfa->iocfc.cb_reqd == BFA_FALSE)
503 break;
504
505 iocfc->bfa->iocfc.op_status = BFA_STATUS_FAILED;
506 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.en_hcb_qe,
507 bfa_iocfc_enable_cb, iocfc->bfa);
508 iocfc->bfa->iocfc.cb_reqd = BFA_FALSE;
509 break;
510 default:
511 bfa_sm_fault(iocfc->bfa, event);
512 break;
513 }
514 }
515
516 static void
517 bfa_iocfc_sm_cfg_wait_entry(struct bfa_iocfc_s *iocfc)
518 {
519 bfa_iocfc_send_cfg(iocfc->bfa);
520 }
521
522 static void
523 bfa_iocfc_sm_cfg_wait(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
524 {
525 bfa_trc(iocfc->bfa, event);
526
527 switch (event) {
528 case IOCFC_E_CFG_DONE:
529 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_operational);
530 if (iocfc->bfa->iocfc.cb_reqd == BFA_FALSE)
531 break;
532
533 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK;
534 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.en_hcb_qe,
535 bfa_iocfc_enable_cb, iocfc->bfa);
536 iocfc->bfa->iocfc.cb_reqd = BFA_FALSE;
537 break;
538 case IOCFC_E_DISABLE:
539 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling);
540 break;
541
542 case IOCFC_E_STOP:
543 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write);
544 break;
545 case IOCFC_E_IOC_FAILED:
546 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed);
547 if (iocfc->bfa->iocfc.cb_reqd == BFA_FALSE)
548 break;
549
550 iocfc->bfa->iocfc.op_status = BFA_STATUS_FAILED;
551 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.en_hcb_qe,
552 bfa_iocfc_enable_cb, iocfc->bfa);
553 iocfc->bfa->iocfc.cb_reqd = BFA_FALSE;
554 break;
555 default:
556 bfa_sm_fault(iocfc->bfa, event);
557 break;
558 }
559 }
560
561 static void
562 bfa_iocfc_sm_disabling_entry(struct bfa_iocfc_s *iocfc)
563 {
564 bfa_ioc_disable(&iocfc->bfa->ioc);
565 }
566
567 static void
568 bfa_iocfc_sm_disabling(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
569 {
570 bfa_trc(iocfc->bfa, event);
571
572 switch (event) {
573 case IOCFC_E_IOC_DISABLED:
574 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabled);
575 break;
576 case IOCFC_E_IOC_ENABLED:
577 case IOCFC_E_DCONF_DONE:
578 case IOCFC_E_CFG_DONE:
579 break;
580 default:
581 bfa_sm_fault(iocfc->bfa, event);
582 break;
583 }
584 }
585
586 static void
587 bfa_iocfc_sm_disabled_entry(struct bfa_iocfc_s *iocfc)
588 {
589 bfa_isr_disable(iocfc->bfa);
590 bfa_iocfc_disable_submod(iocfc->bfa);
591 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK;
592 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.dis_hcb_qe,
593 bfa_iocfc_disable_cb, iocfc->bfa);
594 }
595
596 static void
597 bfa_iocfc_sm_disabled(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
598 {
599 bfa_trc(iocfc->bfa, event);
600
601 switch (event) {
602 case IOCFC_E_STOP:
603 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write);
604 break;
605 case IOCFC_E_ENABLE:
606 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_enabling);
607 break;
608 default:
609 bfa_sm_fault(iocfc->bfa, event);
610 break;
611 }
612 }
613
614 static void
615 bfa_iocfc_sm_failed_entry(struct bfa_iocfc_s *iocfc)
616 {
617 bfa_isr_disable(iocfc->bfa);
618 bfa_iocfc_disable_submod(iocfc->bfa);
619 }
620
621 static void
622 bfa_iocfc_sm_failed(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
623 {
624 bfa_trc(iocfc->bfa, event);
625
626 switch (event) {
627 case IOCFC_E_STOP:
628 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write);
629 break;
630 case IOCFC_E_DISABLE:
631 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling);
632 break;
633 case IOCFC_E_IOC_ENABLED:
634 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_cfg_wait);
635 break;
636 case IOCFC_E_IOC_FAILED:
637 break;
638 default:
639 bfa_sm_fault(iocfc->bfa, event);
640 break;
641 }
642 }
643
644 static void
645 bfa_iocfc_sm_init_failed_entry(struct bfa_iocfc_s *iocfc)
646 {
647 bfa_isr_disable(iocfc->bfa);
648 iocfc->bfa->iocfc.op_status = BFA_STATUS_FAILED;
649 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.init_hcb_qe,
650 bfa_iocfc_init_cb, iocfc->bfa);
651 }
652
653 static void
654 bfa_iocfc_sm_init_failed(struct bfa_iocfc_s *iocfc, enum iocfc_event event)
655 {
656 bfa_trc(iocfc->bfa, event);
657
658 switch (event) {
659 case IOCFC_E_STOP:
660 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping);
661 break;
662 case IOCFC_E_DISABLE:
663 bfa_ioc_disable(&iocfc->bfa->ioc);
664 break;
665 case IOCFC_E_IOC_ENABLED:
666 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_read);
667 break;
668 case IOCFC_E_IOC_DISABLED:
669 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopped);
670 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK;
671 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.dis_hcb_qe,
672 bfa_iocfc_disable_cb, iocfc->bfa);
673 break;
674 case IOCFC_E_IOC_FAILED:
675 break;
676 default:
677 bfa_sm_fault(iocfc->bfa, event);
678 break;
679 }
680 }
681
682 /*
683 * BFA Interrupt handling functions
684 */
685 static void
686 bfa_reqq_resume(struct bfa_s *bfa, int qid)
687 {
688 struct list_head *waitq, *qe, *qen;
689 struct bfa_reqq_wait_s *wqe;
690
691 waitq = bfa_reqq(bfa, qid);
692 list_for_each_safe(qe, qen, waitq) {
693 /*
694 * Callback only as long as there is room in request queue
695 */
696 if (bfa_reqq_full(bfa, qid))
697 break;
698
699 list_del(qe);
700 wqe = (struct bfa_reqq_wait_s *) qe;
701 wqe->qresume(wqe->cbarg);
702 }
703 }
704
705 bfa_boolean_t
706 bfa_isr_rspq(struct bfa_s *bfa, int qid)
707 {
708 struct bfi_msg_s *m;
709 u32 pi, ci;
710 struct list_head *waitq;
711 bfa_boolean_t ret;
712
713 ci = bfa_rspq_ci(bfa, qid);
714 pi = bfa_rspq_pi(bfa, qid);
715
716 ret = (ci != pi);
717
718 while (ci != pi) {
719 m = bfa_rspq_elem(bfa, qid, ci);
720 WARN_ON(m->mhdr.msg_class >= BFI_MC_MAX);
721
722 bfa_isrs[m->mhdr.msg_class] (bfa, m);
723 CQ_INCR(ci, bfa->iocfc.cfg.drvcfg.num_rspq_elems);
724 }
725
726 /*
727 * acknowledge RME completions and update CI
728 */
729 bfa_isr_rspq_ack(bfa, qid, ci);
730
731 /*
732 * Resume any pending requests in the corresponding reqq.
733 */
734 waitq = bfa_reqq(bfa, qid);
735 if (!list_empty(waitq))
736 bfa_reqq_resume(bfa, qid);
737
738 return ret;
739 }
740
741 static inline void
742 bfa_isr_reqq(struct bfa_s *bfa, int qid)
743 {
744 struct list_head *waitq;
745
746 bfa_isr_reqq_ack(bfa, qid);
747
748 /*
749 * Resume any pending requests in the corresponding reqq.
750 */
751 waitq = bfa_reqq(bfa, qid);
752 if (!list_empty(waitq))
753 bfa_reqq_resume(bfa, qid);
754 }
755
756 void
757 bfa_msix_all(struct bfa_s *bfa, int vec)
758 {
759 u32 intr, qintr;
760 int queue;
761
762 intr = readl(bfa->iocfc.bfa_regs.intr_status);
763 if (!intr)
764 return;
765
766 /*
767 * RME completion queue interrupt
768 */
769 qintr = intr & __HFN_INT_RME_MASK;
770 if (qintr && bfa->queue_process) {
771 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++)
772 bfa_isr_rspq(bfa, queue);
773 }
774
775 intr &= ~qintr;
776 if (!intr)
777 return;
778
779 /*
780 * CPE completion queue interrupt
781 */
782 qintr = intr & __HFN_INT_CPE_MASK;
783 if (qintr && bfa->queue_process) {
784 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++)
785 bfa_isr_reqq(bfa, queue);
786 }
787 intr &= ~qintr;
788 if (!intr)
789 return;
790
791 bfa_msix_lpu_err(bfa, intr);
792 }
793
794 bfa_boolean_t
795 bfa_intx(struct bfa_s *bfa)
796 {
797 u32 intr, qintr;
798 int queue;
799 bfa_boolean_t rspq_comp = BFA_FALSE;
800
801 intr = readl(bfa->iocfc.bfa_regs.intr_status);
802
803 qintr = intr & (__HFN_INT_RME_MASK | __HFN_INT_CPE_MASK);
804 if (qintr)
805 writel(qintr, bfa->iocfc.bfa_regs.intr_status);
806
807 /*
808 * Unconditional RME completion queue interrupt
809 */
810 if (bfa->queue_process) {
811 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++)
812 if (bfa_isr_rspq(bfa, queue))
813 rspq_comp = BFA_TRUE;
814 }
815
816 if (!intr)
817 return (qintr | rspq_comp) ? BFA_TRUE : BFA_FALSE;
818
819 /*
820 * CPE completion queue interrupt
821 */
822 qintr = intr & __HFN_INT_CPE_MASK;
823 if (qintr && bfa->queue_process) {
824 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++)
825 bfa_isr_reqq(bfa, queue);
826 }
827 intr &= ~qintr;
828 if (!intr)
829 return BFA_TRUE;
830
831 if (bfa->intr_enabled)
832 bfa_msix_lpu_err(bfa, intr);
833
834 return BFA_TRUE;
835 }
836
837 void
838 bfa_isr_enable(struct bfa_s *bfa)
839 {
840 u32 umsk;
841 int port_id = bfa_ioc_portid(&bfa->ioc);
842
843 bfa_trc(bfa, bfa_ioc_pcifn(&bfa->ioc));
844 bfa_trc(bfa, port_id);
845
846 bfa_msix_ctrl_install(bfa);
847
848 if (bfa_asic_id_ct2(bfa->ioc.pcidev.device_id)) {
849 umsk = __HFN_INT_ERR_MASK_CT2;
850 umsk |= port_id == 0 ?
851 __HFN_INT_FN0_MASK_CT2 : __HFN_INT_FN1_MASK_CT2;
852 } else {
853 umsk = __HFN_INT_ERR_MASK;
854 umsk |= port_id == 0 ? __HFN_INT_FN0_MASK : __HFN_INT_FN1_MASK;
855 }
856
857 writel(umsk, bfa->iocfc.bfa_regs.intr_status);
858 writel(~umsk, bfa->iocfc.bfa_regs.intr_mask);
859 bfa->iocfc.intr_mask = ~umsk;
860 bfa_isr_mode_set(bfa, bfa->msix.nvecs != 0);
861
862 /*
863 * Set the flag indicating successful enabling of interrupts
864 */
865 bfa->intr_enabled = BFA_TRUE;
866 }
867
868 void
869 bfa_isr_disable(struct bfa_s *bfa)
870 {
871 bfa->intr_enabled = BFA_FALSE;
872 bfa_isr_mode_set(bfa, BFA_FALSE);
873 writel(-1L, bfa->iocfc.bfa_regs.intr_mask);
874 bfa_msix_uninstall(bfa);
875 }
876
877 void
878 bfa_msix_reqq(struct bfa_s *bfa, int vec)
879 {
880 bfa_isr_reqq(bfa, vec - bfa->iocfc.hwif.cpe_vec_q0);
881 }
882
883 void
884 bfa_isr_unhandled(struct bfa_s *bfa, struct bfi_msg_s *m)
885 {
886 bfa_trc(bfa, m->mhdr.msg_class);
887 bfa_trc(bfa, m->mhdr.msg_id);
888 bfa_trc(bfa, m->mhdr.mtag.i2htok);
889 WARN_ON(1);
890 bfa_trc_stop(bfa->trcmod);
891 }
892
893 void
894 bfa_msix_rspq(struct bfa_s *bfa, int vec)
895 {
896 bfa_isr_rspq(bfa, vec - bfa->iocfc.hwif.rme_vec_q0);
897 }
898
899 void
900 bfa_msix_lpu_err(struct bfa_s *bfa, int vec)
901 {
902 u32 intr, curr_value;
903 bfa_boolean_t lpu_isr, halt_isr, pss_isr;
904
905 intr = readl(bfa->iocfc.bfa_regs.intr_status);
906
907 if (bfa_asic_id_ct2(bfa->ioc.pcidev.device_id)) {
908 halt_isr = intr & __HFN_INT_CPQ_HALT_CT2;
909 pss_isr = intr & __HFN_INT_ERR_PSS_CT2;
910 lpu_isr = intr & (__HFN_INT_MBOX_LPU0_CT2 |
911 __HFN_INT_MBOX_LPU1_CT2);
912 intr &= __HFN_INT_ERR_MASK_CT2;
913 } else {
914 halt_isr = bfa_asic_id_ct(bfa->ioc.pcidev.device_id) ?
915 (intr & __HFN_INT_LL_HALT) : 0;
916 pss_isr = intr & __HFN_INT_ERR_PSS;
917 lpu_isr = intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1);
918 intr &= __HFN_INT_ERR_MASK;
919 }
920
921 if (lpu_isr)
922 bfa_ioc_mbox_isr(&bfa->ioc);
923
924 if (intr) {
925 if (halt_isr) {
926 /*
927 * If LL_HALT bit is set then FW Init Halt LL Port
928 * Register needs to be cleared as well so Interrupt
929 * Status Register will be cleared.
930 */
931 curr_value = readl(bfa->ioc.ioc_regs.ll_halt);
932 curr_value &= ~__FW_INIT_HALT_P;
933 writel(curr_value, bfa->ioc.ioc_regs.ll_halt);
934 }
935
936 if (pss_isr) {
937 /*
938 * ERR_PSS bit needs to be cleared as well in case
939 * interrups are shared so driver's interrupt handler is
940 * still called even though it is already masked out.
941 */
942 curr_value = readl(
943 bfa->ioc.ioc_regs.pss_err_status_reg);
944 writel(curr_value,
945 bfa->ioc.ioc_regs.pss_err_status_reg);
946 }
947
948 writel(intr, bfa->iocfc.bfa_regs.intr_status);
949 bfa_ioc_error_isr(&bfa->ioc);
950 }
951 }
952
953 /*
954 * BFA IOC FC related functions
955 */
956
957 /*
958 * BFA IOC private functions
959 */
960
961 /*
962 * Use the Mailbox interface to send BFI_IOCFC_H2I_CFG_REQ
963 */
964 static void
965 bfa_iocfc_send_cfg(void *bfa_arg)
966 {
967 struct bfa_s *bfa = bfa_arg;
968 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
969 struct bfi_iocfc_cfg_req_s cfg_req;
970 struct bfi_iocfc_cfg_s *cfg_info = iocfc->cfginfo;
971 struct bfa_iocfc_cfg_s *cfg = &iocfc->cfg;
972 int i;
973
974 WARN_ON(cfg->fwcfg.num_cqs > BFI_IOC_MAX_CQS);
975 bfa_trc(bfa, cfg->fwcfg.num_cqs);
976
977 bfa_iocfc_reset_queues(bfa);
978
979 /*
980 * initialize IOC configuration info
981 */
982 cfg_info->single_msix_vec = 0;
983 if (bfa->msix.nvecs == 1)
984 cfg_info->single_msix_vec = 1;
985 cfg_info->endian_sig = BFI_IOC_ENDIAN_SIG;
986 cfg_info->num_cqs = cfg->fwcfg.num_cqs;
987 cfg_info->num_ioim_reqs = cpu_to_be16(bfa_fcpim_get_throttle_cfg(bfa,
988 cfg->fwcfg.num_ioim_reqs));
989 cfg_info->num_fwtio_reqs = cpu_to_be16(cfg->fwcfg.num_fwtio_reqs);
990
991 bfa_dma_be_addr_set(cfg_info->cfgrsp_addr, iocfc->cfgrsp_dma.pa);
992 /*
993 * dma map REQ and RSP circular queues and shadow pointers
994 */
995 for (i = 0; i < cfg->fwcfg.num_cqs; i++) {
996 bfa_dma_be_addr_set(cfg_info->req_cq_ba[i],
997 iocfc->req_cq_ba[i].pa);
998 bfa_dma_be_addr_set(cfg_info->req_shadow_ci[i],
999 iocfc->req_cq_shadow_ci[i].pa);
1000 cfg_info->req_cq_elems[i] =
1001 cpu_to_be16(cfg->drvcfg.num_reqq_elems);
1002
1003 bfa_dma_be_addr_set(cfg_info->rsp_cq_ba[i],
1004 iocfc->rsp_cq_ba[i].pa);
1005 bfa_dma_be_addr_set(cfg_info->rsp_shadow_pi[i],
1006 iocfc->rsp_cq_shadow_pi[i].pa);
1007 cfg_info->rsp_cq_elems[i] =
1008 cpu_to_be16(cfg->drvcfg.num_rspq_elems);
1009 }
1010
1011 /*
1012 * Enable interrupt coalescing if it is driver init path
1013 * and not ioc disable/enable path.
1014 */
1015 if (bfa_fsm_cmp_state(iocfc, bfa_iocfc_sm_init_cfg_wait))
1016 cfg_info->intr_attr.coalesce = BFA_TRUE;
1017
1018 /*
1019 * dma map IOC configuration itself
1020 */
1021 bfi_h2i_set(cfg_req.mh, BFI_MC_IOCFC, BFI_IOCFC_H2I_CFG_REQ,
1022 bfa_fn_lpu(bfa));
1023 bfa_dma_be_addr_set(cfg_req.ioc_cfg_dma_addr, iocfc->cfg_info.pa);
1024
1025 bfa_ioc_mbox_send(&bfa->ioc, &cfg_req,
1026 sizeof(struct bfi_iocfc_cfg_req_s));
1027 }
1028
1029 static void
1030 bfa_iocfc_init_mem(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg,
1031 struct bfa_pcidev_s *pcidev)
1032 {
1033 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1034
1035 bfa->bfad = bfad;
1036 iocfc->bfa = bfa;
1037 iocfc->cfg = *cfg;
1038
1039 /*
1040 * Initialize chip specific handlers.
1041 */
1042 if (bfa_asic_id_ctc(bfa_ioc_devid(&bfa->ioc))) {
1043 iocfc->hwif.hw_reginit = bfa_hwct_reginit;
1044 iocfc->hwif.hw_reqq_ack = bfa_hwct_reqq_ack;
1045 iocfc->hwif.hw_rspq_ack = bfa_hwct_rspq_ack;
1046 iocfc->hwif.hw_msix_init = bfa_hwct_msix_init;
1047 iocfc->hwif.hw_msix_ctrl_install = bfa_hwct_msix_ctrl_install;
1048 iocfc->hwif.hw_msix_queue_install = bfa_hwct_msix_queue_install;
1049 iocfc->hwif.hw_msix_uninstall = bfa_hwct_msix_uninstall;
1050 iocfc->hwif.hw_isr_mode_set = bfa_hwct_isr_mode_set;
1051 iocfc->hwif.hw_msix_getvecs = bfa_hwct_msix_getvecs;
1052 iocfc->hwif.hw_msix_get_rme_range = bfa_hwct_msix_get_rme_range;
1053 iocfc->hwif.rme_vec_q0 = BFI_MSIX_RME_QMIN_CT;
1054 iocfc->hwif.cpe_vec_q0 = BFI_MSIX_CPE_QMIN_CT;
1055 } else {
1056 iocfc->hwif.hw_reginit = bfa_hwcb_reginit;
1057 iocfc->hwif.hw_reqq_ack = NULL;
1058 iocfc->hwif.hw_rspq_ack = bfa_hwcb_rspq_ack;
1059 iocfc->hwif.hw_msix_init = bfa_hwcb_msix_init;
1060 iocfc->hwif.hw_msix_ctrl_install = bfa_hwcb_msix_ctrl_install;
1061 iocfc->hwif.hw_msix_queue_install = bfa_hwcb_msix_queue_install;
1062 iocfc->hwif.hw_msix_uninstall = bfa_hwcb_msix_uninstall;
1063 iocfc->hwif.hw_isr_mode_set = bfa_hwcb_isr_mode_set;
1064 iocfc->hwif.hw_msix_getvecs = bfa_hwcb_msix_getvecs;
1065 iocfc->hwif.hw_msix_get_rme_range = bfa_hwcb_msix_get_rme_range;
1066 iocfc->hwif.rme_vec_q0 = BFI_MSIX_RME_QMIN_CB +
1067 bfa_ioc_pcifn(&bfa->ioc) * BFI_IOC_MAX_CQS;
1068 iocfc->hwif.cpe_vec_q0 = BFI_MSIX_CPE_QMIN_CB +
1069 bfa_ioc_pcifn(&bfa->ioc) * BFI_IOC_MAX_CQS;
1070 }
1071
1072 if (bfa_asic_id_ct2(bfa_ioc_devid(&bfa->ioc))) {
1073 iocfc->hwif.hw_reginit = bfa_hwct2_reginit;
1074 iocfc->hwif.hw_isr_mode_set = NULL;
1075 iocfc->hwif.hw_rspq_ack = bfa_hwct2_rspq_ack;
1076 }
1077
1078 iocfc->hwif.hw_reginit(bfa);
1079 bfa->msix.nvecs = 0;
1080 }
1081
1082 static void
1083 bfa_iocfc_mem_claim(struct bfa_s *bfa, struct bfa_iocfc_cfg_s *cfg)
1084 {
1085 u8 *dm_kva = NULL;
1086 u64 dm_pa = 0;
1087 int i, per_reqq_sz, per_rspq_sz;
1088 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1089 struct bfa_mem_dma_s *ioc_dma = BFA_MEM_IOC_DMA(bfa);
1090 struct bfa_mem_dma_s *iocfc_dma = BFA_MEM_IOCFC_DMA(bfa);
1091 struct bfa_mem_dma_s *reqq_dma, *rspq_dma;
1092
1093 /* First allocate dma memory for IOC */
1094 bfa_ioc_mem_claim(&bfa->ioc, bfa_mem_dma_virt(ioc_dma),
1095 bfa_mem_dma_phys(ioc_dma));
1096
1097 /* Claim DMA-able memory for the request/response queues */
1098 per_reqq_sz = BFA_ROUNDUP((cfg->drvcfg.num_reqq_elems * BFI_LMSG_SZ),
1099 BFA_DMA_ALIGN_SZ);
1100 per_rspq_sz = BFA_ROUNDUP((cfg->drvcfg.num_rspq_elems * BFI_LMSG_SZ),
1101 BFA_DMA_ALIGN_SZ);
1102
1103 for (i = 0; i < cfg->fwcfg.num_cqs; i++) {
1104 reqq_dma = BFA_MEM_REQQ_DMA(bfa, i);
1105 iocfc->req_cq_ba[i].kva = bfa_mem_dma_virt(reqq_dma);
1106 iocfc->req_cq_ba[i].pa = bfa_mem_dma_phys(reqq_dma);
1107 memset(iocfc->req_cq_ba[i].kva, 0, per_reqq_sz);
1108
1109 rspq_dma = BFA_MEM_RSPQ_DMA(bfa, i);
1110 iocfc->rsp_cq_ba[i].kva = bfa_mem_dma_virt(rspq_dma);
1111 iocfc->rsp_cq_ba[i].pa = bfa_mem_dma_phys(rspq_dma);
1112 memset(iocfc->rsp_cq_ba[i].kva, 0, per_rspq_sz);
1113 }
1114
1115 /* Claim IOCFC dma memory - for shadow CI/PI */
1116 dm_kva = bfa_mem_dma_virt(iocfc_dma);
1117 dm_pa = bfa_mem_dma_phys(iocfc_dma);
1118
1119 for (i = 0; i < cfg->fwcfg.num_cqs; i++) {
1120 iocfc->req_cq_shadow_ci[i].kva = dm_kva;
1121 iocfc->req_cq_shadow_ci[i].pa = dm_pa;
1122 dm_kva += BFA_CACHELINE_SZ;
1123 dm_pa += BFA_CACHELINE_SZ;
1124
1125 iocfc->rsp_cq_shadow_pi[i].kva = dm_kva;
1126 iocfc->rsp_cq_shadow_pi[i].pa = dm_pa;
1127 dm_kva += BFA_CACHELINE_SZ;
1128 dm_pa += BFA_CACHELINE_SZ;
1129 }
1130
1131 /* Claim IOCFC dma memory - for the config info page */
1132 bfa->iocfc.cfg_info.kva = dm_kva;
1133 bfa->iocfc.cfg_info.pa = dm_pa;
1134 bfa->iocfc.cfginfo = (struct bfi_iocfc_cfg_s *) dm_kva;
1135 dm_kva += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfg_s), BFA_CACHELINE_SZ);
1136 dm_pa += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfg_s), BFA_CACHELINE_SZ);
1137
1138 /* Claim IOCFC dma memory - for the config response */
1139 bfa->iocfc.cfgrsp_dma.kva = dm_kva;
1140 bfa->iocfc.cfgrsp_dma.pa = dm_pa;
1141 bfa->iocfc.cfgrsp = (struct bfi_iocfc_cfgrsp_s *) dm_kva;
1142 dm_kva += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfgrsp_s),
1143 BFA_CACHELINE_SZ);
1144 dm_pa += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfgrsp_s),
1145 BFA_CACHELINE_SZ);
1146
1147 /* Claim IOCFC kva memory */
1148 bfa_ioc_debug_memclaim(&bfa->ioc, bfa_mem_kva_curp(iocfc));
1149 bfa_mem_kva_curp(iocfc) += BFA_DBG_FWTRC_LEN;
1150 }
1151
1152 /*
1153 * Start BFA submodules.
1154 */
1155 static void
1156 bfa_iocfc_start_submod(struct bfa_s *bfa)
1157 {
1158 int i;
1159
1160 bfa->queue_process = BFA_TRUE;
1161 for (i = 0; i < BFI_IOC_MAX_CQS; i++)
1162 bfa_isr_rspq_ack(bfa, i, bfa_rspq_ci(bfa, i));
1163
1164 for (i = 0; hal_mods[i]; i++)
1165 hal_mods[i]->start(bfa);
1166
1167 bfa->iocfc.submod_enabled = BFA_TRUE;
1168 }
1169
1170 /*
1171 * Disable BFA submodules.
1172 */
1173 static void
1174 bfa_iocfc_disable_submod(struct bfa_s *bfa)
1175 {
1176 int i;
1177
1178 if (bfa->iocfc.submod_enabled == BFA_FALSE)
1179 return;
1180
1181 for (i = 0; hal_mods[i]; i++)
1182 hal_mods[i]->iocdisable(bfa);
1183
1184 bfa->iocfc.submod_enabled = BFA_FALSE;
1185 }
1186
1187 static void
1188 bfa_iocfc_init_cb(void *bfa_arg, bfa_boolean_t complete)
1189 {
1190 struct bfa_s *bfa = bfa_arg;
1191
1192 if (complete)
1193 bfa_cb_init(bfa->bfad, bfa->iocfc.op_status);
1194 }
1195
1196 static void
1197 bfa_iocfc_stop_cb(void *bfa_arg, bfa_boolean_t compl)
1198 {
1199 struct bfa_s *bfa = bfa_arg;
1200 struct bfad_s *bfad = bfa->bfad;
1201
1202 if (compl)
1203 complete(&bfad->comp);
1204 }
1205
1206 static void
1207 bfa_iocfc_enable_cb(void *bfa_arg, bfa_boolean_t compl)
1208 {
1209 struct bfa_s *bfa = bfa_arg;
1210 struct bfad_s *bfad = bfa->bfad;
1211
1212 if (compl)
1213 complete(&bfad->enable_comp);
1214 }
1215
1216 static void
1217 bfa_iocfc_disable_cb(void *bfa_arg, bfa_boolean_t compl)
1218 {
1219 struct bfa_s *bfa = bfa_arg;
1220 struct bfad_s *bfad = bfa->bfad;
1221
1222 if (compl)
1223 complete(&bfad->disable_comp);
1224 }
1225
1226 /**
1227 * configure queue registers from firmware response
1228 */
1229 static void
1230 bfa_iocfc_qreg(struct bfa_s *bfa, struct bfi_iocfc_qreg_s *qreg)
1231 {
1232 int i;
1233 struct bfa_iocfc_regs_s *r = &bfa->iocfc.bfa_regs;
1234 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
1235
1236 for (i = 0; i < BFI_IOC_MAX_CQS; i++) {
1237 bfa->iocfc.hw_qid[i] = qreg->hw_qid[i];
1238 r->cpe_q_ci[i] = kva + be32_to_cpu(qreg->cpe_q_ci_off[i]);
1239 r->cpe_q_pi[i] = kva + be32_to_cpu(qreg->cpe_q_pi_off[i]);
1240 r->cpe_q_ctrl[i] = kva + be32_to_cpu(qreg->cpe_qctl_off[i]);
1241 r->rme_q_ci[i] = kva + be32_to_cpu(qreg->rme_q_ci_off[i]);
1242 r->rme_q_pi[i] = kva + be32_to_cpu(qreg->rme_q_pi_off[i]);
1243 r->rme_q_ctrl[i] = kva + be32_to_cpu(qreg->rme_qctl_off[i]);
1244 }
1245 }
1246
1247 static void
1248 bfa_iocfc_res_recfg(struct bfa_s *bfa, struct bfa_iocfc_fwcfg_s *fwcfg)
1249 {
1250 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1251 struct bfi_iocfc_cfg_s *cfg_info = iocfc->cfginfo;
1252
1253 bfa_fcxp_res_recfg(bfa, fwcfg->num_fcxp_reqs);
1254 bfa_uf_res_recfg(bfa, fwcfg->num_uf_bufs);
1255 bfa_rport_res_recfg(bfa, fwcfg->num_rports);
1256 bfa_fcp_res_recfg(bfa, cpu_to_be16(cfg_info->num_ioim_reqs),
1257 fwcfg->num_ioim_reqs);
1258 bfa_tskim_res_recfg(bfa, fwcfg->num_tskim_reqs);
1259 }
1260
1261 /*
1262 * Update BFA configuration from firmware configuration.
1263 */
1264 static void
1265 bfa_iocfc_cfgrsp(struct bfa_s *bfa)
1266 {
1267 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1268 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp;
1269 struct bfa_iocfc_fwcfg_s *fwcfg = &cfgrsp->fwcfg;
1270
1271 fwcfg->num_cqs = fwcfg->num_cqs;
1272 fwcfg->num_ioim_reqs = be16_to_cpu(fwcfg->num_ioim_reqs);
1273 fwcfg->num_fwtio_reqs = be16_to_cpu(fwcfg->num_fwtio_reqs);
1274 fwcfg->num_tskim_reqs = be16_to_cpu(fwcfg->num_tskim_reqs);
1275 fwcfg->num_fcxp_reqs = be16_to_cpu(fwcfg->num_fcxp_reqs);
1276 fwcfg->num_uf_bufs = be16_to_cpu(fwcfg->num_uf_bufs);
1277 fwcfg->num_rports = be16_to_cpu(fwcfg->num_rports);
1278
1279 /*
1280 * configure queue register offsets as learnt from firmware
1281 */
1282 bfa_iocfc_qreg(bfa, &cfgrsp->qreg);
1283
1284 /*
1285 * Re-configure resources as learnt from Firmware
1286 */
1287 bfa_iocfc_res_recfg(bfa, fwcfg);
1288
1289 /*
1290 * Install MSIX queue handlers
1291 */
1292 bfa_msix_queue_install(bfa);
1293
1294 if (bfa->iocfc.cfgrsp->pbc_cfg.pbc_pwwn != 0) {
1295 bfa->ioc.attr->pwwn = bfa->iocfc.cfgrsp->pbc_cfg.pbc_pwwn;
1296 bfa->ioc.attr->nwwn = bfa->iocfc.cfgrsp->pbc_cfg.pbc_nwwn;
1297 bfa_fsm_send_event(iocfc, IOCFC_E_CFG_DONE);
1298 }
1299 }
1300
1301 void
1302 bfa_iocfc_reset_queues(struct bfa_s *bfa)
1303 {
1304 int q;
1305
1306 for (q = 0; q < BFI_IOC_MAX_CQS; q++) {
1307 bfa_reqq_ci(bfa, q) = 0;
1308 bfa_reqq_pi(bfa, q) = 0;
1309 bfa_rspq_ci(bfa, q) = 0;
1310 bfa_rspq_pi(bfa, q) = 0;
1311 }
1312 }
1313
1314 /*
1315 * Process FAA pwwn msg from fw.
1316 */
1317 static void
1318 bfa_iocfc_process_faa_addr(struct bfa_s *bfa, struct bfi_faa_addr_msg_s *msg)
1319 {
1320 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1321 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp;
1322
1323 cfgrsp->pbc_cfg.pbc_pwwn = msg->pwwn;
1324 cfgrsp->pbc_cfg.pbc_nwwn = msg->nwwn;
1325
1326 bfa->ioc.attr->pwwn = msg->pwwn;
1327 bfa->ioc.attr->nwwn = msg->nwwn;
1328 bfa_fsm_send_event(iocfc, IOCFC_E_CFG_DONE);
1329 }
1330
1331 /* Fabric Assigned Address specific functions */
1332
1333 /*
1334 * Check whether IOC is ready before sending command down
1335 */
1336 static bfa_status_t
1337 bfa_faa_validate_request(struct bfa_s *bfa)
1338 {
1339 enum bfa_ioc_type_e ioc_type = bfa_get_type(bfa);
1340 u32 card_type = bfa->ioc.attr->card_type;
1341
1342 if (bfa_ioc_is_operational(&bfa->ioc)) {
1343 if ((ioc_type != BFA_IOC_TYPE_FC) || bfa_mfg_is_mezz(card_type))
1344 return BFA_STATUS_FEATURE_NOT_SUPPORTED;
1345 } else {
1346 return BFA_STATUS_IOC_NON_OP;
1347 }
1348
1349 return BFA_STATUS_OK;
1350 }
1351
1352 bfa_status_t
1353 bfa_faa_query(struct bfa_s *bfa, struct bfa_faa_attr_s *attr,
1354 bfa_cb_iocfc_t cbfn, void *cbarg)
1355 {
1356 struct bfi_faa_query_s faa_attr_req;
1357 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1358 bfa_status_t status;
1359
1360 iocfc->faa_args.faa_attr = attr;
1361 iocfc->faa_args.faa_cb.faa_cbfn = cbfn;
1362 iocfc->faa_args.faa_cb.faa_cbarg = cbarg;
1363
1364 status = bfa_faa_validate_request(bfa);
1365 if (status != BFA_STATUS_OK)
1366 return status;
1367
1368 if (iocfc->faa_args.busy == BFA_TRUE)
1369 return BFA_STATUS_DEVBUSY;
1370
1371 iocfc->faa_args.busy = BFA_TRUE;
1372 memset(&faa_attr_req, 0, sizeof(struct bfi_faa_query_s));
1373 bfi_h2i_set(faa_attr_req.mh, BFI_MC_IOCFC,
1374 BFI_IOCFC_H2I_FAA_QUERY_REQ, bfa_fn_lpu(bfa));
1375
1376 bfa_ioc_mbox_send(&bfa->ioc, &faa_attr_req,
1377 sizeof(struct bfi_faa_query_s));
1378
1379 return BFA_STATUS_OK;
1380 }
1381
1382 /*
1383 * FAA query response
1384 */
1385 static void
1386 bfa_faa_query_reply(struct bfa_iocfc_s *iocfc,
1387 bfi_faa_query_rsp_t *rsp)
1388 {
1389 void *cbarg = iocfc->faa_args.faa_cb.faa_cbarg;
1390
1391 if (iocfc->faa_args.faa_attr) {
1392 iocfc->faa_args.faa_attr->faa = rsp->faa;
1393 iocfc->faa_args.faa_attr->faa_state = rsp->faa_status;
1394 iocfc->faa_args.faa_attr->pwwn_source = rsp->addr_source;
1395 }
1396
1397 WARN_ON(!iocfc->faa_args.faa_cb.faa_cbfn);
1398
1399 iocfc->faa_args.faa_cb.faa_cbfn(cbarg, BFA_STATUS_OK);
1400 iocfc->faa_args.busy = BFA_FALSE;
1401 }
1402
1403 /*
1404 * IOC enable request is complete
1405 */
1406 static void
1407 bfa_iocfc_enable_cbfn(void *bfa_arg, enum bfa_status status)
1408 {
1409 struct bfa_s *bfa = bfa_arg;
1410
1411 if (status == BFA_STATUS_OK)
1412 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_ENABLED);
1413 else
1414 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_FAILED);
1415 }
1416
1417 /*
1418 * IOC disable request is complete
1419 */
1420 static void
1421 bfa_iocfc_disable_cbfn(void *bfa_arg)
1422 {
1423 struct bfa_s *bfa = bfa_arg;
1424
1425 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_DISABLED);
1426 }
1427
1428 /*
1429 * Notify sub-modules of hardware failure.
1430 */
1431 static void
1432 bfa_iocfc_hbfail_cbfn(void *bfa_arg)
1433 {
1434 struct bfa_s *bfa = bfa_arg;
1435
1436 bfa->queue_process = BFA_FALSE;
1437 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_FAILED);
1438 }
1439
1440 /*
1441 * Actions on chip-reset completion.
1442 */
1443 static void
1444 bfa_iocfc_reset_cbfn(void *bfa_arg)
1445 {
1446 struct bfa_s *bfa = bfa_arg;
1447
1448 bfa_iocfc_reset_queues(bfa);
1449 bfa_isr_enable(bfa);
1450 }
1451
1452 /*
1453 * Query IOC memory requirement information.
1454 */
1455 void
1456 bfa_iocfc_meminfo(struct bfa_iocfc_cfg_s *cfg, struct bfa_meminfo_s *meminfo,
1457 struct bfa_s *bfa)
1458 {
1459 int q, per_reqq_sz, per_rspq_sz;
1460 struct bfa_mem_dma_s *ioc_dma = BFA_MEM_IOC_DMA(bfa);
1461 struct bfa_mem_dma_s *iocfc_dma = BFA_MEM_IOCFC_DMA(bfa);
1462 struct bfa_mem_kva_s *iocfc_kva = BFA_MEM_IOCFC_KVA(bfa);
1463 u32 dm_len = 0;
1464
1465 /* dma memory setup for IOC */
1466 bfa_mem_dma_setup(meminfo, ioc_dma,
1467 BFA_ROUNDUP(sizeof(struct bfi_ioc_attr_s), BFA_DMA_ALIGN_SZ));
1468
1469 /* dma memory setup for REQ/RSP queues */
1470 per_reqq_sz = BFA_ROUNDUP((cfg->drvcfg.num_reqq_elems * BFI_LMSG_SZ),
1471 BFA_DMA_ALIGN_SZ);
1472 per_rspq_sz = BFA_ROUNDUP((cfg->drvcfg.num_rspq_elems * BFI_LMSG_SZ),
1473 BFA_DMA_ALIGN_SZ);
1474
1475 for (q = 0; q < cfg->fwcfg.num_cqs; q++) {
1476 bfa_mem_dma_setup(meminfo, BFA_MEM_REQQ_DMA(bfa, q),
1477 per_reqq_sz);
1478 bfa_mem_dma_setup(meminfo, BFA_MEM_RSPQ_DMA(bfa, q),
1479 per_rspq_sz);
1480 }
1481
1482 /* IOCFC dma memory - calculate Shadow CI/PI size */
1483 for (q = 0; q < cfg->fwcfg.num_cqs; q++)
1484 dm_len += (2 * BFA_CACHELINE_SZ);
1485
1486 /* IOCFC dma memory - calculate config info / rsp size */
1487 dm_len += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfg_s), BFA_CACHELINE_SZ);
1488 dm_len += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfgrsp_s),
1489 BFA_CACHELINE_SZ);
1490
1491 /* dma memory setup for IOCFC */
1492 bfa_mem_dma_setup(meminfo, iocfc_dma, dm_len);
1493
1494 /* kva memory setup for IOCFC */
1495 bfa_mem_kva_setup(meminfo, iocfc_kva, BFA_DBG_FWTRC_LEN);
1496 }
1497
1498 /*
1499 * Query IOC memory requirement information.
1500 */
1501 void
1502 bfa_iocfc_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg,
1503 struct bfa_pcidev_s *pcidev)
1504 {
1505 int i;
1506 struct bfa_ioc_s *ioc = &bfa->ioc;
1507
1508 bfa_iocfc_cbfn.enable_cbfn = bfa_iocfc_enable_cbfn;
1509 bfa_iocfc_cbfn.disable_cbfn = bfa_iocfc_disable_cbfn;
1510 bfa_iocfc_cbfn.hbfail_cbfn = bfa_iocfc_hbfail_cbfn;
1511 bfa_iocfc_cbfn.reset_cbfn = bfa_iocfc_reset_cbfn;
1512
1513 ioc->trcmod = bfa->trcmod;
1514 bfa_ioc_attach(&bfa->ioc, bfa, &bfa_iocfc_cbfn, &bfa->timer_mod);
1515
1516 bfa_ioc_pci_init(&bfa->ioc, pcidev, BFI_PCIFN_CLASS_FC);
1517 bfa_ioc_mbox_register(&bfa->ioc, bfa_mbox_isrs);
1518
1519 bfa_iocfc_init_mem(bfa, bfad, cfg, pcidev);
1520 bfa_iocfc_mem_claim(bfa, cfg);
1521 INIT_LIST_HEAD(&bfa->timer_mod.timer_q);
1522
1523 INIT_LIST_HEAD(&bfa->comp_q);
1524 for (i = 0; i < BFI_IOC_MAX_CQS; i++)
1525 INIT_LIST_HEAD(&bfa->reqq_waitq[i]);
1526
1527 bfa->iocfc.cb_reqd = BFA_FALSE;
1528 bfa->iocfc.op_status = BFA_STATUS_OK;
1529 bfa->iocfc.submod_enabled = BFA_FALSE;
1530
1531 bfa_fsm_set_state(&bfa->iocfc, bfa_iocfc_sm_stopped);
1532 }
1533
1534 /*
1535 * Query IOC memory requirement information.
1536 */
1537 void
1538 bfa_iocfc_init(struct bfa_s *bfa)
1539 {
1540 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_INIT);
1541 }
1542
1543 /*
1544 * IOC start called from bfa_start(). Called to start IOC operations
1545 * at driver instantiation for this instance.
1546 */
1547 void
1548 bfa_iocfc_start(struct bfa_s *bfa)
1549 {
1550 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_START);
1551 }
1552
1553 /*
1554 * IOC stop called from bfa_stop(). Called only when driver is unloaded
1555 * for this instance.
1556 */
1557 void
1558 bfa_iocfc_stop(struct bfa_s *bfa)
1559 {
1560 bfa->queue_process = BFA_FALSE;
1561 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_STOP);
1562 }
1563
1564 void
1565 bfa_iocfc_isr(void *bfaarg, struct bfi_mbmsg_s *m)
1566 {
1567 struct bfa_s *bfa = bfaarg;
1568 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1569 union bfi_iocfc_i2h_msg_u *msg;
1570
1571 msg = (union bfi_iocfc_i2h_msg_u *) m;
1572 bfa_trc(bfa, msg->mh.msg_id);
1573
1574 switch (msg->mh.msg_id) {
1575 case BFI_IOCFC_I2H_CFG_REPLY:
1576 bfa_iocfc_cfgrsp(bfa);
1577 break;
1578 case BFI_IOCFC_I2H_UPDATEQ_RSP:
1579 iocfc->updateq_cbfn(iocfc->updateq_cbarg, BFA_STATUS_OK);
1580 break;
1581 case BFI_IOCFC_I2H_ADDR_MSG:
1582 bfa_iocfc_process_faa_addr(bfa,
1583 (struct bfi_faa_addr_msg_s *)msg);
1584 break;
1585 case BFI_IOCFC_I2H_FAA_QUERY_RSP:
1586 bfa_faa_query_reply(iocfc, (bfi_faa_query_rsp_t *)msg);
1587 break;
1588 default:
1589 WARN_ON(1);
1590 }
1591 }
1592
1593 void
1594 bfa_iocfc_get_attr(struct bfa_s *bfa, struct bfa_iocfc_attr_s *attr)
1595 {
1596 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1597
1598 attr->intr_attr.coalesce = iocfc->cfginfo->intr_attr.coalesce;
1599
1600 attr->intr_attr.delay = iocfc->cfginfo->intr_attr.delay ?
1601 be16_to_cpu(iocfc->cfginfo->intr_attr.delay) :
1602 be16_to_cpu(iocfc->cfgrsp->intr_attr.delay);
1603
1604 attr->intr_attr.latency = iocfc->cfginfo->intr_attr.latency ?
1605 be16_to_cpu(iocfc->cfginfo->intr_attr.latency) :
1606 be16_to_cpu(iocfc->cfgrsp->intr_attr.latency);
1607
1608 attr->config = iocfc->cfg;
1609 }
1610
1611 bfa_status_t
1612 bfa_iocfc_israttr_set(struct bfa_s *bfa, struct bfa_iocfc_intr_attr_s *attr)
1613 {
1614 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1615 struct bfi_iocfc_set_intr_req_s *m;
1616
1617 iocfc->cfginfo->intr_attr.coalesce = attr->coalesce;
1618 iocfc->cfginfo->intr_attr.delay = cpu_to_be16(attr->delay);
1619 iocfc->cfginfo->intr_attr.latency = cpu_to_be16(attr->latency);
1620
1621 if (!bfa_iocfc_is_operational(bfa))
1622 return BFA_STATUS_OK;
1623
1624 m = bfa_reqq_next(bfa, BFA_REQQ_IOC);
1625 if (!m)
1626 return BFA_STATUS_DEVBUSY;
1627
1628 bfi_h2i_set(m->mh, BFI_MC_IOCFC, BFI_IOCFC_H2I_SET_INTR_REQ,
1629 bfa_fn_lpu(bfa));
1630 m->coalesce = iocfc->cfginfo->intr_attr.coalesce;
1631 m->delay = iocfc->cfginfo->intr_attr.delay;
1632 m->latency = iocfc->cfginfo->intr_attr.latency;
1633
1634 bfa_trc(bfa, attr->delay);
1635 bfa_trc(bfa, attr->latency);
1636
1637 bfa_reqq_produce(bfa, BFA_REQQ_IOC, m->mh);
1638 return BFA_STATUS_OK;
1639 }
1640
1641 void
1642 bfa_iocfc_set_snsbase(struct bfa_s *bfa, int seg_no, u64 snsbase_pa)
1643 {
1644 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1645
1646 iocfc->cfginfo->sense_buf_len = (BFI_IOIM_SNSLEN - 1);
1647 bfa_dma_be_addr_set(iocfc->cfginfo->ioim_snsbase[seg_no], snsbase_pa);
1648 }
1649 /*
1650 * Enable IOC after it is disabled.
1651 */
1652 void
1653 bfa_iocfc_enable(struct bfa_s *bfa)
1654 {
1655 bfa_plog_str(bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_MISC, 0,
1656 "IOC Enable");
1657 bfa->iocfc.cb_reqd = BFA_TRUE;
1658 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_ENABLE);
1659 }
1660
1661 void
1662 bfa_iocfc_disable(struct bfa_s *bfa)
1663 {
1664 bfa_plog_str(bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_MISC, 0,
1665 "IOC Disable");
1666
1667 bfa->queue_process = BFA_FALSE;
1668 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_DISABLE);
1669 }
1670
1671 bfa_boolean_t
1672 bfa_iocfc_is_operational(struct bfa_s *bfa)
1673 {
1674 return bfa_ioc_is_operational(&bfa->ioc) &&
1675 bfa_fsm_cmp_state(&bfa->iocfc, bfa_iocfc_sm_operational);
1676 }
1677
1678 /*
1679 * Return boot target port wwns -- read from boot information in flash.
1680 */
1681 void
1682 bfa_iocfc_get_bootwwns(struct bfa_s *bfa, u8 *nwwns, wwn_t *wwns)
1683 {
1684 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1685 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp;
1686 int i;
1687
1688 if (cfgrsp->pbc_cfg.boot_enabled && cfgrsp->pbc_cfg.nbluns) {
1689 bfa_trc(bfa, cfgrsp->pbc_cfg.nbluns);
1690 *nwwns = cfgrsp->pbc_cfg.nbluns;
1691 for (i = 0; i < cfgrsp->pbc_cfg.nbluns; i++)
1692 wwns[i] = cfgrsp->pbc_cfg.blun[i].tgt_pwwn;
1693
1694 return;
1695 }
1696
1697 *nwwns = cfgrsp->bootwwns.nwwns;
1698 memcpy(wwns, cfgrsp->bootwwns.wwn, sizeof(cfgrsp->bootwwns.wwn));
1699 }
1700
1701 int
1702 bfa_iocfc_get_pbc_vports(struct bfa_s *bfa, struct bfi_pbc_vport_s *pbc_vport)
1703 {
1704 struct bfa_iocfc_s *iocfc = &bfa->iocfc;
1705 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp;
1706
1707 memcpy(pbc_vport, cfgrsp->pbc_cfg.vport, sizeof(cfgrsp->pbc_cfg.vport));
1708 return cfgrsp->pbc_cfg.nvports;
1709 }
1710
1711
1712 /*
1713 * Use this function query the memory requirement of the BFA library.
1714 * This function needs to be called before bfa_attach() to get the
1715 * memory required of the BFA layer for a given driver configuration.
1716 *
1717 * This call will fail, if the cap is out of range compared to pre-defined
1718 * values within the BFA library
1719 *
1720 * @param[in] cfg - pointer to bfa_ioc_cfg_t. Driver layer should indicate
1721 * its configuration in this structure.
1722 * The default values for struct bfa_iocfc_cfg_s can be
1723 * fetched using bfa_cfg_get_default() API.
1724 *
1725 * If cap's boundary check fails, the library will use
1726 * the default bfa_cap_t values (and log a warning msg).
1727 *
1728 * @param[out] meminfo - pointer to bfa_meminfo_t. This content
1729 * indicates the memory type (see bfa_mem_type_t) and
1730 * amount of memory required.
1731 *
1732 * Driver should allocate the memory, populate the
1733 * starting address for each block and provide the same
1734 * structure as input parameter to bfa_attach() call.
1735 *
1736 * @param[in] bfa - pointer to the bfa structure, used while fetching the
1737 * dma, kva memory information of the bfa sub-modules.
1738 *
1739 * @return void
1740 *
1741 * Special Considerations: @note
1742 */
1743 void
1744 bfa_cfg_get_meminfo(struct bfa_iocfc_cfg_s *cfg, struct bfa_meminfo_s *meminfo,
1745 struct bfa_s *bfa)
1746 {
1747 int i;
1748 struct bfa_mem_dma_s *port_dma = BFA_MEM_PORT_DMA(bfa);
1749 struct bfa_mem_dma_s *ablk_dma = BFA_MEM_ABLK_DMA(bfa);
1750 struct bfa_mem_dma_s *cee_dma = BFA_MEM_CEE_DMA(bfa);
1751 struct bfa_mem_dma_s *sfp_dma = BFA_MEM_SFP_DMA(bfa);
1752 struct bfa_mem_dma_s *flash_dma = BFA_MEM_FLASH_DMA(bfa);
1753 struct bfa_mem_dma_s *diag_dma = BFA_MEM_DIAG_DMA(bfa);
1754 struct bfa_mem_dma_s *phy_dma = BFA_MEM_PHY_DMA(bfa);
1755
1756 WARN_ON((cfg == NULL) || (meminfo == NULL));
1757
1758 memset((void *)meminfo, 0, sizeof(struct bfa_meminfo_s));
1759
1760 /* Initialize the DMA & KVA meminfo queues */
1761 INIT_LIST_HEAD(&meminfo->dma_info.qe);
1762 INIT_LIST_HEAD(&meminfo->kva_info.qe);
1763
1764 bfa_iocfc_meminfo(cfg, meminfo, bfa);
1765
1766 for (i = 0; hal_mods[i]; i++)
1767 hal_mods[i]->meminfo(cfg, meminfo, bfa);
1768
1769 /* dma info setup */
1770 bfa_mem_dma_setup(meminfo, port_dma, bfa_port_meminfo());
1771 bfa_mem_dma_setup(meminfo, ablk_dma, bfa_ablk_meminfo());
1772 bfa_mem_dma_setup(meminfo, cee_dma, bfa_cee_meminfo());
1773 bfa_mem_dma_setup(meminfo, sfp_dma, bfa_sfp_meminfo());
1774 bfa_mem_dma_setup(meminfo, flash_dma,
1775 bfa_flash_meminfo(cfg->drvcfg.min_cfg));
1776 bfa_mem_dma_setup(meminfo, diag_dma, bfa_diag_meminfo());
1777 bfa_mem_dma_setup(meminfo, phy_dma,
1778 bfa_phy_meminfo(cfg->drvcfg.min_cfg));
1779 }
1780
1781 /*
1782 * Use this function to do attach the driver instance with the BFA
1783 * library. This function will not trigger any HW initialization
1784 * process (which will be done in bfa_init() call)
1785 *
1786 * This call will fail, if the cap is out of range compared to
1787 * pre-defined values within the BFA library
1788 *
1789 * @param[out] bfa Pointer to bfa_t.
1790 * @param[in] bfad Opaque handle back to the driver's IOC structure
1791 * @param[in] cfg Pointer to bfa_ioc_cfg_t. Should be same structure
1792 * that was used in bfa_cfg_get_meminfo().
1793 * @param[in] meminfo Pointer to bfa_meminfo_t. The driver should
1794 * use the bfa_cfg_get_meminfo() call to
1795 * find the memory blocks required, allocate the
1796 * required memory and provide the starting addresses.
1797 * @param[in] pcidev pointer to struct bfa_pcidev_s
1798 *
1799 * @return
1800 * void
1801 *
1802 * Special Considerations:
1803 *
1804 * @note
1805 *
1806 */
1807 void
1808 bfa_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg,
1809 struct bfa_meminfo_s *meminfo, struct bfa_pcidev_s *pcidev)
1810 {
1811 int i;
1812 struct bfa_mem_dma_s *dma_info, *dma_elem;
1813 struct bfa_mem_kva_s *kva_info, *kva_elem;
1814 struct list_head *dm_qe, *km_qe;
1815
1816 bfa->fcs = BFA_FALSE;
1817
1818 WARN_ON((cfg == NULL) || (meminfo == NULL));
1819
1820 /* Initialize memory pointers for iterative allocation */
1821 dma_info = &meminfo->dma_info;
1822 dma_info->kva_curp = dma_info->kva;
1823 dma_info->dma_curp = dma_info->dma;
1824
1825 kva_info = &meminfo->kva_info;
1826 kva_info->kva_curp = kva_info->kva;
1827
1828 list_for_each(dm_qe, &dma_info->qe) {
1829 dma_elem = (struct bfa_mem_dma_s *) dm_qe;
1830 dma_elem->kva_curp = dma_elem->kva;
1831 dma_elem->dma_curp = dma_elem->dma;
1832 }
1833
1834 list_for_each(km_qe, &kva_info->qe) {
1835 kva_elem = (struct bfa_mem_kva_s *) km_qe;
1836 kva_elem->kva_curp = kva_elem->kva;
1837 }
1838
1839 bfa_iocfc_attach(bfa, bfad, cfg, pcidev);
1840
1841 for (i = 0; hal_mods[i]; i++)
1842 hal_mods[i]->attach(bfa, bfad, cfg, pcidev);
1843
1844 bfa_com_port_attach(bfa);
1845 bfa_com_ablk_attach(bfa);
1846 bfa_com_cee_attach(bfa);
1847 bfa_com_sfp_attach(bfa);
1848 bfa_com_flash_attach(bfa, cfg->drvcfg.min_cfg);
1849 bfa_com_diag_attach(bfa);
1850 bfa_com_phy_attach(bfa, cfg->drvcfg.min_cfg);
1851 }
1852
1853 /*
1854 * Use this function to delete a BFA IOC. IOC should be stopped (by
1855 * calling bfa_stop()) before this function call.
1856 *
1857 * @param[in] bfa - pointer to bfa_t.
1858 *
1859 * @return
1860 * void
1861 *
1862 * Special Considerations:
1863 *
1864 * @note
1865 */
1866 void
1867 bfa_detach(struct bfa_s *bfa)
1868 {
1869 int i;
1870
1871 for (i = 0; hal_mods[i]; i++)
1872 hal_mods[i]->detach(bfa);
1873 bfa_ioc_detach(&bfa->ioc);
1874 }
1875
1876 void
1877 bfa_comp_deq(struct bfa_s *bfa, struct list_head *comp_q)
1878 {
1879 INIT_LIST_HEAD(comp_q);
1880 list_splice_tail_init(&bfa->comp_q, comp_q);
1881 }
1882
1883 void
1884 bfa_comp_process(struct bfa_s *bfa, struct list_head *comp_q)
1885 {
1886 struct list_head *qe;
1887 struct list_head *qen;
1888 struct bfa_cb_qe_s *hcb_qe;
1889 bfa_cb_cbfn_status_t cbfn;
1890
1891 list_for_each_safe(qe, qen, comp_q) {
1892 hcb_qe = (struct bfa_cb_qe_s *) qe;
1893 if (hcb_qe->pre_rmv) {
1894 /* qe is invalid after return, dequeue before cbfn() */
1895 list_del(qe);
1896 cbfn = (bfa_cb_cbfn_status_t)(hcb_qe->cbfn);
1897 cbfn(hcb_qe->cbarg, hcb_qe->fw_status);
1898 } else
1899 hcb_qe->cbfn(hcb_qe->cbarg, BFA_TRUE);
1900 }
1901 }
1902
1903 void
1904 bfa_comp_free(struct bfa_s *bfa, struct list_head *comp_q)
1905 {
1906 struct list_head *qe;
1907 struct bfa_cb_qe_s *hcb_qe;
1908
1909 while (!list_empty(comp_q)) {
1910 bfa_q_deq(comp_q, &qe);
1911 hcb_qe = (struct bfa_cb_qe_s *) qe;
1912 WARN_ON(hcb_qe->pre_rmv);
1913 hcb_qe->cbfn(hcb_qe->cbarg, BFA_FALSE);
1914 }
1915 }
1916
1917 /*
1918 * Return the list of PCI vendor/device id lists supported by this
1919 * BFA instance.
1920 */
1921 void
1922 bfa_get_pciids(struct bfa_pciid_s **pciids, int *npciids)
1923 {
1924 static struct bfa_pciid_s __pciids[] = {
1925 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_FC_8G2P},
1926 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_FC_8G1P},
1927 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_CT},
1928 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_CT_FC},
1929 };
1930
1931 *npciids = sizeof(__pciids) / sizeof(__pciids[0]);
1932 *pciids = __pciids;
1933 }
1934
1935 /*
1936 * Use this function query the default struct bfa_iocfc_cfg_s value (compiled
1937 * into BFA layer). The OS driver can then turn back and overwrite entries that
1938 * have been configured by the user.
1939 *
1940 * @param[in] cfg - pointer to bfa_ioc_cfg_t
1941 *
1942 * @return
1943 * void
1944 *
1945 * Special Considerations:
1946 * note
1947 */
1948 void
1949 bfa_cfg_get_default(struct bfa_iocfc_cfg_s *cfg)
1950 {
1951 cfg->fwcfg.num_fabrics = DEF_CFG_NUM_FABRICS;
1952 cfg->fwcfg.num_lports = DEF_CFG_NUM_LPORTS;
1953 cfg->fwcfg.num_rports = DEF_CFG_NUM_RPORTS;
1954 cfg->fwcfg.num_ioim_reqs = DEF_CFG_NUM_IOIM_REQS;
1955 cfg->fwcfg.num_tskim_reqs = DEF_CFG_NUM_TSKIM_REQS;
1956 cfg->fwcfg.num_fcxp_reqs = DEF_CFG_NUM_FCXP_REQS;
1957 cfg->fwcfg.num_uf_bufs = DEF_CFG_NUM_UF_BUFS;
1958 cfg->fwcfg.num_cqs = DEF_CFG_NUM_CQS;
1959 cfg->fwcfg.num_fwtio_reqs = 0;
1960
1961 cfg->drvcfg.num_reqq_elems = DEF_CFG_NUM_REQQ_ELEMS;
1962 cfg->drvcfg.num_rspq_elems = DEF_CFG_NUM_RSPQ_ELEMS;
1963 cfg->drvcfg.num_sgpgs = DEF_CFG_NUM_SGPGS;
1964 cfg->drvcfg.num_sboot_tgts = DEF_CFG_NUM_SBOOT_TGTS;
1965 cfg->drvcfg.num_sboot_luns = DEF_CFG_NUM_SBOOT_LUNS;
1966 cfg->drvcfg.path_tov = BFA_FCPIM_PATHTOV_DEF;
1967 cfg->drvcfg.ioc_recover = BFA_FALSE;
1968 cfg->drvcfg.delay_comp = BFA_FALSE;
1969
1970 }
1971
1972 void
1973 bfa_cfg_get_min(struct bfa_iocfc_cfg_s *cfg)
1974 {
1975 bfa_cfg_get_default(cfg);
1976 cfg->fwcfg.num_ioim_reqs = BFA_IOIM_MIN;
1977 cfg->fwcfg.num_tskim_reqs = BFA_TSKIM_MIN;
1978 cfg->fwcfg.num_fcxp_reqs = BFA_FCXP_MIN;
1979 cfg->fwcfg.num_uf_bufs = BFA_UF_MIN;
1980 cfg->fwcfg.num_rports = BFA_RPORT_MIN;
1981 cfg->fwcfg.num_fwtio_reqs = 0;
1982
1983 cfg->drvcfg.num_sgpgs = BFA_SGPG_MIN;
1984 cfg->drvcfg.num_reqq_elems = BFA_REQQ_NELEMS_MIN;
1985 cfg->drvcfg.num_rspq_elems = BFA_RSPQ_NELEMS_MIN;
1986 cfg->drvcfg.min_cfg = BFA_TRUE;
1987 }
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