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[media] dvb_frontend: tuner_ops.release returns void
[linux-2.6/btrfs-unstable.git] / drivers / tty / synclinkmp.c
blobdec156586de1bdfcf9ed1439523a884267ff02df
1 /*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/seq_file.h>
54 #include <linux/slab.h>
55 #include <linux/netdevice.h>
56 #include <linux/vmalloc.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/ioctl.h>
60
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
70
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
73 #else
74 #define SYNCLINK_GENERIC_HDLC 0
75 #endif
76
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82 #include <asm/uaccess.h>
83
84 static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
98 };
99
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
107
108 #define BUFFERLISTSIZE 4096
109
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
112 {
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
116 u8 pad1;
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
119 u8 pad2;
120 } SCADESC, *PSCADESC;
121
122 typedef struct _SCADESC_EX
123 {
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
128
129 /* The queue of BH actions to be performed */
130
131 #define BH_RECEIVE 1
132 #define BH_TRANSMIT 2
133 #define BH_STATUS 4
134
135 #define IO_PIN_SHUTDOWN_LIMIT 100
136
137 struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146 };
147
148 /*
149 * Device instance data structure
150 */
151 typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
153 int magic;
154 struct tty_port port;
155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
158
159 struct mgsl_icount icount;
160
161 int timeout;
162 int x_char; /* xon/xoff character */
163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
177
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
180
181 u32 max_frame_size; /* as set by device config */
182
183 u32 pending_bh;
184
185 bool bh_running; /* Protection from multiple */
186 int isr_overflow;
187 bool bh_requested;
188
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
192 int ri_chkcount;
193
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
210 bool rx_enabled;
211 bool rx_overflow;
212
213 bool tx_enabled;
214 bool tx_active;
215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25]; /* device instance name */
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
232
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
235 bool irq_requested; /* true if IRQ requested */
236
237 MGSL_PARAMS params; /* communications parameters */
238
239 unsigned char serial_signals; /* current serial signal states */
240
241 bool irq_occurred; /* for diagnostics use */
242 unsigned int init_error; /* Initialization startup error */
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
250 u32 phys_sca_base;
251 u32 sca_offset;
252 bool sca_base_requested;
253
254 unsigned char* lcr_base; /* local config registers (PCI only) */
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
262 bool sca_statctrl_requested;
263
264 u32 misc_ctrl_value;
265 char *flag_buf;
266 bool drop_rts_on_tx_done;
267
268 struct _input_signal_events input_signal_events;
269
270 /* SPPP/Cisco HDLC device parts */
271 int netcount;
272 spinlock_t netlock;
273
274 #if SYNCLINK_GENERIC_HDLC
275 struct net_device *netdev;
276 #endif
277
278 } SLMP_INFO;
279
280 #define MGSL_MAGIC 0x5401
281
282 /*
283 * define serial signal status change macros
284 */
285 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
286 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
287 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
288 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
289
290 /* Common Register macros */
291 #define LPR 0x00
292 #define PABR0 0x02
293 #define PABR1 0x03
294 #define WCRL 0x04
295 #define WCRM 0x05
296 #define WCRH 0x06
297 #define DPCR 0x08
298 #define DMER 0x09
299 #define ISR0 0x10
300 #define ISR1 0x11
301 #define ISR2 0x12
302 #define IER0 0x14
303 #define IER1 0x15
304 #define IER2 0x16
305 #define ITCR 0x18
306 #define INTVR 0x1a
307 #define IMVR 0x1c
308
309 /* MSCI Register macros */
310 #define TRB 0x20
311 #define TRBL 0x20
312 #define TRBH 0x21
313 #define SR0 0x22
314 #define SR1 0x23
315 #define SR2 0x24
316 #define SR3 0x25
317 #define FST 0x26
318 #define IE0 0x28
319 #define IE1 0x29
320 #define IE2 0x2a
321 #define FIE 0x2b
322 #define CMD 0x2c
323 #define MD0 0x2e
324 #define MD1 0x2f
325 #define MD2 0x30
326 #define CTL 0x31
327 #define SA0 0x32
328 #define SA1 0x33
329 #define IDL 0x34
330 #define TMC 0x35
331 #define RXS 0x36
332 #define TXS 0x37
333 #define TRC0 0x38
334 #define TRC1 0x39
335 #define RRC 0x3a
336 #define CST0 0x3c
337 #define CST1 0x3d
338
339 /* Timer Register Macros */
340 #define TCNT 0x60
341 #define TCNTL 0x60
342 #define TCNTH 0x61
343 #define TCONR 0x62
344 #define TCONRL 0x62
345 #define TCONRH 0x63
346 #define TMCS 0x64
347 #define TEPR 0x65
348
349 /* DMA Controller Register macros */
350 #define DARL 0x80
351 #define DARH 0x81
352 #define DARB 0x82
353 #define BAR 0x80
354 #define BARL 0x80
355 #define BARH 0x81
356 #define BARB 0x82
357 #define SAR 0x84
358 #define SARL 0x84
359 #define SARH 0x85
360 #define SARB 0x86
361 #define CPB 0x86
362 #define CDA 0x88
363 #define CDAL 0x88
364 #define CDAH 0x89
365 #define EDA 0x8a
366 #define EDAL 0x8a
367 #define EDAH 0x8b
368 #define BFL 0x8c
369 #define BFLL 0x8c
370 #define BFLH 0x8d
371 #define BCR 0x8e
372 #define BCRL 0x8e
373 #define BCRH 0x8f
374 #define DSR 0x90
375 #define DMR 0x91
376 #define FCT 0x93
377 #define DIR 0x94
378 #define DCMD 0x95
379
380 /* combine with timer or DMA register address */
381 #define TIMER0 0x00
382 #define TIMER1 0x08
383 #define TIMER2 0x10
384 #define TIMER3 0x18
385 #define RXDMA 0x00
386 #define TXDMA 0x20
387
388 /* SCA Command Codes */
389 #define NOOP 0x00
390 #define TXRESET 0x01
391 #define TXENABLE 0x02
392 #define TXDISABLE 0x03
393 #define TXCRCINIT 0x04
394 #define TXCRCEXCL 0x05
395 #define TXEOM 0x06
396 #define TXABORT 0x07
397 #define MPON 0x08
398 #define TXBUFCLR 0x09
399 #define RXRESET 0x11
400 #define RXENABLE 0x12
401 #define RXDISABLE 0x13
402 #define RXCRCINIT 0x14
403 #define RXREJECT 0x15
404 #define SEARCHMP 0x16
405 #define RXCRCEXCL 0x17
406 #define RXCRCCALC 0x18
407 #define CHRESET 0x21
408 #define HUNT 0x31
409
410 /* DMA command codes */
411 #define SWABORT 0x01
412 #define FEICLEAR 0x02
413
414 /* IE0 */
415 #define TXINTE BIT7
416 #define RXINTE BIT6
417 #define TXRDYE BIT1
418 #define RXRDYE BIT0
419
420 /* IE1 & SR1 */
421 #define UDRN BIT7
422 #define IDLE BIT6
423 #define SYNCD BIT4
424 #define FLGD BIT4
425 #define CCTS BIT3
426 #define CDCD BIT2
427 #define BRKD BIT1
428 #define ABTD BIT1
429 #define GAPD BIT1
430 #define BRKE BIT0
431 #define IDLD BIT0
432
433 /* IE2 & SR2 */
434 #define EOM BIT7
435 #define PMP BIT6
436 #define SHRT BIT6
437 #define PE BIT5
438 #define ABT BIT5
439 #define FRME BIT4
440 #define RBIT BIT4
441 #define OVRN BIT3
442 #define CRCE BIT2
443
444
445 /*
446 * Global linked list of SyncLink devices
447 */
448 static SLMP_INFO *synclinkmp_device_list = NULL;
449 static int synclinkmp_adapter_count = -1;
450 static int synclinkmp_device_count = 0;
451
452 /*
453 * Set this param to non-zero to load eax with the
454 * .text section address and breakpoint on module load.
455 * This is useful for use with gdb and add-symbol-file command.
456 */
457 static bool break_on_load = 0;
458
459 /*
460 * Driver major number, defaults to zero to get auto
461 * assigned major number. May be forced as module parameter.
462 */
463 static int ttymajor = 0;
464
465 /*
466 * Array of user specified options for ISA adapters.
467 */
468 static int debug_level = 0;
469 static int maxframe[MAX_DEVICES] = {0,};
470
471 module_param(break_on_load, bool, 0);
472 module_param(ttymajor, int, 0);
473 module_param(debug_level, int, 0);
474 module_param_array(maxframe, int, NULL, 0);
475
476 static char *driver_name = "SyncLink MultiPort driver";
477 static char *driver_version = "$Revision: 4.38 $";
478
479 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
480 static void synclinkmp_remove_one(struct pci_dev *dev);
481
482 static struct pci_device_id synclinkmp_pci_tbl[] = {
483 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
484 { 0, }, /* terminate list */
485 };
486 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
487
488 MODULE_LICENSE("GPL");
489
490 static struct pci_driver synclinkmp_pci_driver = {
491 .name = "synclinkmp",
492 .id_table = synclinkmp_pci_tbl,
493 .probe = synclinkmp_init_one,
494 .remove = synclinkmp_remove_one,
495 };
496
497
498 static struct tty_driver *serial_driver;
499
500 /* number of characters left in xmit buffer before we ask for more */
501 #define WAKEUP_CHARS 256
502
503
504 /* tty callbacks */
505
506 static int open(struct tty_struct *tty, struct file * filp);
507 static void close(struct tty_struct *tty, struct file * filp);
508 static void hangup(struct tty_struct *tty);
509 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
510
511 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
512 static int put_char(struct tty_struct *tty, unsigned char ch);
513 static void send_xchar(struct tty_struct *tty, char ch);
514 static void wait_until_sent(struct tty_struct *tty, int timeout);
515 static int write_room(struct tty_struct *tty);
516 static void flush_chars(struct tty_struct *tty);
517 static void flush_buffer(struct tty_struct *tty);
518 static void tx_hold(struct tty_struct *tty);
519 static void tx_release(struct tty_struct *tty);
520
521 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
522 static int chars_in_buffer(struct tty_struct *tty);
523 static void throttle(struct tty_struct * tty);
524 static void unthrottle(struct tty_struct * tty);
525 static int set_break(struct tty_struct *tty, int break_state);
526
527 #if SYNCLINK_GENERIC_HDLC
528 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
529 static void hdlcdev_tx_done(SLMP_INFO *info);
530 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
531 static int hdlcdev_init(SLMP_INFO *info);
532 static void hdlcdev_exit(SLMP_INFO *info);
533 #endif
534
535 /* ioctl handlers */
536
537 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
538 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
539 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
541 static int set_txidle(SLMP_INFO *info, int idle_mode);
542 static int tx_enable(SLMP_INFO *info, int enable);
543 static int tx_abort(SLMP_INFO *info);
544 static int rx_enable(SLMP_INFO *info, int enable);
545 static int modem_input_wait(SLMP_INFO *info,int arg);
546 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
547 static int tiocmget(struct tty_struct *tty);
548 static int tiocmset(struct tty_struct *tty,
549 unsigned int set, unsigned int clear);
550 static int set_break(struct tty_struct *tty, int break_state);
551
552 static int add_device(SLMP_INFO *info);
553 static int device_init(int adapter_num, struct pci_dev *pdev);
554 static int claim_resources(SLMP_INFO *info);
555 static void release_resources(SLMP_INFO *info);
556
557 static int startup(SLMP_INFO *info);
558 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
559 static int carrier_raised(struct tty_port *port);
560 static void shutdown(SLMP_INFO *info);
561 static void program_hw(SLMP_INFO *info);
562 static void change_params(SLMP_INFO *info);
563
564 static bool init_adapter(SLMP_INFO *info);
565 static bool register_test(SLMP_INFO *info);
566 static bool irq_test(SLMP_INFO *info);
567 static bool loopback_test(SLMP_INFO *info);
568 static int adapter_test(SLMP_INFO *info);
569 static bool memory_test(SLMP_INFO *info);
570
571 static void reset_adapter(SLMP_INFO *info);
572 static void reset_port(SLMP_INFO *info);
573 static void async_mode(SLMP_INFO *info);
574 static void hdlc_mode(SLMP_INFO *info);
575
576 static void rx_stop(SLMP_INFO *info);
577 static void rx_start(SLMP_INFO *info);
578 static void rx_reset_buffers(SLMP_INFO *info);
579 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
580 static bool rx_get_frame(SLMP_INFO *info);
581
582 static void tx_start(SLMP_INFO *info);
583 static void tx_stop(SLMP_INFO *info);
584 static void tx_load_fifo(SLMP_INFO *info);
585 static void tx_set_idle(SLMP_INFO *info);
586 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
587
588 static void get_signals(SLMP_INFO *info);
589 static void set_signals(SLMP_INFO *info);
590 static void enable_loopback(SLMP_INFO *info, int enable);
591 static void set_rate(SLMP_INFO *info, u32 data_rate);
592
593 static int bh_action(SLMP_INFO *info);
594 static void bh_handler(struct work_struct *work);
595 static void bh_receive(SLMP_INFO *info);
596 static void bh_transmit(SLMP_INFO *info);
597 static void bh_status(SLMP_INFO *info);
598 static void isr_timer(SLMP_INFO *info);
599 static void isr_rxint(SLMP_INFO *info);
600 static void isr_rxrdy(SLMP_INFO *info);
601 static void isr_txint(SLMP_INFO *info);
602 static void isr_txrdy(SLMP_INFO *info);
603 static void isr_rxdmaok(SLMP_INFO *info);
604 static void isr_rxdmaerror(SLMP_INFO *info);
605 static void isr_txdmaok(SLMP_INFO *info);
606 static void isr_txdmaerror(SLMP_INFO *info);
607 static void isr_io_pin(SLMP_INFO *info, u16 status);
608
609 static int alloc_dma_bufs(SLMP_INFO *info);
610 static void free_dma_bufs(SLMP_INFO *info);
611 static int alloc_buf_list(SLMP_INFO *info);
612 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
613 static int alloc_tmp_rx_buf(SLMP_INFO *info);
614 static void free_tmp_rx_buf(SLMP_INFO *info);
615
616 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
617 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
618 static void tx_timeout(unsigned long context);
619 static void status_timeout(unsigned long context);
620
621 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
623 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
624 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
625 static unsigned char read_status_reg(SLMP_INFO * info);
626 static void write_control_reg(SLMP_INFO * info);
627
628
629 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
630 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
631 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
632
633 static u32 misc_ctrl_value = 0x007e4040;
634 static u32 lcr1_brdr_value = 0x00800028;
635
636 static u32 read_ahead_count = 8;
637
638 /* DPCR, DMA Priority Control
639 *
640 * 07..05 Not used, must be 0
641 * 04 BRC, bus release condition: 0=all transfers complete
642 * 1=release after 1 xfer on all channels
643 * 03 CCC, channel change condition: 0=every cycle
644 * 1=after each channel completes all xfers
645 * 02..00 PR<2..0>, priority 100=round robin
646 *
647 * 00000100 = 0x00
648 */
649 static unsigned char dma_priority = 0x04;
650
651 // Number of bytes that can be written to shared RAM
652 // in a single write operation
653 static u32 sca_pci_load_interval = 64;
654
655 /*
656 * 1st function defined in .text section. Calling this function in
657 * init_module() followed by a breakpoint allows a remote debugger
658 * (gdb) to get the .text address for the add-symbol-file command.
659 * This allows remote debugging of dynamically loadable modules.
660 */
661 static void* synclinkmp_get_text_ptr(void);
662 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
663
664 static inline int sanity_check(SLMP_INFO *info,
665 char *name, const char *routine)
666 {
667 #ifdef SANITY_CHECK
668 static const char *badmagic =
669 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
670 static const char *badinfo =
671 "Warning: null synclinkmp_struct for (%s) in %s\n";
672
673 if (!info) {
674 printk(badinfo, name, routine);
675 return 1;
676 }
677 if (info->magic != MGSL_MAGIC) {
678 printk(badmagic, name, routine);
679 return 1;
680 }
681 #else
682 if (!info)
683 return 1;
684 #endif
685 return 0;
686 }
687
688 /**
689 * line discipline callback wrappers
690 *
691 * The wrappers maintain line discipline references
692 * while calling into the line discipline.
693 *
694 * ldisc_receive_buf - pass receive data to line discipline
695 */
696
697 static void ldisc_receive_buf(struct tty_struct *tty,
698 const __u8 *data, char *flags, int count)
699 {
700 struct tty_ldisc *ld;
701 if (!tty)
702 return;
703 ld = tty_ldisc_ref(tty);
704 if (ld) {
705 if (ld->ops->receive_buf)
706 ld->ops->receive_buf(tty, data, flags, count);
707 tty_ldisc_deref(ld);
708 }
709 }
710
711 /* tty callbacks */
712
713 static int install(struct tty_driver *driver, struct tty_struct *tty)
714 {
715 SLMP_INFO *info;
716 int line = tty->index;
717
718 if (line >= synclinkmp_device_count) {
719 printk("%s(%d): open with invalid line #%d.\n",
720 __FILE__,__LINE__,line);
721 return -ENODEV;
722 }
723
724 info = synclinkmp_device_list;
725 while (info && info->line != line)
726 info = info->next_device;
727 if (sanity_check(info, tty->name, "open"))
728 return -ENODEV;
729 if (info->init_error) {
730 printk("%s(%d):%s device is not allocated, init error=%d\n",
731 __FILE__, __LINE__, info->device_name,
732 info->init_error);
733 return -ENODEV;
734 }
735
736 tty->driver_data = info;
737
738 return tty_port_install(&info->port, driver, tty);
739 }
740
741 /* Called when a port is opened. Init and enable port.
742 */
743 static int open(struct tty_struct *tty, struct file *filp)
744 {
745 SLMP_INFO *info = tty->driver_data;
746 unsigned long flags;
747 int retval;
748
749 info->port.tty = tty;
750
751 if (debug_level >= DEBUG_LEVEL_INFO)
752 printk("%s(%d):%s open(), old ref count = %d\n",
753 __FILE__,__LINE__,tty->driver->name, info->port.count);
754
755 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
756
757 spin_lock_irqsave(&info->netlock, flags);
758 if (info->netcount) {
759 retval = -EBUSY;
760 spin_unlock_irqrestore(&info->netlock, flags);
761 goto cleanup;
762 }
763 info->port.count++;
764 spin_unlock_irqrestore(&info->netlock, flags);
765
766 if (info->port.count == 1) {
767 /* 1st open on this device, init hardware */
768 retval = startup(info);
769 if (retval < 0)
770 goto cleanup;
771 }
772
773 retval = block_til_ready(tty, filp, info);
774 if (retval) {
775 if (debug_level >= DEBUG_LEVEL_INFO)
776 printk("%s(%d):%s block_til_ready() returned %d\n",
777 __FILE__,__LINE__, info->device_name, retval);
778 goto cleanup;
779 }
780
781 if (debug_level >= DEBUG_LEVEL_INFO)
782 printk("%s(%d):%s open() success\n",
783 __FILE__,__LINE__, info->device_name);
784 retval = 0;
785
786 cleanup:
787 if (retval) {
788 if (tty->count == 1)
789 info->port.tty = NULL; /* tty layer will release tty struct */
790 if(info->port.count)
791 info->port.count--;
792 }
793
794 return retval;
795 }
796
797 /* Called when port is closed. Wait for remaining data to be
798 * sent. Disable port and free resources.
799 */
800 static void close(struct tty_struct *tty, struct file *filp)
801 {
802 SLMP_INFO * info = tty->driver_data;
803
804 if (sanity_check(info, tty->name, "close"))
805 return;
806
807 if (debug_level >= DEBUG_LEVEL_INFO)
808 printk("%s(%d):%s close() entry, count=%d\n",
809 __FILE__,__LINE__, info->device_name, info->port.count);
810
811 if (tty_port_close_start(&info->port, tty, filp) == 0)
812 goto cleanup;
813
814 mutex_lock(&info->port.mutex);
815 if (tty_port_initialized(&info->port))
816 wait_until_sent(tty, info->timeout);
817
818 flush_buffer(tty);
819 tty_ldisc_flush(tty);
820 shutdown(info);
821 mutex_unlock(&info->port.mutex);
822
823 tty_port_close_end(&info->port, tty);
824 info->port.tty = NULL;
825 cleanup:
826 if (debug_level >= DEBUG_LEVEL_INFO)
827 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
828 tty->driver->name, info->port.count);
829 }
830
831 /* Called by tty_hangup() when a hangup is signaled.
832 * This is the same as closing all open descriptors for the port.
833 */
834 static void hangup(struct tty_struct *tty)
835 {
836 SLMP_INFO *info = tty->driver_data;
837 unsigned long flags;
838
839 if (debug_level >= DEBUG_LEVEL_INFO)
840 printk("%s(%d):%s hangup()\n",
841 __FILE__,__LINE__, info->device_name );
842
843 if (sanity_check(info, tty->name, "hangup"))
844 return;
845
846 mutex_lock(&info->port.mutex);
847 flush_buffer(tty);
848 shutdown(info);
849
850 spin_lock_irqsave(&info->port.lock, flags);
851 info->port.count = 0;
852 info->port.tty = NULL;
853 spin_unlock_irqrestore(&info->port.lock, flags);
854 tty_port_set_active(&info->port, 1);
855 mutex_unlock(&info->port.mutex);
856
857 wake_up_interruptible(&info->port.open_wait);
858 }
859
860 /* Set new termios settings
861 */
862 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
863 {
864 SLMP_INFO *info = tty->driver_data;
865 unsigned long flags;
866
867 if (debug_level >= DEBUG_LEVEL_INFO)
868 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
869 tty->driver->name );
870
871 change_params(info);
872
873 /* Handle transition to B0 status */
874 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
875 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
876 spin_lock_irqsave(&info->lock,flags);
877 set_signals(info);
878 spin_unlock_irqrestore(&info->lock,flags);
879 }
880
881 /* Handle transition away from B0 status */
882 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
883 info->serial_signals |= SerialSignal_DTR;
884 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
885 info->serial_signals |= SerialSignal_RTS;
886 spin_lock_irqsave(&info->lock,flags);
887 set_signals(info);
888 spin_unlock_irqrestore(&info->lock,flags);
889 }
890
891 /* Handle turning off CRTSCTS */
892 if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
893 tty->hw_stopped = 0;
894 tx_release(tty);
895 }
896 }
897
898 /* Send a block of data
899 *
900 * Arguments:
901 *
902 * tty pointer to tty information structure
903 * buf pointer to buffer containing send data
904 * count size of send data in bytes
905 *
906 * Return Value: number of characters written
907 */
908 static int write(struct tty_struct *tty,
909 const unsigned char *buf, int count)
910 {
911 int c, ret = 0;
912 SLMP_INFO *info = tty->driver_data;
913 unsigned long flags;
914
915 if (debug_level >= DEBUG_LEVEL_INFO)
916 printk("%s(%d):%s write() count=%d\n",
917 __FILE__,__LINE__,info->device_name,count);
918
919 if (sanity_check(info, tty->name, "write"))
920 goto cleanup;
921
922 if (!info->tx_buf)
923 goto cleanup;
924
925 if (info->params.mode == MGSL_MODE_HDLC) {
926 if (count > info->max_frame_size) {
927 ret = -EIO;
928 goto cleanup;
929 }
930 if (info->tx_active)
931 goto cleanup;
932 if (info->tx_count) {
933 /* send accumulated data from send_char() calls */
934 /* as frame and wait before accepting more data. */
935 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
936 goto start;
937 }
938 ret = info->tx_count = count;
939 tx_load_dma_buffer(info, buf, count);
940 goto start;
941 }
942
943 for (;;) {
944 c = min_t(int, count,
945 min(info->max_frame_size - info->tx_count - 1,
946 info->max_frame_size - info->tx_put));
947 if (c <= 0)
948 break;
949
950 memcpy(info->tx_buf + info->tx_put, buf, c);
951
952 spin_lock_irqsave(&info->lock,flags);
953 info->tx_put += c;
954 if (info->tx_put >= info->max_frame_size)
955 info->tx_put -= info->max_frame_size;
956 info->tx_count += c;
957 spin_unlock_irqrestore(&info->lock,flags);
958
959 buf += c;
960 count -= c;
961 ret += c;
962 }
963
964 if (info->params.mode == MGSL_MODE_HDLC) {
965 if (count) {
966 ret = info->tx_count = 0;
967 goto cleanup;
968 }
969 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
970 }
971 start:
972 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
973 spin_lock_irqsave(&info->lock,flags);
974 if (!info->tx_active)
975 tx_start(info);
976 spin_unlock_irqrestore(&info->lock,flags);
977 }
978
979 cleanup:
980 if (debug_level >= DEBUG_LEVEL_INFO)
981 printk( "%s(%d):%s write() returning=%d\n",
982 __FILE__,__LINE__,info->device_name,ret);
983 return ret;
984 }
985
986 /* Add a character to the transmit buffer.
987 */
988 static int put_char(struct tty_struct *tty, unsigned char ch)
989 {
990 SLMP_INFO *info = tty->driver_data;
991 unsigned long flags;
992 int ret = 0;
993
994 if ( debug_level >= DEBUG_LEVEL_INFO ) {
995 printk( "%s(%d):%s put_char(%d)\n",
996 __FILE__,__LINE__,info->device_name,ch);
997 }
998
999 if (sanity_check(info, tty->name, "put_char"))
1000 return 0;
1001
1002 if (!info->tx_buf)
1003 return 0;
1004
1005 spin_lock_irqsave(&info->lock,flags);
1006
1007 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1008 !info->tx_active ) {
1009
1010 if (info->tx_count < info->max_frame_size - 1) {
1011 info->tx_buf[info->tx_put++] = ch;
1012 if (info->tx_put >= info->max_frame_size)
1013 info->tx_put -= info->max_frame_size;
1014 info->tx_count++;
1015 ret = 1;
1016 }
1017 }
1018
1019 spin_unlock_irqrestore(&info->lock,flags);
1020 return ret;
1021 }
1022
1023 /* Send a high-priority XON/XOFF character
1024 */
1025 static void send_xchar(struct tty_struct *tty, char ch)
1026 {
1027 SLMP_INFO *info = tty->driver_data;
1028 unsigned long flags;
1029
1030 if (debug_level >= DEBUG_LEVEL_INFO)
1031 printk("%s(%d):%s send_xchar(%d)\n",
1032 __FILE__,__LINE__, info->device_name, ch );
1033
1034 if (sanity_check(info, tty->name, "send_xchar"))
1035 return;
1036
1037 info->x_char = ch;
1038 if (ch) {
1039 /* Make sure transmit interrupts are on */
1040 spin_lock_irqsave(&info->lock,flags);
1041 if (!info->tx_enabled)
1042 tx_start(info);
1043 spin_unlock_irqrestore(&info->lock,flags);
1044 }
1045 }
1046
1047 /* Wait until the transmitter is empty.
1048 */
1049 static void wait_until_sent(struct tty_struct *tty, int timeout)
1050 {
1051 SLMP_INFO * info = tty->driver_data;
1052 unsigned long orig_jiffies, char_time;
1053
1054 if (!info )
1055 return;
1056
1057 if (debug_level >= DEBUG_LEVEL_INFO)
1058 printk("%s(%d):%s wait_until_sent() entry\n",
1059 __FILE__,__LINE__, info->device_name );
1060
1061 if (sanity_check(info, tty->name, "wait_until_sent"))
1062 return;
1063
1064 if (!tty_port_initialized(&info->port))
1065 goto exit;
1066
1067 orig_jiffies = jiffies;
1068
1069 /* Set check interval to 1/5 of estimated time to
1070 * send a character, and make it at least 1. The check
1071 * interval should also be less than the timeout.
1072 * Note: use tight timings here to satisfy the NIST-PCTS.
1073 */
1074
1075 if ( info->params.data_rate ) {
1076 char_time = info->timeout/(32 * 5);
1077 if (!char_time)
1078 char_time++;
1079 } else
1080 char_time = 1;
1081
1082 if (timeout)
1083 char_time = min_t(unsigned long, char_time, timeout);
1084
1085 if ( info->params.mode == MGSL_MODE_HDLC ) {
1086 while (info->tx_active) {
1087 msleep_interruptible(jiffies_to_msecs(char_time));
1088 if (signal_pending(current))
1089 break;
1090 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1091 break;
1092 }
1093 } else {
1094 /*
1095 * TODO: determine if there is something similar to USC16C32
1096 * TXSTATUS_ALL_SENT status
1097 */
1098 while ( info->tx_active && info->tx_enabled) {
1099 msleep_interruptible(jiffies_to_msecs(char_time));
1100 if (signal_pending(current))
1101 break;
1102 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1103 break;
1104 }
1105 }
1106
1107 exit:
1108 if (debug_level >= DEBUG_LEVEL_INFO)
1109 printk("%s(%d):%s wait_until_sent() exit\n",
1110 __FILE__,__LINE__, info->device_name );
1111 }
1112
1113 /* Return the count of free bytes in transmit buffer
1114 */
1115 static int write_room(struct tty_struct *tty)
1116 {
1117 SLMP_INFO *info = tty->driver_data;
1118 int ret;
1119
1120 if (sanity_check(info, tty->name, "write_room"))
1121 return 0;
1122
1123 if (info->params.mode == MGSL_MODE_HDLC) {
1124 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1125 } else {
1126 ret = info->max_frame_size - info->tx_count - 1;
1127 if (ret < 0)
1128 ret = 0;
1129 }
1130
1131 if (debug_level >= DEBUG_LEVEL_INFO)
1132 printk("%s(%d):%s write_room()=%d\n",
1133 __FILE__, __LINE__, info->device_name, ret);
1134
1135 return ret;
1136 }
1137
1138 /* enable transmitter and send remaining buffered characters
1139 */
1140 static void flush_chars(struct tty_struct *tty)
1141 {
1142 SLMP_INFO *info = tty->driver_data;
1143 unsigned long flags;
1144
1145 if ( debug_level >= DEBUG_LEVEL_INFO )
1146 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1147 __FILE__,__LINE__,info->device_name,info->tx_count);
1148
1149 if (sanity_check(info, tty->name, "flush_chars"))
1150 return;
1151
1152 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1153 !info->tx_buf)
1154 return;
1155
1156 if ( debug_level >= DEBUG_LEVEL_INFO )
1157 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1158 __FILE__,__LINE__,info->device_name );
1159
1160 spin_lock_irqsave(&info->lock,flags);
1161
1162 if (!info->tx_active) {
1163 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1164 info->tx_count ) {
1165 /* operating in synchronous (frame oriented) mode */
1166 /* copy data from circular tx_buf to */
1167 /* transmit DMA buffer. */
1168 tx_load_dma_buffer(info,
1169 info->tx_buf,info->tx_count);
1170 }
1171 tx_start(info);
1172 }
1173
1174 spin_unlock_irqrestore(&info->lock,flags);
1175 }
1176
1177 /* Discard all data in the send buffer
1178 */
1179 static void flush_buffer(struct tty_struct *tty)
1180 {
1181 SLMP_INFO *info = tty->driver_data;
1182 unsigned long flags;
1183
1184 if (debug_level >= DEBUG_LEVEL_INFO)
1185 printk("%s(%d):%s flush_buffer() entry\n",
1186 __FILE__,__LINE__, info->device_name );
1187
1188 if (sanity_check(info, tty->name, "flush_buffer"))
1189 return;
1190
1191 spin_lock_irqsave(&info->lock,flags);
1192 info->tx_count = info->tx_put = info->tx_get = 0;
1193 del_timer(&info->tx_timer);
1194 spin_unlock_irqrestore(&info->lock,flags);
1195
1196 tty_wakeup(tty);
1197 }
1198
1199 /* throttle (stop) transmitter
1200 */
1201 static void tx_hold(struct tty_struct *tty)
1202 {
1203 SLMP_INFO *info = tty->driver_data;
1204 unsigned long flags;
1205
1206 if (sanity_check(info, tty->name, "tx_hold"))
1207 return;
1208
1209 if ( debug_level >= DEBUG_LEVEL_INFO )
1210 printk("%s(%d):%s tx_hold()\n",
1211 __FILE__,__LINE__,info->device_name);
1212
1213 spin_lock_irqsave(&info->lock,flags);
1214 if (info->tx_enabled)
1215 tx_stop(info);
1216 spin_unlock_irqrestore(&info->lock,flags);
1217 }
1218
1219 /* release (start) transmitter
1220 */
1221 static void tx_release(struct tty_struct *tty)
1222 {
1223 SLMP_INFO *info = tty->driver_data;
1224 unsigned long flags;
1225
1226 if (sanity_check(info, tty->name, "tx_release"))
1227 return;
1228
1229 if ( debug_level >= DEBUG_LEVEL_INFO )
1230 printk("%s(%d):%s tx_release()\n",
1231 __FILE__,__LINE__,info->device_name);
1232
1233 spin_lock_irqsave(&info->lock,flags);
1234 if (!info->tx_enabled)
1235 tx_start(info);
1236 spin_unlock_irqrestore(&info->lock,flags);
1237 }
1238
1239 /* Service an IOCTL request
1240 *
1241 * Arguments:
1242 *
1243 * tty pointer to tty instance data
1244 * cmd IOCTL command code
1245 * arg command argument/context
1246 *
1247 * Return Value: 0 if success, otherwise error code
1248 */
1249 static int ioctl(struct tty_struct *tty,
1250 unsigned int cmd, unsigned long arg)
1251 {
1252 SLMP_INFO *info = tty->driver_data;
1253 void __user *argp = (void __user *)arg;
1254
1255 if (debug_level >= DEBUG_LEVEL_INFO)
1256 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1257 info->device_name, cmd );
1258
1259 if (sanity_check(info, tty->name, "ioctl"))
1260 return -ENODEV;
1261
1262 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1263 (cmd != TIOCMIWAIT)) {
1264 if (tty_io_error(tty))
1265 return -EIO;
1266 }
1267
1268 switch (cmd) {
1269 case MGSL_IOCGPARAMS:
1270 return get_params(info, argp);
1271 case MGSL_IOCSPARAMS:
1272 return set_params(info, argp);
1273 case MGSL_IOCGTXIDLE:
1274 return get_txidle(info, argp);
1275 case MGSL_IOCSTXIDLE:
1276 return set_txidle(info, (int)arg);
1277 case MGSL_IOCTXENABLE:
1278 return tx_enable(info, (int)arg);
1279 case MGSL_IOCRXENABLE:
1280 return rx_enable(info, (int)arg);
1281 case MGSL_IOCTXABORT:
1282 return tx_abort(info);
1283 case MGSL_IOCGSTATS:
1284 return get_stats(info, argp);
1285 case MGSL_IOCWAITEVENT:
1286 return wait_mgsl_event(info, argp);
1287 case MGSL_IOCLOOPTXDONE:
1288 return 0; // TODO: Not supported, need to document
1289 /* Wait for modem input (DCD,RI,DSR,CTS) change
1290 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1291 */
1292 case TIOCMIWAIT:
1293 return modem_input_wait(info,(int)arg);
1294
1295 /*
1296 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1297 * Return: write counters to the user passed counter struct
1298 * NB: both 1->0 and 0->1 transitions are counted except for
1299 * RI where only 0->1 is counted.
1300 */
1301 default:
1302 return -ENOIOCTLCMD;
1303 }
1304 return 0;
1305 }
1306
1307 static int get_icount(struct tty_struct *tty,
1308 struct serial_icounter_struct *icount)
1309 {
1310 SLMP_INFO *info = tty->driver_data;
1311 struct mgsl_icount cnow; /* kernel counter temps */
1312 unsigned long flags;
1313
1314 spin_lock_irqsave(&info->lock,flags);
1315 cnow = info->icount;
1316 spin_unlock_irqrestore(&info->lock,flags);
1317
1318 icount->cts = cnow.cts;
1319 icount->dsr = cnow.dsr;
1320 icount->rng = cnow.rng;
1321 icount->dcd = cnow.dcd;
1322 icount->rx = cnow.rx;
1323 icount->tx = cnow.tx;
1324 icount->frame = cnow.frame;
1325 icount->overrun = cnow.overrun;
1326 icount->parity = cnow.parity;
1327 icount->brk = cnow.brk;
1328 icount->buf_overrun = cnow.buf_overrun;
1329
1330 return 0;
1331 }
1332
1333 /*
1334 * /proc fs routines....
1335 */
1336
1337 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1338 {
1339 char stat_buf[30];
1340 unsigned long flags;
1341
1342 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1343 "\tIRQ=%d MaxFrameSize=%u\n",
1344 info->device_name,
1345 info->phys_sca_base,
1346 info->phys_memory_base,
1347 info->phys_statctrl_base,
1348 info->phys_lcr_base,
1349 info->irq_level,
1350 info->max_frame_size );
1351
1352 /* output current serial signal states */
1353 spin_lock_irqsave(&info->lock,flags);
1354 get_signals(info);
1355 spin_unlock_irqrestore(&info->lock,flags);
1356
1357 stat_buf[0] = 0;
1358 stat_buf[1] = 0;
1359 if (info->serial_signals & SerialSignal_RTS)
1360 strcat(stat_buf, "|RTS");
1361 if (info->serial_signals & SerialSignal_CTS)
1362 strcat(stat_buf, "|CTS");
1363 if (info->serial_signals & SerialSignal_DTR)
1364 strcat(stat_buf, "|DTR");
1365 if (info->serial_signals & SerialSignal_DSR)
1366 strcat(stat_buf, "|DSR");
1367 if (info->serial_signals & SerialSignal_DCD)
1368 strcat(stat_buf, "|CD");
1369 if (info->serial_signals & SerialSignal_RI)
1370 strcat(stat_buf, "|RI");
1371
1372 if (info->params.mode == MGSL_MODE_HDLC) {
1373 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1374 info->icount.txok, info->icount.rxok);
1375 if (info->icount.txunder)
1376 seq_printf(m, " txunder:%d", info->icount.txunder);
1377 if (info->icount.txabort)
1378 seq_printf(m, " txabort:%d", info->icount.txabort);
1379 if (info->icount.rxshort)
1380 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1381 if (info->icount.rxlong)
1382 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1383 if (info->icount.rxover)
1384 seq_printf(m, " rxover:%d", info->icount.rxover);
1385 if (info->icount.rxcrc)
1386 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1387 } else {
1388 seq_printf(m, "\tASYNC tx:%d rx:%d",
1389 info->icount.tx, info->icount.rx);
1390 if (info->icount.frame)
1391 seq_printf(m, " fe:%d", info->icount.frame);
1392 if (info->icount.parity)
1393 seq_printf(m, " pe:%d", info->icount.parity);
1394 if (info->icount.brk)
1395 seq_printf(m, " brk:%d", info->icount.brk);
1396 if (info->icount.overrun)
1397 seq_printf(m, " oe:%d", info->icount.overrun);
1398 }
1399
1400 /* Append serial signal status to end */
1401 seq_printf(m, " %s\n", stat_buf+1);
1402
1403 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1404 info->tx_active,info->bh_requested,info->bh_running,
1405 info->pending_bh);
1406 }
1407
1408 /* Called to print information about devices
1409 */
1410 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1411 {
1412 SLMP_INFO *info;
1413
1414 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1415
1416 info = synclinkmp_device_list;
1417 while( info ) {
1418 line_info(m, info);
1419 info = info->next_device;
1420 }
1421 return 0;
1422 }
1423
1424 static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1425 {
1426 return single_open(file, synclinkmp_proc_show, NULL);
1427 }
1428
1429 static const struct file_operations synclinkmp_proc_fops = {
1430 .owner = THIS_MODULE,
1431 .open = synclinkmp_proc_open,
1432 .read = seq_read,
1433 .llseek = seq_lseek,
1434 .release = single_release,
1435 };
1436
1437 /* Return the count of bytes in transmit buffer
1438 */
1439 static int chars_in_buffer(struct tty_struct *tty)
1440 {
1441 SLMP_INFO *info = tty->driver_data;
1442
1443 if (sanity_check(info, tty->name, "chars_in_buffer"))
1444 return 0;
1445
1446 if (debug_level >= DEBUG_LEVEL_INFO)
1447 printk("%s(%d):%s chars_in_buffer()=%d\n",
1448 __FILE__, __LINE__, info->device_name, info->tx_count);
1449
1450 return info->tx_count;
1451 }
1452
1453 /* Signal remote device to throttle send data (our receive data)
1454 */
1455 static void throttle(struct tty_struct * tty)
1456 {
1457 SLMP_INFO *info = tty->driver_data;
1458 unsigned long flags;
1459
1460 if (debug_level >= DEBUG_LEVEL_INFO)
1461 printk("%s(%d):%s throttle() entry\n",
1462 __FILE__,__LINE__, info->device_name );
1463
1464 if (sanity_check(info, tty->name, "throttle"))
1465 return;
1466
1467 if (I_IXOFF(tty))
1468 send_xchar(tty, STOP_CHAR(tty));
1469
1470 if (C_CRTSCTS(tty)) {
1471 spin_lock_irqsave(&info->lock,flags);
1472 info->serial_signals &= ~SerialSignal_RTS;
1473 set_signals(info);
1474 spin_unlock_irqrestore(&info->lock,flags);
1475 }
1476 }
1477
1478 /* Signal remote device to stop throttling send data (our receive data)
1479 */
1480 static void unthrottle(struct tty_struct * tty)
1481 {
1482 SLMP_INFO *info = tty->driver_data;
1483 unsigned long flags;
1484
1485 if (debug_level >= DEBUG_LEVEL_INFO)
1486 printk("%s(%d):%s unthrottle() entry\n",
1487 __FILE__,__LINE__, info->device_name );
1488
1489 if (sanity_check(info, tty->name, "unthrottle"))
1490 return;
1491
1492 if (I_IXOFF(tty)) {
1493 if (info->x_char)
1494 info->x_char = 0;
1495 else
1496 send_xchar(tty, START_CHAR(tty));
1497 }
1498
1499 if (C_CRTSCTS(tty)) {
1500 spin_lock_irqsave(&info->lock,flags);
1501 info->serial_signals |= SerialSignal_RTS;
1502 set_signals(info);
1503 spin_unlock_irqrestore(&info->lock,flags);
1504 }
1505 }
1506
1507 /* set or clear transmit break condition
1508 * break_state -1=set break condition, 0=clear
1509 */
1510 static int set_break(struct tty_struct *tty, int break_state)
1511 {
1512 unsigned char RegValue;
1513 SLMP_INFO * info = tty->driver_data;
1514 unsigned long flags;
1515
1516 if (debug_level >= DEBUG_LEVEL_INFO)
1517 printk("%s(%d):%s set_break(%d)\n",
1518 __FILE__,__LINE__, info->device_name, break_state);
1519
1520 if (sanity_check(info, tty->name, "set_break"))
1521 return -EINVAL;
1522
1523 spin_lock_irqsave(&info->lock,flags);
1524 RegValue = read_reg(info, CTL);
1525 if (break_state == -1)
1526 RegValue |= BIT3;
1527 else
1528 RegValue &= ~BIT3;
1529 write_reg(info, CTL, RegValue);
1530 spin_unlock_irqrestore(&info->lock,flags);
1531 return 0;
1532 }
1533
1534 #if SYNCLINK_GENERIC_HDLC
1535
1536 /**
1537 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1538 * set encoding and frame check sequence (FCS) options
1539 *
1540 * dev pointer to network device structure
1541 * encoding serial encoding setting
1542 * parity FCS setting
1543 *
1544 * returns 0 if success, otherwise error code
1545 */
1546 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1547 unsigned short parity)
1548 {
1549 SLMP_INFO *info = dev_to_port(dev);
1550 unsigned char new_encoding;
1551 unsigned short new_crctype;
1552
1553 /* return error if TTY interface open */
1554 if (info->port.count)
1555 return -EBUSY;
1556
1557 switch (encoding)
1558 {
1559 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1560 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1561 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1562 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1563 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1564 default: return -EINVAL;
1565 }
1566
1567 switch (parity)
1568 {
1569 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1570 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1571 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1572 default: return -EINVAL;
1573 }
1574
1575 info->params.encoding = new_encoding;
1576 info->params.crc_type = new_crctype;
1577
1578 /* if network interface up, reprogram hardware */
1579 if (info->netcount)
1580 program_hw(info);
1581
1582 return 0;
1583 }
1584
1585 /**
1586 * called by generic HDLC layer to send frame
1587 *
1588 * skb socket buffer containing HDLC frame
1589 * dev pointer to network device structure
1590 */
1591 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1592 struct net_device *dev)
1593 {
1594 SLMP_INFO *info = dev_to_port(dev);
1595 unsigned long flags;
1596
1597 if (debug_level >= DEBUG_LEVEL_INFO)
1598 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1599
1600 /* stop sending until this frame completes */
1601 netif_stop_queue(dev);
1602
1603 /* copy data to device buffers */
1604 info->tx_count = skb->len;
1605 tx_load_dma_buffer(info, skb->data, skb->len);
1606
1607 /* update network statistics */
1608 dev->stats.tx_packets++;
1609 dev->stats.tx_bytes += skb->len;
1610
1611 /* done with socket buffer, so free it */
1612 dev_kfree_skb(skb);
1613
1614 /* save start time for transmit timeout detection */
1615 netif_trans_update(dev);
1616
1617 /* start hardware transmitter if necessary */
1618 spin_lock_irqsave(&info->lock,flags);
1619 if (!info->tx_active)
1620 tx_start(info);
1621 spin_unlock_irqrestore(&info->lock,flags);
1622
1623 return NETDEV_TX_OK;
1624 }
1625
1626 /**
1627 * called by network layer when interface enabled
1628 * claim resources and initialize hardware
1629 *
1630 * dev pointer to network device structure
1631 *
1632 * returns 0 if success, otherwise error code
1633 */
1634 static int hdlcdev_open(struct net_device *dev)
1635 {
1636 SLMP_INFO *info = dev_to_port(dev);
1637 int rc;
1638 unsigned long flags;
1639
1640 if (debug_level >= DEBUG_LEVEL_INFO)
1641 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1642
1643 /* generic HDLC layer open processing */
1644 rc = hdlc_open(dev);
1645 if (rc)
1646 return rc;
1647
1648 /* arbitrate between network and tty opens */
1649 spin_lock_irqsave(&info->netlock, flags);
1650 if (info->port.count != 0 || info->netcount != 0) {
1651 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1652 spin_unlock_irqrestore(&info->netlock, flags);
1653 return -EBUSY;
1654 }
1655 info->netcount=1;
1656 spin_unlock_irqrestore(&info->netlock, flags);
1657
1658 /* claim resources and init adapter */
1659 if ((rc = startup(info)) != 0) {
1660 spin_lock_irqsave(&info->netlock, flags);
1661 info->netcount=0;
1662 spin_unlock_irqrestore(&info->netlock, flags);
1663 return rc;
1664 }
1665
1666 /* assert RTS and DTR, apply hardware settings */
1667 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1668 program_hw(info);
1669
1670 /* enable network layer transmit */
1671 netif_trans_update(dev);
1672 netif_start_queue(dev);
1673
1674 /* inform generic HDLC layer of current DCD status */
1675 spin_lock_irqsave(&info->lock, flags);
1676 get_signals(info);
1677 spin_unlock_irqrestore(&info->lock, flags);
1678 if (info->serial_signals & SerialSignal_DCD)
1679 netif_carrier_on(dev);
1680 else
1681 netif_carrier_off(dev);
1682 return 0;
1683 }
1684
1685 /**
1686 * called by network layer when interface is disabled
1687 * shutdown hardware and release resources
1688 *
1689 * dev pointer to network device structure
1690 *
1691 * returns 0 if success, otherwise error code
1692 */
1693 static int hdlcdev_close(struct net_device *dev)
1694 {
1695 SLMP_INFO *info = dev_to_port(dev);
1696 unsigned long flags;
1697
1698 if (debug_level >= DEBUG_LEVEL_INFO)
1699 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1700
1701 netif_stop_queue(dev);
1702
1703 /* shutdown adapter and release resources */
1704 shutdown(info);
1705
1706 hdlc_close(dev);
1707
1708 spin_lock_irqsave(&info->netlock, flags);
1709 info->netcount=0;
1710 spin_unlock_irqrestore(&info->netlock, flags);
1711
1712 return 0;
1713 }
1714
1715 /**
1716 * called by network layer to process IOCTL call to network device
1717 *
1718 * dev pointer to network device structure
1719 * ifr pointer to network interface request structure
1720 * cmd IOCTL command code
1721 *
1722 * returns 0 if success, otherwise error code
1723 */
1724 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1725 {
1726 const size_t size = sizeof(sync_serial_settings);
1727 sync_serial_settings new_line;
1728 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1729 SLMP_INFO *info = dev_to_port(dev);
1730 unsigned int flags;
1731
1732 if (debug_level >= DEBUG_LEVEL_INFO)
1733 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1734
1735 /* return error if TTY interface open */
1736 if (info->port.count)
1737 return -EBUSY;
1738
1739 if (cmd != SIOCWANDEV)
1740 return hdlc_ioctl(dev, ifr, cmd);
1741
1742 switch(ifr->ifr_settings.type) {
1743 case IF_GET_IFACE: /* return current sync_serial_settings */
1744
1745 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1746 if (ifr->ifr_settings.size < size) {
1747 ifr->ifr_settings.size = size; /* data size wanted */
1748 return -ENOBUFS;
1749 }
1750
1751 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1752 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1753 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1754 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1755
1756 memset(&new_line, 0, sizeof(new_line));
1757 switch (flags){
1758 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1759 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1760 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1761 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1762 default: new_line.clock_type = CLOCK_DEFAULT;
1763 }
1764
1765 new_line.clock_rate = info->params.clock_speed;
1766 new_line.loopback = info->params.loopback ? 1:0;
1767
1768 if (copy_to_user(line, &new_line, size))
1769 return -EFAULT;
1770 return 0;
1771
1772 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1773
1774 if(!capable(CAP_NET_ADMIN))
1775 return -EPERM;
1776 if (copy_from_user(&new_line, line, size))
1777 return -EFAULT;
1778
1779 switch (new_line.clock_type)
1780 {
1781 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1782 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1783 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1784 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1785 case CLOCK_DEFAULT: flags = info->params.flags &
1786 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1787 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1788 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1789 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1790 default: return -EINVAL;
1791 }
1792
1793 if (new_line.loopback != 0 && new_line.loopback != 1)
1794 return -EINVAL;
1795
1796 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1797 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1798 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1799 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1800 info->params.flags |= flags;
1801
1802 info->params.loopback = new_line.loopback;
1803
1804 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1805 info->params.clock_speed = new_line.clock_rate;
1806 else
1807 info->params.clock_speed = 0;
1808
1809 /* if network interface up, reprogram hardware */
1810 if (info->netcount)
1811 program_hw(info);
1812 return 0;
1813
1814 default:
1815 return hdlc_ioctl(dev, ifr, cmd);
1816 }
1817 }
1818
1819 /**
1820 * called by network layer when transmit timeout is detected
1821 *
1822 * dev pointer to network device structure
1823 */
1824 static void hdlcdev_tx_timeout(struct net_device *dev)
1825 {
1826 SLMP_INFO *info = dev_to_port(dev);
1827 unsigned long flags;
1828
1829 if (debug_level >= DEBUG_LEVEL_INFO)
1830 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1831
1832 dev->stats.tx_errors++;
1833 dev->stats.tx_aborted_errors++;
1834
1835 spin_lock_irqsave(&info->lock,flags);
1836 tx_stop(info);
1837 spin_unlock_irqrestore(&info->lock,flags);
1838
1839 netif_wake_queue(dev);
1840 }
1841
1842 /**
1843 * called by device driver when transmit completes
1844 * reenable network layer transmit if stopped
1845 *
1846 * info pointer to device instance information
1847 */
1848 static void hdlcdev_tx_done(SLMP_INFO *info)
1849 {
1850 if (netif_queue_stopped(info->netdev))
1851 netif_wake_queue(info->netdev);
1852 }
1853
1854 /**
1855 * called by device driver when frame received
1856 * pass frame to network layer
1857 *
1858 * info pointer to device instance information
1859 * buf pointer to buffer contianing frame data
1860 * size count of data bytes in buf
1861 */
1862 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1863 {
1864 struct sk_buff *skb = dev_alloc_skb(size);
1865 struct net_device *dev = info->netdev;
1866
1867 if (debug_level >= DEBUG_LEVEL_INFO)
1868 printk("hdlcdev_rx(%s)\n",dev->name);
1869
1870 if (skb == NULL) {
1871 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1872 dev->name);
1873 dev->stats.rx_dropped++;
1874 return;
1875 }
1876
1877 memcpy(skb_put(skb, size), buf, size);
1878
1879 skb->protocol = hdlc_type_trans(skb, dev);
1880
1881 dev->stats.rx_packets++;
1882 dev->stats.rx_bytes += size;
1883
1884 netif_rx(skb);
1885 }
1886
1887 static const struct net_device_ops hdlcdev_ops = {
1888 .ndo_open = hdlcdev_open,
1889 .ndo_stop = hdlcdev_close,
1890 .ndo_change_mtu = hdlc_change_mtu,
1891 .ndo_start_xmit = hdlc_start_xmit,
1892 .ndo_do_ioctl = hdlcdev_ioctl,
1893 .ndo_tx_timeout = hdlcdev_tx_timeout,
1894 };
1895
1896 /**
1897 * called by device driver when adding device instance
1898 * do generic HDLC initialization
1899 *
1900 * info pointer to device instance information
1901 *
1902 * returns 0 if success, otherwise error code
1903 */
1904 static int hdlcdev_init(SLMP_INFO *info)
1905 {
1906 int rc;
1907 struct net_device *dev;
1908 hdlc_device *hdlc;
1909
1910 /* allocate and initialize network and HDLC layer objects */
1911
1912 dev = alloc_hdlcdev(info);
1913 if (!dev) {
1914 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1915 return -ENOMEM;
1916 }
1917
1918 /* for network layer reporting purposes only */
1919 dev->mem_start = info->phys_sca_base;
1920 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1921 dev->irq = info->irq_level;
1922
1923 /* network layer callbacks and settings */
1924 dev->netdev_ops = &hdlcdev_ops;
1925 dev->watchdog_timeo = 10 * HZ;
1926 dev->tx_queue_len = 50;
1927
1928 /* generic HDLC layer callbacks and settings */
1929 hdlc = dev_to_hdlc(dev);
1930 hdlc->attach = hdlcdev_attach;
1931 hdlc->xmit = hdlcdev_xmit;
1932
1933 /* register objects with HDLC layer */
1934 rc = register_hdlc_device(dev);
1935 if (rc) {
1936 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1937 free_netdev(dev);
1938 return rc;
1939 }
1940
1941 info->netdev = dev;
1942 return 0;
1943 }
1944
1945 /**
1946 * called by device driver when removing device instance
1947 * do generic HDLC cleanup
1948 *
1949 * info pointer to device instance information
1950 */
1951 static void hdlcdev_exit(SLMP_INFO *info)
1952 {
1953 unregister_hdlc_device(info->netdev);
1954 free_netdev(info->netdev);
1955 info->netdev = NULL;
1956 }
1957
1958 #endif /* CONFIG_HDLC */
1959
1960
1961 /* Return next bottom half action to perform.
1962 * Return Value: BH action code or 0 if nothing to do.
1963 */
1964 static int bh_action(SLMP_INFO *info)
1965 {
1966 unsigned long flags;
1967 int rc = 0;
1968
1969 spin_lock_irqsave(&info->lock,flags);
1970
1971 if (info->pending_bh & BH_RECEIVE) {
1972 info->pending_bh &= ~BH_RECEIVE;
1973 rc = BH_RECEIVE;
1974 } else if (info->pending_bh & BH_TRANSMIT) {
1975 info->pending_bh &= ~BH_TRANSMIT;
1976 rc = BH_TRANSMIT;
1977 } else if (info->pending_bh & BH_STATUS) {
1978 info->pending_bh &= ~BH_STATUS;
1979 rc = BH_STATUS;
1980 }
1981
1982 if (!rc) {
1983 /* Mark BH routine as complete */
1984 info->bh_running = false;
1985 info->bh_requested = false;
1986 }
1987
1988 spin_unlock_irqrestore(&info->lock,flags);
1989
1990 return rc;
1991 }
1992
1993 /* Perform bottom half processing of work items queued by ISR.
1994 */
1995 static void bh_handler(struct work_struct *work)
1996 {
1997 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
1998 int action;
1999
2000 if ( debug_level >= DEBUG_LEVEL_BH )
2001 printk( "%s(%d):%s bh_handler() entry\n",
2002 __FILE__,__LINE__,info->device_name);
2003
2004 info->bh_running = true;
2005
2006 while((action = bh_action(info)) != 0) {
2007
2008 /* Process work item */
2009 if ( debug_level >= DEBUG_LEVEL_BH )
2010 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2011 __FILE__,__LINE__,info->device_name, action);
2012
2013 switch (action) {
2014
2015 case BH_RECEIVE:
2016 bh_receive(info);
2017 break;
2018 case BH_TRANSMIT:
2019 bh_transmit(info);
2020 break;
2021 case BH_STATUS:
2022 bh_status(info);
2023 break;
2024 default:
2025 /* unknown work item ID */
2026 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2027 __FILE__,__LINE__,info->device_name,action);
2028 break;
2029 }
2030 }
2031
2032 if ( debug_level >= DEBUG_LEVEL_BH )
2033 printk( "%s(%d):%s bh_handler() exit\n",
2034 __FILE__,__LINE__,info->device_name);
2035 }
2036
2037 static void bh_receive(SLMP_INFO *info)
2038 {
2039 if ( debug_level >= DEBUG_LEVEL_BH )
2040 printk( "%s(%d):%s bh_receive()\n",
2041 __FILE__,__LINE__,info->device_name);
2042
2043 while( rx_get_frame(info) );
2044 }
2045
2046 static void bh_transmit(SLMP_INFO *info)
2047 {
2048 struct tty_struct *tty = info->port.tty;
2049
2050 if ( debug_level >= DEBUG_LEVEL_BH )
2051 printk( "%s(%d):%s bh_transmit() entry\n",
2052 __FILE__,__LINE__,info->device_name);
2053
2054 if (tty)
2055 tty_wakeup(tty);
2056 }
2057
2058 static void bh_status(SLMP_INFO *info)
2059 {
2060 if ( debug_level >= DEBUG_LEVEL_BH )
2061 printk( "%s(%d):%s bh_status() entry\n",
2062 __FILE__,__LINE__,info->device_name);
2063
2064 info->ri_chkcount = 0;
2065 info->dsr_chkcount = 0;
2066 info->dcd_chkcount = 0;
2067 info->cts_chkcount = 0;
2068 }
2069
2070 static void isr_timer(SLMP_INFO * info)
2071 {
2072 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2073
2074 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2075 write_reg(info, IER2, 0);
2076
2077 /* TMCS, Timer Control/Status Register
2078 *
2079 * 07 CMF, Compare match flag (read only) 1=match
2080 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2081 * 05 Reserved, must be 0
2082 * 04 TME, Timer Enable
2083 * 03..00 Reserved, must be 0
2084 *
2085 * 0000 0000
2086 */
2087 write_reg(info, (unsigned char)(timer + TMCS), 0);
2088
2089 info->irq_occurred = true;
2090
2091 if ( debug_level >= DEBUG_LEVEL_ISR )
2092 printk("%s(%d):%s isr_timer()\n",
2093 __FILE__,__LINE__,info->device_name);
2094 }
2095
2096 static void isr_rxint(SLMP_INFO * info)
2097 {
2098 struct tty_struct *tty = info->port.tty;
2099 struct mgsl_icount *icount = &info->icount;
2100 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2101 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2102
2103 /* clear status bits */
2104 if (status)
2105 write_reg(info, SR1, status);
2106
2107 if (status2)
2108 write_reg(info, SR2, status2);
2109
2110 if ( debug_level >= DEBUG_LEVEL_ISR )
2111 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2112 __FILE__,__LINE__,info->device_name,status,status2);
2113
2114 if (info->params.mode == MGSL_MODE_ASYNC) {
2115 if (status & BRKD) {
2116 icount->brk++;
2117
2118 /* process break detection if tty control
2119 * is not set to ignore it
2120 */
2121 if (!(status & info->ignore_status_mask1)) {
2122 if (info->read_status_mask1 & BRKD) {
2123 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2124 if (tty && (info->port.flags & ASYNC_SAK))
2125 do_SAK(tty);
2126 }
2127 }
2128 }
2129 }
2130 else {
2131 if (status & (FLGD|IDLD)) {
2132 if (status & FLGD)
2133 info->icount.exithunt++;
2134 else if (status & IDLD)
2135 info->icount.rxidle++;
2136 wake_up_interruptible(&info->event_wait_q);
2137 }
2138 }
2139
2140 if (status & CDCD) {
2141 /* simulate a common modem status change interrupt
2142 * for our handler
2143 */
2144 get_signals( info );
2145 isr_io_pin(info,
2146 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2147 }
2148 }
2149
2150 /*
2151 * handle async rx data interrupts
2152 */
2153 static void isr_rxrdy(SLMP_INFO * info)
2154 {
2155 u16 status;
2156 unsigned char DataByte;
2157 struct mgsl_icount *icount = &info->icount;
2158
2159 if ( debug_level >= DEBUG_LEVEL_ISR )
2160 printk("%s(%d):%s isr_rxrdy\n",
2161 __FILE__,__LINE__,info->device_name);
2162
2163 while((status = read_reg(info,CST0)) & BIT0)
2164 {
2165 int flag = 0;
2166 bool over = false;
2167 DataByte = read_reg(info,TRB);
2168
2169 icount->rx++;
2170
2171 if ( status & (PE + FRME + OVRN) ) {
2172 printk("%s(%d):%s rxerr=%04X\n",
2173 __FILE__,__LINE__,info->device_name,status);
2174
2175 /* update error statistics */
2176 if (status & PE)
2177 icount->parity++;
2178 else if (status & FRME)
2179 icount->frame++;
2180 else if (status & OVRN)
2181 icount->overrun++;
2182
2183 /* discard char if tty control flags say so */
2184 if (status & info->ignore_status_mask2)
2185 continue;
2186
2187 status &= info->read_status_mask2;
2188
2189 if (status & PE)
2190 flag = TTY_PARITY;
2191 else if (status & FRME)
2192 flag = TTY_FRAME;
2193 if (status & OVRN) {
2194 /* Overrun is special, since it's
2195 * reported immediately, and doesn't
2196 * affect the current character
2197 */
2198 over = true;
2199 }
2200 } /* end of if (error) */
2201
2202 tty_insert_flip_char(&info->port, DataByte, flag);
2203 if (over)
2204 tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
2205 }
2206
2207 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2208 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2209 __FILE__,__LINE__,info->device_name,
2210 icount->rx,icount->brk,icount->parity,
2211 icount->frame,icount->overrun);
2212 }
2213
2214 tty_flip_buffer_push(&info->port);
2215 }
2216
2217 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2218 {
2219 if ( debug_level >= DEBUG_LEVEL_ISR )
2220 printk("%s(%d):%s isr_txeom status=%02x\n",
2221 __FILE__,__LINE__,info->device_name,status);
2222
2223 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2224 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2225 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2226
2227 if (status & UDRN) {
2228 write_reg(info, CMD, TXRESET);
2229 write_reg(info, CMD, TXENABLE);
2230 } else
2231 write_reg(info, CMD, TXBUFCLR);
2232
2233 /* disable and clear tx interrupts */
2234 info->ie0_value &= ~TXRDYE;
2235 info->ie1_value &= ~(IDLE + UDRN);
2236 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2237 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2238
2239 if ( info->tx_active ) {
2240 if (info->params.mode != MGSL_MODE_ASYNC) {
2241 if (status & UDRN)
2242 info->icount.txunder++;
2243 else if (status & IDLE)
2244 info->icount.txok++;
2245 }
2246
2247 info->tx_active = false;
2248 info->tx_count = info->tx_put = info->tx_get = 0;
2249
2250 del_timer(&info->tx_timer);
2251
2252 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2253 info->serial_signals &= ~SerialSignal_RTS;
2254 info->drop_rts_on_tx_done = false;
2255 set_signals(info);
2256 }
2257
2258 #if SYNCLINK_GENERIC_HDLC
2259 if (info->netcount)
2260 hdlcdev_tx_done(info);
2261 else
2262 #endif
2263 {
2264 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2265 tx_stop(info);
2266 return;
2267 }
2268 info->pending_bh |= BH_TRANSMIT;
2269 }
2270 }
2271 }
2272
2273
2274 /*
2275 * handle tx status interrupts
2276 */
2277 static void isr_txint(SLMP_INFO * info)
2278 {
2279 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2280
2281 /* clear status bits */
2282 write_reg(info, SR1, status);
2283
2284 if ( debug_level >= DEBUG_LEVEL_ISR )
2285 printk("%s(%d):%s isr_txint status=%02x\n",
2286 __FILE__,__LINE__,info->device_name,status);
2287
2288 if (status & (UDRN + IDLE))
2289 isr_txeom(info, status);
2290
2291 if (status & CCTS) {
2292 /* simulate a common modem status change interrupt
2293 * for our handler
2294 */
2295 get_signals( info );
2296 isr_io_pin(info,
2297 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2298
2299 }
2300 }
2301
2302 /*
2303 * handle async tx data interrupts
2304 */
2305 static void isr_txrdy(SLMP_INFO * info)
2306 {
2307 if ( debug_level >= DEBUG_LEVEL_ISR )
2308 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2309 __FILE__,__LINE__,info->device_name,info->tx_count);
2310
2311 if (info->params.mode != MGSL_MODE_ASYNC) {
2312 /* disable TXRDY IRQ, enable IDLE IRQ */
2313 info->ie0_value &= ~TXRDYE;
2314 info->ie1_value |= IDLE;
2315 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2316 return;
2317 }
2318
2319 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2320 tx_stop(info);
2321 return;
2322 }
2323
2324 if ( info->tx_count )
2325 tx_load_fifo( info );
2326 else {
2327 info->tx_active = false;
2328 info->ie0_value &= ~TXRDYE;
2329 write_reg(info, IE0, info->ie0_value);
2330 }
2331
2332 if (info->tx_count < WAKEUP_CHARS)
2333 info->pending_bh |= BH_TRANSMIT;
2334 }
2335
2336 static void isr_rxdmaok(SLMP_INFO * info)
2337 {
2338 /* BIT7 = EOT (end of transfer)
2339 * BIT6 = EOM (end of message/frame)
2340 */
2341 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2342
2343 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2344 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2345
2346 if ( debug_level >= DEBUG_LEVEL_ISR )
2347 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2348 __FILE__,__LINE__,info->device_name,status);
2349
2350 info->pending_bh |= BH_RECEIVE;
2351 }
2352
2353 static void isr_rxdmaerror(SLMP_INFO * info)
2354 {
2355 /* BIT5 = BOF (buffer overflow)
2356 * BIT4 = COF (counter overflow)
2357 */
2358 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2359
2360 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2361 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2362
2363 if ( debug_level >= DEBUG_LEVEL_ISR )
2364 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2365 __FILE__,__LINE__,info->device_name,status);
2366
2367 info->rx_overflow = true;
2368 info->pending_bh |= BH_RECEIVE;
2369 }
2370
2371 static void isr_txdmaok(SLMP_INFO * info)
2372 {
2373 unsigned char status_reg1 = read_reg(info, SR1);
2374
2375 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2376 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2377 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2378
2379 if ( debug_level >= DEBUG_LEVEL_ISR )
2380 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2381 __FILE__,__LINE__,info->device_name,status_reg1);
2382
2383 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2384 write_reg16(info, TRC0, 0);
2385 info->ie0_value |= TXRDYE;
2386 write_reg(info, IE0, info->ie0_value);
2387 }
2388
2389 static void isr_txdmaerror(SLMP_INFO * info)
2390 {
2391 /* BIT5 = BOF (buffer overflow)
2392 * BIT4 = COF (counter overflow)
2393 */
2394 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2395
2396 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2397 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2398
2399 if ( debug_level >= DEBUG_LEVEL_ISR )
2400 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2401 __FILE__,__LINE__,info->device_name,status);
2402 }
2403
2404 /* handle input serial signal changes
2405 */
2406 static void isr_io_pin( SLMP_INFO *info, u16 status )
2407 {
2408 struct mgsl_icount *icount;
2409
2410 if ( debug_level >= DEBUG_LEVEL_ISR )
2411 printk("%s(%d):isr_io_pin status=%04X\n",
2412 __FILE__,__LINE__,status);
2413
2414 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2415 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2416 icount = &info->icount;
2417 /* update input line counters */
2418 if (status & MISCSTATUS_RI_LATCHED) {
2419 icount->rng++;
2420 if ( status & SerialSignal_RI )
2421 info->input_signal_events.ri_up++;
2422 else
2423 info->input_signal_events.ri_down++;
2424 }
2425 if (status & MISCSTATUS_DSR_LATCHED) {
2426 icount->dsr++;
2427 if ( status & SerialSignal_DSR )
2428 info->input_signal_events.dsr_up++;
2429 else
2430 info->input_signal_events.dsr_down++;
2431 }
2432 if (status & MISCSTATUS_DCD_LATCHED) {
2433 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2434 info->ie1_value &= ~CDCD;
2435 write_reg(info, IE1, info->ie1_value);
2436 }
2437 icount->dcd++;
2438 if (status & SerialSignal_DCD) {
2439 info->input_signal_events.dcd_up++;
2440 } else
2441 info->input_signal_events.dcd_down++;
2442 #if SYNCLINK_GENERIC_HDLC
2443 if (info->netcount) {
2444 if (status & SerialSignal_DCD)
2445 netif_carrier_on(info->netdev);
2446 else
2447 netif_carrier_off(info->netdev);
2448 }
2449 #endif
2450 }
2451 if (status & MISCSTATUS_CTS_LATCHED)
2452 {
2453 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2454 info->ie1_value &= ~CCTS;
2455 write_reg(info, IE1, info->ie1_value);
2456 }
2457 icount->cts++;
2458 if ( status & SerialSignal_CTS )
2459 info->input_signal_events.cts_up++;
2460 else
2461 info->input_signal_events.cts_down++;
2462 }
2463 wake_up_interruptible(&info->status_event_wait_q);
2464 wake_up_interruptible(&info->event_wait_q);
2465
2466 if (tty_port_check_carrier(&info->port) &&
2467 (status & MISCSTATUS_DCD_LATCHED) ) {
2468 if ( debug_level >= DEBUG_LEVEL_ISR )
2469 printk("%s CD now %s...", info->device_name,
2470 (status & SerialSignal_DCD) ? "on" : "off");
2471 if (status & SerialSignal_DCD)
2472 wake_up_interruptible(&info->port.open_wait);
2473 else {
2474 if ( debug_level >= DEBUG_LEVEL_ISR )
2475 printk("doing serial hangup...");
2476 if (info->port.tty)
2477 tty_hangup(info->port.tty);
2478 }
2479 }
2480
2481 if (tty_port_cts_enabled(&info->port) &&
2482 (status & MISCSTATUS_CTS_LATCHED) ) {
2483 if ( info->port.tty ) {
2484 if (info->port.tty->hw_stopped) {
2485 if (status & SerialSignal_CTS) {
2486 if ( debug_level >= DEBUG_LEVEL_ISR )
2487 printk("CTS tx start...");
2488 info->port.tty->hw_stopped = 0;
2489 tx_start(info);
2490 info->pending_bh |= BH_TRANSMIT;
2491 return;
2492 }
2493 } else {
2494 if (!(status & SerialSignal_CTS)) {
2495 if ( debug_level >= DEBUG_LEVEL_ISR )
2496 printk("CTS tx stop...");
2497 info->port.tty->hw_stopped = 1;
2498 tx_stop(info);
2499 }
2500 }
2501 }
2502 }
2503 }
2504
2505 info->pending_bh |= BH_STATUS;
2506 }
2507
2508 /* Interrupt service routine entry point.
2509 *
2510 * Arguments:
2511 * irq interrupt number that caused interrupt
2512 * dev_id device ID supplied during interrupt registration
2513 * regs interrupted processor context
2514 */
2515 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2516 {
2517 SLMP_INFO *info = dev_id;
2518 unsigned char status, status0, status1=0;
2519 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2520 unsigned char timerstatus0, timerstatus1=0;
2521 unsigned char shift;
2522 unsigned int i;
2523 unsigned short tmp;
2524
2525 if ( debug_level >= DEBUG_LEVEL_ISR )
2526 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2527 __FILE__, __LINE__, info->irq_level);
2528
2529 spin_lock(&info->lock);
2530
2531 for(;;) {
2532
2533 /* get status for SCA0 (ports 0-1) */
2534 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2535 status0 = (unsigned char)tmp;
2536 dmastatus0 = (unsigned char)(tmp>>8);
2537 timerstatus0 = read_reg(info, ISR2);
2538
2539 if ( debug_level >= DEBUG_LEVEL_ISR )
2540 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2541 __FILE__, __LINE__, info->device_name,
2542 status0, dmastatus0, timerstatus0);
2543
2544 if (info->port_count == 4) {
2545 /* get status for SCA1 (ports 2-3) */
2546 tmp = read_reg16(info->port_array[2], ISR0);
2547 status1 = (unsigned char)tmp;
2548 dmastatus1 = (unsigned char)(tmp>>8);
2549 timerstatus1 = read_reg(info->port_array[2], ISR2);
2550
2551 if ( debug_level >= DEBUG_LEVEL_ISR )
2552 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2553 __FILE__,__LINE__,info->device_name,
2554 status1,dmastatus1,timerstatus1);
2555 }
2556
2557 if (!status0 && !dmastatus0 && !timerstatus0 &&
2558 !status1 && !dmastatus1 && !timerstatus1)
2559 break;
2560
2561 for(i=0; i < info->port_count ; i++) {
2562 if (info->port_array[i] == NULL)
2563 continue;
2564 if (i < 2) {
2565 status = status0;
2566 dmastatus = dmastatus0;
2567 } else {
2568 status = status1;
2569 dmastatus = dmastatus1;
2570 }
2571
2572 shift = i & 1 ? 4 :0;
2573
2574 if (status & BIT0 << shift)
2575 isr_rxrdy(info->port_array[i]);
2576 if (status & BIT1 << shift)
2577 isr_txrdy(info->port_array[i]);
2578 if (status & BIT2 << shift)
2579 isr_rxint(info->port_array[i]);
2580 if (status & BIT3 << shift)
2581 isr_txint(info->port_array[i]);
2582
2583 if (dmastatus & BIT0 << shift)
2584 isr_rxdmaerror(info->port_array[i]);
2585 if (dmastatus & BIT1 << shift)
2586 isr_rxdmaok(info->port_array[i]);
2587 if (dmastatus & BIT2 << shift)
2588 isr_txdmaerror(info->port_array[i]);
2589 if (dmastatus & BIT3 << shift)
2590 isr_txdmaok(info->port_array[i]);
2591 }
2592
2593 if (timerstatus0 & (BIT5 | BIT4))
2594 isr_timer(info->port_array[0]);
2595 if (timerstatus0 & (BIT7 | BIT6))
2596 isr_timer(info->port_array[1]);
2597 if (timerstatus1 & (BIT5 | BIT4))
2598 isr_timer(info->port_array[2]);
2599 if (timerstatus1 & (BIT7 | BIT6))
2600 isr_timer(info->port_array[3]);
2601 }
2602
2603 for(i=0; i < info->port_count ; i++) {
2604 SLMP_INFO * port = info->port_array[i];
2605
2606 /* Request bottom half processing if there's something
2607 * for it to do and the bh is not already running.
2608 *
2609 * Note: startup adapter diags require interrupts.
2610 * do not request bottom half processing if the
2611 * device is not open in a normal mode.
2612 */
2613 if ( port && (port->port.count || port->netcount) &&
2614 port->pending_bh && !port->bh_running &&
2615 !port->bh_requested ) {
2616 if ( debug_level >= DEBUG_LEVEL_ISR )
2617 printk("%s(%d):%s queueing bh task.\n",
2618 __FILE__,__LINE__,port->device_name);
2619 schedule_work(&port->task);
2620 port->bh_requested = true;
2621 }
2622 }
2623
2624 spin_unlock(&info->lock);
2625
2626 if ( debug_level >= DEBUG_LEVEL_ISR )
2627 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2628 __FILE__, __LINE__, info->irq_level);
2629 return IRQ_HANDLED;
2630 }
2631
2632 /* Initialize and start device.
2633 */
2634 static int startup(SLMP_INFO * info)
2635 {
2636 if ( debug_level >= DEBUG_LEVEL_INFO )
2637 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2638
2639 if (tty_port_initialized(&info->port))
2640 return 0;
2641
2642 if (!info->tx_buf) {
2643 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2644 if (!info->tx_buf) {
2645 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2646 __FILE__,__LINE__,info->device_name);
2647 return -ENOMEM;
2648 }
2649 }
2650
2651 info->pending_bh = 0;
2652
2653 memset(&info->icount, 0, sizeof(info->icount));
2654
2655 /* program hardware for current parameters */
2656 reset_port(info);
2657
2658 change_params(info);
2659
2660 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2661
2662 if (info->port.tty)
2663 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2664
2665 tty_port_set_initialized(&info->port, 1);
2666
2667 return 0;
2668 }
2669
2670 /* Called by close() and hangup() to shutdown hardware
2671 */
2672 static void shutdown(SLMP_INFO * info)
2673 {
2674 unsigned long flags;
2675
2676 if (!tty_port_initialized(&info->port))
2677 return;
2678
2679 if (debug_level >= DEBUG_LEVEL_INFO)
2680 printk("%s(%d):%s synclinkmp_shutdown()\n",
2681 __FILE__,__LINE__, info->device_name );
2682
2683 /* clear status wait queue because status changes */
2684 /* can't happen after shutting down the hardware */
2685 wake_up_interruptible(&info->status_event_wait_q);
2686 wake_up_interruptible(&info->event_wait_q);
2687
2688 del_timer(&info->tx_timer);
2689 del_timer(&info->status_timer);
2690
2691 kfree(info->tx_buf);
2692 info->tx_buf = NULL;
2693
2694 spin_lock_irqsave(&info->lock,flags);
2695
2696 reset_port(info);
2697
2698 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2699 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2700 set_signals(info);
2701 }
2702
2703 spin_unlock_irqrestore(&info->lock,flags);
2704
2705 if (info->port.tty)
2706 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2707
2708 tty_port_set_initialized(&info->port, 0);
2709 }
2710
2711 static void program_hw(SLMP_INFO *info)
2712 {
2713 unsigned long flags;
2714
2715 spin_lock_irqsave(&info->lock,flags);
2716
2717 rx_stop(info);
2718 tx_stop(info);
2719
2720 info->tx_count = info->tx_put = info->tx_get = 0;
2721
2722 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2723 hdlc_mode(info);
2724 else
2725 async_mode(info);
2726
2727 set_signals(info);
2728
2729 info->dcd_chkcount = 0;
2730 info->cts_chkcount = 0;
2731 info->ri_chkcount = 0;
2732 info->dsr_chkcount = 0;
2733
2734 info->ie1_value |= (CDCD|CCTS);
2735 write_reg(info, IE1, info->ie1_value);
2736
2737 get_signals(info);
2738
2739 if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
2740 rx_start(info);
2741
2742 spin_unlock_irqrestore(&info->lock,flags);
2743 }
2744
2745 /* Reconfigure adapter based on new parameters
2746 */
2747 static void change_params(SLMP_INFO *info)
2748 {
2749 unsigned cflag;
2750 int bits_per_char;
2751
2752 if (!info->port.tty)
2753 return;
2754
2755 if (debug_level >= DEBUG_LEVEL_INFO)
2756 printk("%s(%d):%s change_params()\n",
2757 __FILE__,__LINE__, info->device_name );
2758
2759 cflag = info->port.tty->termios.c_cflag;
2760
2761 /* if B0 rate (hangup) specified then negate RTS and DTR */
2762 /* otherwise assert RTS and DTR */
2763 if (cflag & CBAUD)
2764 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
2765 else
2766 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2767
2768 /* byte size and parity */
2769
2770 switch (cflag & CSIZE) {
2771 case CS5: info->params.data_bits = 5; break;
2772 case CS6: info->params.data_bits = 6; break;
2773 case CS7: info->params.data_bits = 7; break;
2774 case CS8: info->params.data_bits = 8; break;
2775 /* Never happens, but GCC is too dumb to figure it out */
2776 default: info->params.data_bits = 7; break;
2777 }
2778
2779 if (cflag & CSTOPB)
2780 info->params.stop_bits = 2;
2781 else
2782 info->params.stop_bits = 1;
2783
2784 info->params.parity = ASYNC_PARITY_NONE;
2785 if (cflag & PARENB) {
2786 if (cflag & PARODD)
2787 info->params.parity = ASYNC_PARITY_ODD;
2788 else
2789 info->params.parity = ASYNC_PARITY_EVEN;
2790 #ifdef CMSPAR
2791 if (cflag & CMSPAR)
2792 info->params.parity = ASYNC_PARITY_SPACE;
2793 #endif
2794 }
2795
2796 /* calculate number of jiffies to transmit a full
2797 * FIFO (32 bytes) at specified data rate
2798 */
2799 bits_per_char = info->params.data_bits +
2800 info->params.stop_bits + 1;
2801
2802 /* if port data rate is set to 460800 or less then
2803 * allow tty settings to override, otherwise keep the
2804 * current data rate.
2805 */
2806 if (info->params.data_rate <= 460800) {
2807 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2808 }
2809
2810 if ( info->params.data_rate ) {
2811 info->timeout = (32*HZ*bits_per_char) /
2812 info->params.data_rate;
2813 }
2814 info->timeout += HZ/50; /* Add .02 seconds of slop */
2815
2816 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2817 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2818
2819 /* process tty input control flags */
2820
2821 info->read_status_mask2 = OVRN;
2822 if (I_INPCK(info->port.tty))
2823 info->read_status_mask2 |= PE | FRME;
2824 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2825 info->read_status_mask1 |= BRKD;
2826 if (I_IGNPAR(info->port.tty))
2827 info->ignore_status_mask2 |= PE | FRME;
2828 if (I_IGNBRK(info->port.tty)) {
2829 info->ignore_status_mask1 |= BRKD;
2830 /* If ignoring parity and break indicators, ignore
2831 * overruns too. (For real raw support).
2832 */
2833 if (I_IGNPAR(info->port.tty))
2834 info->ignore_status_mask2 |= OVRN;
2835 }
2836
2837 program_hw(info);
2838 }
2839
2840 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2841 {
2842 int err;
2843
2844 if (debug_level >= DEBUG_LEVEL_INFO)
2845 printk("%s(%d):%s get_params()\n",
2846 __FILE__,__LINE__, info->device_name);
2847
2848 if (!user_icount) {
2849 memset(&info->icount, 0, sizeof(info->icount));
2850 } else {
2851 mutex_lock(&info->port.mutex);
2852 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2853 mutex_unlock(&info->port.mutex);
2854 if (err)
2855 return -EFAULT;
2856 }
2857
2858 return 0;
2859 }
2860
2861 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2862 {
2863 int err;
2864 if (debug_level >= DEBUG_LEVEL_INFO)
2865 printk("%s(%d):%s get_params()\n",
2866 __FILE__,__LINE__, info->device_name);
2867
2868 mutex_lock(&info->port.mutex);
2869 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2870 mutex_unlock(&info->port.mutex);
2871 if (err) {
2872 if ( debug_level >= DEBUG_LEVEL_INFO )
2873 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2874 __FILE__,__LINE__,info->device_name);
2875 return -EFAULT;
2876 }
2877
2878 return 0;
2879 }
2880
2881 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2882 {
2883 unsigned long flags;
2884 MGSL_PARAMS tmp_params;
2885 int err;
2886
2887 if (debug_level >= DEBUG_LEVEL_INFO)
2888 printk("%s(%d):%s set_params\n",
2889 __FILE__,__LINE__,info->device_name );
2890 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2891 if (err) {
2892 if ( debug_level >= DEBUG_LEVEL_INFO )
2893 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2894 __FILE__,__LINE__,info->device_name);
2895 return -EFAULT;
2896 }
2897
2898 mutex_lock(&info->port.mutex);
2899 spin_lock_irqsave(&info->lock,flags);
2900 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2901 spin_unlock_irqrestore(&info->lock,flags);
2902
2903 change_params(info);
2904 mutex_unlock(&info->port.mutex);
2905
2906 return 0;
2907 }
2908
2909 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2910 {
2911 int err;
2912
2913 if (debug_level >= DEBUG_LEVEL_INFO)
2914 printk("%s(%d):%s get_txidle()=%d\n",
2915 __FILE__,__LINE__, info->device_name, info->idle_mode);
2916
2917 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2918 if (err) {
2919 if ( debug_level >= DEBUG_LEVEL_INFO )
2920 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2921 __FILE__,__LINE__,info->device_name);
2922 return -EFAULT;
2923 }
2924
2925 return 0;
2926 }
2927
2928 static int set_txidle(SLMP_INFO * info, int idle_mode)
2929 {
2930 unsigned long flags;
2931
2932 if (debug_level >= DEBUG_LEVEL_INFO)
2933 printk("%s(%d):%s set_txidle(%d)\n",
2934 __FILE__,__LINE__,info->device_name, idle_mode );
2935
2936 spin_lock_irqsave(&info->lock,flags);
2937 info->idle_mode = idle_mode;
2938 tx_set_idle( info );
2939 spin_unlock_irqrestore(&info->lock,flags);
2940 return 0;
2941 }
2942
2943 static int tx_enable(SLMP_INFO * info, int enable)
2944 {
2945 unsigned long flags;
2946
2947 if (debug_level >= DEBUG_LEVEL_INFO)
2948 printk("%s(%d):%s tx_enable(%d)\n",
2949 __FILE__,__LINE__,info->device_name, enable);
2950
2951 spin_lock_irqsave(&info->lock,flags);
2952 if ( enable ) {
2953 if ( !info->tx_enabled ) {
2954 tx_start(info);
2955 }
2956 } else {
2957 if ( info->tx_enabled )
2958 tx_stop(info);
2959 }
2960 spin_unlock_irqrestore(&info->lock,flags);
2961 return 0;
2962 }
2963
2964 /* abort send HDLC frame
2965 */
2966 static int tx_abort(SLMP_INFO * info)
2967 {
2968 unsigned long flags;
2969
2970 if (debug_level >= DEBUG_LEVEL_INFO)
2971 printk("%s(%d):%s tx_abort()\n",
2972 __FILE__,__LINE__,info->device_name);
2973
2974 spin_lock_irqsave(&info->lock,flags);
2975 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2976 info->ie1_value &= ~UDRN;
2977 info->ie1_value |= IDLE;
2978 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
2979 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
2980
2981 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
2982 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2983
2984 write_reg(info, CMD, TXABORT);
2985 }
2986 spin_unlock_irqrestore(&info->lock,flags);
2987 return 0;
2988 }
2989
2990 static int rx_enable(SLMP_INFO * info, int enable)
2991 {
2992 unsigned long flags;
2993
2994 if (debug_level >= DEBUG_LEVEL_INFO)
2995 printk("%s(%d):%s rx_enable(%d)\n",
2996 __FILE__,__LINE__,info->device_name,enable);
2997
2998 spin_lock_irqsave(&info->lock,flags);
2999 if ( enable ) {
3000 if ( !info->rx_enabled )
3001 rx_start(info);
3002 } else {
3003 if ( info->rx_enabled )
3004 rx_stop(info);
3005 }
3006 spin_unlock_irqrestore(&info->lock,flags);
3007 return 0;
3008 }
3009
3010 /* wait for specified event to occur
3011 */
3012 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3013 {
3014 unsigned long flags;
3015 int s;
3016 int rc=0;
3017 struct mgsl_icount cprev, cnow;
3018 int events;
3019 int mask;
3020 struct _input_signal_events oldsigs, newsigs;
3021 DECLARE_WAITQUEUE(wait, current);
3022
3023 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3024 if (rc) {
3025 return -EFAULT;
3026 }
3027
3028 if (debug_level >= DEBUG_LEVEL_INFO)
3029 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3030 __FILE__,__LINE__,info->device_name,mask);
3031
3032 spin_lock_irqsave(&info->lock,flags);
3033
3034 /* return immediately if state matches requested events */
3035 get_signals(info);
3036 s = info->serial_signals;
3037
3038 events = mask &
3039 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3040 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3041 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3042 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3043 if (events) {
3044 spin_unlock_irqrestore(&info->lock,flags);
3045 goto exit;
3046 }
3047
3048 /* save current irq counts */
3049 cprev = info->icount;
3050 oldsigs = info->input_signal_events;
3051
3052 /* enable hunt and idle irqs if needed */
3053 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3054 unsigned char oldval = info->ie1_value;
3055 unsigned char newval = oldval +
3056 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3057 (mask & MgslEvent_IdleReceived ? IDLD:0);
3058 if ( oldval != newval ) {
3059 info->ie1_value = newval;
3060 write_reg(info, IE1, info->ie1_value);
3061 }
3062 }
3063
3064 set_current_state(TASK_INTERRUPTIBLE);
3065 add_wait_queue(&info->event_wait_q, &wait);
3066
3067 spin_unlock_irqrestore(&info->lock,flags);
3068
3069 for(;;) {
3070 schedule();
3071 if (signal_pending(current)) {
3072 rc = -ERESTARTSYS;
3073 break;
3074 }
3075
3076 /* get current irq counts */
3077 spin_lock_irqsave(&info->lock,flags);
3078 cnow = info->icount;
3079 newsigs = info->input_signal_events;
3080 set_current_state(TASK_INTERRUPTIBLE);
3081 spin_unlock_irqrestore(&info->lock,flags);
3082
3083 /* if no change, wait aborted for some reason */
3084 if (newsigs.dsr_up == oldsigs.dsr_up &&
3085 newsigs.dsr_down == oldsigs.dsr_down &&
3086 newsigs.dcd_up == oldsigs.dcd_up &&
3087 newsigs.dcd_down == oldsigs.dcd_down &&
3088 newsigs.cts_up == oldsigs.cts_up &&
3089 newsigs.cts_down == oldsigs.cts_down &&
3090 newsigs.ri_up == oldsigs.ri_up &&
3091 newsigs.ri_down == oldsigs.ri_down &&
3092 cnow.exithunt == cprev.exithunt &&
3093 cnow.rxidle == cprev.rxidle) {
3094 rc = -EIO;
3095 break;
3096 }
3097
3098 events = mask &
3099 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3100 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3101 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3102 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3103 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3104 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3105 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3106 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3107 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3108 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3109 if (events)
3110 break;
3111
3112 cprev = cnow;
3113 oldsigs = newsigs;
3114 }
3115
3116 remove_wait_queue(&info->event_wait_q, &wait);
3117 set_current_state(TASK_RUNNING);
3118
3119
3120 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3121 spin_lock_irqsave(&info->lock,flags);
3122 if (!waitqueue_active(&info->event_wait_q)) {
3123 /* disable enable exit hunt mode/idle rcvd IRQs */
3124 info->ie1_value &= ~(FLGD|IDLD);
3125 write_reg(info, IE1, info->ie1_value);
3126 }
3127 spin_unlock_irqrestore(&info->lock,flags);
3128 }
3129 exit:
3130 if ( rc == 0 )
3131 PUT_USER(rc, events, mask_ptr);
3132
3133 return rc;
3134 }
3135
3136 static int modem_input_wait(SLMP_INFO *info,int arg)
3137 {
3138 unsigned long flags;
3139 int rc;
3140 struct mgsl_icount cprev, cnow;
3141 DECLARE_WAITQUEUE(wait, current);
3142
3143 /* save current irq counts */
3144 spin_lock_irqsave(&info->lock,flags);
3145 cprev = info->icount;
3146 add_wait_queue(&info->status_event_wait_q, &wait);
3147 set_current_state(TASK_INTERRUPTIBLE);
3148 spin_unlock_irqrestore(&info->lock,flags);
3149
3150 for(;;) {
3151 schedule();
3152 if (signal_pending(current)) {
3153 rc = -ERESTARTSYS;
3154 break;
3155 }
3156
3157 /* get new irq counts */
3158 spin_lock_irqsave(&info->lock,flags);
3159 cnow = info->icount;
3160 set_current_state(TASK_INTERRUPTIBLE);
3161 spin_unlock_irqrestore(&info->lock,flags);
3162
3163 /* if no change, wait aborted for some reason */
3164 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3165 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3166 rc = -EIO;
3167 break;
3168 }
3169
3170 /* check for change in caller specified modem input */
3171 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3172 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3173 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3174 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3175 rc = 0;
3176 break;
3177 }
3178
3179 cprev = cnow;
3180 }
3181 remove_wait_queue(&info->status_event_wait_q, &wait);
3182 set_current_state(TASK_RUNNING);
3183 return rc;
3184 }
3185
3186 /* return the state of the serial control and status signals
3187 */
3188 static int tiocmget(struct tty_struct *tty)
3189 {
3190 SLMP_INFO *info = tty->driver_data;
3191 unsigned int result;
3192 unsigned long flags;
3193
3194 spin_lock_irqsave(&info->lock,flags);
3195 get_signals(info);
3196 spin_unlock_irqrestore(&info->lock,flags);
3197
3198 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
3199 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
3200 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
3201 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) |
3202 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
3203 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
3204
3205 if (debug_level >= DEBUG_LEVEL_INFO)
3206 printk("%s(%d):%s tiocmget() value=%08X\n",
3207 __FILE__,__LINE__, info->device_name, result );
3208 return result;
3209 }
3210
3211 /* set modem control signals (DTR/RTS)
3212 */
3213 static int tiocmset(struct tty_struct *tty,
3214 unsigned int set, unsigned int clear)
3215 {
3216 SLMP_INFO *info = tty->driver_data;
3217 unsigned long flags;
3218
3219 if (debug_level >= DEBUG_LEVEL_INFO)
3220 printk("%s(%d):%s tiocmset(%x,%x)\n",
3221 __FILE__,__LINE__,info->device_name, set, clear);
3222
3223 if (set & TIOCM_RTS)
3224 info->serial_signals |= SerialSignal_RTS;
3225 if (set & TIOCM_DTR)
3226 info->serial_signals |= SerialSignal_DTR;
3227 if (clear & TIOCM_RTS)
3228 info->serial_signals &= ~SerialSignal_RTS;
3229 if (clear & TIOCM_DTR)
3230 info->serial_signals &= ~SerialSignal_DTR;
3231
3232 spin_lock_irqsave(&info->lock,flags);
3233 set_signals(info);
3234 spin_unlock_irqrestore(&info->lock,flags);
3235
3236 return 0;
3237 }
3238
3239 static int carrier_raised(struct tty_port *port)
3240 {
3241 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3242 unsigned long flags;
3243
3244 spin_lock_irqsave(&info->lock,flags);
3245 get_signals(info);
3246 spin_unlock_irqrestore(&info->lock,flags);
3247
3248 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3249 }
3250
3251 static void dtr_rts(struct tty_port *port, int on)
3252 {
3253 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3254 unsigned long flags;
3255
3256 spin_lock_irqsave(&info->lock,flags);
3257 if (on)
3258 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3259 else
3260 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3261 set_signals(info);
3262 spin_unlock_irqrestore(&info->lock,flags);
3263 }
3264
3265 /* Block the current process until the specified port is ready to open.
3266 */
3267 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3268 SLMP_INFO *info)
3269 {
3270 DECLARE_WAITQUEUE(wait, current);
3271 int retval;
3272 bool do_clocal = false;
3273 unsigned long flags;
3274 int cd;
3275 struct tty_port *port = &info->port;
3276
3277 if (debug_level >= DEBUG_LEVEL_INFO)
3278 printk("%s(%d):%s block_til_ready()\n",
3279 __FILE__,__LINE__, tty->driver->name );
3280
3281 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3282 /* nonblock mode is set or port is not enabled */
3283 /* just verify that callout device is not active */
3284 tty_port_set_active(port, 1);
3285 return 0;
3286 }
3287
3288 if (C_CLOCAL(tty))
3289 do_clocal = true;
3290
3291 /* Wait for carrier detect and the line to become
3292 * free (i.e., not in use by the callout). While we are in
3293 * this loop, port->count is dropped by one, so that
3294 * close() knows when to free things. We restore it upon
3295 * exit, either normal or abnormal.
3296 */
3297
3298 retval = 0;
3299 add_wait_queue(&port->open_wait, &wait);
3300
3301 if (debug_level >= DEBUG_LEVEL_INFO)
3302 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3303 __FILE__,__LINE__, tty->driver->name, port->count );
3304
3305 spin_lock_irqsave(&info->lock, flags);
3306 port->count--;
3307 spin_unlock_irqrestore(&info->lock, flags);
3308 port->blocked_open++;
3309
3310 while (1) {
3311 if (C_BAUD(tty) && tty_port_initialized(port))
3312 tty_port_raise_dtr_rts(port);
3313
3314 set_current_state(TASK_INTERRUPTIBLE);
3315
3316 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3317 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3318 -EAGAIN : -ERESTARTSYS;
3319 break;
3320 }
3321
3322 cd = tty_port_carrier_raised(port);
3323 if (do_clocal || cd)
3324 break;
3325
3326 if (signal_pending(current)) {
3327 retval = -ERESTARTSYS;
3328 break;
3329 }
3330
3331 if (debug_level >= DEBUG_LEVEL_INFO)
3332 printk("%s(%d):%s block_til_ready() count=%d\n",
3333 __FILE__,__LINE__, tty->driver->name, port->count );
3334
3335 tty_unlock(tty);
3336 schedule();
3337 tty_lock(tty);
3338 }
3339
3340 set_current_state(TASK_RUNNING);
3341 remove_wait_queue(&port->open_wait, &wait);
3342 if (!tty_hung_up_p(filp))
3343 port->count++;
3344 port->blocked_open--;
3345
3346 if (debug_level >= DEBUG_LEVEL_INFO)
3347 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3348 __FILE__,__LINE__, tty->driver->name, port->count );
3349
3350 if (!retval)
3351 tty_port_set_active(port, 1);
3352
3353 return retval;
3354 }
3355
3356 static int alloc_dma_bufs(SLMP_INFO *info)
3357 {
3358 unsigned short BuffersPerFrame;
3359 unsigned short BufferCount;
3360
3361 // Force allocation to start at 64K boundary for each port.
3362 // This is necessary because *all* buffer descriptors for a port
3363 // *must* be in the same 64K block. All descriptors on a port
3364 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3365 // into the CBP register.
3366 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3367
3368 /* Calculate the number of DMA buffers necessary to hold the */
3369 /* largest allowable frame size. Note: If the max frame size is */
3370 /* not an even multiple of the DMA buffer size then we need to */
3371 /* round the buffer count per frame up one. */
3372
3373 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3374 if ( info->max_frame_size % SCABUFSIZE )
3375 BuffersPerFrame++;
3376
3377 /* calculate total number of data buffers (SCABUFSIZE) possible
3378 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3379 * for the descriptor list (BUFFERLISTSIZE).
3380 */
3381 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3382
3383 /* limit number of buffers to maximum amount of descriptors */
3384 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3385 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3386
3387 /* use enough buffers to transmit one max size frame */
3388 info->tx_buf_count = BuffersPerFrame + 1;
3389
3390 /* never use more than half the available buffers for transmit */
3391 if (info->tx_buf_count > (BufferCount/2))
3392 info->tx_buf_count = BufferCount/2;
3393
3394 if (info->tx_buf_count > SCAMAXDESC)
3395 info->tx_buf_count = SCAMAXDESC;
3396
3397 /* use remaining buffers for receive */
3398 info->rx_buf_count = BufferCount - info->tx_buf_count;
3399
3400 if (info->rx_buf_count > SCAMAXDESC)
3401 info->rx_buf_count = SCAMAXDESC;
3402
3403 if ( debug_level >= DEBUG_LEVEL_INFO )
3404 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3405 __FILE__,__LINE__, info->device_name,
3406 info->tx_buf_count,info->rx_buf_count);
3407
3408 if ( alloc_buf_list( info ) < 0 ||
3409 alloc_frame_bufs(info,
3410 info->rx_buf_list,
3411 info->rx_buf_list_ex,
3412 info->rx_buf_count) < 0 ||
3413 alloc_frame_bufs(info,
3414 info->tx_buf_list,
3415 info->tx_buf_list_ex,
3416 info->tx_buf_count) < 0 ||
3417 alloc_tmp_rx_buf(info) < 0 ) {
3418 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3419 __FILE__,__LINE__, info->device_name);
3420 return -ENOMEM;
3421 }
3422
3423 rx_reset_buffers( info );
3424
3425 return 0;
3426 }
3427
3428 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3429 */
3430 static int alloc_buf_list(SLMP_INFO *info)
3431 {
3432 unsigned int i;
3433
3434 /* build list in adapter shared memory */
3435 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3436 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3437 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3438
3439 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3440
3441 /* Save virtual address pointers to the receive and */
3442 /* transmit buffer lists. (Receive 1st). These pointers will */
3443 /* be used by the processor to access the lists. */
3444 info->rx_buf_list = (SCADESC *)info->buffer_list;
3445
3446 info->tx_buf_list = (SCADESC *)info->buffer_list;
3447 info->tx_buf_list += info->rx_buf_count;
3448
3449 /* Build links for circular buffer entry lists (tx and rx)
3450 *
3451 * Note: links are physical addresses read by the SCA device
3452 * to determine the next buffer entry to use.
3453 */
3454
3455 for ( i = 0; i < info->rx_buf_count; i++ ) {
3456 /* calculate and store physical address of this buffer entry */
3457 info->rx_buf_list_ex[i].phys_entry =
3458 info->buffer_list_phys + (i * SCABUFSIZE);
3459
3460 /* calculate and store physical address of */
3461 /* next entry in cirular list of entries */
3462 info->rx_buf_list[i].next = info->buffer_list_phys;
3463 if ( i < info->rx_buf_count - 1 )
3464 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3465
3466 info->rx_buf_list[i].length = SCABUFSIZE;
3467 }
3468
3469 for ( i = 0; i < info->tx_buf_count; i++ ) {
3470 /* calculate and store physical address of this buffer entry */
3471 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3472 ((info->rx_buf_count + i) * sizeof(SCADESC));
3473
3474 /* calculate and store physical address of */
3475 /* next entry in cirular list of entries */
3476
3477 info->tx_buf_list[i].next = info->buffer_list_phys +
3478 info->rx_buf_count * sizeof(SCADESC);
3479
3480 if ( i < info->tx_buf_count - 1 )
3481 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3482 }
3483
3484 return 0;
3485 }
3486
3487 /* Allocate the frame DMA buffers used by the specified buffer list.
3488 */
3489 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3490 {
3491 int i;
3492 unsigned long phys_addr;
3493
3494 for ( i = 0; i < count; i++ ) {
3495 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3496 phys_addr = info->port_array[0]->last_mem_alloc;
3497 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3498
3499 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3500 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3501 }
3502
3503 return 0;
3504 }
3505
3506 static void free_dma_bufs(SLMP_INFO *info)
3507 {
3508 info->buffer_list = NULL;
3509 info->rx_buf_list = NULL;
3510 info->tx_buf_list = NULL;
3511 }
3512
3513 /* allocate buffer large enough to hold max_frame_size.
3514 * This buffer is used to pass an assembled frame to the line discipline.
3515 */
3516 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3517 {
3518 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3519 if (info->tmp_rx_buf == NULL)
3520 return -ENOMEM;
3521 /* unused flag buffer to satisfy receive_buf calling interface */
3522 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3523 if (!info->flag_buf) {
3524 kfree(info->tmp_rx_buf);
3525 info->tmp_rx_buf = NULL;
3526 return -ENOMEM;
3527 }
3528 return 0;
3529 }
3530
3531 static void free_tmp_rx_buf(SLMP_INFO *info)
3532 {
3533 kfree(info->tmp_rx_buf);
3534 info->tmp_rx_buf = NULL;
3535 kfree(info->flag_buf);
3536 info->flag_buf = NULL;
3537 }
3538
3539 static int claim_resources(SLMP_INFO *info)
3540 {
3541 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3542 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3543 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3544 info->init_error = DiagStatus_AddressConflict;
3545 goto errout;
3546 }
3547 else
3548 info->shared_mem_requested = true;
3549
3550 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3551 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3552 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3553 info->init_error = DiagStatus_AddressConflict;
3554 goto errout;
3555 }
3556 else
3557 info->lcr_mem_requested = true;
3558
3559 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3560 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3561 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3562 info->init_error = DiagStatus_AddressConflict;
3563 goto errout;
3564 }
3565 else
3566 info->sca_base_requested = true;
3567
3568 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3569 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3570 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3571 info->init_error = DiagStatus_AddressConflict;
3572 goto errout;
3573 }
3574 else
3575 info->sca_statctrl_requested = true;
3576
3577 info->memory_base = ioremap_nocache(info->phys_memory_base,
3578 SCA_MEM_SIZE);
3579 if (!info->memory_base) {
3580 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3581 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3582 info->init_error = DiagStatus_CantAssignPciResources;
3583 goto errout;
3584 }
3585
3586 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3587 if (!info->lcr_base) {
3588 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3589 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3590 info->init_error = DiagStatus_CantAssignPciResources;
3591 goto errout;
3592 }
3593 info->lcr_base += info->lcr_offset;
3594
3595 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3596 if (!info->sca_base) {
3597 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3598 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3599 info->init_error = DiagStatus_CantAssignPciResources;
3600 goto errout;
3601 }
3602 info->sca_base += info->sca_offset;
3603
3604 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3605 PAGE_SIZE);
3606 if (!info->statctrl_base) {
3607 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3608 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3609 info->init_error = DiagStatus_CantAssignPciResources;
3610 goto errout;
3611 }
3612 info->statctrl_base += info->statctrl_offset;
3613
3614 if ( !memory_test(info) ) {
3615 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3616 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3617 info->init_error = DiagStatus_MemoryError;
3618 goto errout;
3619 }
3620
3621 return 0;
3622
3623 errout:
3624 release_resources( info );
3625 return -ENODEV;
3626 }
3627
3628 static void release_resources(SLMP_INFO *info)
3629 {
3630 if ( debug_level >= DEBUG_LEVEL_INFO )
3631 printk( "%s(%d):%s release_resources() entry\n",
3632 __FILE__,__LINE__,info->device_name );
3633
3634 if ( info->irq_requested ) {
3635 free_irq(info->irq_level, info);
3636 info->irq_requested = false;
3637 }
3638
3639 if ( info->shared_mem_requested ) {
3640 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3641 info->shared_mem_requested = false;
3642 }
3643 if ( info->lcr_mem_requested ) {
3644 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3645 info->lcr_mem_requested = false;
3646 }
3647 if ( info->sca_base_requested ) {
3648 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3649 info->sca_base_requested = false;
3650 }
3651 if ( info->sca_statctrl_requested ) {
3652 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3653 info->sca_statctrl_requested = false;
3654 }
3655
3656 if (info->memory_base){
3657 iounmap(info->memory_base);
3658 info->memory_base = NULL;
3659 }
3660
3661 if (info->sca_base) {
3662 iounmap(info->sca_base - info->sca_offset);
3663 info->sca_base=NULL;
3664 }
3665
3666 if (info->statctrl_base) {
3667 iounmap(info->statctrl_base - info->statctrl_offset);
3668 info->statctrl_base=NULL;
3669 }
3670
3671 if (info->lcr_base){
3672 iounmap(info->lcr_base - info->lcr_offset);
3673 info->lcr_base = NULL;
3674 }
3675
3676 if ( debug_level >= DEBUG_LEVEL_INFO )
3677 printk( "%s(%d):%s release_resources() exit\n",
3678 __FILE__,__LINE__,info->device_name );
3679 }
3680
3681 /* Add the specified device instance data structure to the
3682 * global linked list of devices and increment the device count.
3683 */
3684 static int add_device(SLMP_INFO *info)
3685 {
3686 info->next_device = NULL;
3687 info->line = synclinkmp_device_count;
3688 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3689
3690 if (info->line < MAX_DEVICES) {
3691 if (maxframe[info->line])
3692 info->max_frame_size = maxframe[info->line];
3693 }
3694
3695 synclinkmp_device_count++;
3696
3697 if ( !synclinkmp_device_list )
3698 synclinkmp_device_list = info;
3699 else {
3700 SLMP_INFO *current_dev = synclinkmp_device_list;
3701 while( current_dev->next_device )
3702 current_dev = current_dev->next_device;
3703 current_dev->next_device = info;
3704 }
3705
3706 if ( info->max_frame_size < 4096 )
3707 info->max_frame_size = 4096;
3708 else if ( info->max_frame_size > 65535 )
3709 info->max_frame_size = 65535;
3710
3711 printk( "SyncLink MultiPort %s: "
3712 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3713 info->device_name,
3714 info->phys_sca_base,
3715 info->phys_memory_base,
3716 info->phys_statctrl_base,
3717 info->phys_lcr_base,
3718 info->irq_level,
3719 info->max_frame_size );
3720
3721 #if SYNCLINK_GENERIC_HDLC
3722 return hdlcdev_init(info);
3723 #else
3724 return 0;
3725 #endif
3726 }
3727
3728 static const struct tty_port_operations port_ops = {
3729 .carrier_raised = carrier_raised,
3730 .dtr_rts = dtr_rts,
3731 };
3732
3733 /* Allocate and initialize a device instance structure
3734 *
3735 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3736 */
3737 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3738 {
3739 SLMP_INFO *info;
3740
3741 info = kzalloc(sizeof(SLMP_INFO),
3742 GFP_KERNEL);
3743
3744 if (!info) {
3745 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3746 __FILE__,__LINE__, adapter_num, port_num);
3747 } else {
3748 tty_port_init(&info->port);
3749 info->port.ops = &port_ops;
3750 info->magic = MGSL_MAGIC;
3751 INIT_WORK(&info->task, bh_handler);
3752 info->max_frame_size = 4096;
3753 info->port.close_delay = 5*HZ/10;
3754 info->port.closing_wait = 30*HZ;
3755 init_waitqueue_head(&info->status_event_wait_q);
3756 init_waitqueue_head(&info->event_wait_q);
3757 spin_lock_init(&info->netlock);
3758 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3759 info->idle_mode = HDLC_TXIDLE_FLAGS;
3760 info->adapter_num = adapter_num;
3761 info->port_num = port_num;
3762
3763 /* Copy configuration info to device instance data */
3764 info->irq_level = pdev->irq;
3765 info->phys_lcr_base = pci_resource_start(pdev,0);
3766 info->phys_sca_base = pci_resource_start(pdev,2);
3767 info->phys_memory_base = pci_resource_start(pdev,3);
3768 info->phys_statctrl_base = pci_resource_start(pdev,4);
3769
3770 /* Because veremap only works on page boundaries we must map
3771 * a larger area than is actually implemented for the LCR
3772 * memory range. We map a full page starting at the page boundary.
3773 */
3774 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3775 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3776
3777 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3778 info->phys_sca_base &= ~(PAGE_SIZE-1);
3779
3780 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3781 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3782
3783 info->bus_type = MGSL_BUS_TYPE_PCI;
3784 info->irq_flags = IRQF_SHARED;
3785
3786 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3787 setup_timer(&info->status_timer, status_timeout,
3788 (unsigned long)info);
3789
3790 /* Store the PCI9050 misc control register value because a flaw
3791 * in the PCI9050 prevents LCR registers from being read if
3792 * BIOS assigns an LCR base address with bit 7 set.
3793 *
3794 * Only the misc control register is accessed for which only
3795 * write access is needed, so set an initial value and change
3796 * bits to the device instance data as we write the value
3797 * to the actual misc control register.
3798 */
3799 info->misc_ctrl_value = 0x087e4546;
3800
3801 /* initial port state is unknown - if startup errors
3802 * occur, init_error will be set to indicate the
3803 * problem. Once the port is fully initialized,
3804 * this value will be set to 0 to indicate the
3805 * port is available.
3806 */
3807 info->init_error = -1;
3808 }
3809
3810 return info;
3811 }
3812
3813 static int device_init(int adapter_num, struct pci_dev *pdev)
3814 {
3815 SLMP_INFO *port_array[SCA_MAX_PORTS];
3816 int port, rc;
3817
3818 /* allocate device instances for up to SCA_MAX_PORTS devices */
3819 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3820 port_array[port] = alloc_dev(adapter_num,port,pdev);
3821 if( port_array[port] == NULL ) {
3822 for (--port; port >= 0; --port) {
3823 tty_port_destroy(&port_array[port]->port);
3824 kfree(port_array[port]);
3825 }
3826 return -ENOMEM;
3827 }
3828 }
3829
3830 /* give copy of port_array to all ports and add to device list */
3831 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3832 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3833 rc = add_device( port_array[port] );
3834 if (rc)
3835 goto err_add;
3836 spin_lock_init(&port_array[port]->lock);
3837 }
3838
3839 /* Allocate and claim adapter resources */
3840 if ( !claim_resources(port_array[0]) ) {
3841
3842 alloc_dma_bufs(port_array[0]);
3843
3844 /* copy resource information from first port to others */
3845 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3846 port_array[port]->lock = port_array[0]->lock;
3847 port_array[port]->irq_level = port_array[0]->irq_level;
3848 port_array[port]->memory_base = port_array[0]->memory_base;
3849 port_array[port]->sca_base = port_array[0]->sca_base;
3850 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3851 port_array[port]->lcr_base = port_array[0]->lcr_base;
3852 alloc_dma_bufs(port_array[port]);
3853 }
3854
3855 rc = request_irq(port_array[0]->irq_level,
3856 synclinkmp_interrupt,
3857 port_array[0]->irq_flags,
3858 port_array[0]->device_name,
3859 port_array[0]);
3860 if ( rc ) {
3861 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3862 __FILE__,__LINE__,
3863 port_array[0]->device_name,
3864 port_array[0]->irq_level );
3865 goto err_irq;
3866 }
3867 port_array[0]->irq_requested = true;
3868 adapter_test(port_array[0]);
3869 }
3870 return 0;
3871 err_irq:
3872 release_resources( port_array[0] );
3873 err_add:
3874 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3875 tty_port_destroy(&port_array[port]->port);
3876 kfree(port_array[port]);
3877 }
3878 return rc;
3879 }
3880
3881 static const struct tty_operations ops = {
3882 .install = install,
3883 .open = open,
3884 .close = close,
3885 .write = write,
3886 .put_char = put_char,
3887 .flush_chars = flush_chars,
3888 .write_room = write_room,
3889 .chars_in_buffer = chars_in_buffer,
3890 .flush_buffer = flush_buffer,
3891 .ioctl = ioctl,
3892 .throttle = throttle,
3893 .unthrottle = unthrottle,
3894 .send_xchar = send_xchar,
3895 .break_ctl = set_break,
3896 .wait_until_sent = wait_until_sent,
3897 .set_termios = set_termios,
3898 .stop = tx_hold,
3899 .start = tx_release,
3900 .hangup = hangup,
3901 .tiocmget = tiocmget,
3902 .tiocmset = tiocmset,
3903 .get_icount = get_icount,
3904 .proc_fops = &synclinkmp_proc_fops,
3905 };
3906
3907
3908 static void synclinkmp_cleanup(void)
3909 {
3910 int rc;
3911 SLMP_INFO *info;
3912 SLMP_INFO *tmp;
3913
3914 printk("Unloading %s %s\n", driver_name, driver_version);
3915
3916 if (serial_driver) {
3917 rc = tty_unregister_driver(serial_driver);
3918 if (rc)
3919 printk("%s(%d) failed to unregister tty driver err=%d\n",
3920 __FILE__,__LINE__,rc);
3921 put_tty_driver(serial_driver);
3922 }
3923
3924 /* reset devices */
3925 info = synclinkmp_device_list;
3926 while(info) {
3927 reset_port(info);
3928 info = info->next_device;
3929 }
3930
3931 /* release devices */
3932 info = synclinkmp_device_list;
3933 while(info) {
3934 #if SYNCLINK_GENERIC_HDLC
3935 hdlcdev_exit(info);
3936 #endif
3937 free_dma_bufs(info);
3938 free_tmp_rx_buf(info);
3939 if ( info->port_num == 0 ) {
3940 if (info->sca_base)
3941 write_reg(info, LPR, 1); /* set low power mode */
3942 release_resources(info);
3943 }
3944 tmp = info;
3945 info = info->next_device;
3946 tty_port_destroy(&tmp->port);
3947 kfree(tmp);
3948 }
3949
3950 pci_unregister_driver(&synclinkmp_pci_driver);
3951 }
3952
3953 /* Driver initialization entry point.
3954 */
3955
3956 static int __init synclinkmp_init(void)
3957 {
3958 int rc;
3959
3960 if (break_on_load) {
3961 synclinkmp_get_text_ptr();
3962 BREAKPOINT();
3963 }
3964
3965 printk("%s %s\n", driver_name, driver_version);
3966
3967 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3968 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3969 return rc;
3970 }
3971
3972 serial_driver = alloc_tty_driver(128);
3973 if (!serial_driver) {
3974 rc = -ENOMEM;
3975 goto error;
3976 }
3977
3978 /* Initialize the tty_driver structure */
3979
3980 serial_driver->driver_name = "synclinkmp";
3981 serial_driver->name = "ttySLM";
3982 serial_driver->major = ttymajor;
3983 serial_driver->minor_start = 64;
3984 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3985 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3986 serial_driver->init_termios = tty_std_termios;
3987 serial_driver->init_termios.c_cflag =
3988 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3989 serial_driver->init_termios.c_ispeed = 9600;
3990 serial_driver->init_termios.c_ospeed = 9600;
3991 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3992 tty_set_operations(serial_driver, &ops);
3993 if ((rc = tty_register_driver(serial_driver)) < 0) {
3994 printk("%s(%d):Couldn't register serial driver\n",
3995 __FILE__,__LINE__);
3996 put_tty_driver(serial_driver);
3997 serial_driver = NULL;
3998 goto error;
3999 }
4000
4001 printk("%s %s, tty major#%d\n",
4002 driver_name, driver_version,
4003 serial_driver->major);
4004
4005 return 0;
4006
4007 error:
4008 synclinkmp_cleanup();
4009 return rc;
4010 }
4011
4012 static void __exit synclinkmp_exit(void)
4013 {
4014 synclinkmp_cleanup();
4015 }
4016
4017 module_init(synclinkmp_init);
4018 module_exit(synclinkmp_exit);
4019
4020 /* Set the port for internal loopback mode.
4021 * The TxCLK and RxCLK signals are generated from the BRG and
4022 * the TxD is looped back to the RxD internally.
4023 */
4024 static void enable_loopback(SLMP_INFO *info, int enable)
4025 {
4026 if (enable) {
4027 /* MD2 (Mode Register 2)
4028 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4029 */
4030 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4031
4032 /* degate external TxC clock source */
4033 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4034 write_control_reg(info);
4035
4036 /* RXS/TXS (Rx/Tx clock source)
4037 * 07 Reserved, must be 0
4038 * 06..04 Clock Source, 100=BRG
4039 * 03..00 Clock Divisor, 0000=1
4040 */
4041 write_reg(info, RXS, 0x40);
4042 write_reg(info, TXS, 0x40);
4043
4044 } else {
4045 /* MD2 (Mode Register 2)
4046 * 01..00 CNCT<1..0> Channel connection, 0=normal
4047 */
4048 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4049
4050 /* RXS/TXS (Rx/Tx clock source)
4051 * 07 Reserved, must be 0
4052 * 06..04 Clock Source, 000=RxC/TxC Pin
4053 * 03..00 Clock Divisor, 0000=1
4054 */
4055 write_reg(info, RXS, 0x00);
4056 write_reg(info, TXS, 0x00);
4057 }
4058
4059 /* set LinkSpeed if available, otherwise default to 2Mbps */
4060 if (info->params.clock_speed)
4061 set_rate(info, info->params.clock_speed);
4062 else
4063 set_rate(info, 3686400);
4064 }
4065
4066 /* Set the baud rate register to the desired speed
4067 *
4068 * data_rate data rate of clock in bits per second
4069 * A data rate of 0 disables the AUX clock.
4070 */
4071 static void set_rate( SLMP_INFO *info, u32 data_rate )
4072 {
4073 u32 TMCValue;
4074 unsigned char BRValue;
4075 u32 Divisor=0;
4076
4077 /* fBRG = fCLK/(TMC * 2^BR)
4078 */
4079 if (data_rate != 0) {
4080 Divisor = 14745600/data_rate;
4081 if (!Divisor)
4082 Divisor = 1;
4083
4084 TMCValue = Divisor;
4085
4086 BRValue = 0;
4087 if (TMCValue != 1 && TMCValue != 2) {
4088 /* BRValue of 0 provides 50/50 duty cycle *only* when
4089 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4090 * 50/50 duty cycle.
4091 */
4092 BRValue = 1;
4093 TMCValue >>= 1;
4094 }
4095
4096 /* while TMCValue is too big for TMC register, divide
4097 * by 2 and increment BR exponent.
4098 */
4099 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4100 TMCValue >>= 1;
4101
4102 write_reg(info, TXS,
4103 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4104 write_reg(info, RXS,
4105 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4106 write_reg(info, TMC, (unsigned char)TMCValue);
4107 }
4108 else {
4109 write_reg(info, TXS,0);
4110 write_reg(info, RXS,0);
4111 write_reg(info, TMC, 0);
4112 }
4113 }
4114
4115 /* Disable receiver
4116 */
4117 static void rx_stop(SLMP_INFO *info)
4118 {
4119 if (debug_level >= DEBUG_LEVEL_ISR)
4120 printk("%s(%d):%s rx_stop()\n",
4121 __FILE__,__LINE__, info->device_name );
4122
4123 write_reg(info, CMD, RXRESET);
4124
4125 info->ie0_value &= ~RXRDYE;
4126 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4127
4128 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4129 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4130 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4131
4132 info->rx_enabled = false;
4133 info->rx_overflow = false;
4134 }
4135
4136 /* enable the receiver
4137 */
4138 static void rx_start(SLMP_INFO *info)
4139 {
4140 int i;
4141
4142 if (debug_level >= DEBUG_LEVEL_ISR)
4143 printk("%s(%d):%s rx_start()\n",
4144 __FILE__,__LINE__, info->device_name );
4145
4146 write_reg(info, CMD, RXRESET);
4147
4148 if ( info->params.mode == MGSL_MODE_HDLC ) {
4149 /* HDLC, disabe IRQ on rxdata */
4150 info->ie0_value &= ~RXRDYE;
4151 write_reg(info, IE0, info->ie0_value);
4152
4153 /* Reset all Rx DMA buffers and program rx dma */
4154 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4155 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4156
4157 for (i = 0; i < info->rx_buf_count; i++) {
4158 info->rx_buf_list[i].status = 0xff;
4159
4160 // throttle to 4 shared memory writes at a time to prevent
4161 // hogging local bus (keep latency time for DMA requests low).
4162 if (!(i % 4))
4163 read_status_reg(info);
4164 }
4165 info->current_rx_buf = 0;
4166
4167 /* set current/1st descriptor address */
4168 write_reg16(info, RXDMA + CDA,
4169 info->rx_buf_list_ex[0].phys_entry);
4170
4171 /* set new last rx descriptor address */
4172 write_reg16(info, RXDMA + EDA,
4173 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4174
4175 /* set buffer length (shared by all rx dma data buffers) */
4176 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4177
4178 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4179 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4180 } else {
4181 /* async, enable IRQ on rxdata */
4182 info->ie0_value |= RXRDYE;
4183 write_reg(info, IE0, info->ie0_value);
4184 }
4185
4186 write_reg(info, CMD, RXENABLE);
4187
4188 info->rx_overflow = false;
4189 info->rx_enabled = true;
4190 }
4191
4192 /* Enable the transmitter and send a transmit frame if
4193 * one is loaded in the DMA buffers.
4194 */
4195 static void tx_start(SLMP_INFO *info)
4196 {
4197 if (debug_level >= DEBUG_LEVEL_ISR)
4198 printk("%s(%d):%s tx_start() tx_count=%d\n",
4199 __FILE__,__LINE__, info->device_name,info->tx_count );
4200
4201 if (!info->tx_enabled ) {
4202 write_reg(info, CMD, TXRESET);
4203 write_reg(info, CMD, TXENABLE);
4204 info->tx_enabled = true;
4205 }
4206
4207 if ( info->tx_count ) {
4208
4209 /* If auto RTS enabled and RTS is inactive, then assert */
4210 /* RTS and set a flag indicating that the driver should */
4211 /* negate RTS when the transmission completes. */
4212
4213 info->drop_rts_on_tx_done = false;
4214
4215 if (info->params.mode != MGSL_MODE_ASYNC) {
4216
4217 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4218 get_signals( info );
4219 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4220 info->serial_signals |= SerialSignal_RTS;
4221 set_signals( info );
4222 info->drop_rts_on_tx_done = true;
4223 }
4224 }
4225
4226 write_reg16(info, TRC0,
4227 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4228
4229 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4230 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4231
4232 /* set TX CDA (current descriptor address) */
4233 write_reg16(info, TXDMA + CDA,
4234 info->tx_buf_list_ex[0].phys_entry);
4235
4236 /* set TX EDA (last descriptor address) */
4237 write_reg16(info, TXDMA + EDA,
4238 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4239
4240 /* enable underrun IRQ */
4241 info->ie1_value &= ~IDLE;
4242 info->ie1_value |= UDRN;
4243 write_reg(info, IE1, info->ie1_value);
4244 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4245
4246 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4247 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4248
4249 mod_timer(&info->tx_timer, jiffies +
4250 msecs_to_jiffies(5000));
4251 }
4252 else {
4253 tx_load_fifo(info);
4254 /* async, enable IRQ on txdata */
4255 info->ie0_value |= TXRDYE;
4256 write_reg(info, IE0, info->ie0_value);
4257 }
4258
4259 info->tx_active = true;
4260 }
4261 }
4262
4263 /* stop the transmitter and DMA
4264 */
4265 static void tx_stop( SLMP_INFO *info )
4266 {
4267 if (debug_level >= DEBUG_LEVEL_ISR)
4268 printk("%s(%d):%s tx_stop()\n",
4269 __FILE__,__LINE__, info->device_name );
4270
4271 del_timer(&info->tx_timer);
4272
4273 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4274 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4275
4276 write_reg(info, CMD, TXRESET);
4277
4278 info->ie1_value &= ~(UDRN + IDLE);
4279 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4280 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4281
4282 info->ie0_value &= ~TXRDYE;
4283 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4284
4285 info->tx_enabled = false;
4286 info->tx_active = false;
4287 }
4288
4289 /* Fill the transmit FIFO until the FIFO is full or
4290 * there is no more data to load.
4291 */
4292 static void tx_load_fifo(SLMP_INFO *info)
4293 {
4294 u8 TwoBytes[2];
4295
4296 /* do nothing is now tx data available and no XON/XOFF pending */
4297
4298 if ( !info->tx_count && !info->x_char )
4299 return;
4300
4301 /* load the Transmit FIFO until FIFOs full or all data sent */
4302
4303 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4304
4305 /* there is more space in the transmit FIFO and */
4306 /* there is more data in transmit buffer */
4307
4308 if ( (info->tx_count > 1) && !info->x_char ) {
4309 /* write 16-bits */
4310 TwoBytes[0] = info->tx_buf[info->tx_get++];
4311 if (info->tx_get >= info->max_frame_size)
4312 info->tx_get -= info->max_frame_size;
4313 TwoBytes[1] = info->tx_buf[info->tx_get++];
4314 if (info->tx_get >= info->max_frame_size)
4315 info->tx_get -= info->max_frame_size;
4316
4317 write_reg16(info, TRB, *((u16 *)TwoBytes));
4318
4319 info->tx_count -= 2;
4320 info->icount.tx += 2;
4321 } else {
4322 /* only 1 byte left to transmit or 1 FIFO slot left */
4323
4324 if (info->x_char) {
4325 /* transmit pending high priority char */
4326 write_reg(info, TRB, info->x_char);
4327 info->x_char = 0;
4328 } else {
4329 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4330 if (info->tx_get >= info->max_frame_size)
4331 info->tx_get -= info->max_frame_size;
4332 info->tx_count--;
4333 }
4334 info->icount.tx++;
4335 }
4336 }
4337 }
4338
4339 /* Reset a port to a known state
4340 */
4341 static void reset_port(SLMP_INFO *info)
4342 {
4343 if (info->sca_base) {
4344
4345 tx_stop(info);
4346 rx_stop(info);
4347
4348 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4349 set_signals(info);
4350
4351 /* disable all port interrupts */
4352 info->ie0_value = 0;
4353 info->ie1_value = 0;
4354 info->ie2_value = 0;
4355 write_reg(info, IE0, info->ie0_value);
4356 write_reg(info, IE1, info->ie1_value);
4357 write_reg(info, IE2, info->ie2_value);
4358
4359 write_reg(info, CMD, CHRESET);
4360 }
4361 }
4362
4363 /* Reset all the ports to a known state.
4364 */
4365 static void reset_adapter(SLMP_INFO *info)
4366 {
4367 int i;
4368
4369 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4370 if (info->port_array[i])
4371 reset_port(info->port_array[i]);
4372 }
4373 }
4374
4375 /* Program port for asynchronous communications.
4376 */
4377 static void async_mode(SLMP_INFO *info)
4378 {
4379
4380 unsigned char RegValue;
4381
4382 tx_stop(info);
4383 rx_stop(info);
4384
4385 /* MD0, Mode Register 0
4386 *
4387 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4388 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4389 * 03 Reserved, must be 0
4390 * 02 CRCCC, CRC Calculation, 0=disabled
4391 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4392 *
4393 * 0000 0000
4394 */
4395 RegValue = 0x00;
4396 if (info->params.stop_bits != 1)
4397 RegValue |= BIT1;
4398 write_reg(info, MD0, RegValue);
4399
4400 /* MD1, Mode Register 1
4401 *
4402 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4403 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4404 * 03..02 RXCHR<1..0>, rx char size
4405 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4406 *
4407 * 0100 0000
4408 */
4409 RegValue = 0x40;
4410 switch (info->params.data_bits) {
4411 case 7: RegValue |= BIT4 + BIT2; break;
4412 case 6: RegValue |= BIT5 + BIT3; break;
4413 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4414 }
4415 if (info->params.parity != ASYNC_PARITY_NONE) {
4416 RegValue |= BIT1;
4417 if (info->params.parity == ASYNC_PARITY_ODD)
4418 RegValue |= BIT0;
4419 }
4420 write_reg(info, MD1, RegValue);
4421
4422 /* MD2, Mode Register 2
4423 *
4424 * 07..02 Reserved, must be 0
4425 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4426 *
4427 * 0000 0000
4428 */
4429 RegValue = 0x00;
4430 if (info->params.loopback)
4431 RegValue |= (BIT1 + BIT0);
4432 write_reg(info, MD2, RegValue);
4433
4434 /* RXS, Receive clock source
4435 *
4436 * 07 Reserved, must be 0
4437 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4438 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4439 */
4440 RegValue=BIT6;
4441 write_reg(info, RXS, RegValue);
4442
4443 /* TXS, Transmit clock source
4444 *
4445 * 07 Reserved, must be 0
4446 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4447 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4448 */
4449 RegValue=BIT6;
4450 write_reg(info, TXS, RegValue);
4451
4452 /* Control Register
4453 *
4454 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4455 */
4456 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4457 write_control_reg(info);
4458
4459 tx_set_idle(info);
4460
4461 /* RRC Receive Ready Control 0
4462 *
4463 * 07..05 Reserved, must be 0
4464 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4465 */
4466 write_reg(info, RRC, 0x00);
4467
4468 /* TRC0 Transmit Ready Control 0
4469 *
4470 * 07..05 Reserved, must be 0
4471 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4472 */
4473 write_reg(info, TRC0, 0x10);
4474
4475 /* TRC1 Transmit Ready Control 1
4476 *
4477 * 07..05 Reserved, must be 0
4478 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4479 */
4480 write_reg(info, TRC1, 0x1e);
4481
4482 /* CTL, MSCI control register
4483 *
4484 * 07..06 Reserved, set to 0
4485 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4486 * 04 IDLC, idle control, 0=mark 1=idle register
4487 * 03 BRK, break, 0=off 1 =on (async)
4488 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4489 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4490 * 00 RTS, RTS output control, 0=active 1=inactive
4491 *
4492 * 0001 0001
4493 */
4494 RegValue = 0x10;
4495 if (!(info->serial_signals & SerialSignal_RTS))
4496 RegValue |= 0x01;
4497 write_reg(info, CTL, RegValue);
4498
4499 /* enable status interrupts */
4500 info->ie0_value |= TXINTE + RXINTE;
4501 write_reg(info, IE0, info->ie0_value);
4502
4503 /* enable break detect interrupt */
4504 info->ie1_value = BRKD;
4505 write_reg(info, IE1, info->ie1_value);
4506
4507 /* enable rx overrun interrupt */
4508 info->ie2_value = OVRN;
4509 write_reg(info, IE2, info->ie2_value);
4510
4511 set_rate( info, info->params.data_rate * 16 );
4512 }
4513
4514 /* Program the SCA for HDLC communications.
4515 */
4516 static void hdlc_mode(SLMP_INFO *info)
4517 {
4518 unsigned char RegValue;
4519 u32 DpllDivisor;
4520
4521 // Can't use DPLL because SCA outputs recovered clock on RxC when
4522 // DPLL mode selected. This causes output contention with RxC receiver.
4523 // Use of DPLL would require external hardware to disable RxC receiver
4524 // when DPLL mode selected.
4525 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4526
4527 /* disable DMA interrupts */
4528 write_reg(info, TXDMA + DIR, 0);
4529 write_reg(info, RXDMA + DIR, 0);
4530
4531 /* MD0, Mode Register 0
4532 *
4533 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4534 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4535 * 03 Reserved, must be 0
4536 * 02 CRCCC, CRC Calculation, 1=enabled
4537 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4538 * 00 CRC0, CRC initial value, 1 = all 1s
4539 *
4540 * 1000 0001
4541 */
4542 RegValue = 0x81;
4543 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4544 RegValue |= BIT4;
4545 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4546 RegValue |= BIT4;
4547 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4548 RegValue |= BIT2 + BIT1;
4549 write_reg(info, MD0, RegValue);
4550
4551 /* MD1, Mode Register 1
4552 *
4553 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4554 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4555 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4556 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4557 *
4558 * 0000 0000
4559 */
4560 RegValue = 0x00;
4561 write_reg(info, MD1, RegValue);
4562
4563 /* MD2, Mode Register 2
4564 *
4565 * 07 NRZFM, 0=NRZ, 1=FM
4566 * 06..05 CODE<1..0> Encoding, 00=NRZ
4567 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4568 * 02 Reserved, must be 0
4569 * 01..00 CNCT<1..0> Channel connection, 0=normal
4570 *
4571 * 0000 0000
4572 */
4573 RegValue = 0x00;
4574 switch(info->params.encoding) {
4575 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4576 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4577 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4578 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4579 #if 0
4580 case HDLC_ENCODING_NRZB: /* not supported */
4581 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4582 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4583 #endif
4584 }
4585 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4586 DpllDivisor = 16;
4587 RegValue |= BIT3;
4588 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4589 DpllDivisor = 8;
4590 } else {
4591 DpllDivisor = 32;
4592 RegValue |= BIT4;
4593 }
4594 write_reg(info, MD2, RegValue);
4595
4596
4597 /* RXS, Receive clock source
4598 *
4599 * 07 Reserved, must be 0
4600 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4601 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4602 */
4603 RegValue=0;
4604 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4605 RegValue |= BIT6;
4606 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4607 RegValue |= BIT6 + BIT5;
4608 write_reg(info, RXS, RegValue);
4609
4610 /* TXS, Transmit clock source
4611 *
4612 * 07 Reserved, must be 0
4613 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4614 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4615 */
4616 RegValue=0;
4617 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4618 RegValue |= BIT6;
4619 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4620 RegValue |= BIT6 + BIT5;
4621 write_reg(info, TXS, RegValue);
4622
4623 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4624 set_rate(info, info->params.clock_speed * DpllDivisor);
4625 else
4626 set_rate(info, info->params.clock_speed);
4627
4628 /* GPDATA (General Purpose I/O Data Register)
4629 *
4630 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4631 */
4632 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4633 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4634 else
4635 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4636 write_control_reg(info);
4637
4638 /* RRC Receive Ready Control 0
4639 *
4640 * 07..05 Reserved, must be 0
4641 * 04..00 RRC<4..0> Rx FIFO trigger active
4642 */
4643 write_reg(info, RRC, rx_active_fifo_level);
4644
4645 /* TRC0 Transmit Ready Control 0
4646 *
4647 * 07..05 Reserved, must be 0
4648 * 04..00 TRC<4..0> Tx FIFO trigger active
4649 */
4650 write_reg(info, TRC0, tx_active_fifo_level);
4651
4652 /* TRC1 Transmit Ready Control 1
4653 *
4654 * 07..05 Reserved, must be 0
4655 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4656 */
4657 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4658
4659 /* DMR, DMA Mode Register
4660 *
4661 * 07..05 Reserved, must be 0
4662 * 04 TMOD, Transfer Mode: 1=chained-block
4663 * 03 Reserved, must be 0
4664 * 02 NF, Number of Frames: 1=multi-frame
4665 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4666 * 00 Reserved, must be 0
4667 *
4668 * 0001 0100
4669 */
4670 write_reg(info, TXDMA + DMR, 0x14);
4671 write_reg(info, RXDMA + DMR, 0x14);
4672
4673 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4674 write_reg(info, RXDMA + CPB,
4675 (unsigned char)(info->buffer_list_phys >> 16));
4676
4677 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4678 write_reg(info, TXDMA + CPB,
4679 (unsigned char)(info->buffer_list_phys >> 16));
4680
4681 /* enable status interrupts. other code enables/disables
4682 * the individual sources for these two interrupt classes.
4683 */
4684 info->ie0_value |= TXINTE + RXINTE;
4685 write_reg(info, IE0, info->ie0_value);
4686
4687 /* CTL, MSCI control register
4688 *
4689 * 07..06 Reserved, set to 0
4690 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4691 * 04 IDLC, idle control, 0=mark 1=idle register
4692 * 03 BRK, break, 0=off 1 =on (async)
4693 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4694 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4695 * 00 RTS, RTS output control, 0=active 1=inactive
4696 *
4697 * 0001 0001
4698 */
4699 RegValue = 0x10;
4700 if (!(info->serial_signals & SerialSignal_RTS))
4701 RegValue |= 0x01;
4702 write_reg(info, CTL, RegValue);
4703
4704 /* preamble not supported ! */
4705
4706 tx_set_idle(info);
4707 tx_stop(info);
4708 rx_stop(info);
4709
4710 set_rate(info, info->params.clock_speed);
4711
4712 if (info->params.loopback)
4713 enable_loopback(info,1);
4714 }
4715
4716 /* Set the transmit HDLC idle mode
4717 */
4718 static void tx_set_idle(SLMP_INFO *info)
4719 {
4720 unsigned char RegValue = 0xff;
4721
4722 /* Map API idle mode to SCA register bits */
4723 switch(info->idle_mode) {
4724 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4725 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4726 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4727 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4728 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4729 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4730 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4731 }
4732
4733 write_reg(info, IDL, RegValue);
4734 }
4735
4736 /* Query the adapter for the state of the V24 status (input) signals.
4737 */
4738 static void get_signals(SLMP_INFO *info)
4739 {
4740 u16 status = read_reg(info, SR3);
4741 u16 gpstatus = read_status_reg(info);
4742 u16 testbit;
4743
4744 /* clear all serial signals except RTS and DTR */
4745 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
4746
4747 /* set serial signal bits to reflect MISR */
4748
4749 if (!(status & BIT3))
4750 info->serial_signals |= SerialSignal_CTS;
4751
4752 if ( !(status & BIT2))
4753 info->serial_signals |= SerialSignal_DCD;
4754
4755 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4756 if (!(gpstatus & testbit))
4757 info->serial_signals |= SerialSignal_RI;
4758
4759 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4760 if (!(gpstatus & testbit))
4761 info->serial_signals |= SerialSignal_DSR;
4762 }
4763
4764 /* Set the state of RTS and DTR based on contents of
4765 * serial_signals member of device context.
4766 */
4767 static void set_signals(SLMP_INFO *info)
4768 {
4769 unsigned char RegValue;
4770 u16 EnableBit;
4771
4772 RegValue = read_reg(info, CTL);
4773 if (info->serial_signals & SerialSignal_RTS)
4774 RegValue &= ~BIT0;
4775 else
4776 RegValue |= BIT0;
4777 write_reg(info, CTL, RegValue);
4778
4779 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4780 EnableBit = BIT1 << (info->port_num*2);
4781 if (info->serial_signals & SerialSignal_DTR)
4782 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4783 else
4784 info->port_array[0]->ctrlreg_value |= EnableBit;
4785 write_control_reg(info);
4786 }
4787
4788 /*******************/
4789 /* DMA Buffer Code */
4790 /*******************/
4791
4792 /* Set the count for all receive buffers to SCABUFSIZE
4793 * and set the current buffer to the first buffer. This effectively
4794 * makes all buffers free and discards any data in buffers.
4795 */
4796 static void rx_reset_buffers(SLMP_INFO *info)
4797 {
4798 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4799 }
4800
4801 /* Free the buffers used by a received frame
4802 *
4803 * info pointer to device instance data
4804 * first index of 1st receive buffer of frame
4805 * last index of last receive buffer of frame
4806 */
4807 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4808 {
4809 bool done = false;
4810
4811 while(!done) {
4812 /* reset current buffer for reuse */
4813 info->rx_buf_list[first].status = 0xff;
4814
4815 if (first == last) {
4816 done = true;
4817 /* set new last rx descriptor address */
4818 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4819 }
4820
4821 first++;
4822 if (first == info->rx_buf_count)
4823 first = 0;
4824 }
4825
4826 /* set current buffer to next buffer after last buffer of frame */
4827 info->current_rx_buf = first;
4828 }
4829
4830 /* Return a received frame from the receive DMA buffers.
4831 * Only frames received without errors are returned.
4832 *
4833 * Return Value: true if frame returned, otherwise false
4834 */
4835 static bool rx_get_frame(SLMP_INFO *info)
4836 {
4837 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4838 unsigned short status;
4839 unsigned int framesize = 0;
4840 bool ReturnCode = false;
4841 unsigned long flags;
4842 struct tty_struct *tty = info->port.tty;
4843 unsigned char addr_field = 0xff;
4844 SCADESC *desc;
4845 SCADESC_EX *desc_ex;
4846
4847 CheckAgain:
4848 /* assume no frame returned, set zero length */
4849 framesize = 0;
4850 addr_field = 0xff;
4851
4852 /*
4853 * current_rx_buf points to the 1st buffer of the next available
4854 * receive frame. To find the last buffer of the frame look for
4855 * a non-zero status field in the buffer entries. (The status
4856 * field is set by the 16C32 after completing a receive frame.
4857 */
4858 StartIndex = EndIndex = info->current_rx_buf;
4859
4860 for ( ;; ) {
4861 desc = &info->rx_buf_list[EndIndex];
4862 desc_ex = &info->rx_buf_list_ex[EndIndex];
4863
4864 if (desc->status == 0xff)
4865 goto Cleanup; /* current desc still in use, no frames available */
4866
4867 if (framesize == 0 && info->params.addr_filter != 0xff)
4868 addr_field = desc_ex->virt_addr[0];
4869
4870 framesize += desc->length;
4871
4872 /* Status != 0 means last buffer of frame */
4873 if (desc->status)
4874 break;
4875
4876 EndIndex++;
4877 if (EndIndex == info->rx_buf_count)
4878 EndIndex = 0;
4879
4880 if (EndIndex == info->current_rx_buf) {
4881 /* all buffers have been 'used' but none mark */
4882 /* the end of a frame. Reset buffers and receiver. */
4883 if ( info->rx_enabled ){
4884 spin_lock_irqsave(&info->lock,flags);
4885 rx_start(info);
4886 spin_unlock_irqrestore(&info->lock,flags);
4887 }
4888 goto Cleanup;
4889 }
4890
4891 }
4892
4893 /* check status of receive frame */
4894
4895 /* frame status is byte stored after frame data
4896 *
4897 * 7 EOM (end of msg), 1 = last buffer of frame
4898 * 6 Short Frame, 1 = short frame
4899 * 5 Abort, 1 = frame aborted
4900 * 4 Residue, 1 = last byte is partial
4901 * 3 Overrun, 1 = overrun occurred during frame reception
4902 * 2 CRC, 1 = CRC error detected
4903 *
4904 */
4905 status = desc->status;
4906
4907 /* ignore CRC bit if not using CRC (bit is undefined) */
4908 /* Note:CRC is not save to data buffer */
4909 if (info->params.crc_type == HDLC_CRC_NONE)
4910 status &= ~BIT2;
4911
4912 if (framesize == 0 ||
4913 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4914 /* discard 0 byte frames, this seems to occur sometime
4915 * when remote is idling flags.
4916 */
4917 rx_free_frame_buffers(info, StartIndex, EndIndex);
4918 goto CheckAgain;
4919 }
4920
4921 if (framesize < 2)
4922 status |= BIT6;
4923
4924 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4925 /* received frame has errors,
4926 * update counts and mark frame size as 0
4927 */
4928 if (status & BIT6)
4929 info->icount.rxshort++;
4930 else if (status & BIT5)
4931 info->icount.rxabort++;
4932 else if (status & BIT3)
4933 info->icount.rxover++;
4934 else
4935 info->icount.rxcrc++;
4936
4937 framesize = 0;
4938 #if SYNCLINK_GENERIC_HDLC
4939 {
4940 info->netdev->stats.rx_errors++;
4941 info->netdev->stats.rx_frame_errors++;
4942 }
4943 #endif
4944 }
4945
4946 if ( debug_level >= DEBUG_LEVEL_BH )
4947 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4948 __FILE__,__LINE__,info->device_name,status,framesize);
4949
4950 if ( debug_level >= DEBUG_LEVEL_DATA )
4951 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4952 min_t(unsigned int, framesize, SCABUFSIZE), 0);
4953
4954 if (framesize) {
4955 if (framesize > info->max_frame_size)
4956 info->icount.rxlong++;
4957 else {
4958 /* copy dma buffer(s) to contiguous intermediate buffer */
4959 int copy_count = framesize;
4960 int index = StartIndex;
4961 unsigned char *ptmp = info->tmp_rx_buf;
4962 info->tmp_rx_buf_count = framesize;
4963
4964 info->icount.rxok++;
4965
4966 while(copy_count) {
4967 int partial_count = min(copy_count,SCABUFSIZE);
4968 memcpy( ptmp,
4969 info->rx_buf_list_ex[index].virt_addr,
4970 partial_count );
4971 ptmp += partial_count;
4972 copy_count -= partial_count;
4973
4974 if ( ++index == info->rx_buf_count )
4975 index = 0;
4976 }
4977
4978 #if SYNCLINK_GENERIC_HDLC
4979 if (info->netcount)
4980 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4981 else
4982 #endif
4983 ldisc_receive_buf(tty,info->tmp_rx_buf,
4984 info->flag_buf, framesize);
4985 }
4986 }
4987 /* Free the buffers used by this frame. */
4988 rx_free_frame_buffers( info, StartIndex, EndIndex );
4989
4990 ReturnCode = true;
4991
4992 Cleanup:
4993 if ( info->rx_enabled && info->rx_overflow ) {
4994 /* Receiver is enabled, but needs to restarted due to
4995 * rx buffer overflow. If buffers are empty, restart receiver.
4996 */
4997 if (info->rx_buf_list[EndIndex].status == 0xff) {
4998 spin_lock_irqsave(&info->lock,flags);
4999 rx_start(info);
5000 spin_unlock_irqrestore(&info->lock,flags);
5001 }
5002 }
5003
5004 return ReturnCode;
5005 }
5006
5007 /* load the transmit DMA buffer with data
5008 */
5009 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5010 {
5011 unsigned short copy_count;
5012 unsigned int i = 0;
5013 SCADESC *desc;
5014 SCADESC_EX *desc_ex;
5015
5016 if ( debug_level >= DEBUG_LEVEL_DATA )
5017 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5018
5019 /* Copy source buffer to one or more DMA buffers, starting with
5020 * the first transmit dma buffer.
5021 */
5022 for(i=0;;)
5023 {
5024 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5025
5026 desc = &info->tx_buf_list[i];
5027 desc_ex = &info->tx_buf_list_ex[i];
5028
5029 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5030
5031 desc->length = copy_count;
5032 desc->status = 0;
5033
5034 buf += copy_count;
5035 count -= copy_count;
5036
5037 if (!count)
5038 break;
5039
5040 i++;
5041 if (i >= info->tx_buf_count)
5042 i = 0;
5043 }
5044
5045 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5046 info->last_tx_buf = ++i;
5047 }
5048
5049 static bool register_test(SLMP_INFO *info)
5050 {
5051 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5052 static unsigned int count = ARRAY_SIZE(testval);
5053 unsigned int i;
5054 bool rc = true;
5055 unsigned long flags;
5056
5057 spin_lock_irqsave(&info->lock,flags);
5058 reset_port(info);
5059
5060 /* assume failure */
5061 info->init_error = DiagStatus_AddressFailure;
5062
5063 /* Write bit patterns to various registers but do it out of */
5064 /* sync, then read back and verify values. */
5065
5066 for (i = 0 ; i < count ; i++) {
5067 write_reg(info, TMC, testval[i]);
5068 write_reg(info, IDL, testval[(i+1)%count]);
5069 write_reg(info, SA0, testval[(i+2)%count]);
5070 write_reg(info, SA1, testval[(i+3)%count]);
5071
5072 if ( (read_reg(info, TMC) != testval[i]) ||
5073 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5074 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5075 (read_reg(info, SA1) != testval[(i+3)%count]) )
5076 {
5077 rc = false;
5078 break;
5079 }
5080 }
5081
5082 reset_port(info);
5083 spin_unlock_irqrestore(&info->lock,flags);
5084
5085 return rc;
5086 }
5087
5088 static bool irq_test(SLMP_INFO *info)
5089 {
5090 unsigned long timeout;
5091 unsigned long flags;
5092
5093 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5094
5095 spin_lock_irqsave(&info->lock,flags);
5096 reset_port(info);
5097
5098 /* assume failure */
5099 info->init_error = DiagStatus_IrqFailure;
5100 info->irq_occurred = false;
5101
5102 /* setup timer0 on SCA0 to interrupt */
5103
5104 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5105 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5106
5107 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5108 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5109
5110
5111 /* TMCS, Timer Control/Status Register
5112 *
5113 * 07 CMF, Compare match flag (read only) 1=match
5114 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5115 * 05 Reserved, must be 0
5116 * 04 TME, Timer Enable
5117 * 03..00 Reserved, must be 0
5118 *
5119 * 0101 0000
5120 */
5121 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5122
5123 spin_unlock_irqrestore(&info->lock,flags);
5124
5125 timeout=100;
5126 while( timeout-- && !info->irq_occurred ) {
5127 msleep_interruptible(10);
5128 }
5129
5130 spin_lock_irqsave(&info->lock,flags);
5131 reset_port(info);
5132 spin_unlock_irqrestore(&info->lock,flags);
5133
5134 return info->irq_occurred;
5135 }
5136
5137 /* initialize individual SCA device (2 ports)
5138 */
5139 static bool sca_init(SLMP_INFO *info)
5140 {
5141 /* set wait controller to single mem partition (low), no wait states */
5142 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5143 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5144 write_reg(info, WCRL, 0); /* wait controller low range */
5145 write_reg(info, WCRM, 0); /* wait controller mid range */
5146 write_reg(info, WCRH, 0); /* wait controller high range */
5147
5148 /* DPCR, DMA Priority Control
5149 *
5150 * 07..05 Not used, must be 0
5151 * 04 BRC, bus release condition: 0=all transfers complete
5152 * 03 CCC, channel change condition: 0=every cycle
5153 * 02..00 PR<2..0>, priority 100=round robin
5154 *
5155 * 00000100 = 0x04
5156 */
5157 write_reg(info, DPCR, dma_priority);
5158
5159 /* DMA Master Enable, BIT7: 1=enable all channels */
5160 write_reg(info, DMER, 0x80);
5161
5162 /* enable all interrupt classes */
5163 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5164 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5165 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5166
5167 /* ITCR, interrupt control register
5168 * 07 IPC, interrupt priority, 0=MSCI->DMA
5169 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5170 * 04 VOS, Vector Output, 0=unmodified vector
5171 * 03..00 Reserved, must be 0
5172 */
5173 write_reg(info, ITCR, 0);
5174
5175 return true;
5176 }
5177
5178 /* initialize adapter hardware
5179 */
5180 static bool init_adapter(SLMP_INFO *info)
5181 {
5182 int i;
5183
5184 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5185 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5186 u32 readval;
5187
5188 info->misc_ctrl_value |= BIT30;
5189 *MiscCtrl = info->misc_ctrl_value;
5190
5191 /*
5192 * Force at least 170ns delay before clearing
5193 * reset bit. Each read from LCR takes at least
5194 * 30ns so 10 times for 300ns to be safe.
5195 */
5196 for(i=0;i<10;i++)
5197 readval = *MiscCtrl;
5198
5199 info->misc_ctrl_value &= ~BIT30;
5200 *MiscCtrl = info->misc_ctrl_value;
5201
5202 /* init control reg (all DTRs off, all clksel=input) */
5203 info->ctrlreg_value = 0xaa;
5204 write_control_reg(info);
5205
5206 {
5207 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5208 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5209
5210 switch(read_ahead_count)
5211 {
5212 case 16:
5213 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5214 break;
5215 case 8:
5216 lcr1_brdr_value |= BIT5 + BIT4;
5217 break;
5218 case 4:
5219 lcr1_brdr_value |= BIT5 + BIT3;
5220 break;
5221 case 0:
5222 lcr1_brdr_value |= BIT5;
5223 break;
5224 }
5225
5226 *LCR1BRDR = lcr1_brdr_value;
5227 *MiscCtrl = misc_ctrl_value;
5228 }
5229
5230 sca_init(info->port_array[0]);
5231 sca_init(info->port_array[2]);
5232
5233 return true;
5234 }
5235
5236 /* Loopback an HDLC frame to test the hardware
5237 * interrupt and DMA functions.
5238 */
5239 static bool loopback_test(SLMP_INFO *info)
5240 {
5241 #define TESTFRAMESIZE 20
5242
5243 unsigned long timeout;
5244 u16 count = TESTFRAMESIZE;
5245 unsigned char buf[TESTFRAMESIZE];
5246 bool rc = false;
5247 unsigned long flags;
5248
5249 struct tty_struct *oldtty = info->port.tty;
5250 u32 speed = info->params.clock_speed;
5251
5252 info->params.clock_speed = 3686400;
5253 info->port.tty = NULL;
5254
5255 /* assume failure */
5256 info->init_error = DiagStatus_DmaFailure;
5257
5258 /* build and send transmit frame */
5259 for (count = 0; count < TESTFRAMESIZE;++count)
5260 buf[count] = (unsigned char)count;
5261
5262 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5263
5264 /* program hardware for HDLC and enabled receiver */
5265 spin_lock_irqsave(&info->lock,flags);
5266 hdlc_mode(info);
5267 enable_loopback(info,1);
5268 rx_start(info);
5269 info->tx_count = count;
5270 tx_load_dma_buffer(info,buf,count);
5271 tx_start(info);
5272 spin_unlock_irqrestore(&info->lock,flags);
5273
5274 /* wait for receive complete */
5275 /* Set a timeout for waiting for interrupt. */
5276 for ( timeout = 100; timeout; --timeout ) {
5277 msleep_interruptible(10);
5278
5279 if (rx_get_frame(info)) {
5280 rc = true;
5281 break;
5282 }
5283 }
5284
5285 /* verify received frame length and contents */
5286 if (rc &&
5287 ( info->tmp_rx_buf_count != count ||
5288 memcmp(buf, info->tmp_rx_buf,count))) {
5289 rc = false;
5290 }
5291
5292 spin_lock_irqsave(&info->lock,flags);
5293 reset_adapter(info);
5294 spin_unlock_irqrestore(&info->lock,flags);
5295
5296 info->params.clock_speed = speed;
5297 info->port.tty = oldtty;
5298
5299 return rc;
5300 }
5301
5302 /* Perform diagnostics on hardware
5303 */
5304 static int adapter_test( SLMP_INFO *info )
5305 {
5306 unsigned long flags;
5307 if ( debug_level >= DEBUG_LEVEL_INFO )
5308 printk( "%s(%d):Testing device %s\n",
5309 __FILE__,__LINE__,info->device_name );
5310
5311 spin_lock_irqsave(&info->lock,flags);
5312 init_adapter(info);
5313 spin_unlock_irqrestore(&info->lock,flags);
5314
5315 info->port_array[0]->port_count = 0;
5316
5317 if ( register_test(info->port_array[0]) &&
5318 register_test(info->port_array[1])) {
5319
5320 info->port_array[0]->port_count = 2;
5321
5322 if ( register_test(info->port_array[2]) &&
5323 register_test(info->port_array[3]) )
5324 info->port_array[0]->port_count += 2;
5325 }
5326 else {
5327 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5328 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5329 return -ENODEV;
5330 }
5331
5332 if ( !irq_test(info->port_array[0]) ||
5333 !irq_test(info->port_array[1]) ||
5334 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5335 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5336 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5337 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5338 return -ENODEV;
5339 }
5340
5341 if (!loopback_test(info->port_array[0]) ||
5342 !loopback_test(info->port_array[1]) ||
5343 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5344 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5345 printk( "%s(%d):DMA test failure for device %s\n",
5346 __FILE__,__LINE__,info->device_name);
5347 return -ENODEV;
5348 }
5349
5350 if ( debug_level >= DEBUG_LEVEL_INFO )
5351 printk( "%s(%d):device %s passed diagnostics\n",
5352 __FILE__,__LINE__,info->device_name );
5353
5354 info->port_array[0]->init_error = 0;
5355 info->port_array[1]->init_error = 0;
5356 if ( info->port_count > 2 ) {
5357 info->port_array[2]->init_error = 0;
5358 info->port_array[3]->init_error = 0;
5359 }
5360
5361 return 0;
5362 }
5363
5364 /* Test the shared memory on a PCI adapter.
5365 */
5366 static bool memory_test(SLMP_INFO *info)
5367 {
5368 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5369 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5370 unsigned long count = ARRAY_SIZE(testval);
5371 unsigned long i;
5372 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5373 unsigned long * addr = (unsigned long *)info->memory_base;
5374
5375 /* Test data lines with test pattern at one location. */
5376
5377 for ( i = 0 ; i < count ; i++ ) {
5378 *addr = testval[i];
5379 if ( *addr != testval[i] )
5380 return false;
5381 }
5382
5383 /* Test address lines with incrementing pattern over */
5384 /* entire address range. */
5385
5386 for ( i = 0 ; i < limit ; i++ ) {
5387 *addr = i * 4;
5388 addr++;
5389 }
5390
5391 addr = (unsigned long *)info->memory_base;
5392
5393 for ( i = 0 ; i < limit ; i++ ) {
5394 if ( *addr != i * 4 )
5395 return false;
5396 addr++;
5397 }
5398
5399 memset( info->memory_base, 0, SCA_MEM_SIZE );
5400 return true;
5401 }
5402
5403 /* Load data into PCI adapter shared memory.
5404 *
5405 * The PCI9050 releases control of the local bus
5406 * after completing the current read or write operation.
5407 *
5408 * While the PCI9050 write FIFO not empty, the
5409 * PCI9050 treats all of the writes as a single transaction
5410 * and does not release the bus. This causes DMA latency problems
5411 * at high speeds when copying large data blocks to the shared memory.
5412 *
5413 * This function breaks a write into multiple transations by
5414 * interleaving a read which flushes the write FIFO and 'completes'
5415 * the write transation. This allows any pending DMA request to gain control
5416 * of the local bus in a timely fasion.
5417 */
5418 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5419 {
5420 /* A load interval of 16 allows for 4 32-bit writes at */
5421 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5422
5423 unsigned short interval = count / sca_pci_load_interval;
5424 unsigned short i;
5425
5426 for ( i = 0 ; i < interval ; i++ )
5427 {
5428 memcpy(dest, src, sca_pci_load_interval);
5429 read_status_reg(info);
5430 dest += sca_pci_load_interval;
5431 src += sca_pci_load_interval;
5432 }
5433
5434 memcpy(dest, src, count % sca_pci_load_interval);
5435 }
5436
5437 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5438 {
5439 int i;
5440 int linecount;
5441 if (xmit)
5442 printk("%s tx data:\n",info->device_name);
5443 else
5444 printk("%s rx data:\n",info->device_name);
5445
5446 while(count) {
5447 if (count > 16)
5448 linecount = 16;
5449 else
5450 linecount = count;
5451
5452 for(i=0;i<linecount;i++)
5453 printk("%02X ",(unsigned char)data[i]);
5454 for(;i<17;i++)
5455 printk(" ");
5456 for(i=0;i<linecount;i++) {
5457 if (data[i]>=040 && data[i]<=0176)
5458 printk("%c",data[i]);
5459 else
5460 printk(".");
5461 }
5462 printk("\n");
5463
5464 data += linecount;
5465 count -= linecount;
5466 }
5467 } /* end of trace_block() */
5468
5469 /* called when HDLC frame times out
5470 * update stats and do tx completion processing
5471 */
5472 static void tx_timeout(unsigned long context)
5473 {
5474 SLMP_INFO *info = (SLMP_INFO*)context;
5475 unsigned long flags;
5476
5477 if ( debug_level >= DEBUG_LEVEL_INFO )
5478 printk( "%s(%d):%s tx_timeout()\n",
5479 __FILE__,__LINE__,info->device_name);
5480 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5481 info->icount.txtimeout++;
5482 }
5483 spin_lock_irqsave(&info->lock,flags);
5484 info->tx_active = false;
5485 info->tx_count = info->tx_put = info->tx_get = 0;
5486
5487 spin_unlock_irqrestore(&info->lock,flags);
5488
5489 #if SYNCLINK_GENERIC_HDLC
5490 if (info->netcount)
5491 hdlcdev_tx_done(info);
5492 else
5493 #endif
5494 bh_transmit(info);
5495 }
5496
5497 /* called to periodically check the DSR/RI modem signal input status
5498 */
5499 static void status_timeout(unsigned long context)
5500 {
5501 u16 status = 0;
5502 SLMP_INFO *info = (SLMP_INFO*)context;
5503 unsigned long flags;
5504 unsigned char delta;
5505
5506
5507 spin_lock_irqsave(&info->lock,flags);
5508 get_signals(info);
5509 spin_unlock_irqrestore(&info->lock,flags);
5510
5511 /* check for DSR/RI state change */
5512
5513 delta = info->old_signals ^ info->serial_signals;
5514 info->old_signals = info->serial_signals;
5515
5516 if (delta & SerialSignal_DSR)
5517 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5518
5519 if (delta & SerialSignal_RI)
5520 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5521
5522 if (delta & SerialSignal_DCD)
5523 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5524
5525 if (delta & SerialSignal_CTS)
5526 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5527
5528 if (status)
5529 isr_io_pin(info,status);
5530
5531 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5532 }
5533
5534
5535 /* Register Access Routines -
5536 * All registers are memory mapped
5537 */
5538 #define CALC_REGADDR() \
5539 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5540 if (info->port_num > 1) \
5541 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5542 if ( info->port_num & 1) { \
5543 if (Addr > 0x7f) \
5544 RegAddr += 0x40; /* DMA access */ \
5545 else if (Addr > 0x1f && Addr < 0x60) \
5546 RegAddr += 0x20; /* MSCI access */ \
5547 }
5548
5549
5550 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5551 {
5552 CALC_REGADDR();
5553 return *RegAddr;
5554 }
5555 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5556 {
5557 CALC_REGADDR();
5558 *RegAddr = Value;
5559 }
5560
5561 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5562 {
5563 CALC_REGADDR();
5564 return *((u16 *)RegAddr);
5565 }
5566
5567 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5568 {
5569 CALC_REGADDR();
5570 *((u16 *)RegAddr) = Value;
5571 }
5572
5573 static unsigned char read_status_reg(SLMP_INFO * info)
5574 {
5575 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5576 return *RegAddr;
5577 }
5578
5579 static void write_control_reg(SLMP_INFO * info)
5580 {
5581 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5582 *RegAddr = info->port_array[0]->ctrlreg_value;
5583 }
5584
5585
5586 static int synclinkmp_init_one (struct pci_dev *dev,
5587 const struct pci_device_id *ent)
5588 {
5589 if (pci_enable_device(dev)) {
5590 printk("error enabling pci device %p\n", dev);
5591 return -EIO;
5592 }
5593 return device_init( ++synclinkmp_adapter_count, dev );
5594 }
5595
5596 static void synclinkmp_remove_one (struct pci_dev *dev)
5597 {
5598 }
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