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b43: support new RX header, noticed to be used in 598.314+ fw
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / b43 / dma.c
blobd0d9aee44a59a8868af94dd5e92df958d76560f4
1 /*
2
3 Broadcom B43 wireless driver
4
5 DMA ringbuffer and descriptor allocation/management
6
7 Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
8
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
27
28 */
29
30 #include "b43.h"
31 #include "dma.h"
32 #include "main.h"
33 #include "debugfs.h"
34 #include "xmit.h"
35
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <linux/etherdevice.h>
41 #include <linux/slab.h>
42 #include <asm/div64.h>
43
44
45 /* Required number of TX DMA slots per TX frame.
46 * This currently is 2, because we put the header and the ieee80211 frame
47 * into separate slots. */
48 #define TX_SLOTS_PER_FRAME 2
49
50
51 /* 32bit DMA ops. */
52 static
53 struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
54 int slot,
55 struct b43_dmadesc_meta **meta)
56 {
57 struct b43_dmadesc32 *desc;
58
59 *meta = &(ring->meta[slot]);
60 desc = ring->descbase;
61 desc = &(desc[slot]);
62
63 return (struct b43_dmadesc_generic *)desc;
64 }
65
66 static void op32_fill_descriptor(struct b43_dmaring *ring,
67 struct b43_dmadesc_generic *desc,
68 dma_addr_t dmaaddr, u16 bufsize,
69 int start, int end, int irq)
70 {
71 struct b43_dmadesc32 *descbase = ring->descbase;
72 int slot;
73 u32 ctl;
74 u32 addr;
75 u32 addrext;
76
77 slot = (int)(&(desc->dma32) - descbase);
78 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
79
80 addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
81 addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
82 >> SSB_DMA_TRANSLATION_SHIFT;
83 addr |= ring->dev->dma.translation;
84 ctl = bufsize & B43_DMA32_DCTL_BYTECNT;
85 if (slot == ring->nr_slots - 1)
86 ctl |= B43_DMA32_DCTL_DTABLEEND;
87 if (start)
88 ctl |= B43_DMA32_DCTL_FRAMESTART;
89 if (end)
90 ctl |= B43_DMA32_DCTL_FRAMEEND;
91 if (irq)
92 ctl |= B43_DMA32_DCTL_IRQ;
93 ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
94 & B43_DMA32_DCTL_ADDREXT_MASK;
95
96 desc->dma32.control = cpu_to_le32(ctl);
97 desc->dma32.address = cpu_to_le32(addr);
98 }
99
100 static void op32_poke_tx(struct b43_dmaring *ring, int slot)
101 {
102 b43_dma_write(ring, B43_DMA32_TXINDEX,
103 (u32) (slot * sizeof(struct b43_dmadesc32)));
104 }
105
106 static void op32_tx_suspend(struct b43_dmaring *ring)
107 {
108 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
109 | B43_DMA32_TXSUSPEND);
110 }
111
112 static void op32_tx_resume(struct b43_dmaring *ring)
113 {
114 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
115 & ~B43_DMA32_TXSUSPEND);
116 }
117
118 static int op32_get_current_rxslot(struct b43_dmaring *ring)
119 {
120 u32 val;
121
122 val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
123 val &= B43_DMA32_RXDPTR;
124
125 return (val / sizeof(struct b43_dmadesc32));
126 }
127
128 static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
129 {
130 b43_dma_write(ring, B43_DMA32_RXINDEX,
131 (u32) (slot * sizeof(struct b43_dmadesc32)));
132 }
133
134 static const struct b43_dma_ops dma32_ops = {
135 .idx2desc = op32_idx2desc,
136 .fill_descriptor = op32_fill_descriptor,
137 .poke_tx = op32_poke_tx,
138 .tx_suspend = op32_tx_suspend,
139 .tx_resume = op32_tx_resume,
140 .get_current_rxslot = op32_get_current_rxslot,
141 .set_current_rxslot = op32_set_current_rxslot,
142 };
143
144 /* 64bit DMA ops. */
145 static
146 struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
147 int slot,
148 struct b43_dmadesc_meta **meta)
149 {
150 struct b43_dmadesc64 *desc;
151
152 *meta = &(ring->meta[slot]);
153 desc = ring->descbase;
154 desc = &(desc[slot]);
155
156 return (struct b43_dmadesc_generic *)desc;
157 }
158
159 static void op64_fill_descriptor(struct b43_dmaring *ring,
160 struct b43_dmadesc_generic *desc,
161 dma_addr_t dmaaddr, u16 bufsize,
162 int start, int end, int irq)
163 {
164 struct b43_dmadesc64 *descbase = ring->descbase;
165 int slot;
166 u32 ctl0 = 0, ctl1 = 0;
167 u32 addrlo, addrhi;
168 u32 addrext;
169
170 slot = (int)(&(desc->dma64) - descbase);
171 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
172
173 addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
174 addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
175 addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
176 >> SSB_DMA_TRANSLATION_SHIFT;
177 addrhi |= ring->dev->dma.translation;
178 if (slot == ring->nr_slots - 1)
179 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
180 if (start)
181 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
182 if (end)
183 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
184 if (irq)
185 ctl0 |= B43_DMA64_DCTL0_IRQ;
186 ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT;
187 ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
188 & B43_DMA64_DCTL1_ADDREXT_MASK;
189
190 desc->dma64.control0 = cpu_to_le32(ctl0);
191 desc->dma64.control1 = cpu_to_le32(ctl1);
192 desc->dma64.address_low = cpu_to_le32(addrlo);
193 desc->dma64.address_high = cpu_to_le32(addrhi);
194 }
195
196 static void op64_poke_tx(struct b43_dmaring *ring, int slot)
197 {
198 b43_dma_write(ring, B43_DMA64_TXINDEX,
199 (u32) (slot * sizeof(struct b43_dmadesc64)));
200 }
201
202 static void op64_tx_suspend(struct b43_dmaring *ring)
203 {
204 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
205 | B43_DMA64_TXSUSPEND);
206 }
207
208 static void op64_tx_resume(struct b43_dmaring *ring)
209 {
210 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
211 & ~B43_DMA64_TXSUSPEND);
212 }
213
214 static int op64_get_current_rxslot(struct b43_dmaring *ring)
215 {
216 u32 val;
217
218 val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
219 val &= B43_DMA64_RXSTATDPTR;
220
221 return (val / sizeof(struct b43_dmadesc64));
222 }
223
224 static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
225 {
226 b43_dma_write(ring, B43_DMA64_RXINDEX,
227 (u32) (slot * sizeof(struct b43_dmadesc64)));
228 }
229
230 static const struct b43_dma_ops dma64_ops = {
231 .idx2desc = op64_idx2desc,
232 .fill_descriptor = op64_fill_descriptor,
233 .poke_tx = op64_poke_tx,
234 .tx_suspend = op64_tx_suspend,
235 .tx_resume = op64_tx_resume,
236 .get_current_rxslot = op64_get_current_rxslot,
237 .set_current_rxslot = op64_set_current_rxslot,
238 };
239
240 static inline int free_slots(struct b43_dmaring *ring)
241 {
242 return (ring->nr_slots - ring->used_slots);
243 }
244
245 static inline int next_slot(struct b43_dmaring *ring, int slot)
246 {
247 B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
248 if (slot == ring->nr_slots - 1)
249 return 0;
250 return slot + 1;
251 }
252
253 static inline int prev_slot(struct b43_dmaring *ring, int slot)
254 {
255 B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
256 if (slot == 0)
257 return ring->nr_slots - 1;
258 return slot - 1;
259 }
260
261 #ifdef CONFIG_B43_DEBUG
262 static void update_max_used_slots(struct b43_dmaring *ring,
263 int current_used_slots)
264 {
265 if (current_used_slots <= ring->max_used_slots)
266 return;
267 ring->max_used_slots = current_used_slots;
268 if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
269 b43dbg(ring->dev->wl,
270 "max_used_slots increased to %d on %s ring %d\n",
271 ring->max_used_slots,
272 ring->tx ? "TX" : "RX", ring->index);
273 }
274 }
275 #else
276 static inline
277 void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
278 {
279 }
280 #endif /* DEBUG */
281
282 /* Request a slot for usage. */
283 static inline int request_slot(struct b43_dmaring *ring)
284 {
285 int slot;
286
287 B43_WARN_ON(!ring->tx);
288 B43_WARN_ON(ring->stopped);
289 B43_WARN_ON(free_slots(ring) == 0);
290
291 slot = next_slot(ring, ring->current_slot);
292 ring->current_slot = slot;
293 ring->used_slots++;
294
295 update_max_used_slots(ring, ring->used_slots);
296
297 return slot;
298 }
299
300 static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
301 {
302 static const u16 map64[] = {
303 B43_MMIO_DMA64_BASE0,
304 B43_MMIO_DMA64_BASE1,
305 B43_MMIO_DMA64_BASE2,
306 B43_MMIO_DMA64_BASE3,
307 B43_MMIO_DMA64_BASE4,
308 B43_MMIO_DMA64_BASE5,
309 };
310 static const u16 map32[] = {
311 B43_MMIO_DMA32_BASE0,
312 B43_MMIO_DMA32_BASE1,
313 B43_MMIO_DMA32_BASE2,
314 B43_MMIO_DMA32_BASE3,
315 B43_MMIO_DMA32_BASE4,
316 B43_MMIO_DMA32_BASE5,
317 };
318
319 if (type == B43_DMA_64BIT) {
320 B43_WARN_ON(!(controller_idx >= 0 &&
321 controller_idx < ARRAY_SIZE(map64)));
322 return map64[controller_idx];
323 }
324 B43_WARN_ON(!(controller_idx >= 0 &&
325 controller_idx < ARRAY_SIZE(map32)));
326 return map32[controller_idx];
327 }
328
329 static inline
330 dma_addr_t map_descbuffer(struct b43_dmaring *ring,
331 unsigned char *buf, size_t len, int tx)
332 {
333 dma_addr_t dmaaddr;
334
335 if (tx) {
336 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
337 buf, len, DMA_TO_DEVICE);
338 } else {
339 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
340 buf, len, DMA_FROM_DEVICE);
341 }
342
343 return dmaaddr;
344 }
345
346 static inline
347 void unmap_descbuffer(struct b43_dmaring *ring,
348 dma_addr_t addr, size_t len, int tx)
349 {
350 if (tx) {
351 dma_unmap_single(ring->dev->dev->dma_dev,
352 addr, len, DMA_TO_DEVICE);
353 } else {
354 dma_unmap_single(ring->dev->dev->dma_dev,
355 addr, len, DMA_FROM_DEVICE);
356 }
357 }
358
359 static inline
360 void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
361 dma_addr_t addr, size_t len)
362 {
363 B43_WARN_ON(ring->tx);
364 dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
365 addr, len, DMA_FROM_DEVICE);
366 }
367
368 static inline
369 void sync_descbuffer_for_device(struct b43_dmaring *ring,
370 dma_addr_t addr, size_t len)
371 {
372 B43_WARN_ON(ring->tx);
373 dma_sync_single_for_device(ring->dev->dev->dma_dev,
374 addr, len, DMA_FROM_DEVICE);
375 }
376
377 static inline
378 void free_descriptor_buffer(struct b43_dmaring *ring,
379 struct b43_dmadesc_meta *meta)
380 {
381 if (meta->skb) {
382 dev_kfree_skb_any(meta->skb);
383 meta->skb = NULL;
384 }
385 }
386
387 static int alloc_ringmemory(struct b43_dmaring *ring)
388 {
389 gfp_t flags = GFP_KERNEL;
390
391 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
392 * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
393 * has shown that 4K is sufficient for the latter as long as the buffer
394 * does not cross an 8K boundary.
395 *
396 * For unknown reasons - possibly a hardware error - the BCM4311 rev
397 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
398 * which accounts for the GFP_DMA flag below.
399 *
400 * The flags here must match the flags in free_ringmemory below!
401 */
402 if (ring->type == B43_DMA_64BIT)
403 flags |= GFP_DMA;
404 ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
405 B43_DMA_RINGMEMSIZE,
406 &(ring->dmabase), flags);
407 if (!ring->descbase) {
408 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
409 return -ENOMEM;
410 }
411 memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
412
413 return 0;
414 }
415
416 static void free_ringmemory(struct b43_dmaring *ring)
417 {
418 dma_free_coherent(ring->dev->dev->dma_dev, B43_DMA_RINGMEMSIZE,
419 ring->descbase, ring->dmabase);
420 }
421
422 /* Reset the RX DMA channel */
423 static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
424 enum b43_dmatype type)
425 {
426 int i;
427 u32 value;
428 u16 offset;
429
430 might_sleep();
431
432 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
433 b43_write32(dev, mmio_base + offset, 0);
434 for (i = 0; i < 10; i++) {
435 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
436 B43_DMA32_RXSTATUS;
437 value = b43_read32(dev, mmio_base + offset);
438 if (type == B43_DMA_64BIT) {
439 value &= B43_DMA64_RXSTAT;
440 if (value == B43_DMA64_RXSTAT_DISABLED) {
441 i = -1;
442 break;
443 }
444 } else {
445 value &= B43_DMA32_RXSTATE;
446 if (value == B43_DMA32_RXSTAT_DISABLED) {
447 i = -1;
448 break;
449 }
450 }
451 msleep(1);
452 }
453 if (i != -1) {
454 b43err(dev->wl, "DMA RX reset timed out\n");
455 return -ENODEV;
456 }
457
458 return 0;
459 }
460
461 /* Reset the TX DMA channel */
462 static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
463 enum b43_dmatype type)
464 {
465 int i;
466 u32 value;
467 u16 offset;
468
469 might_sleep();
470
471 for (i = 0; i < 10; i++) {
472 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
473 B43_DMA32_TXSTATUS;
474 value = b43_read32(dev, mmio_base + offset);
475 if (type == B43_DMA_64BIT) {
476 value &= B43_DMA64_TXSTAT;
477 if (value == B43_DMA64_TXSTAT_DISABLED ||
478 value == B43_DMA64_TXSTAT_IDLEWAIT ||
479 value == B43_DMA64_TXSTAT_STOPPED)
480 break;
481 } else {
482 value &= B43_DMA32_TXSTATE;
483 if (value == B43_DMA32_TXSTAT_DISABLED ||
484 value == B43_DMA32_TXSTAT_IDLEWAIT ||
485 value == B43_DMA32_TXSTAT_STOPPED)
486 break;
487 }
488 msleep(1);
489 }
490 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
491 b43_write32(dev, mmio_base + offset, 0);
492 for (i = 0; i < 10; i++) {
493 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
494 B43_DMA32_TXSTATUS;
495 value = b43_read32(dev, mmio_base + offset);
496 if (type == B43_DMA_64BIT) {
497 value &= B43_DMA64_TXSTAT;
498 if (value == B43_DMA64_TXSTAT_DISABLED) {
499 i = -1;
500 break;
501 }
502 } else {
503 value &= B43_DMA32_TXSTATE;
504 if (value == B43_DMA32_TXSTAT_DISABLED) {
505 i = -1;
506 break;
507 }
508 }
509 msleep(1);
510 }
511 if (i != -1) {
512 b43err(dev->wl, "DMA TX reset timed out\n");
513 return -ENODEV;
514 }
515 /* ensure the reset is completed. */
516 msleep(1);
517
518 return 0;
519 }
520
521 /* Check if a DMA mapping address is invalid. */
522 static bool b43_dma_mapping_error(struct b43_dmaring *ring,
523 dma_addr_t addr,
524 size_t buffersize, bool dma_to_device)
525 {
526 if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
527 return 1;
528
529 switch (ring->type) {
530 case B43_DMA_30BIT:
531 if ((u64)addr + buffersize > (1ULL << 30))
532 goto address_error;
533 break;
534 case B43_DMA_32BIT:
535 if ((u64)addr + buffersize > (1ULL << 32))
536 goto address_error;
537 break;
538 case B43_DMA_64BIT:
539 /* Currently we can't have addresses beyond
540 * 64bit in the kernel. */
541 break;
542 }
543
544 /* The address is OK. */
545 return 0;
546
547 address_error:
548 /* We can't support this address. Unmap it again. */
549 unmap_descbuffer(ring, addr, buffersize, dma_to_device);
550
551 return 1;
552 }
553
554 static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb)
555 {
556 unsigned char *f = skb->data + ring->frameoffset;
557
558 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF);
559 }
560
561 static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb)
562 {
563 struct b43_rxhdr_fw4 *rxhdr;
564 unsigned char *frame;
565
566 /* This poisons the RX buffer to detect DMA failures. */
567
568 rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
569 rxhdr->frame_len = 0;
570
571 B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);
572 frame = skb->data + ring->frameoffset;
573 memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */);
574 }
575
576 static int setup_rx_descbuffer(struct b43_dmaring *ring,
577 struct b43_dmadesc_generic *desc,
578 struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
579 {
580 dma_addr_t dmaaddr;
581 struct sk_buff *skb;
582
583 B43_WARN_ON(ring->tx);
584
585 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
586 if (unlikely(!skb))
587 return -ENOMEM;
588 b43_poison_rx_buffer(ring, skb);
589 dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
590 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
591 /* ugh. try to realloc in zone_dma */
592 gfp_flags |= GFP_DMA;
593
594 dev_kfree_skb_any(skb);
595
596 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
597 if (unlikely(!skb))
598 return -ENOMEM;
599 b43_poison_rx_buffer(ring, skb);
600 dmaaddr = map_descbuffer(ring, skb->data,
601 ring->rx_buffersize, 0);
602 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
603 b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
604 dev_kfree_skb_any(skb);
605 return -EIO;
606 }
607 }
608
609 meta->skb = skb;
610 meta->dmaaddr = dmaaddr;
611 ring->ops->fill_descriptor(ring, desc, dmaaddr,
612 ring->rx_buffersize, 0, 0, 0);
613
614 return 0;
615 }
616
617 /* Allocate the initial descbuffers.
618 * This is used for an RX ring only.
619 */
620 static int alloc_initial_descbuffers(struct b43_dmaring *ring)
621 {
622 int i, err = -ENOMEM;
623 struct b43_dmadesc_generic *desc;
624 struct b43_dmadesc_meta *meta;
625
626 for (i = 0; i < ring->nr_slots; i++) {
627 desc = ring->ops->idx2desc(ring, i, &meta);
628
629 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
630 if (err) {
631 b43err(ring->dev->wl,
632 "Failed to allocate initial descbuffers\n");
633 goto err_unwind;
634 }
635 }
636 mb();
637 ring->used_slots = ring->nr_slots;
638 err = 0;
639 out:
640 return err;
641
642 err_unwind:
643 for (i--; i >= 0; i--) {
644 desc = ring->ops->idx2desc(ring, i, &meta);
645
646 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
647 dev_kfree_skb(meta->skb);
648 }
649 goto out;
650 }
651
652 /* Do initial setup of the DMA controller.
653 * Reset the controller, write the ring busaddress
654 * and switch the "enable" bit on.
655 */
656 static int dmacontroller_setup(struct b43_dmaring *ring)
657 {
658 int err = 0;
659 u32 value;
660 u32 addrext;
661 u32 trans = ring->dev->dma.translation;
662 bool parity = ring->dev->dma.parity;
663
664 if (ring->tx) {
665 if (ring->type == B43_DMA_64BIT) {
666 u64 ringbase = (u64) (ring->dmabase);
667
668 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
669 >> SSB_DMA_TRANSLATION_SHIFT;
670 value = B43_DMA64_TXENABLE;
671 value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
672 & B43_DMA64_TXADDREXT_MASK;
673 if (!parity)
674 value |= B43_DMA64_TXPARITYDISABLE;
675 b43_dma_write(ring, B43_DMA64_TXCTL, value);
676 b43_dma_write(ring, B43_DMA64_TXRINGLO,
677 (ringbase & 0xFFFFFFFF));
678 b43_dma_write(ring, B43_DMA64_TXRINGHI,
679 ((ringbase >> 32) &
680 ~SSB_DMA_TRANSLATION_MASK)
681 | trans);
682 } else {
683 u32 ringbase = (u32) (ring->dmabase);
684
685 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
686 >> SSB_DMA_TRANSLATION_SHIFT;
687 value = B43_DMA32_TXENABLE;
688 value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
689 & B43_DMA32_TXADDREXT_MASK;
690 if (!parity)
691 value |= B43_DMA32_TXPARITYDISABLE;
692 b43_dma_write(ring, B43_DMA32_TXCTL, value);
693 b43_dma_write(ring, B43_DMA32_TXRING,
694 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
695 | trans);
696 }
697 } else {
698 err = alloc_initial_descbuffers(ring);
699 if (err)
700 goto out;
701 if (ring->type == B43_DMA_64BIT) {
702 u64 ringbase = (u64) (ring->dmabase);
703
704 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
705 >> SSB_DMA_TRANSLATION_SHIFT;
706 value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
707 value |= B43_DMA64_RXENABLE;
708 value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
709 & B43_DMA64_RXADDREXT_MASK;
710 if (!parity)
711 value |= B43_DMA64_RXPARITYDISABLE;
712 b43_dma_write(ring, B43_DMA64_RXCTL, value);
713 b43_dma_write(ring, B43_DMA64_RXRINGLO,
714 (ringbase & 0xFFFFFFFF));
715 b43_dma_write(ring, B43_DMA64_RXRINGHI,
716 ((ringbase >> 32) &
717 ~SSB_DMA_TRANSLATION_MASK)
718 | trans);
719 b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
720 sizeof(struct b43_dmadesc64));
721 } else {
722 u32 ringbase = (u32) (ring->dmabase);
723
724 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
725 >> SSB_DMA_TRANSLATION_SHIFT;
726 value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
727 value |= B43_DMA32_RXENABLE;
728 value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
729 & B43_DMA32_RXADDREXT_MASK;
730 if (!parity)
731 value |= B43_DMA32_RXPARITYDISABLE;
732 b43_dma_write(ring, B43_DMA32_RXCTL, value);
733 b43_dma_write(ring, B43_DMA32_RXRING,
734 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
735 | trans);
736 b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
737 sizeof(struct b43_dmadesc32));
738 }
739 }
740
741 out:
742 return err;
743 }
744
745 /* Shutdown the DMA controller. */
746 static void dmacontroller_cleanup(struct b43_dmaring *ring)
747 {
748 if (ring->tx) {
749 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
750 ring->type);
751 if (ring->type == B43_DMA_64BIT) {
752 b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
753 b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
754 } else
755 b43_dma_write(ring, B43_DMA32_TXRING, 0);
756 } else {
757 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
758 ring->type);
759 if (ring->type == B43_DMA_64BIT) {
760 b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
761 b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
762 } else
763 b43_dma_write(ring, B43_DMA32_RXRING, 0);
764 }
765 }
766
767 static void free_all_descbuffers(struct b43_dmaring *ring)
768 {
769 struct b43_dmadesc_meta *meta;
770 int i;
771
772 if (!ring->used_slots)
773 return;
774 for (i = 0; i < ring->nr_slots; i++) {
775 /* get meta - ignore returned value */
776 ring->ops->idx2desc(ring, i, &meta);
777
778 if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) {
779 B43_WARN_ON(!ring->tx);
780 continue;
781 }
782 if (ring->tx) {
783 unmap_descbuffer(ring, meta->dmaaddr,
784 meta->skb->len, 1);
785 } else {
786 unmap_descbuffer(ring, meta->dmaaddr,
787 ring->rx_buffersize, 0);
788 }
789 free_descriptor_buffer(ring, meta);
790 }
791 }
792
793 static u64 supported_dma_mask(struct b43_wldev *dev)
794 {
795 u32 tmp;
796 u16 mmio_base;
797
798 tmp = b43_read32(dev, SSB_TMSHIGH);
799 if (tmp & SSB_TMSHIGH_DMA64)
800 return DMA_BIT_MASK(64);
801 mmio_base = b43_dmacontroller_base(0, 0);
802 b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
803 tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
804 if (tmp & B43_DMA32_TXADDREXT_MASK)
805 return DMA_BIT_MASK(32);
806
807 return DMA_BIT_MASK(30);
808 }
809
810 static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
811 {
812 if (dmamask == DMA_BIT_MASK(30))
813 return B43_DMA_30BIT;
814 if (dmamask == DMA_BIT_MASK(32))
815 return B43_DMA_32BIT;
816 if (dmamask == DMA_BIT_MASK(64))
817 return B43_DMA_64BIT;
818 B43_WARN_ON(1);
819 return B43_DMA_30BIT;
820 }
821
822 /* Main initialization function. */
823 static
824 struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
825 int controller_index,
826 int for_tx,
827 enum b43_dmatype type)
828 {
829 struct b43_dmaring *ring;
830 int i, err;
831 dma_addr_t dma_test;
832
833 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
834 if (!ring)
835 goto out;
836
837 ring->nr_slots = B43_RXRING_SLOTS;
838 if (for_tx)
839 ring->nr_slots = B43_TXRING_SLOTS;
840
841 ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta),
842 GFP_KERNEL);
843 if (!ring->meta)
844 goto err_kfree_ring;
845 for (i = 0; i < ring->nr_slots; i++)
846 ring->meta->skb = B43_DMA_PTR_POISON;
847
848 ring->type = type;
849 ring->dev = dev;
850 ring->mmio_base = b43_dmacontroller_base(type, controller_index);
851 ring->index = controller_index;
852 if (type == B43_DMA_64BIT)
853 ring->ops = &dma64_ops;
854 else
855 ring->ops = &dma32_ops;
856 if (for_tx) {
857 ring->tx = 1;
858 ring->current_slot = -1;
859 } else {
860 if (ring->index == 0) {
861 switch (dev->fw.hdr_format) {
862 case B43_FW_HDR_598:
863 ring->rx_buffersize = B43_DMA0_RX_FW598_BUFSIZE;
864 ring->frameoffset = B43_DMA0_RX_FW598_FO;
865 break;
866 case B43_FW_HDR_410:
867 case B43_FW_HDR_351:
868 ring->rx_buffersize = B43_DMA0_RX_FW351_BUFSIZE;
869 ring->frameoffset = B43_DMA0_RX_FW351_FO;
870 break;
871 }
872 } else
873 B43_WARN_ON(1);
874 }
875 #ifdef CONFIG_B43_DEBUG
876 ring->last_injected_overflow = jiffies;
877 #endif
878
879 if (for_tx) {
880 /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */
881 BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0);
882
883 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
884 b43_txhdr_size(dev),
885 GFP_KERNEL);
886 if (!ring->txhdr_cache)
887 goto err_kfree_meta;
888
889 /* test for ability to dma to txhdr_cache */
890 dma_test = dma_map_single(dev->dev->dma_dev,
891 ring->txhdr_cache,
892 b43_txhdr_size(dev),
893 DMA_TO_DEVICE);
894
895 if (b43_dma_mapping_error(ring, dma_test,
896 b43_txhdr_size(dev), 1)) {
897 /* ugh realloc */
898 kfree(ring->txhdr_cache);
899 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
900 b43_txhdr_size(dev),
901 GFP_KERNEL | GFP_DMA);
902 if (!ring->txhdr_cache)
903 goto err_kfree_meta;
904
905 dma_test = dma_map_single(dev->dev->dma_dev,
906 ring->txhdr_cache,
907 b43_txhdr_size(dev),
908 DMA_TO_DEVICE);
909
910 if (b43_dma_mapping_error(ring, dma_test,
911 b43_txhdr_size(dev), 1)) {
912
913 b43err(dev->wl,
914 "TXHDR DMA allocation failed\n");
915 goto err_kfree_txhdr_cache;
916 }
917 }
918
919 dma_unmap_single(dev->dev->dma_dev,
920 dma_test, b43_txhdr_size(dev),
921 DMA_TO_DEVICE);
922 }
923
924 err = alloc_ringmemory(ring);
925 if (err)
926 goto err_kfree_txhdr_cache;
927 err = dmacontroller_setup(ring);
928 if (err)
929 goto err_free_ringmemory;
930
931 out:
932 return ring;
933
934 err_free_ringmemory:
935 free_ringmemory(ring);
936 err_kfree_txhdr_cache:
937 kfree(ring->txhdr_cache);
938 err_kfree_meta:
939 kfree(ring->meta);
940 err_kfree_ring:
941 kfree(ring);
942 ring = NULL;
943 goto out;
944 }
945
946 #define divide(a, b) ({ \
947 typeof(a) __a = a; \
948 do_div(__a, b); \
949 __a; \
950 })
951
952 #define modulo(a, b) ({ \
953 typeof(a) __a = a; \
954 do_div(__a, b); \
955 })
956
957 /* Main cleanup function. */
958 static void b43_destroy_dmaring(struct b43_dmaring *ring,
959 const char *ringname)
960 {
961 if (!ring)
962 return;
963
964 #ifdef CONFIG_B43_DEBUG
965 {
966 /* Print some statistics. */
967 u64 failed_packets = ring->nr_failed_tx_packets;
968 u64 succeed_packets = ring->nr_succeed_tx_packets;
969 u64 nr_packets = failed_packets + succeed_packets;
970 u64 permille_failed = 0, average_tries = 0;
971
972 if (nr_packets)
973 permille_failed = divide(failed_packets * 1000, nr_packets);
974 if (nr_packets)
975 average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
976
977 b43dbg(ring->dev->wl, "DMA-%u %s: "
978 "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
979 "Average tries %llu.%02llu\n",
980 (unsigned int)(ring->type), ringname,
981 ring->max_used_slots,
982 ring->nr_slots,
983 (unsigned long long)failed_packets,
984 (unsigned long long)nr_packets,
985 (unsigned long long)divide(permille_failed, 10),
986 (unsigned long long)modulo(permille_failed, 10),
987 (unsigned long long)divide(average_tries, 100),
988 (unsigned long long)modulo(average_tries, 100));
989 }
990 #endif /* DEBUG */
991
992 /* Device IRQs are disabled prior entering this function,
993 * so no need to take care of concurrency with rx handler stuff.
994 */
995 dmacontroller_cleanup(ring);
996 free_all_descbuffers(ring);
997 free_ringmemory(ring);
998
999 kfree(ring->txhdr_cache);
1000 kfree(ring->meta);
1001 kfree(ring);
1002 }
1003
1004 #define destroy_ring(dma, ring) do { \
1005 b43_destroy_dmaring((dma)->ring, __stringify(ring)); \
1006 (dma)->ring = NULL; \
1007 } while (0)
1008
1009 void b43_dma_free(struct b43_wldev *dev)
1010 {
1011 struct b43_dma *dma;
1012
1013 if (b43_using_pio_transfers(dev))
1014 return;
1015 dma = &dev->dma;
1016
1017 destroy_ring(dma, rx_ring);
1018 destroy_ring(dma, tx_ring_AC_BK);
1019 destroy_ring(dma, tx_ring_AC_BE);
1020 destroy_ring(dma, tx_ring_AC_VI);
1021 destroy_ring(dma, tx_ring_AC_VO);
1022 destroy_ring(dma, tx_ring_mcast);
1023 }
1024
1025 static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
1026 {
1027 u64 orig_mask = mask;
1028 bool fallback = 0;
1029 int err;
1030
1031 /* Try to set the DMA mask. If it fails, try falling back to a
1032 * lower mask, as we can always also support a lower one. */
1033 while (1) {
1034 err = dma_set_mask(dev->dev->dma_dev, mask);
1035 if (!err) {
1036 err = dma_set_coherent_mask(dev->dev->dma_dev, mask);
1037 if (!err)
1038 break;
1039 }
1040 if (mask == DMA_BIT_MASK(64)) {
1041 mask = DMA_BIT_MASK(32);
1042 fallback = 1;
1043 continue;
1044 }
1045 if (mask == DMA_BIT_MASK(32)) {
1046 mask = DMA_BIT_MASK(30);
1047 fallback = 1;
1048 continue;
1049 }
1050 b43err(dev->wl, "The machine/kernel does not support "
1051 "the required %u-bit DMA mask\n",
1052 (unsigned int)dma_mask_to_engine_type(orig_mask));
1053 return -EOPNOTSUPP;
1054 }
1055 if (fallback) {
1056 b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
1057 (unsigned int)dma_mask_to_engine_type(orig_mask),
1058 (unsigned int)dma_mask_to_engine_type(mask));
1059 }
1060
1061 return 0;
1062 }
1063
1064 int b43_dma_init(struct b43_wldev *dev)
1065 {
1066 struct b43_dma *dma = &dev->dma;
1067 int err;
1068 u64 dmamask;
1069 enum b43_dmatype type;
1070
1071 dmamask = supported_dma_mask(dev);
1072 type = dma_mask_to_engine_type(dmamask);
1073 err = b43_dma_set_mask(dev, dmamask);
1074 if (err)
1075 return err;
1076
1077 switch (dev->dev->bus_type) {
1078 #ifdef CONFIG_B43_BCMA
1079 case B43_BUS_BCMA:
1080 dma->translation = bcma_core_dma_translation(dev->dev->bdev);
1081 break;
1082 #endif
1083 #ifdef CONFIG_B43_SSB
1084 case B43_BUS_SSB:
1085 dma->translation = ssb_dma_translation(dev->dev->sdev);
1086 break;
1087 #endif
1088 }
1089
1090 dma->parity = true;
1091 #ifdef CONFIG_B43_BCMA
1092 /* TODO: find out which SSB devices need disabling parity */
1093 if (dev->dev->bus_type == B43_BUS_BCMA)
1094 dma->parity = false;
1095 #endif
1096
1097 err = -ENOMEM;
1098 /* setup TX DMA channels. */
1099 dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1100 if (!dma->tx_ring_AC_BK)
1101 goto out;
1102
1103 dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1104 if (!dma->tx_ring_AC_BE)
1105 goto err_destroy_bk;
1106
1107 dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1108 if (!dma->tx_ring_AC_VI)
1109 goto err_destroy_be;
1110
1111 dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1112 if (!dma->tx_ring_AC_VO)
1113 goto err_destroy_vi;
1114
1115 dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1116 if (!dma->tx_ring_mcast)
1117 goto err_destroy_vo;
1118
1119 /* setup RX DMA channel. */
1120 dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1121 if (!dma->rx_ring)
1122 goto err_destroy_mcast;
1123
1124 /* No support for the TX status DMA ring. */
1125 B43_WARN_ON(dev->dev->core_rev < 5);
1126
1127 b43dbg(dev->wl, "%u-bit DMA initialized\n",
1128 (unsigned int)type);
1129 err = 0;
1130 out:
1131 return err;
1132
1133 err_destroy_mcast:
1134 destroy_ring(dma, tx_ring_mcast);
1135 err_destroy_vo:
1136 destroy_ring(dma, tx_ring_AC_VO);
1137 err_destroy_vi:
1138 destroy_ring(dma, tx_ring_AC_VI);
1139 err_destroy_be:
1140 destroy_ring(dma, tx_ring_AC_BE);
1141 err_destroy_bk:
1142 destroy_ring(dma, tx_ring_AC_BK);
1143 return err;
1144 }
1145
1146 /* Generate a cookie for the TX header. */
1147 static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1148 {
1149 u16 cookie;
1150
1151 /* Use the upper 4 bits of the cookie as
1152 * DMA controller ID and store the slot number
1153 * in the lower 12 bits.
1154 * Note that the cookie must never be 0, as this
1155 * is a special value used in RX path.
1156 * It can also not be 0xFFFF because that is special
1157 * for multicast frames.
1158 */
1159 cookie = (((u16)ring->index + 1) << 12);
1160 B43_WARN_ON(slot & ~0x0FFF);
1161 cookie |= (u16)slot;
1162
1163 return cookie;
1164 }
1165
1166 /* Inspect a cookie and find out to which controller/slot it belongs. */
1167 static
1168 struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1169 {
1170 struct b43_dma *dma = &dev->dma;
1171 struct b43_dmaring *ring = NULL;
1172
1173 switch (cookie & 0xF000) {
1174 case 0x1000:
1175 ring = dma->tx_ring_AC_BK;
1176 break;
1177 case 0x2000:
1178 ring = dma->tx_ring_AC_BE;
1179 break;
1180 case 0x3000:
1181 ring = dma->tx_ring_AC_VI;
1182 break;
1183 case 0x4000:
1184 ring = dma->tx_ring_AC_VO;
1185 break;
1186 case 0x5000:
1187 ring = dma->tx_ring_mcast;
1188 break;
1189 }
1190 *slot = (cookie & 0x0FFF);
1191 if (unlikely(!ring || *slot < 0 || *slot >= ring->nr_slots)) {
1192 b43dbg(dev->wl, "TX-status contains "
1193 "invalid cookie: 0x%04X\n", cookie);
1194 return NULL;
1195 }
1196
1197 return ring;
1198 }
1199
1200 static int dma_tx_fragment(struct b43_dmaring *ring,
1201 struct sk_buff *skb)
1202 {
1203 const struct b43_dma_ops *ops = ring->ops;
1204 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1205 struct b43_private_tx_info *priv_info = b43_get_priv_tx_info(info);
1206 u8 *header;
1207 int slot, old_top_slot, old_used_slots;
1208 int err;
1209 struct b43_dmadesc_generic *desc;
1210 struct b43_dmadesc_meta *meta;
1211 struct b43_dmadesc_meta *meta_hdr;
1212 u16 cookie;
1213 size_t hdrsize = b43_txhdr_size(ring->dev);
1214
1215 /* Important note: If the number of used DMA slots per TX frame
1216 * is changed here, the TX_SLOTS_PER_FRAME definition at the top of
1217 * the file has to be updated, too!
1218 */
1219
1220 old_top_slot = ring->current_slot;
1221 old_used_slots = ring->used_slots;
1222
1223 /* Get a slot for the header. */
1224 slot = request_slot(ring);
1225 desc = ops->idx2desc(ring, slot, &meta_hdr);
1226 memset(meta_hdr, 0, sizeof(*meta_hdr));
1227
1228 header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]);
1229 cookie = generate_cookie(ring, slot);
1230 err = b43_generate_txhdr(ring->dev, header,
1231 skb, info, cookie);
1232 if (unlikely(err)) {
1233 ring->current_slot = old_top_slot;
1234 ring->used_slots = old_used_slots;
1235 return err;
1236 }
1237
1238 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1239 hdrsize, 1);
1240 if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
1241 ring->current_slot = old_top_slot;
1242 ring->used_slots = old_used_slots;
1243 return -EIO;
1244 }
1245 ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1246 hdrsize, 1, 0, 0);
1247
1248 /* Get a slot for the payload. */
1249 slot = request_slot(ring);
1250 desc = ops->idx2desc(ring, slot, &meta);
1251 memset(meta, 0, sizeof(*meta));
1252
1253 meta->skb = skb;
1254 meta->is_last_fragment = 1;
1255 priv_info->bouncebuffer = NULL;
1256
1257 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1258 /* create a bounce buffer in zone_dma on mapping failure. */
1259 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1260 priv_info->bouncebuffer = kmemdup(skb->data, skb->len,
1261 GFP_ATOMIC | GFP_DMA);
1262 if (!priv_info->bouncebuffer) {
1263 ring->current_slot = old_top_slot;
1264 ring->used_slots = old_used_slots;
1265 err = -ENOMEM;
1266 goto out_unmap_hdr;
1267 }
1268
1269 meta->dmaaddr = map_descbuffer(ring, priv_info->bouncebuffer, skb->len, 1);
1270 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1271 kfree(priv_info->bouncebuffer);
1272 priv_info->bouncebuffer = NULL;
1273 ring->current_slot = old_top_slot;
1274 ring->used_slots = old_used_slots;
1275 err = -EIO;
1276 goto out_unmap_hdr;
1277 }
1278 }
1279
1280 ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1281
1282 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1283 /* Tell the firmware about the cookie of the last
1284 * mcast frame, so it can clear the more-data bit in it. */
1285 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1286 B43_SHM_SH_MCASTCOOKIE, cookie);
1287 }
1288 /* Now transfer the whole frame. */
1289 wmb();
1290 ops->poke_tx(ring, next_slot(ring, slot));
1291 return 0;
1292
1293 out_unmap_hdr:
1294 unmap_descbuffer(ring, meta_hdr->dmaaddr,
1295 hdrsize, 1);
1296 return err;
1297 }
1298
1299 static inline int should_inject_overflow(struct b43_dmaring *ring)
1300 {
1301 #ifdef CONFIG_B43_DEBUG
1302 if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1303 /* Check if we should inject another ringbuffer overflow
1304 * to test handling of this situation in the stack. */
1305 unsigned long next_overflow;
1306
1307 next_overflow = ring->last_injected_overflow + HZ;
1308 if (time_after(jiffies, next_overflow)) {
1309 ring->last_injected_overflow = jiffies;
1310 b43dbg(ring->dev->wl,
1311 "Injecting TX ring overflow on "
1312 "DMA controller %d\n", ring->index);
1313 return 1;
1314 }
1315 }
1316 #endif /* CONFIG_B43_DEBUG */
1317 return 0;
1318 }
1319
1320 /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1321 static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev,
1322 u8 queue_prio)
1323 {
1324 struct b43_dmaring *ring;
1325
1326 if (dev->qos_enabled) {
1327 /* 0 = highest priority */
1328 switch (queue_prio) {
1329 default:
1330 B43_WARN_ON(1);
1331 /* fallthrough */
1332 case 0:
1333 ring = dev->dma.tx_ring_AC_VO;
1334 break;
1335 case 1:
1336 ring = dev->dma.tx_ring_AC_VI;
1337 break;
1338 case 2:
1339 ring = dev->dma.tx_ring_AC_BE;
1340 break;
1341 case 3:
1342 ring = dev->dma.tx_ring_AC_BK;
1343 break;
1344 }
1345 } else
1346 ring = dev->dma.tx_ring_AC_BE;
1347
1348 return ring;
1349 }
1350
1351 int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
1352 {
1353 struct b43_dmaring *ring;
1354 struct ieee80211_hdr *hdr;
1355 int err = 0;
1356 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1357
1358 hdr = (struct ieee80211_hdr *)skb->data;
1359 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1360 /* The multicast ring will be sent after the DTIM */
1361 ring = dev->dma.tx_ring_mcast;
1362 /* Set the more-data bit. Ucode will clear it on
1363 * the last frame for us. */
1364 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1365 } else {
1366 /* Decide by priority where to put this frame. */
1367 ring = select_ring_by_priority(
1368 dev, skb_get_queue_mapping(skb));
1369 }
1370
1371 B43_WARN_ON(!ring->tx);
1372
1373 if (unlikely(ring->stopped)) {
1374 /* We get here only because of a bug in mac80211.
1375 * Because of a race, one packet may be queued after
1376 * the queue is stopped, thus we got called when we shouldn't.
1377 * For now, just refuse the transmit. */
1378 if (b43_debug(dev, B43_DBG_DMAVERBOSE))
1379 b43err(dev->wl, "Packet after queue stopped\n");
1380 err = -ENOSPC;
1381 goto out;
1382 }
1383
1384 if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) {
1385 /* If we get here, we have a real error with the queue
1386 * full, but queues not stopped. */
1387 b43err(dev->wl, "DMA queue overflow\n");
1388 err = -ENOSPC;
1389 goto out;
1390 }
1391
1392 /* Assign the queue number to the ring (if not already done before)
1393 * so TX status handling can use it. The queue to ring mapping is
1394 * static, so we don't need to store it per frame. */
1395 ring->queue_prio = skb_get_queue_mapping(skb);
1396
1397 err = dma_tx_fragment(ring, skb);
1398 if (unlikely(err == -ENOKEY)) {
1399 /* Drop this packet, as we don't have the encryption key
1400 * anymore and must not transmit it unencrypted. */
1401 dev_kfree_skb_any(skb);
1402 err = 0;
1403 goto out;
1404 }
1405 if (unlikely(err)) {
1406 b43err(dev->wl, "DMA tx mapping failure\n");
1407 goto out;
1408 }
1409 if ((free_slots(ring) < TX_SLOTS_PER_FRAME) ||
1410 should_inject_overflow(ring)) {
1411 /* This TX ring is full. */
1412 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
1413 ring->stopped = 1;
1414 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1415 b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1416 }
1417 }
1418 out:
1419
1420 return err;
1421 }
1422
1423 void b43_dma_handle_txstatus(struct b43_wldev *dev,
1424 const struct b43_txstatus *status)
1425 {
1426 const struct b43_dma_ops *ops;
1427 struct b43_dmaring *ring;
1428 struct b43_dmadesc_meta *meta;
1429 int slot, firstused;
1430 bool frame_succeed;
1431
1432 ring = parse_cookie(dev, status->cookie, &slot);
1433 if (unlikely(!ring))
1434 return;
1435 B43_WARN_ON(!ring->tx);
1436
1437 /* Sanity check: TX packets are processed in-order on one ring.
1438 * Check if the slot deduced from the cookie really is the first
1439 * used slot. */
1440 firstused = ring->current_slot - ring->used_slots + 1;
1441 if (firstused < 0)
1442 firstused = ring->nr_slots + firstused;
1443 if (unlikely(slot != firstused)) {
1444 /* This possibly is a firmware bug and will result in
1445 * malfunction, memory leaks and/or stall of DMA functionality. */
1446 b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. "
1447 "Expected %d, but got %d\n",
1448 ring->index, firstused, slot);
1449 return;
1450 }
1451
1452 ops = ring->ops;
1453 while (1) {
1454 B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);
1455 /* get meta - ignore returned value */
1456 ops->idx2desc(ring, slot, &meta);
1457
1458 if (b43_dma_ptr_is_poisoned(meta->skb)) {
1459 b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) "
1460 "on ring %d\n",
1461 slot, firstused, ring->index);
1462 break;
1463 }
1464 if (meta->skb) {
1465 struct b43_private_tx_info *priv_info =
1466 b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
1467
1468 unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
1469 kfree(priv_info->bouncebuffer);
1470 priv_info->bouncebuffer = NULL;
1471 } else {
1472 unmap_descbuffer(ring, meta->dmaaddr,
1473 b43_txhdr_size(dev), 1);
1474 }
1475
1476 if (meta->is_last_fragment) {
1477 struct ieee80211_tx_info *info;
1478
1479 if (unlikely(!meta->skb)) {
1480 /* This is a scatter-gather fragment of a frame, so
1481 * the skb pointer must not be NULL. */
1482 b43dbg(dev->wl, "TX status unexpected NULL skb "
1483 "at slot %d (first=%d) on ring %d\n",
1484 slot, firstused, ring->index);
1485 break;
1486 }
1487
1488 info = IEEE80211_SKB_CB(meta->skb);
1489
1490 /*
1491 * Call back to inform the ieee80211 subsystem about
1492 * the status of the transmission.
1493 */
1494 frame_succeed = b43_fill_txstatus_report(dev, info, status);
1495 #ifdef CONFIG_B43_DEBUG
1496 if (frame_succeed)
1497 ring->nr_succeed_tx_packets++;
1498 else
1499 ring->nr_failed_tx_packets++;
1500 ring->nr_total_packet_tries += status->frame_count;
1501 #endif /* DEBUG */
1502 ieee80211_tx_status(dev->wl->hw, meta->skb);
1503
1504 /* skb will be freed by ieee80211_tx_status().
1505 * Poison our pointer. */
1506 meta->skb = B43_DMA_PTR_POISON;
1507 } else {
1508 /* No need to call free_descriptor_buffer here, as
1509 * this is only the txhdr, which is not allocated.
1510 */
1511 if (unlikely(meta->skb)) {
1512 b43dbg(dev->wl, "TX status unexpected non-NULL skb "
1513 "at slot %d (first=%d) on ring %d\n",
1514 slot, firstused, ring->index);
1515 break;
1516 }
1517 }
1518
1519 /* Everything unmapped and free'd. So it's not used anymore. */
1520 ring->used_slots--;
1521
1522 if (meta->is_last_fragment) {
1523 /* This is the last scatter-gather
1524 * fragment of the frame. We are done. */
1525 break;
1526 }
1527 slot = next_slot(ring, slot);
1528 }
1529 if (ring->stopped) {
1530 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
1531 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
1532 ring->stopped = 0;
1533 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1534 b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1535 }
1536 }
1537 }
1538
1539 static void dma_rx(struct b43_dmaring *ring, int *slot)
1540 {
1541 const struct b43_dma_ops *ops = ring->ops;
1542 struct b43_dmadesc_generic *desc;
1543 struct b43_dmadesc_meta *meta;
1544 struct b43_rxhdr_fw4 *rxhdr;
1545 struct sk_buff *skb;
1546 u16 len;
1547 int err;
1548 dma_addr_t dmaaddr;
1549
1550 desc = ops->idx2desc(ring, *slot, &meta);
1551
1552 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1553 skb = meta->skb;
1554
1555 rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1556 len = le16_to_cpu(rxhdr->frame_len);
1557 if (len == 0) {
1558 int i = 0;
1559
1560 do {
1561 udelay(2);
1562 barrier();
1563 len = le16_to_cpu(rxhdr->frame_len);
1564 } while (len == 0 && i++ < 5);
1565 if (unlikely(len == 0)) {
1566 dmaaddr = meta->dmaaddr;
1567 goto drop_recycle_buffer;
1568 }
1569 }
1570 if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) {
1571 /* Something went wrong with the DMA.
1572 * The device did not touch the buffer and did not overwrite the poison. */
1573 b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n");
1574 dmaaddr = meta->dmaaddr;
1575 goto drop_recycle_buffer;
1576 }
1577 if (unlikely(len + ring->frameoffset > ring->rx_buffersize)) {
1578 /* The data did not fit into one descriptor buffer
1579 * and is split over multiple buffers.
1580 * This should never happen, as we try to allocate buffers
1581 * big enough. So simply ignore this packet.
1582 */
1583 int cnt = 0;
1584 s32 tmp = len;
1585
1586 while (1) {
1587 desc = ops->idx2desc(ring, *slot, &meta);
1588 /* recycle the descriptor buffer. */
1589 b43_poison_rx_buffer(ring, meta->skb);
1590 sync_descbuffer_for_device(ring, meta->dmaaddr,
1591 ring->rx_buffersize);
1592 *slot = next_slot(ring, *slot);
1593 cnt++;
1594 tmp -= ring->rx_buffersize;
1595 if (tmp <= 0)
1596 break;
1597 }
1598 b43err(ring->dev->wl, "DMA RX buffer too small "
1599 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1600 len, ring->rx_buffersize, cnt);
1601 goto drop;
1602 }
1603
1604 dmaaddr = meta->dmaaddr;
1605 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1606 if (unlikely(err)) {
1607 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1608 goto drop_recycle_buffer;
1609 }
1610
1611 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1612 skb_put(skb, len + ring->frameoffset);
1613 skb_pull(skb, ring->frameoffset);
1614
1615 b43_rx(ring->dev, skb, rxhdr);
1616 drop:
1617 return;
1618
1619 drop_recycle_buffer:
1620 /* Poison and recycle the RX buffer. */
1621 b43_poison_rx_buffer(ring, skb);
1622 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1623 }
1624
1625 void b43_dma_rx(struct b43_dmaring *ring)
1626 {
1627 const struct b43_dma_ops *ops = ring->ops;
1628 int slot, current_slot;
1629 int used_slots = 0;
1630
1631 B43_WARN_ON(ring->tx);
1632 current_slot = ops->get_current_rxslot(ring);
1633 B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1634
1635 slot = ring->current_slot;
1636 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1637 dma_rx(ring, &slot);
1638 update_max_used_slots(ring, ++used_slots);
1639 }
1640 wmb();
1641 ops->set_current_rxslot(ring, slot);
1642 ring->current_slot = slot;
1643 }
1644
1645 static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1646 {
1647 B43_WARN_ON(!ring->tx);
1648 ring->ops->tx_suspend(ring);
1649 }
1650
1651 static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1652 {
1653 B43_WARN_ON(!ring->tx);
1654 ring->ops->tx_resume(ring);
1655 }
1656
1657 void b43_dma_tx_suspend(struct b43_wldev *dev)
1658 {
1659 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1660 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1661 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1662 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1663 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1664 b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
1665 }
1666
1667 void b43_dma_tx_resume(struct b43_wldev *dev)
1668 {
1669 b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1670 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1671 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1672 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1673 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
1674 b43_power_saving_ctl_bits(dev, 0);
1675 }
1676
1677 static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1678 u16 mmio_base, bool enable)
1679 {
1680 u32 ctl;
1681
1682 if (type == B43_DMA_64BIT) {
1683 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1684 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1685 if (enable)
1686 ctl |= B43_DMA64_RXDIRECTFIFO;
1687 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1688 } else {
1689 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1690 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1691 if (enable)
1692 ctl |= B43_DMA32_RXDIRECTFIFO;
1693 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1694 }
1695 }
1696
1697 /* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1698 * This is called from PIO code, so DMA structures are not available. */
1699 void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1700 unsigned int engine_index, bool enable)
1701 {
1702 enum b43_dmatype type;
1703 u16 mmio_base;
1704
1705 type = dma_mask_to_engine_type(supported_dma_mask(dev));
1706
1707 mmio_base = b43_dmacontroller_base(type, engine_index);
1708 direct_fifo_rx(dev, type, mmio_base, enable);
1709 }
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