| blob | 2eca8475d39671f6c295066075722d9e038c0074 |
1 /*
2 * linux/arch/arm/mach-omap2/prcm.c
3 *
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
14 * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24 #include <linux/delay.h>
26 #include <plat/common.h>
27 #include <plat/prcm.h>
28 #include <plat/irqs.h>
42 #define MAX_MODULE_ENABLE_WAIT 100000
45 u32 control_padconf_sys_nirq;
46 u32 iva2_cm_clksel1;
47 u32 iva2_cm_clksel2;
48 u32 cm_sysconfig;
49 u32 sgx_cm_clksel;
50 u32 dss_cm_clksel;
51 u32 cam_cm_clksel;
52 u32 per_cm_clksel;
53 u32 emu_cm_clksel;
54 u32 emu_cm_clkstctrl;
55 u32 pll_cm_autoidle2;
56 u32 pll_cm_clksel4;
57 u32 pll_cm_clksel5;
58 u32 pll_cm_clken2;
59 u32 cm_polctrl;
60 u32 iva2_cm_fclken;
61 u32 iva2_cm_clken_pll;
62 u32 core_cm_fclken1;
63 u32 core_cm_fclken3;
64 u32 sgx_cm_fclken;
65 u32 wkup_cm_fclken;
66 u32 dss_cm_fclken;
67 u32 cam_cm_fclken;
68 u32 per_cm_fclken;
69 u32 usbhost_cm_fclken;
70 u32 core_cm_iclken1;
71 u32 core_cm_iclken2;
72 u32 core_cm_iclken3;
73 u32 sgx_cm_iclken;
74 u32 wkup_cm_iclken;
75 u32 dss_cm_iclken;
76 u32 cam_cm_iclken;
77 u32 per_cm_iclken;
78 u32 usbhost_cm_iclken;
79 u32 iva2_cm_autiidle2;
80 u32 mpu_cm_autoidle2;
81 u32 iva2_cm_clkstctrl;
82 u32 mpu_cm_clkstctrl;
83 u32 core_cm_clkstctrl;
84 u32 sgx_cm_clkstctrl;
85 u32 dss_cm_clkstctrl;
86 u32 cam_cm_clkstctrl;
87 u32 per_cm_clkstctrl;
88 u32 neon_cm_clkstctrl;
89 u32 usbhost_cm_clkstctrl;
90 u32 core_cm_autoidle1;
91 u32 core_cm_autoidle2;
92 u32 core_cm_autoidle3;
93 u32 wkup_cm_autoidle;
94 u32 dss_cm_autoidle;
95 u32 cam_cm_autoidle;
96 u32 per_cm_autoidle;
97 u32 usbhost_cm_autoidle;
98 u32 sgx_cm_sleepdep;
99 u32 dss_cm_sleepdep;
100 u32 cam_cm_sleepdep;
101 u32 per_cm_sleepdep;
102 u32 usbhost_cm_sleepdep;
103 u32 cm_clkout_ctrl;
104 u32 prm_clkout_ctrl;
105 u32 sgx_pm_wkdep;
106 u32 dss_pm_wkdep;
107 u32 cam_pm_wkdep;
108 u32 per_pm_wkdep;
109 u32 neon_pm_wkdep;
110 u32 usbhost_pm_wkdep;
111 u32 core_pm_mpugrpsel1;
112 u32 iva2_pm_ivagrpsel1;
113 u32 core_pm_mpugrpsel3;
114 u32 core_pm_ivagrpsel3;
115 u32 wkup_pm_mpugrpsel;
116 u32 wkup_pm_ivagrpsel;
117 u32 per_pm_mpugrpsel;
118 u32 per_pm_ivagrpsel;
119 u32 wkup_pm_wken;
120 };
125 {
126 /* XXX This presumably needs modification for 34XX */
133 }
136 /* Resets clock rates and reboots the system. Only called from system.h */
138 {
150 else
155 OMAP2_RM_RSTCTRL);
159 }
162 {
165 }
169 {
172 }
174 /* Read a register in a PRM module */
176 {
178 }
180 /* Write into a register in a PRM module */
182 {
184 }
186 /* Read-modify-write a register in a PRM module. Caller must lock */
188 {
189 u32 v;
197 }
199 /* Read a PRM register, AND it, and shift the result down to bit 0 */
201 {
202 u32 v;
209 }
211 /* Read a PRM register, AND it, and shift the result down to bit 0 */
213 {
214 u32 v;
221 }
223 /* Read-modify-write a register in a PRM module. Caller must lock */
225 {
226 u32 v;
234 }
235 /* Read a register in a CM module */
237 {
239 }
241 /* Write into a register in a CM module */
243 {
245 }
247 /* Read-modify-write a register in a CM module. Caller must lock */
249 {
250 u32 v;
258 }
260 /**
261 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
262 * @reg: physical address of module IDLEST register
263 * @mask: value to mask against to determine if the module is active
264 * @idlest: idle state indicator (0 or 1) for the clock
265 * @name: name of the clock (for printk)
266 *
267 * Returns 1 if the module indicated readiness in time, or 0 if it
268 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
269 */
272 {
278 else
281 /* Wait for lock */
288 else
293 };
296 {
297 /* Static mapping, never released */
301 }
305 }
309 }
310 }
312 #ifdef CONFIG_ARCH_OMAP3
314 {
346 OMAP3430_CM_CLKEN_PLL);
393 OMAP2_CM_CLKSTCTRL);
404 OMAP2_CM_CLKSTCTRL);
432 OMAP3_CM_CLKOUT_CTRL_OFFSET);
434 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
465 }
468 {
470 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
472 CM_CLKSEL1);
474 CM_CLKSEL2);
477 CM_CLKSEL);
479 CM_CLKSEL);
481 CM_CLKSEL);
483 CM_CLKSEL);
485 CM_CLKSEL1);
487 OMAP2_CM_CLKSTCTRL);
489 CM_AUTOIDLE2);
491 OMAP3430ES2_CM_CLKSEL4);
493 OMAP3430ES2_CM_CLKSEL5);
495 OMAP3430ES2_CM_CLKEN2);
498 CM_FCLKEN);
500 OMAP3430_CM_CLKEN_PLL);
503 OMAP3430ES2_CM_FCLKEN3);
505 CM_FCLKEN);
508 CM_FCLKEN);
510 CM_FCLKEN);
512 CM_FCLKEN);
519 CM_ICLKEN);
522 CM_ICLKEN);
524 CM_ICLKEN);
526 CM_ICLKEN);
530 CM_AUTOIDLE2);
533 OMAP2_CM_CLKSTCTRL);
535 OMAP2_CM_CLKSTCTRL);
537 OMAP2_CM_CLKSTCTRL);
539 OMAP2_CM_CLKSTCTRL);
541 OMAP2_CM_CLKSTCTRL);
543 OMAP2_CM_CLKSTCTRL);
545 OMAP2_CM_CLKSTCTRL);
547 OMAP2_CM_CLKSTCTRL);
551 CM_AUTOIDLE1);
553 CM_AUTOIDLE2);
555 CM_AUTOIDLE3);
558 CM_AUTOIDLE);
560 CM_AUTOIDLE);
562 CM_AUTOIDLE);
566 OMAP3430_CM_SLEEPDEP);
568 OMAP3430_CM_SLEEPDEP);
570 OMAP3430_CM_SLEEPDEP);
572 OMAP3430_CM_SLEEPDEP);
576 OMAP3_CM_CLKOUT_CTRL_OFFSET);
578 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
580 PM_WKDEP);
582 PM_WKDEP);
584 PM_WKDEP);
586 PM_WKDEP);
588 PM_WKDEP);
592 OMAP3430_PM_MPUGRPSEL1);
594 OMAP3430_PM_IVAGRPSEL1);
596 OMAP3430ES2_PM_MPUGRPSEL3);
598 OMAP3430ES2_PM_IVAGRPSEL3);
600 OMAP3430_PM_MPUGRPSEL);
602 OMAP3430_PM_IVAGRPSEL);
604 OMAP3430_PM_MPUGRPSEL);
606 OMAP3430_PM_IVAGRPSEL);
609 }
610 #endif