drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include <drm/drm_crtc.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include <drm/drm_dp_helper.h>
  35
  36 /**
  37  * _wait_for - magic (register) wait macro
  38  *
  39  * Does the right thing for modeset paths when run under kdgb or similar atomic
  40  * contexts. Note that it's important that we check the condition again after
  41  * having timed out, since the timeout could be due to preemption or similar and
  42  * we've never had a chance to check the condition before the timeout.
  43  */
  44 #define _wait_for(COND, MS, W) ({ \
  45         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  46         int ret__ = 0;                                                  \
  47         while (!(COND)) {                                               \
  48                 if (time_after(jiffies, timeout__)) {                   \
  49                         if (!(COND))                                    \
  50                                 ret__ = -ETIMEDOUT;                     \
  51                         break;                                          \
  52                 }                                                       \
  53                 if (W && drm_can_sleep())  {                            \
  54                         msleep(W);                                      \
  55                 } else {                                                \
  56                         cpu_relax();                                    \
  57                 }                                                       \
  58         }                                                               \
  59         ret__;                                                          \
  60 })
  61
  62 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  63 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  64 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  65                                                DIV_ROUND_UP((US), 1000), 0)
  66
  67 #define KHz(x) (1000*x)
  68 #define MHz(x) KHz(1000*x)
  69
  70 /*
  71  * Display related stuff
  72  */
  73
  74 /* store information about an Ixxx DVO */
  75 /* The i830->i865 use multiple DVOs with multiple i2cs */
  76 /* the i915, i945 have a single sDVO i2c bus - which is different */
  77 #define MAX_OUTPUTS 6
  78 /* maximum connectors per crtcs in the mode set */
  79 #define INTELFB_CONN_LIMIT 4
  80
  81 #define INTEL_I2C_BUS_DVO 1
  82 #define INTEL_I2C_BUS_SDVO 2
  83
  84 /* these are outputs from the chip - integrated only
  85    external chips are via DVO or SDVO output */
  86 #define INTEL_OUTPUT_UNUSED 0
  87 #define INTEL_OUTPUT_ANALOG 1
  88 #define INTEL_OUTPUT_DVO 2
  89 #define INTEL_OUTPUT_SDVO 3
  90 #define INTEL_OUTPUT_LVDS 4
  91 #define INTEL_OUTPUT_TVOUT 5
  92 #define INTEL_OUTPUT_HDMI 6
  93 #define INTEL_OUTPUT_DISPLAYPORT 7
  94 #define INTEL_OUTPUT_EDP 8
  95 #define INTEL_OUTPUT_UNKNOWN 9
  96
  97 #define INTEL_DVO_CHIP_NONE 0
  98 #define INTEL_DVO_CHIP_LVDS 1
  99 #define INTEL_DVO_CHIP_TMDS 2
 100 #define INTEL_DVO_CHIP_TVOUT 4
 101
 102 struct intel_framebuffer {
 103         struct drm_framebuffer base;
 104         struct drm_i915_gem_object *obj;
 105 };
 106
 107 struct intel_fbdev {
 108         struct drm_fb_helper helper;
 109         struct intel_framebuffer ifb;
 110         struct list_head fbdev_list;
 111         struct drm_display_mode *our_mode;
 112 };
 113
 114 struct intel_encoder {
 115         struct drm_encoder base;
 116         /*
 117          * The new crtc this encoder will be driven from. Only differs from
 118          * base->crtc while a modeset is in progress.
 119          */
 120         struct intel_crtc *new_crtc;
 121
 122         int type;
 123         bool needs_tv_clock;
 124         /*
 125          * Intel hw has only one MUX where encoders could be clone, hence a
 126          * simple flag is enough to compute the possible_clones mask.
 127          */
 128         bool cloneable;
 129         bool connectors_active;
 130         void (*hot_plug)(struct intel_encoder *);
 131         bool (*compute_config)(struct intel_encoder *,
 132                                struct intel_crtc_config *);
 133         void (*pre_pll_enable)(struct intel_encoder *);
 134         void (*pre_enable)(struct intel_encoder *);
 135         void (*enable)(struct intel_encoder *);
 136         void (*mode_set)(struct intel_encoder *intel_encoder);
 137         void (*disable)(struct intel_encoder *);
 138         void (*post_disable)(struct intel_encoder *);
 139         /* Read out the current hw state of this connector, returning true if
 140          * the encoder is active. If the encoder is enabled it also set the pipe
 141          * it is connected to in the pipe parameter. */
 142         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 143         int crtc_mask;
 144         enum hpd_pin hpd_pin;
 145 };
 146
 147 struct intel_panel {
 148         struct drm_display_mode *fixed_mode;
 149         int fitting_mode;
 150 };
 151
 152 struct intel_connector {
 153         struct drm_connector base;
 154         /*
 155          * The fixed encoder this connector is connected to.
 156          */
 157         struct intel_encoder *encoder;
 158
 159         /*
 160          * The new encoder this connector will be driven. Only differs from
 161          * encoder while a modeset is in progress.
 162          */
 163         struct intel_encoder *new_encoder;
 164
 165         /* Reads out the current hw, returning true if the connector is enabled
 166          * and active (i.e. dpms ON state). */
 167         bool (*get_hw_state)(struct intel_connector *);
 168
 169         /* Panel info for eDP and LVDS */
 170         struct intel_panel panel;
 171
 172         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 173         struct edid *edid;
 174 };
 175
 176 struct intel_crtc_config {
 177         struct drm_display_mode requested_mode;
 178         struct drm_display_mode adjusted_mode;
 179         /* This flag must be set by the encoder's compute_config callback if it
 180          * changes the crtc timings in the mode to prevent the crtc fixup from
 181          * overwriting them.  Currently only lvds needs that. */
 182         bool timings_set;
 183         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 184          * between pch encoders and cpu encoders. */
 185         bool has_pch_encoder;
 186
 187         /*
 188          * Use reduced/limited/broadcast rbg range, compressing from the full
 189          * range fed into the crtcs.
 190          */
 191         bool limited_color_range;
 192
 193         /* DP has a bunch of special case unfortunately, so mark the pipe
 194          * accordingly. */
 195         bool has_dp_encoder;
 196         bool dither;
 197
 198         /* Controls for the clock computation, to override various stages. */
 199         bool clock_set;
 200
 201         /* Settings for the intel dpll used on pretty much everything but
 202          * haswell. */
 203         struct dpll {
 204                 unsigned n;
 205                 unsigned m1, m2;
 206                 unsigned p1, p2;
 207         } dpll;
 208
 209         int pipe_bpp;
 210         struct intel_link_m_n dp_m_n;
 211         /**
 212          * This is currently used by DP and HDMI encoders since those can have a
 213          * target pixel clock != the port link clock (which is currently stored
 214          * in adjusted_mode->clock).
 215          */
 216         int pixel_target_clock;
 217         /* Used by SDVO (and if we ever fix it, HDMI). */
 218         unsigned pixel_multiplier;
 219 };
 220
 221 struct intel_crtc {
 222         struct drm_crtc base;
 223         enum pipe pipe;
 224         enum plane plane;
 225         enum transcoder cpu_transcoder;
 226         u8 lut_r[256], lut_g[256], lut_b[256];
 227         /*
 228          * Whether the crtc and the connected output pipeline is active. Implies
 229          * that crtc->enabled is set, i.e. the current mode configuration has
 230          * some outputs connected to this crtc.
 231          */
 232         bool active;
 233         bool eld_vld;
 234         bool primary_disabled; /* is the crtc obscured by a plane? */
 235         bool lowfreq_avail;
 236         struct intel_overlay *overlay;
 237         struct intel_unpin_work *unpin_work;
 238         int fdi_lanes;
 239
 240         atomic_t unpin_work_count;
 241
 242         /* Display surface base address adjustement for pageflips. Note that on
 243          * gen4+ this only adjusts up to a tile, offsets within a tile are
 244          * handled in the hw itself (with the TILEOFF register). */
 245         unsigned long dspaddr_offset;
 246
 247         struct drm_i915_gem_object *cursor_bo;
 248         uint32_t cursor_addr;
 249         int16_t cursor_x, cursor_y;
 250         int16_t cursor_width, cursor_height;
 251         bool cursor_visible;
 252
 253         struct intel_crtc_config config;
 254
 255         /* We can share PLLs across outputs if the timings match */
 256         struct intel_pch_pll *pch_pll;
 257         uint32_t ddi_pll_sel;
 258
 259         /* reset counter value when the last flip was submitted */
 260         unsigned int reset_counter;
 261 };
 262
 263 struct intel_plane {
 264         struct drm_plane base;
 265         int plane;
 266         enum pipe pipe;
 267         struct drm_i915_gem_object *obj;
 268         bool can_scale;
 269         int max_downscale;
 270         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 271         int crtc_x, crtc_y;
 272         unsigned int crtc_w, crtc_h;
 273         uint32_t src_x, src_y;
 274         uint32_t src_w, src_h;
 275         void (*update_plane)(struct drm_plane *plane,
 276                              struct drm_framebuffer *fb,
 277                              struct drm_i915_gem_object *obj,
 278                              int crtc_x, int crtc_y,
 279                              unsigned int crtc_w, unsigned int crtc_h,
 280                              uint32_t x, uint32_t y,
 281                              uint32_t src_w, uint32_t src_h);
 282         void (*disable_plane)(struct drm_plane *plane);
 283         int (*update_colorkey)(struct drm_plane *plane,
 284                                struct drm_intel_sprite_colorkey *key);
 285         void (*get_colorkey)(struct drm_plane *plane,
 286                              struct drm_intel_sprite_colorkey *key);
 287 };
 288
 289 struct intel_watermark_params {
 290         unsigned long fifo_size;
 291         unsigned long max_wm;
 292         unsigned long default_wm;
 293         unsigned long guard_size;
 294         unsigned long cacheline_size;
 295 };
 296
 297 struct cxsr_latency {
 298         int is_desktop;
 299         int is_ddr3;
 300         unsigned long fsb_freq;
 301         unsigned long mem_freq;
 302         unsigned long display_sr;
 303         unsigned long display_hpll_disable;
 304         unsigned long cursor_sr;
 305         unsigned long cursor_hpll_disable;
 306 };
 307
 308 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 309 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 310 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 311 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 312 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 313
 314 #define DIP_HEADER_SIZE 5
 315
 316 #define DIP_TYPE_AVI    0x82
 317 #define DIP_VERSION_AVI 0x2
 318 #define DIP_LEN_AVI     13
 319 #define DIP_AVI_PR_1    0
 320 #define DIP_AVI_PR_2    1
 321 #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
 322 #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
 323 #define DIP_AVI_RGB_QUANT_RANGE_FULL    (2 << 2)
 324
 325 #define DIP_TYPE_SPD    0x83
 326 #define DIP_VERSION_SPD 0x1
 327 #define DIP_LEN_SPD     25
 328 #define DIP_SPD_UNKNOWN 0
 329 #define DIP_SPD_DSTB    0x1
 330 #define DIP_SPD_DVDP    0x2
 331 #define DIP_SPD_DVHS    0x3
 332 #define DIP_SPD_HDDVR   0x4
 333 #define DIP_SPD_DVC     0x5
 334 #define DIP_SPD_DSC     0x6
 335 #define DIP_SPD_VCD     0x7
 336 #define DIP_SPD_GAME    0x8
 337 #define DIP_SPD_PC      0x9
 338 #define DIP_SPD_BD      0xa
 339 #define DIP_SPD_SCD     0xb
 340
 341 struct dip_infoframe {
 342         uint8_t type;           /* HB0 */
 343         uint8_t ver;            /* HB1 */
 344         uint8_t len;            /* HB2 - body len, not including checksum */
 345         uint8_t ecc;            /* Header ECC */
 346         uint8_t checksum;       /* PB0 */
 347         union {
 348                 struct {
 349                         /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
 350                         uint8_t Y_A_B_S;
 351                         /* PB2 - C 7:6, M 5:4, R 3:0 */
 352                         uint8_t C_M_R;
 353                         /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
 354                         uint8_t ITC_EC_Q_SC;
 355                         /* PB4 - VIC 6:0 */
 356                         uint8_t VIC;
 357                         /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
 358                         uint8_t YQ_CN_PR;
 359                         /* PB6 to PB13 */
 360                         uint16_t top_bar_end;
 361                         uint16_t bottom_bar_start;
 362                         uint16_t left_bar_end;
 363                         uint16_t right_bar_start;
 364                 } __attribute__ ((packed)) avi;
 365                 struct {
 366                         uint8_t vn[8];
 367                         uint8_t pd[16];
 368                         uint8_t sdi;
 369                 } __attribute__ ((packed)) spd;
 370                 uint8_t payload[27];
 371         } __attribute__ ((packed)) body;
 372 } __attribute__((packed));
 373
 374 struct intel_hdmi {
 375         u32 hdmi_reg;
 376         int ddc_bus;
 377         uint32_t color_range;
 378         bool color_range_auto;
 379         bool has_hdmi_sink;
 380         bool has_audio;
 381         enum hdmi_force_audio force_audio;
 382         bool rgb_quant_range_selectable;
 383         void (*write_infoframe)(struct drm_encoder *encoder,
 384                                 struct dip_infoframe *frame);
 385         void (*set_infoframes)(struct drm_encoder *encoder,
 386                                struct drm_display_mode *adjusted_mode);
 387 };
 388
 389 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 390 #define DP_LINK_CONFIGURATION_SIZE      9
 391
 392 struct intel_dp {
 393         uint32_t output_reg;
 394         uint32_t aux_ch_ctl_reg;
 395         uint32_t DP;
 396         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
 397         bool has_audio;
 398         enum hdmi_force_audio force_audio;
 399         uint32_t color_range;
 400         bool color_range_auto;
 401         uint8_t link_bw;
 402         uint8_t lane_count;
 403         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 404         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 405         struct i2c_adapter adapter;
 406         struct i2c_algo_dp_aux_data algo;
 407         bool is_pch_edp;
 408         uint8_t train_set[4];
 409         int panel_power_up_delay;
 410         int panel_power_down_delay;
 411         int panel_power_cycle_delay;
 412         int backlight_on_delay;
 413         int backlight_off_delay;
 414         struct delayed_work panel_vdd_work;
 415         bool want_panel_vdd;
 416         struct intel_connector *attached_connector;
 417 };
 418
 419 struct intel_digital_port {
 420         struct intel_encoder base;
 421         enum port port;
 422         u32 port_reversal;
 423         struct intel_dp dp;
 424         struct intel_hdmi hdmi;
 425 };
 426
 427 static inline struct drm_crtc *
 428 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 429 {
 430         struct drm_i915_private *dev_priv = dev->dev_private;
 431         return dev_priv->pipe_to_crtc_mapping[pipe];
 432 }
 433
 434 static inline struct drm_crtc *
 435 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 436 {
 437         struct drm_i915_private *dev_priv = dev->dev_private;
 438         return dev_priv->plane_to_crtc_mapping[plane];
 439 }
 440
 441 struct intel_unpin_work {
 442         struct work_struct work;
 443         struct drm_crtc *crtc;
 444         struct drm_i915_gem_object *old_fb_obj;
 445         struct drm_i915_gem_object *pending_flip_obj;
 446         struct drm_pending_vblank_event *event;
 447         atomic_t pending;
 448 #define INTEL_FLIP_INACTIVE     0
 449 #define INTEL_FLIP_PENDING      1
 450 #define INTEL_FLIP_COMPLETE     2
 451         bool enable_stall_check;
 452 };
 453
 454 struct intel_fbc_work {
 455         struct delayed_work work;
 456         struct drm_crtc *crtc;
 457         struct drm_framebuffer *fb;
 458         int interval;
 459 };
 460
 461 int intel_pch_rawclk(struct drm_device *dev);
 462
 463 int intel_connector_update_modes(struct drm_connector *connector,
 464                                 struct edid *edid);
 465 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 466
 467 extern void intel_attach_force_audio_property(struct drm_connector *connector);
 468 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 469
 470 extern void intel_crt_init(struct drm_device *dev);
 471 extern void intel_hdmi_init(struct drm_device *dev,
 472                             int hdmi_reg, enum port port);
 473 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 474                                       struct intel_connector *intel_connector);
 475 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 476 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 477                                       struct intel_crtc_config *pipe_config);
 478 extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
 479 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
 480                             bool is_sdvob);
 481 extern void intel_dvo_init(struct drm_device *dev);
 482 extern void intel_tv_init(struct drm_device *dev);
 483 extern void intel_mark_busy(struct drm_device *dev);
 484 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
 485 extern void intel_mark_idle(struct drm_device *dev);
 486 extern bool intel_lvds_init(struct drm_device *dev);
 487 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
 488 extern void intel_dp_init(struct drm_device *dev, int output_reg,
 489                           enum port port);
 490 extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 491                                     struct intel_connector *intel_connector);
 492 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
 493 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
 494 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 495 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 496 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 497 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
 498 extern bool intel_dp_compute_config(struct intel_encoder *encoder,
 499                                     struct intel_crtc_config *pipe_config);
 500 extern bool intel_dpd_is_edp(struct drm_device *dev);
 501 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
 502 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
 503 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
 504 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
 505 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 506 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 507 extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
 508 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 509 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
 510                                       enum plane plane);
 511
 512 /* intel_panel.c */
 513 extern int intel_panel_init(struct intel_panel *panel,
 514                             struct drm_display_mode *fixed_mode);
 515 extern void intel_panel_fini(struct intel_panel *panel);
 516
 517 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
 518                                    struct drm_display_mode *adjusted_mode);
 519 extern void intel_pch_panel_fitting(struct drm_device *dev,
 520                                     int fitting_mode,
 521                                     const struct drm_display_mode *mode,
 522                                     struct drm_display_mode *adjusted_mode);
 523 extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
 524 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
 525 extern int intel_panel_setup_backlight(struct drm_connector *connector);
 526 extern void intel_panel_enable_backlight(struct drm_device *dev,
 527                                          enum pipe pipe);
 528 extern void intel_panel_disable_backlight(struct drm_device *dev);
 529 extern void intel_panel_destroy_backlight(struct drm_device *dev);
 530 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 531
 532 struct intel_set_config {
 533         struct drm_encoder **save_connector_encoders;
 534         struct drm_crtc **save_encoder_crtcs;
 535
 536         bool fb_changed;
 537         bool mode_changed;
 538 };
 539
 540 extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
 541                           int x, int y, struct drm_framebuffer *old_fb);
 542 extern void intel_modeset_disable(struct drm_device *dev);
 543 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
 544 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
 545 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
 546 extern void intel_encoder_destroy(struct drm_encoder *encoder);
 547 extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
 548 extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
 549 extern void intel_connector_dpms(struct drm_connector *, int mode);
 550 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
 551 extern void intel_modeset_check_state(struct drm_device *dev);
 552 extern void intel_plane_restore(struct drm_plane *plane);
 553
 554
 555 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
 556 {
 557         return to_intel_connector(connector)->encoder;
 558 }
 559
 560 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 561 {
 562         struct intel_digital_port *intel_dig_port =
 563                 container_of(encoder, struct intel_digital_port, base.base);
 564         return &intel_dig_port->dp;
 565 }
 566
 567 static inline struct intel_digital_port *
 568 enc_to_dig_port(struct drm_encoder *encoder)
 569 {
 570         return container_of(encoder, struct intel_digital_port, base.base);
 571 }
 572
 573 static inline struct intel_digital_port *
 574 dp_to_dig_port(struct intel_dp *intel_dp)
 575 {
 576         return container_of(intel_dp, struct intel_digital_port, dp);
 577 }
 578
 579 static inline struct intel_digital_port *
 580 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 581 {
 582         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 583 }
 584
 585 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 586                                 struct intel_digital_port *port);
 587
 588 extern void intel_connector_attach_encoder(struct intel_connector *connector,
 589                                            struct intel_encoder *encoder);
 590 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 591
 592 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 593                                                     struct drm_crtc *crtc);
 594 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 595                                 struct drm_file *file_priv);
 596 extern enum transcoder
 597 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 598                              enum pipe pipe);
 599 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 600 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 601 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 602
 603 struct intel_load_detect_pipe {
 604         struct drm_framebuffer *release_fb;
 605         bool load_detect_temp;
 606         int dpms_mode;
 607 };
 608 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
 609                                        struct drm_display_mode *mode,
 610                                        struct intel_load_detect_pipe *old);
 611 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
 612                                            struct intel_load_detect_pipe *old);
 613
 614 extern void intelfb_restore(void);
 615 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 616                                     u16 blue, int regno);
 617 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 618                                     u16 *blue, int regno);
 619 extern void intel_enable_clock_gating(struct drm_device *dev);
 620
 621 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 622                                       struct drm_i915_gem_object *obj,
 623                                       struct intel_ring_buffer *pipelined);
 624 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 625
 626 extern int intel_framebuffer_init(struct drm_device *dev,
 627                                   struct intel_framebuffer *ifb,
 628                                   struct drm_mode_fb_cmd2 *mode_cmd,
 629                                   struct drm_i915_gem_object *obj);
 630 extern int intel_fbdev_init(struct drm_device *dev);
 631 extern void intel_fbdev_initial_config(struct drm_device *dev);
 632 extern void intel_fbdev_fini(struct drm_device *dev);
 633 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 634 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
 635 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
 636 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 637
 638 extern void intel_setup_overlay(struct drm_device *dev);
 639 extern void intel_cleanup_overlay(struct drm_device *dev);
 640 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
 641 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
 642                                    struct drm_file *file_priv);
 643 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
 644                                struct drm_file *file_priv);
 645
 646 extern void intel_fb_output_poll_changed(struct drm_device *dev);
 647 extern void intel_fb_restore_mode(struct drm_device *dev);
 648
 649 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 650                         bool state);
 651 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 652 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 653
 654 extern void intel_init_clock_gating(struct drm_device *dev);
 655 extern void intel_write_eld(struct drm_encoder *encoder,
 656                             struct drm_display_mode *mode);
 657 extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
 658 extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 659                                          struct intel_link_m_n *m_n);
 660 extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
 661                                          struct intel_link_m_n *m_n);
 662 extern void intel_prepare_ddi(struct drm_device *dev);
 663 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
 664 extern void intel_ddi_init(struct drm_device *dev, enum port port);
 665
 666 /* For use by IVB LP watermark workaround in intel_sprite.c */
 667 extern void intel_update_watermarks(struct drm_device *dev);
 668 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
 669                                            uint32_t sprite_width,
 670                                            int pixel_size);
 671 extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
 672                          struct drm_display_mode *mode);
 673
 674 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 675                                                     unsigned int tiling_mode,
 676                                                     unsigned int bpp,
 677                                                     unsigned int pitch);
 678
 679 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 680                                      struct drm_file *file_priv);
 681 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 682                                      struct drm_file *file_priv);
 683
 684 extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
 685
 686 /* Power-related functions, located in intel_pm.c */
 687 extern void intel_init_pm(struct drm_device *dev);
 688 /* FBC */
 689 extern bool intel_fbc_enabled(struct drm_device *dev);
 690 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
 691 extern void intel_update_fbc(struct drm_device *dev);
 692 /* IPS */
 693 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 694 extern void intel_gpu_ips_teardown(void);
 695
 696 extern bool intel_using_power_well(struct drm_device *dev);
 697 extern void intel_init_power_well(struct drm_device *dev);
 698 extern void intel_set_power_well(struct drm_device *dev, bool enable);
 699 extern void intel_enable_gt_powersave(struct drm_device *dev);
 700 extern void intel_disable_gt_powersave(struct drm_device *dev);
 701 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
 702 extern void ironlake_teardown_rc6(struct drm_device *dev);
 703
 704 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 705                                    enum pipe *pipe);
 706 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 707 extern void intel_ddi_pll_init(struct drm_device *dev);
 708 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 709 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 710                                               enum transcoder cpu_transcoder);
 711 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 712 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 713 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 714 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
 715 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 716 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 717 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 718 extern bool
 719 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 720 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 721
 722 extern void intel_display_handle_reset(struct drm_device *dev);
 723
 724 #endif /* __INTEL_DRV_H__ */