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serial: sh-sci: Fix module clock refcounting.
[linux-2.6/btrfs-unstable.git] / drivers / serial / sh-sci.c
blobe5cf57f482cf1aa0a83f4fad095d293d35a311d6
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2006 Paul Mundt
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #undef DEBUG
25
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/timer.h>
29 #include <linux/interrupt.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/major.h>
34 #include <linux/string.h>
35 #include <linux/sysrq.h>
36 #include <linux/ioport.h>
37 #include <linux/mm.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/console.h>
41 #include <linux/platform_device.h>
42
43 #ifdef CONFIG_CPU_FREQ
44 #include <linux/notifier.h>
45 #include <linux/cpufreq.h>
46 #endif
47
48 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
49 #include <linux/ctype.h>
50 #include <asm/clock.h>
51 #include <asm/sh_bios.h>
52 #include <asm/kgdb.h>
53 #endif
54
55 #include <asm/sci.h>
56 #include "sh-sci.h"
57
58 struct sci_port {
59 struct uart_port port;
60
61 /* Port type */
62 unsigned int type;
63
64 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
65 unsigned int irqs[SCIx_NR_IRQS];
66
67 /* Port pin configuration */
68 void (*init_pins)(struct uart_port *port,
69 unsigned int cflag);
70
71 /* Port enable callback */
72 void (*enable)(struct uart_port *port);
73
74 /* Port disable callback */
75 void (*disable)(struct uart_port *port);
76
77 /* Break timer */
78 struct timer_list break_timer;
79 int break_flag;
80
81 /* Port clock */
82 struct clk *clk;
83 };
84
85 #ifdef CONFIG_SH_KGDB
86 static struct sci_port *kgdb_sci_port;
87 #endif
88
89 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
90 static struct sci_port *serial_console_port;
91 #endif
92
93 /* Function prototypes */
94 static void sci_stop_tx(struct uart_port *port);
95
96 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
97
98 static struct sci_port sci_ports[SCI_NPORTS];
99 static struct uart_driver sci_uart_driver;
100
101 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
102 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
103 static inline void handle_error(struct uart_port *port)
104 {
105 /* Clear error flags */
106 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
107 }
108
109 static int get_char(struct uart_port *port)
110 {
111 unsigned long flags;
112 unsigned short status;
113 int c;
114
115 spin_lock_irqsave(&port->lock, flags);
116 do {
117 status = sci_in(port, SCxSR);
118 if (status & SCxSR_ERRORS(port)) {
119 handle_error(port);
120 continue;
121 }
122 } while (!(status & SCxSR_RDxF(port)));
123 c = sci_in(port, SCxRDR);
124 sci_in(port, SCxSR); /* Dummy read */
125 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
126 spin_unlock_irqrestore(&port->lock, flags);
127
128 return c;
129 }
130 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
131
132 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
133 static void put_char(struct uart_port *port, char c)
134 {
135 unsigned long flags;
136 unsigned short status;
137
138 spin_lock_irqsave(&port->lock, flags);
139
140 do {
141 status = sci_in(port, SCxSR);
142 } while (!(status & SCxSR_TDxE(port)));
143
144 sci_out(port, SCxTDR, c);
145 sci_in(port, SCxSR); /* Dummy read */
146 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
147
148 spin_unlock_irqrestore(&port->lock, flags);
149 }
150 #endif
151
152 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
153 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
154 {
155 struct uart_port *port = &sci_port->port;
156 const unsigned char *p = buffer;
157 int i;
158
159 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
160 int checksum;
161 int usegdb=0;
162
163 #ifdef CONFIG_SH_STANDARD_BIOS
164 /* This call only does a trap the first time it is
165 * called, and so is safe to do here unconditionally
166 */
167 usegdb |= sh_bios_in_gdb_mode();
168 #endif
169 #ifdef CONFIG_SH_KGDB
170 usegdb |= (kgdb_in_gdb_mode && (sci_port == kgdb_sci_port));
171 #endif
172
173 if (usegdb) {
174 /* $<packet info>#<checksum>. */
175 do {
176 unsigned char c;
177 put_char(port, '$');
178 put_char(port, 'O'); /* 'O'utput to console */
179 checksum = 'O';
180
181 for (i=0; i<count; i++) { /* Don't use run length encoding */
182 int h, l;
183
184 c = *p++;
185 h = highhex(c);
186 l = lowhex(c);
187 put_char(port, h);
188 put_char(port, l);
189 checksum += h + l;
190 }
191 put_char(port, '#');
192 put_char(port, highhex(checksum));
193 put_char(port, lowhex(checksum));
194 } while (get_char(port) != '+');
195 } else
196 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
197 for (i=0; i<count; i++) {
198 if (*p == 10)
199 put_char(port, '\r');
200 put_char(port, *p++);
201 }
202 }
203 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
204
205 #ifdef CONFIG_SH_KGDB
206 static int kgdb_sci_getchar(void)
207 {
208 int c;
209
210 /* Keep trying to read a character, this could be neater */
211 while ((c = get_char(&kgdb_sci_port->port)) < 0)
212 cpu_relax();
213
214 return c;
215 }
216
217 static inline void kgdb_sci_putchar(int c)
218 {
219 put_char(&kgdb_sci_port->port, c);
220 }
221 #endif /* CONFIG_SH_KGDB */
222
223 #if defined(__H8300S__)
224 enum { sci_disable, sci_enable };
225
226 static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
227 {
228 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
229 int ch = (port->mapbase - SMR0) >> 3;
230 unsigned char mask = 1 << (ch+1);
231
232 if (ctrl == sci_disable) {
233 *mstpcrl |= mask;
234 } else {
235 *mstpcrl &= ~mask;
236 }
237 }
238
239 static inline void h8300_sci_enable(struct uart_port *port)
240 {
241 h8300_sci_config(port, sci_enable);
242 }
243
244 static inline void h8300_sci_disable(struct uart_port *port)
245 {
246 h8300_sci_config(port, sci_disable);
247 }
248 #endif
249
250 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
251 defined(__H8300H__) || defined(__H8300S__)
252 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
253 {
254 int ch = (port->mapbase - SMR0) >> 3;
255
256 /* set DDR regs */
257 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
258 h8300_sci_pins[ch].rx,
259 H8300_GPIO_INPUT);
260 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
261 h8300_sci_pins[ch].tx,
262 H8300_GPIO_OUTPUT);
263
264 /* tx mark output*/
265 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
266 }
267 #else
268 #define sci_init_pins_sci NULL
269 #endif
270
271 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
272 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
273 {
274 unsigned int fcr_val = 0;
275
276 if (cflag & CRTSCTS)
277 fcr_val |= SCFCR_MCE;
278
279 sci_out(port, SCFCR, fcr_val);
280 }
281 #else
282 #define sci_init_pins_irda NULL
283 #endif
284
285 #ifdef SCI_ONLY
286 #define sci_init_pins_scif NULL
287 #endif
288
289 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
290 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
291 /* SH7300 doesn't use RTS/CTS */
292 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
293 {
294 sci_out(port, SCFCR, 0);
295 }
296 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
297 static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
298 {
299 unsigned int fcr_val = 0;
300
301 set_sh771x_scif_pfc(port);
302 if (cflag & CRTSCTS) {
303 fcr_val |= SCFCR_MCE;
304 }
305 sci_out(port, SCFCR, fcr_val);
306 }
307 #elif defined(CONFIG_CPU_SH3)
308 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
309 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
310 {
311 unsigned int fcr_val = 0;
312 unsigned short data;
313
314 /* We need to set SCPCR to enable RTS/CTS */
315 data = ctrl_inw(SCPCR);
316 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
317 ctrl_outw(data & 0x0fcf, SCPCR);
318
319 if (cflag & CRTSCTS)
320 fcr_val |= SCFCR_MCE;
321 else {
322 /* We need to set SCPCR to enable RTS/CTS */
323 data = ctrl_inw(SCPCR);
324 /* Clear out SCP7MD1,0, SCP4MD1,0,
325 Set SCP6MD1,0 = {01} (output) */
326 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
327
328 data = ctrl_inb(SCPDR);
329 /* Set /RTS2 (bit6) = 0 */
330 ctrl_outb(data & 0xbf, SCPDR);
331 }
332
333 sci_out(port, SCFCR, fcr_val);
334 }
335 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
336 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
337 {
338 unsigned int fcr_val = 0;
339
340 if (cflag & CRTSCTS) {
341 fcr_val |= SCFCR_MCE;
342
343 ctrl_outw(0x0000, PORT_PSCR);
344 } else {
345 unsigned short data;
346
347 data = ctrl_inw(PORT_PSCR);
348 data &= 0x033f;
349 data |= 0x0400;
350 ctrl_outw(data, PORT_PSCR);
351
352 ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0);
353 }
354
355 sci_out(port, SCFCR, fcr_val);
356 }
357 #else
358 /* For SH7750 */
359 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
360 {
361 unsigned int fcr_val = 0;
362
363 if (cflag & CRTSCTS) {
364 fcr_val |= SCFCR_MCE;
365 } else {
366 #ifdef CONFIG_CPU_SUBTYPE_SH7343
367 /* Nothing */
368 #elif defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
369 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
370 #else
371 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
372 #endif
373 }
374 sci_out(port, SCFCR, fcr_val);
375 }
376 #endif
377
378 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
379 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
380 defined(CONFIG_CPU_SUBTYPE_SH7785)
381 static inline int scif_txroom(struct uart_port *port)
382 {
383 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
384 }
385
386 static inline int scif_rxroom(struct uart_port *port)
387 {
388 return sci_in(port, SCRFDR) & 0x7f;
389 }
390 #else
391 static inline int scif_txroom(struct uart_port *port)
392 {
393 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
394 }
395
396 static inline int scif_rxroom(struct uart_port *port)
397 {
398 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
399 }
400 #endif
401 #endif /* SCIF_ONLY || SCI_AND_SCIF */
402
403 static inline int sci_txroom(struct uart_port *port)
404 {
405 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
406 }
407
408 static inline int sci_rxroom(struct uart_port *port)
409 {
410 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
411 }
412
413 /* ********************************************************************** *
414 * the interrupt related routines *
415 * ********************************************************************** */
416
417 static void sci_transmit_chars(struct uart_port *port)
418 {
419 struct circ_buf *xmit = &port->info->xmit;
420 unsigned int stopped = uart_tx_stopped(port);
421 unsigned short status;
422 unsigned short ctrl;
423 int count;
424
425 status = sci_in(port, SCxSR);
426 if (!(status & SCxSR_TDxE(port))) {
427 ctrl = sci_in(port, SCSCR);
428 if (uart_circ_empty(xmit)) {
429 ctrl &= ~SCI_CTRL_FLAGS_TIE;
430 } else {
431 ctrl |= SCI_CTRL_FLAGS_TIE;
432 }
433 sci_out(port, SCSCR, ctrl);
434 return;
435 }
436
437 #ifndef SCI_ONLY
438 if (port->type == PORT_SCIF)
439 count = scif_txroom(port);
440 else
441 #endif
442 count = sci_txroom(port);
443
444 do {
445 unsigned char c;
446
447 if (port->x_char) {
448 c = port->x_char;
449 port->x_char = 0;
450 } else if (!uart_circ_empty(xmit) && !stopped) {
451 c = xmit->buf[xmit->tail];
452 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
453 } else {
454 break;
455 }
456
457 sci_out(port, SCxTDR, c);
458
459 port->icount.tx++;
460 } while (--count > 0);
461
462 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
463
464 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
465 uart_write_wakeup(port);
466 if (uart_circ_empty(xmit)) {
467 sci_stop_tx(port);
468 } else {
469 ctrl = sci_in(port, SCSCR);
470
471 #if !defined(SCI_ONLY)
472 if (port->type == PORT_SCIF) {
473 sci_in(port, SCxSR); /* Dummy read */
474 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
475 }
476 #endif
477
478 ctrl |= SCI_CTRL_FLAGS_TIE;
479 sci_out(port, SCSCR, ctrl);
480 }
481 }
482
483 /* On SH3, SCIF may read end-of-break as a space->mark char */
484 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
485
486 static inline void sci_receive_chars(struct uart_port *port)
487 {
488 struct sci_port *sci_port = (struct sci_port *)port;
489 struct tty_struct *tty = port->info->tty;
490 int i, count, copied = 0;
491 unsigned short status;
492 unsigned char flag;
493
494 status = sci_in(port, SCxSR);
495 if (!(status & SCxSR_RDxF(port)))
496 return;
497
498 while (1) {
499 #if !defined(SCI_ONLY)
500 if (port->type == PORT_SCIF)
501 count = scif_rxroom(port);
502 else
503 #endif
504 count = sci_rxroom(port);
505
506 /* Don't copy more bytes than there is room for in the buffer */
507 count = tty_buffer_request_room(tty, count);
508
509 /* If for any reason we can't copy more data, we're done! */
510 if (count == 0)
511 break;
512
513 if (port->type == PORT_SCI) {
514 char c = sci_in(port, SCxRDR);
515 if (uart_handle_sysrq_char(port, c) || sci_port->break_flag)
516 count = 0;
517 else {
518 tty_insert_flip_char(tty, c, TTY_NORMAL);
519 }
520 } else {
521 for (i=0; i<count; i++) {
522 char c = sci_in(port, SCxRDR);
523 status = sci_in(port, SCxSR);
524 #if defined(CONFIG_CPU_SH3)
525 /* Skip "chars" during break */
526 if (sci_port->break_flag) {
527 if ((c == 0) &&
528 (status & SCxSR_FER(port))) {
529 count--; i--;
530 continue;
531 }
532
533 /* Nonzero => end-of-break */
534 pr_debug("scif: debounce<%02x>\n", c);
535 sci_port->break_flag = 0;
536
537 if (STEPFN(c)) {
538 count--; i--;
539 continue;
540 }
541 }
542 #endif /* CONFIG_CPU_SH3 */
543 if (uart_handle_sysrq_char(port, c)) {
544 count--; i--;
545 continue;
546 }
547
548 /* Store data and status */
549 if (status&SCxSR_FER(port)) {
550 flag = TTY_FRAME;
551 pr_debug("sci: frame error\n");
552 } else if (status&SCxSR_PER(port)) {
553 flag = TTY_PARITY;
554 pr_debug("sci: parity error\n");
555 } else
556 flag = TTY_NORMAL;
557 tty_insert_flip_char(tty, c, flag);
558 }
559 }
560
561 sci_in(port, SCxSR); /* dummy read */
562 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
563
564 copied += count;
565 port->icount.rx += count;
566 }
567
568 if (copied) {
569 /* Tell the rest of the system the news. New characters! */
570 tty_flip_buffer_push(tty);
571 } else {
572 sci_in(port, SCxSR); /* dummy read */
573 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
574 }
575 }
576
577 #define SCI_BREAK_JIFFIES (HZ/20)
578 /* The sci generates interrupts during the break,
579 * 1 per millisecond or so during the break period, for 9600 baud.
580 * So dont bother disabling interrupts.
581 * But dont want more than 1 break event.
582 * Use a kernel timer to periodically poll the rx line until
583 * the break is finished.
584 */
585 static void sci_schedule_break_timer(struct sci_port *port)
586 {
587 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
588 add_timer(&port->break_timer);
589 }
590 /* Ensure that two consecutive samples find the break over. */
591 static void sci_break_timer(unsigned long data)
592 {
593 struct sci_port *port = (struct sci_port *)data;
594
595 if (sci_rxd_in(&port->port) == 0) {
596 port->break_flag = 1;
597 sci_schedule_break_timer(port);
598 } else if (port->break_flag == 1) {
599 /* break is over. */
600 port->break_flag = 2;
601 sci_schedule_break_timer(port);
602 } else
603 port->break_flag = 0;
604 }
605
606 static inline int sci_handle_errors(struct uart_port *port)
607 {
608 int copied = 0;
609 unsigned short status = sci_in(port, SCxSR);
610 struct tty_struct *tty = port->info->tty;
611
612 if (status & SCxSR_ORER(port)) {
613 /* overrun error */
614 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
615 copied++;
616 pr_debug("sci: overrun error\n");
617 }
618
619 if (status & SCxSR_FER(port)) {
620 if (sci_rxd_in(port) == 0) {
621 /* Notify of BREAK */
622 struct sci_port *sci_port = (struct sci_port *)port;
623
624 if (!sci_port->break_flag) {
625 sci_port->break_flag = 1;
626 sci_schedule_break_timer(sci_port);
627
628 /* Do sysrq handling. */
629 if (uart_handle_break(port))
630 return 0;
631 pr_debug("sci: BREAK detected\n");
632 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
633 copied++;
634 }
635 } else {
636 /* frame error */
637 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
638 copied++;
639 pr_debug("sci: frame error\n");
640 }
641 }
642
643 if (status & SCxSR_PER(port)) {
644 /* parity error */
645 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
646 copied++;
647 pr_debug("sci: parity error\n");
648 }
649
650 if (copied)
651 tty_flip_buffer_push(tty);
652
653 return copied;
654 }
655
656 static inline int sci_handle_breaks(struct uart_port *port)
657 {
658 int copied = 0;
659 unsigned short status = sci_in(port, SCxSR);
660 struct tty_struct *tty = port->info->tty;
661 struct sci_port *s = &sci_ports[port->line];
662
663 if (uart_handle_break(port))
664 return 0;
665
666 if (!s->break_flag && status & SCxSR_BRK(port)) {
667 #if defined(CONFIG_CPU_SH3)
668 /* Debounce break */
669 s->break_flag = 1;
670 #endif
671 /* Notify of BREAK */
672 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
673 copied++;
674 pr_debug("sci: BREAK detected\n");
675 }
676
677 #if defined(SCIF_ORER)
678 /* XXX: Handle SCIF overrun error */
679 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
680 sci_out(port, SCLSR, 0);
681 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
682 copied++;
683 pr_debug("sci: overrun error\n");
684 }
685 }
686 #endif
687
688 if (copied)
689 tty_flip_buffer_push(tty);
690
691 return copied;
692 }
693
694 static irqreturn_t sci_rx_interrupt(int irq, void *port)
695 {
696 /* I think sci_receive_chars has to be called irrespective
697 * of whether the I_IXOFF is set, otherwise, how is the interrupt
698 * to be disabled?
699 */
700 sci_receive_chars(port);
701
702 return IRQ_HANDLED;
703 }
704
705 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
706 {
707 struct uart_port *port = ptr;
708
709 spin_lock_irq(&port->lock);
710 sci_transmit_chars(port);
711 spin_unlock_irq(&port->lock);
712
713 return IRQ_HANDLED;
714 }
715
716 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
717 {
718 struct uart_port *port = ptr;
719
720 /* Handle errors */
721 if (port->type == PORT_SCI) {
722 if (sci_handle_errors(port)) {
723 /* discard character in rx buffer */
724 sci_in(port, SCxSR);
725 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
726 }
727 } else {
728 #if defined(SCIF_ORER)
729 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
730 struct tty_struct *tty = port->info->tty;
731
732 sci_out(port, SCLSR, 0);
733 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
734 tty_flip_buffer_push(tty);
735 pr_debug("scif: overrun error\n");
736 }
737 #endif
738 sci_rx_interrupt(irq, ptr);
739 }
740
741 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
742
743 /* Kick the transmission */
744 sci_tx_interrupt(irq, ptr);
745
746 return IRQ_HANDLED;
747 }
748
749 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
750 {
751 struct uart_port *port = ptr;
752
753 /* Handle BREAKs */
754 sci_handle_breaks(port);
755 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
756
757 return IRQ_HANDLED;
758 }
759
760 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
761 {
762 unsigned short ssr_status, scr_status;
763 struct uart_port *port = ptr;
764
765 ssr_status = sci_in(port,SCxSR);
766 scr_status = sci_in(port,SCSCR);
767
768 /* Tx Interrupt */
769 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
770 sci_tx_interrupt(irq, ptr);
771 /* Rx Interrupt */
772 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
773 sci_rx_interrupt(irq, ptr);
774 /* Error Interrupt */
775 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
776 sci_er_interrupt(irq, ptr);
777 /* Break Interrupt */
778 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
779 sci_br_interrupt(irq, ptr);
780
781 return IRQ_HANDLED;
782 }
783
784 #ifdef CONFIG_CPU_FREQ
785 /*
786 * Here we define a transistion notifier so that we can update all of our
787 * ports' baud rate when the peripheral clock changes.
788 */
789 static int sci_notifier(struct notifier_block *self,
790 unsigned long phase, void *p)
791 {
792 struct cpufreq_freqs *freqs = p;
793 int i;
794
795 if ((phase == CPUFREQ_POSTCHANGE) ||
796 (phase == CPUFREQ_RESUMECHANGE)){
797 for (i = 0; i < SCI_NPORTS; i++) {
798 struct uart_port *port = &sci_ports[i].port;
799 struct clk *clk;
800
801 /*
802 * Update the uartclk per-port if frequency has
803 * changed, since it will no longer necessarily be
804 * consistent with the old frequency.
805 *
806 * Really we want to be able to do something like
807 * uart_change_speed() or something along those lines
808 * here to implicitly reset the per-port baud rate..
809 *
810 * Clean this up later..
811 */
812 clk = clk_get(NULL, "module_clk");
813 port->uartclk = clk_get_rate(clk) * 16;
814 clk_put(clk);
815 }
816
817 printk(KERN_INFO "%s: got a postchange notification "
818 "for cpu %d (old %d, new %d)\n",
819 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
820 }
821
822 return NOTIFY_OK;
823 }
824
825 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
826 #endif /* CONFIG_CPU_FREQ */
827
828 static int sci_request_irq(struct sci_port *port)
829 {
830 int i;
831 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
832 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
833 sci_br_interrupt,
834 };
835 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
836 "SCI Transmit Data Empty", "SCI Break" };
837
838 if (port->irqs[0] == port->irqs[1]) {
839 if (!port->irqs[0]) {
840 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
841 return -ENODEV;
842 }
843
844 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
845 IRQF_DISABLED, "sci", port)) {
846 printk(KERN_ERR "sci: Cannot allocate irq.\n");
847 return -ENODEV;
848 }
849 } else {
850 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
851 if (!port->irqs[i])
852 continue;
853 if (request_irq(port->irqs[i], handlers[i],
854 IRQF_DISABLED, desc[i], port)) {
855 printk(KERN_ERR "sci: Cannot allocate irq.\n");
856 return -ENODEV;
857 }
858 }
859 }
860
861 return 0;
862 }
863
864 static void sci_free_irq(struct sci_port *port)
865 {
866 int i;
867
868 if (port->irqs[0] == port->irqs[1]) {
869 if (!port->irqs[0])
870 printk("sci: sci_free_irq error\n");
871 else
872 free_irq(port->irqs[0], port);
873 } else {
874 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
875 if (!port->irqs[i])
876 continue;
877
878 free_irq(port->irqs[i], port);
879 }
880 }
881 }
882
883 static unsigned int sci_tx_empty(struct uart_port *port)
884 {
885 /* Can't detect */
886 return TIOCSER_TEMT;
887 }
888
889 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
890 {
891 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
892 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
893 /* If you have signals for DTR and DCD, please implement here. */
894 }
895
896 static unsigned int sci_get_mctrl(struct uart_port *port)
897 {
898 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
899 and CTS/RTS */
900
901 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
902 }
903
904 static void sci_start_tx(struct uart_port *port)
905 {
906 unsigned short ctrl;
907
908 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
909 ctrl = sci_in(port, SCSCR);
910 ctrl |= SCI_CTRL_FLAGS_TIE;
911 sci_out(port, SCSCR, ctrl);
912 }
913
914 static void sci_stop_tx(struct uart_port *port)
915 {
916 unsigned short ctrl;
917
918 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
919 ctrl = sci_in(port, SCSCR);
920 ctrl &= ~SCI_CTRL_FLAGS_TIE;
921 sci_out(port, SCSCR, ctrl);
922 }
923
924 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
925 {
926 unsigned short ctrl;
927
928 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
929 ctrl = sci_in(port, SCSCR);
930 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
931 sci_out(port, SCSCR, ctrl);
932 }
933
934 static void sci_stop_rx(struct uart_port *port)
935 {
936 unsigned short ctrl;
937
938 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
939 ctrl = sci_in(port, SCSCR);
940 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
941 sci_out(port, SCSCR, ctrl);
942 }
943
944 static void sci_enable_ms(struct uart_port *port)
945 {
946 /* Nothing here yet .. */
947 }
948
949 static void sci_break_ctl(struct uart_port *port, int break_state)
950 {
951 /* Nothing here yet .. */
952 }
953
954 static int sci_startup(struct uart_port *port)
955 {
956 struct sci_port *s = &sci_ports[port->line];
957
958 if (s->enable)
959 s->enable(port);
960
961 s->clk = clk_get(NULL, "module_clk");
962
963 sci_request_irq(s);
964 sci_start_tx(port);
965 sci_start_rx(port, 1);
966
967 return 0;
968 }
969
970 static void sci_shutdown(struct uart_port *port)
971 {
972 struct sci_port *s = &sci_ports[port->line];
973
974 sci_stop_rx(port);
975 sci_stop_tx(port);
976 sci_free_irq(s);
977
978 if (s->disable)
979 s->disable(port);
980
981 clk_put(s->clk);
982 s->clk = NULL;
983 }
984
985 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
986 struct ktermios *old)
987 {
988 struct sci_port *s = &sci_ports[port->line];
989 unsigned int status, baud, smr_val;
990 int t;
991
992 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
993
994 switch (baud) {
995 case 0:
996 t = -1;
997 break;
998 default:
999 {
1000 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1001 t = SCBRR_VALUE(baud, clk_get_rate(s->clk));
1002 #else
1003 t = SCBRR_VALUE(baud);
1004 #endif
1005 break;
1006 }
1007 }
1008
1009 do {
1010 status = sci_in(port, SCxSR);
1011 } while (!(status & SCxSR_TEND(port)));
1012
1013 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1014
1015 #if !defined(SCI_ONLY)
1016 if (port->type == PORT_SCIF)
1017 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1018 #endif
1019
1020 smr_val = sci_in(port, SCSMR) & 3;
1021 if ((termios->c_cflag & CSIZE) == CS7)
1022 smr_val |= 0x40;
1023 if (termios->c_cflag & PARENB)
1024 smr_val |= 0x20;
1025 if (termios->c_cflag & PARODD)
1026 smr_val |= 0x30;
1027 if (termios->c_cflag & CSTOPB)
1028 smr_val |= 0x08;
1029
1030 uart_update_timeout(port, termios->c_cflag, baud);
1031
1032 sci_out(port, SCSMR, smr_val);
1033
1034 if (t > 0) {
1035 if(t >= 256) {
1036 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1037 t >>= 2;
1038 } else {
1039 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1040 }
1041 sci_out(port, SCBRR, t);
1042 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1043 }
1044
1045 if (likely(s->init_pins))
1046 s->init_pins(port, termios->c_cflag);
1047
1048 sci_out(port, SCSCR, SCSCR_INIT(port));
1049
1050 if ((termios->c_cflag & CREAD) != 0)
1051 sci_start_rx(port,0);
1052 }
1053
1054 static const char *sci_type(struct uart_port *port)
1055 {
1056 switch (port->type) {
1057 case PORT_SCI: return "sci";
1058 case PORT_SCIF: return "scif";
1059 case PORT_IRDA: return "irda";
1060 }
1061
1062 return 0;
1063 }
1064
1065 static void sci_release_port(struct uart_port *port)
1066 {
1067 /* Nothing here yet .. */
1068 }
1069
1070 static int sci_request_port(struct uart_port *port)
1071 {
1072 /* Nothing here yet .. */
1073 return 0;
1074 }
1075
1076 static void sci_config_port(struct uart_port *port, int flags)
1077 {
1078 struct sci_port *s = &sci_ports[port->line];
1079
1080 port->type = s->type;
1081
1082 switch (port->type) {
1083 case PORT_SCI:
1084 s->init_pins = sci_init_pins_sci;
1085 break;
1086 case PORT_SCIF:
1087 s->init_pins = sci_init_pins_scif;
1088 break;
1089 case PORT_IRDA:
1090 s->init_pins = sci_init_pins_irda;
1091 break;
1092 }
1093
1094 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1095 if (port->mapbase == 0)
1096 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1097
1098 port->membase = (void __iomem *)port->mapbase;
1099 #endif
1100 }
1101
1102 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1103 {
1104 struct sci_port *s = &sci_ports[port->line];
1105
1106 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1107 return -EINVAL;
1108 if (ser->baud_base < 2400)
1109 /* No paper tape reader for Mitch.. */
1110 return -EINVAL;
1111
1112 return 0;
1113 }
1114
1115 static struct uart_ops sci_uart_ops = {
1116 .tx_empty = sci_tx_empty,
1117 .set_mctrl = sci_set_mctrl,
1118 .get_mctrl = sci_get_mctrl,
1119 .start_tx = sci_start_tx,
1120 .stop_tx = sci_stop_tx,
1121 .stop_rx = sci_stop_rx,
1122 .enable_ms = sci_enable_ms,
1123 .break_ctl = sci_break_ctl,
1124 .startup = sci_startup,
1125 .shutdown = sci_shutdown,
1126 .set_termios = sci_set_termios,
1127 .type = sci_type,
1128 .release_port = sci_release_port,
1129 .request_port = sci_request_port,
1130 .config_port = sci_config_port,
1131 .verify_port = sci_verify_port,
1132 };
1133
1134 static void __init sci_init_ports(void)
1135 {
1136 static int first = 1;
1137 int i;
1138
1139 if (!first)
1140 return;
1141
1142 first = 0;
1143
1144 for (i = 0; i < SCI_NPORTS; i++) {
1145 sci_ports[i].port.ops = &sci_uart_ops;
1146 sci_ports[i].port.iotype = UPIO_MEM;
1147 sci_ports[i].port.line = i;
1148 sci_ports[i].port.fifosize = 1;
1149
1150 #if defined(__H8300H__) || defined(__H8300S__)
1151 #ifdef __H8300S__
1152 sci_ports[i].enable = h8300_sci_enable;
1153 sci_ports[i].disable = h8300_sci_disable;
1154 #endif
1155 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1156 #elif defined(CONFIG_SUPERH64)
1157 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1158 #else
1159 /*
1160 * XXX: We should use a proper SCI/SCIF clock
1161 */
1162 {
1163 struct clk *clk = clk_get(NULL, "module_clk");
1164 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1165 clk_put(clk);
1166 }
1167 #endif
1168
1169 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1170 sci_ports[i].break_timer.function = sci_break_timer;
1171
1172 init_timer(&sci_ports[i].break_timer);
1173 }
1174 }
1175
1176 int __init early_sci_setup(struct uart_port *port)
1177 {
1178 if (unlikely(port->line > SCI_NPORTS))
1179 return -ENODEV;
1180
1181 sci_init_ports();
1182
1183 sci_ports[port->line].port.membase = port->membase;
1184 sci_ports[port->line].port.mapbase = port->mapbase;
1185 sci_ports[port->line].port.type = port->type;
1186
1187 return 0;
1188 }
1189
1190 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1191 /*
1192 * Print a string to the serial port trying not to disturb
1193 * any possible real use of the port...
1194 */
1195 static void serial_console_write(struct console *co, const char *s,
1196 unsigned count)
1197 {
1198 put_string(serial_console_port, s, count);
1199 }
1200
1201 static int __init serial_console_setup(struct console *co, char *options)
1202 {
1203 struct uart_port *port;
1204 int baud = 115200;
1205 int bits = 8;
1206 int parity = 'n';
1207 int flow = 'n';
1208 int ret;
1209
1210 /*
1211 * Check whether an invalid uart number has been specified, and
1212 * if so, search for the first available port that does have
1213 * console support.
1214 */
1215 if (co->index >= SCI_NPORTS)
1216 co->index = 0;
1217
1218 serial_console_port = &sci_ports[co->index];
1219 port = &serial_console_port->port;
1220
1221 /*
1222 * Also need to check port->type, we don't actually have any
1223 * UPIO_PORT ports, but uart_report_port() handily misreports
1224 * it anyways if we don't have a port available by the time this is
1225 * called.
1226 */
1227 if (!port->type)
1228 return -ENODEV;
1229 if (!port->membase || !port->mapbase)
1230 return -ENODEV;
1231
1232 port->type = serial_console_port->type;
1233
1234 if (port->flags & UPF_IOREMAP)
1235 sci_config_port(port, 0);
1236
1237 if (serial_console_port->enable)
1238 serial_console_port->enable(port);
1239
1240 if (options)
1241 uart_parse_options(options, &baud, &parity, &bits, &flow);
1242
1243 ret = uart_set_options(port, co, baud, parity, bits, flow);
1244 #if defined(__H8300H__) || defined(__H8300S__)
1245 /* disable rx interrupt */
1246 if (ret == 0)
1247 sci_stop_rx(port);
1248 #endif
1249 return ret;
1250 }
1251
1252 static struct console serial_console = {
1253 .name = "ttySC",
1254 .device = uart_console_device,
1255 .write = serial_console_write,
1256 .setup = serial_console_setup,
1257 .flags = CON_PRINTBUFFER,
1258 .index = -1,
1259 .data = &sci_uart_driver,
1260 };
1261
1262 static int __init sci_console_init(void)
1263 {
1264 sci_init_ports();
1265 register_console(&serial_console);
1266 return 0;
1267 }
1268 console_initcall(sci_console_init);
1269 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1270
1271 #ifdef CONFIG_SH_KGDB
1272 /*
1273 * FIXME: Most of this can go away.. at the moment, we rely on
1274 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1275 * most of that can easily be done here instead.
1276 *
1277 * For the time being, just accept the values that were parsed earlier..
1278 */
1279 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1280 int *parity, int *bits)
1281 {
1282 *baud = kgdb_baud;
1283 *parity = tolower(kgdb_parity);
1284 *bits = kgdb_bits - '0';
1285 }
1286
1287 /*
1288 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1289 * care of the early-on initialization for kgdb, regardless of whether we
1290 * actually use kgdb as a console or not.
1291 *
1292 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1293 */
1294 int __init kgdb_console_setup(struct console *co, char *options)
1295 {
1296 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1297 int baud = 38400;
1298 int bits = 8;
1299 int parity = 'n';
1300 int flow = 'n';
1301
1302 if (co->index != kgdb_portnum)
1303 co->index = kgdb_portnum;
1304
1305 kgdb_sci_port = &sci_ports[co->index];
1306 port = &kgdb_sci_port->port;
1307
1308 /*
1309 * Also need to check port->type, we don't actually have any
1310 * UPIO_PORT ports, but uart_report_port() handily misreports
1311 * it anyways if we don't have a port available by the time this is
1312 * called.
1313 */
1314 if (!port->type)
1315 return -ENODEV;
1316 if (!port->membase || !port->mapbase)
1317 return -ENODEV;
1318
1319 if (options)
1320 uart_parse_options(options, &baud, &parity, &bits, &flow);
1321 else
1322 kgdb_console_get_options(port, &baud, &parity, &bits);
1323
1324 kgdb_getchar = kgdb_sci_getchar;
1325 kgdb_putchar = kgdb_sci_putchar;
1326
1327 return uart_set_options(port, co, baud, parity, bits, flow);
1328 }
1329 #endif /* CONFIG_SH_KGDB */
1330
1331 #ifdef CONFIG_SH_KGDB_CONSOLE
1332 static struct console kgdb_console = {
1333 .name = "ttySC",
1334 .device = uart_console_device,
1335 .write = kgdb_console_write,
1336 .setup = kgdb_console_setup,
1337 .flags = CON_PRINTBUFFER,
1338 .index = -1,
1339 .data = &sci_uart_driver,
1340 };
1341
1342 /* Register the KGDB console so we get messages (d'oh!) */
1343 static int __init kgdb_console_init(void)
1344 {
1345 sci_init_ports();
1346 register_console(&kgdb_console);
1347 return 0;
1348 }
1349 console_initcall(kgdb_console_init);
1350 #endif /* CONFIG_SH_KGDB_CONSOLE */
1351
1352 #if defined(CONFIG_SH_KGDB_CONSOLE)
1353 #define SCI_CONSOLE &kgdb_console
1354 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1355 #define SCI_CONSOLE &serial_console
1356 #else
1357 #define SCI_CONSOLE 0
1358 #endif
1359
1360 static char banner[] __initdata =
1361 KERN_INFO "SuperH SCI(F) driver initialized\n";
1362
1363 static struct uart_driver sci_uart_driver = {
1364 .owner = THIS_MODULE,
1365 .driver_name = "sci",
1366 .dev_name = "ttySC",
1367 .major = SCI_MAJOR,
1368 .minor = SCI_MINOR_START,
1369 .nr = SCI_NPORTS,
1370 .cons = SCI_CONSOLE,
1371 };
1372
1373 /*
1374 * Register a set of serial devices attached to a platform device. The
1375 * list is terminated with a zero flags entry, which means we expect
1376 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1377 * remapping (such as sh64) should also set UPF_IOREMAP.
1378 */
1379 static int __devinit sci_probe(struct platform_device *dev)
1380 {
1381 struct plat_sci_port *p = dev->dev.platform_data;
1382 int i;
1383
1384 for (i = 0; p && p->flags != 0; p++, i++) {
1385 struct sci_port *sciport = &sci_ports[i];
1386
1387 /* Sanity check */
1388 if (unlikely(i == SCI_NPORTS)) {
1389 dev_notice(&dev->dev, "Attempting to register port "
1390 "%d when only %d are available.\n",
1391 i+1, SCI_NPORTS);
1392 dev_notice(&dev->dev, "Consider bumping "
1393 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1394 break;
1395 }
1396
1397 sciport->port.mapbase = p->mapbase;
1398
1399 /*
1400 * For the simple (and majority of) cases where we don't need
1401 * to do any remapping, just cast the cookie directly.
1402 */
1403 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1404 p->membase = (void __iomem *)p->mapbase;
1405
1406 sciport->port.membase = p->membase;
1407
1408 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1409 sciport->port.flags = p->flags;
1410 sciport->port.dev = &dev->dev;
1411
1412 sciport->type = sciport->port.type = p->type;
1413
1414 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1415
1416 uart_add_one_port(&sci_uart_driver, &sciport->port);
1417 }
1418
1419 #if defined(CONFIG_SH_KGDB) && !defined(CONFIG_SH_KGDB_CONSOLE)
1420 kgdb_sci_port = &sci_ports[kgdb_portnum];
1421 kgdb_getchar = kgdb_sci_getchar;
1422 kgdb_putchar = kgdb_sci_putchar;
1423 #endif
1424
1425 #ifdef CONFIG_CPU_FREQ
1426 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1427 dev_info(&dev->dev, "sci: CPU frequency notifier registered\n");
1428 #endif
1429
1430 #ifdef CONFIG_SH_STANDARD_BIOS
1431 sh_bios_gdb_detach();
1432 #endif
1433
1434 return 0;
1435 }
1436
1437 static int __devexit sci_remove(struct platform_device *dev)
1438 {
1439 int i;
1440
1441 for (i = 0; i < SCI_NPORTS; i++)
1442 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1443
1444 return 0;
1445 }
1446
1447 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1448 {
1449 int i;
1450
1451 for (i = 0; i < SCI_NPORTS; i++) {
1452 struct sci_port *p = &sci_ports[i];
1453
1454 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1455 uart_suspend_port(&sci_uart_driver, &p->port);
1456 }
1457
1458 return 0;
1459 }
1460
1461 static int sci_resume(struct platform_device *dev)
1462 {
1463 int i;
1464
1465 for (i = 0; i < SCI_NPORTS; i++) {
1466 struct sci_port *p = &sci_ports[i];
1467
1468 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1469 uart_resume_port(&sci_uart_driver, &p->port);
1470 }
1471
1472 return 0;
1473 }
1474
1475 static struct platform_driver sci_driver = {
1476 .probe = sci_probe,
1477 .remove = __devexit_p(sci_remove),
1478 .suspend = sci_suspend,
1479 .resume = sci_resume,
1480 .driver = {
1481 .name = "sh-sci",
1482 .owner = THIS_MODULE,
1483 },
1484 };
1485
1486 static int __init sci_init(void)
1487 {
1488 int ret;
1489
1490 printk(banner);
1491
1492 sci_init_ports();
1493
1494 ret = uart_register_driver(&sci_uart_driver);
1495 if (likely(ret == 0)) {
1496 ret = platform_driver_register(&sci_driver);
1497 if (unlikely(ret))
1498 uart_unregister_driver(&sci_uart_driver);
1499 }
1500
1501 return ret;
1502 }
1503
1504 static void __exit sci_exit(void)
1505 {
1506 platform_driver_unregister(&sci_driver);
1507 uart_unregister_driver(&sci_uart_driver);
1508 }
1509
1510 module_init(sci_init);
1511 module_exit(sci_exit);
1512
1513 MODULE_LICENSE("GPL");
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