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be2net: Fixup profile management routines
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
blobbc6f95814998e669f68128469e619d99c7152156
1 /*
2 * Copyright (C) 2005 - 2013 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18 #include <linux/module.h>
19 #include "be.h"
20 #include "be_cmds.h"
21
22 static struct be_cmd_priv_map cmd_priv_map[] = {
23 {
24 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
25 CMD_SUBSYSTEM_ETH,
26 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
27 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
28 },
29 {
30 OPCODE_COMMON_GET_FLOW_CONTROL,
31 CMD_SUBSYSTEM_COMMON,
32 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
33 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
34 },
35 {
36 OPCODE_COMMON_SET_FLOW_CONTROL,
37 CMD_SUBSYSTEM_COMMON,
38 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
39 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
40 },
41 {
42 OPCODE_ETH_GET_PPORT_STATS,
43 CMD_SUBSYSTEM_ETH,
44 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
45 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
46 },
47 {
48 OPCODE_COMMON_GET_PHY_DETAILS,
49 CMD_SUBSYSTEM_COMMON,
50 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
51 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
52 }
53 };
54
55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
56 u8 subsystem)
57 {
58 int i;
59 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
60 u32 cmd_privileges = adapter->cmd_privileges;
61
62 for (i = 0; i < num_entries; i++)
63 if (opcode == cmd_priv_map[i].opcode &&
64 subsystem == cmd_priv_map[i].subsystem)
65 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
66 return false;
67
68 return true;
69 }
70
71 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
72 {
73 return wrb->payload.embedded_payload;
74 }
75
76 static void be_mcc_notify(struct be_adapter *adapter)
77 {
78 struct be_queue_info *mccq = &adapter->mcc_obj.q;
79 u32 val = 0;
80
81 if (be_error(adapter))
82 return;
83
84 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
85 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
86
87 wmb();
88 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
89 }
90
91 /* To check if valid bit is set, check the entire word as we don't know
92 * the endianness of the data (old entry is host endian while a new entry is
93 * little endian) */
94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
95 {
96 u32 flags;
97
98 if (compl->flags != 0) {
99 flags = le32_to_cpu(compl->flags);
100 if (flags & CQE_FLAGS_VALID_MASK) {
101 compl->flags = flags;
102 return true;
103 }
104 }
105 return false;
106 }
107
108 /* Need to reset the entire word that houses the valid bit */
109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
110 {
111 compl->flags = 0;
112 }
113
114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
115 {
116 unsigned long addr;
117
118 addr = tag1;
119 addr = ((addr << 16) << 16) | tag0;
120 return (void *)addr;
121 }
122
123 static int be_mcc_compl_process(struct be_adapter *adapter,
124 struct be_mcc_compl *compl)
125 {
126 u16 compl_status, extd_status;
127 struct be_cmd_resp_hdr *resp_hdr;
128 u8 opcode = 0, subsystem = 0;
129
130 /* Just swap the status to host endian; mcc tag is opaquely copied
131 * from mcc_wrb */
132 be_dws_le_to_cpu(compl, 4);
133
134 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
135 CQE_STATUS_COMPL_MASK;
136
137 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
138
139 if (resp_hdr) {
140 opcode = resp_hdr->opcode;
141 subsystem = resp_hdr->subsystem;
142 }
143
144 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
145 (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
146 (subsystem == CMD_SUBSYSTEM_COMMON)) {
147 adapter->flash_status = compl_status;
148 complete(&adapter->flash_compl);
149 }
150
151 if (compl_status == MCC_STATUS_SUCCESS) {
152 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
153 (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
154 (subsystem == CMD_SUBSYSTEM_ETH)) {
155 be_parse_stats(adapter);
156 adapter->stats_cmd_sent = false;
157 }
158 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
159 subsystem == CMD_SUBSYSTEM_COMMON) {
160 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
161 (void *)resp_hdr;
162 adapter->drv_stats.be_on_die_temperature =
163 resp->on_die_temperature;
164 }
165 } else {
166 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
167 adapter->be_get_temp_freq = 0;
168
169 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
170 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
171 goto done;
172
173 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
174 dev_warn(&adapter->pdev->dev,
175 "VF is not privileged to issue opcode %d-%d\n",
176 opcode, subsystem);
177 } else {
178 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
179 CQE_STATUS_EXTD_MASK;
180 dev_err(&adapter->pdev->dev,
181 "opcode %d-%d failed:status %d-%d\n",
182 opcode, subsystem, compl_status, extd_status);
183 }
184 }
185 done:
186 return compl_status;
187 }
188
189 /* Link state evt is a string of bytes; no need for endian swapping */
190 static void be_async_link_state_process(struct be_adapter *adapter,
191 struct be_async_event_link_state *evt)
192 {
193 /* When link status changes, link speed must be re-queried from FW */
194 adapter->phy.link_speed = -1;
195
196 /* Ignore physical link event */
197 if (lancer_chip(adapter) &&
198 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
199 return;
200
201 /* For the initial link status do not rely on the ASYNC event as
202 * it may not be received in some cases.
203 */
204 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
205 be_link_status_update(adapter, evt->port_link_status);
206 }
207
208 /* Grp5 CoS Priority evt */
209 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
210 struct be_async_event_grp5_cos_priority *evt)
211 {
212 if (evt->valid) {
213 adapter->vlan_prio_bmap = evt->available_priority_bmap;
214 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
215 adapter->recommended_prio =
216 evt->reco_default_priority << VLAN_PRIO_SHIFT;
217 }
218 }
219
220 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
221 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
222 struct be_async_event_grp5_qos_link_speed *evt)
223 {
224 if (adapter->phy.link_speed >= 0 &&
225 evt->physical_port == adapter->port_num)
226 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
227 }
228
229 /*Grp5 PVID evt*/
230 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
231 struct be_async_event_grp5_pvid_state *evt)
232 {
233 if (evt->enabled)
234 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
235 else
236 adapter->pvid = 0;
237 }
238
239 static void be_async_grp5_evt_process(struct be_adapter *adapter,
240 u32 trailer, struct be_mcc_compl *evt)
241 {
242 u8 event_type = 0;
243
244 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
245 ASYNC_TRAILER_EVENT_TYPE_MASK;
246
247 switch (event_type) {
248 case ASYNC_EVENT_COS_PRIORITY:
249 be_async_grp5_cos_priority_process(adapter,
250 (struct be_async_event_grp5_cos_priority *)evt);
251 break;
252 case ASYNC_EVENT_QOS_SPEED:
253 be_async_grp5_qos_speed_process(adapter,
254 (struct be_async_event_grp5_qos_link_speed *)evt);
255 break;
256 case ASYNC_EVENT_PVID_STATE:
257 be_async_grp5_pvid_state_process(adapter,
258 (struct be_async_event_grp5_pvid_state *)evt);
259 break;
260 default:
261 dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n",
262 event_type);
263 break;
264 }
265 }
266
267 static void be_async_dbg_evt_process(struct be_adapter *adapter,
268 u32 trailer, struct be_mcc_compl *cmp)
269 {
270 u8 event_type = 0;
271 struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
272
273 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
274 ASYNC_TRAILER_EVENT_TYPE_MASK;
275
276 switch (event_type) {
277 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
278 if (evt->valid)
279 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
280 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
281 break;
282 default:
283 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
284 event_type);
285 break;
286 }
287 }
288
289 static inline bool is_link_state_evt(u32 trailer)
290 {
291 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
292 ASYNC_TRAILER_EVENT_CODE_MASK) ==
293 ASYNC_EVENT_CODE_LINK_STATE;
294 }
295
296 static inline bool is_grp5_evt(u32 trailer)
297 {
298 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
299 ASYNC_TRAILER_EVENT_CODE_MASK) ==
300 ASYNC_EVENT_CODE_GRP_5);
301 }
302
303 static inline bool is_dbg_evt(u32 trailer)
304 {
305 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
306 ASYNC_TRAILER_EVENT_CODE_MASK) ==
307 ASYNC_EVENT_CODE_QNQ);
308 }
309
310 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
311 {
312 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
313 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
314
315 if (be_mcc_compl_is_new(compl)) {
316 queue_tail_inc(mcc_cq);
317 return compl;
318 }
319 return NULL;
320 }
321
322 void be_async_mcc_enable(struct be_adapter *adapter)
323 {
324 spin_lock_bh(&adapter->mcc_cq_lock);
325
326 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
327 adapter->mcc_obj.rearm_cq = true;
328
329 spin_unlock_bh(&adapter->mcc_cq_lock);
330 }
331
332 void be_async_mcc_disable(struct be_adapter *adapter)
333 {
334 spin_lock_bh(&adapter->mcc_cq_lock);
335
336 adapter->mcc_obj.rearm_cq = false;
337 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
338
339 spin_unlock_bh(&adapter->mcc_cq_lock);
340 }
341
342 int be_process_mcc(struct be_adapter *adapter)
343 {
344 struct be_mcc_compl *compl;
345 int num = 0, status = 0;
346 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
347
348 spin_lock(&adapter->mcc_cq_lock);
349 while ((compl = be_mcc_compl_get(adapter))) {
350 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
351 /* Interpret flags as an async trailer */
352 if (is_link_state_evt(compl->flags))
353 be_async_link_state_process(adapter,
354 (struct be_async_event_link_state *) compl);
355 else if (is_grp5_evt(compl->flags))
356 be_async_grp5_evt_process(adapter,
357 compl->flags, compl);
358 else if (is_dbg_evt(compl->flags))
359 be_async_dbg_evt_process(adapter,
360 compl->flags, compl);
361 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
362 status = be_mcc_compl_process(adapter, compl);
363 atomic_dec(&mcc_obj->q.used);
364 }
365 be_mcc_compl_use(compl);
366 num++;
367 }
368
369 if (num)
370 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
371
372 spin_unlock(&adapter->mcc_cq_lock);
373 return status;
374 }
375
376 /* Wait till no more pending mcc requests are present */
377 static int be_mcc_wait_compl(struct be_adapter *adapter)
378 {
379 #define mcc_timeout 120000 /* 12s timeout */
380 int i, status = 0;
381 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
382
383 for (i = 0; i < mcc_timeout; i++) {
384 if (be_error(adapter))
385 return -EIO;
386
387 local_bh_disable();
388 status = be_process_mcc(adapter);
389 local_bh_enable();
390
391 if (atomic_read(&mcc_obj->q.used) == 0)
392 break;
393 udelay(100);
394 }
395 if (i == mcc_timeout) {
396 dev_err(&adapter->pdev->dev, "FW not responding\n");
397 adapter->fw_timeout = true;
398 return -EIO;
399 }
400 return status;
401 }
402
403 /* Notify MCC requests and wait for completion */
404 static int be_mcc_notify_wait(struct be_adapter *adapter)
405 {
406 int status;
407 struct be_mcc_wrb *wrb;
408 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
409 u16 index = mcc_obj->q.head;
410 struct be_cmd_resp_hdr *resp;
411
412 index_dec(&index, mcc_obj->q.len);
413 wrb = queue_index_node(&mcc_obj->q, index);
414
415 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
416
417 be_mcc_notify(adapter);
418
419 status = be_mcc_wait_compl(adapter);
420 if (status == -EIO)
421 goto out;
422
423 status = resp->status;
424 out:
425 return status;
426 }
427
428 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
429 {
430 int msecs = 0;
431 u32 ready;
432
433 do {
434 if (be_error(adapter))
435 return -EIO;
436
437 ready = ioread32(db);
438 if (ready == 0xffffffff)
439 return -1;
440
441 ready &= MPU_MAILBOX_DB_RDY_MASK;
442 if (ready)
443 break;
444
445 if (msecs > 4000) {
446 dev_err(&adapter->pdev->dev, "FW not responding\n");
447 adapter->fw_timeout = true;
448 be_detect_error(adapter);
449 return -1;
450 }
451
452 msleep(1);
453 msecs++;
454 } while (true);
455
456 return 0;
457 }
458
459 /*
460 * Insert the mailbox address into the doorbell in two steps
461 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
462 */
463 static int be_mbox_notify_wait(struct be_adapter *adapter)
464 {
465 int status;
466 u32 val = 0;
467 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
468 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
469 struct be_mcc_mailbox *mbox = mbox_mem->va;
470 struct be_mcc_compl *compl = &mbox->compl;
471
472 /* wait for ready to be set */
473 status = be_mbox_db_ready_wait(adapter, db);
474 if (status != 0)
475 return status;
476
477 val |= MPU_MAILBOX_DB_HI_MASK;
478 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
479 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
480 iowrite32(val, db);
481
482 /* wait for ready to be set */
483 status = be_mbox_db_ready_wait(adapter, db);
484 if (status != 0)
485 return status;
486
487 val = 0;
488 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
489 val |= (u32)(mbox_mem->dma >> 4) << 2;
490 iowrite32(val, db);
491
492 status = be_mbox_db_ready_wait(adapter, db);
493 if (status != 0)
494 return status;
495
496 /* A cq entry has been made now */
497 if (be_mcc_compl_is_new(compl)) {
498 status = be_mcc_compl_process(adapter, &mbox->compl);
499 be_mcc_compl_use(compl);
500 if (status)
501 return status;
502 } else {
503 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
504 return -1;
505 }
506 return 0;
507 }
508
509 static u16 be_POST_stage_get(struct be_adapter *adapter)
510 {
511 u32 sem;
512
513 if (BEx_chip(adapter))
514 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
515 else
516 pci_read_config_dword(adapter->pdev,
517 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
518
519 return sem & POST_STAGE_MASK;
520 }
521
522 int lancer_wait_ready(struct be_adapter *adapter)
523 {
524 #define SLIPORT_READY_TIMEOUT 30
525 u32 sliport_status;
526 int status = 0, i;
527
528 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
529 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
530 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
531 break;
532
533 msleep(1000);
534 }
535
536 if (i == SLIPORT_READY_TIMEOUT)
537 status = -1;
538
539 return status;
540 }
541
542 static bool lancer_provisioning_error(struct be_adapter *adapter)
543 {
544 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
545 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
546 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
547 sliport_err1 = ioread32(adapter->db +
548 SLIPORT_ERROR1_OFFSET);
549 sliport_err2 = ioread32(adapter->db +
550 SLIPORT_ERROR2_OFFSET);
551
552 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
553 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
554 return true;
555 }
556 return false;
557 }
558
559 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
560 {
561 int status;
562 u32 sliport_status, err, reset_needed;
563 bool resource_error;
564
565 resource_error = lancer_provisioning_error(adapter);
566 if (resource_error)
567 return -EAGAIN;
568
569 status = lancer_wait_ready(adapter);
570 if (!status) {
571 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
572 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
573 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
574 if (err && reset_needed) {
575 iowrite32(SLI_PORT_CONTROL_IP_MASK,
576 adapter->db + SLIPORT_CONTROL_OFFSET);
577
578 /* check adapter has corrected the error */
579 status = lancer_wait_ready(adapter);
580 sliport_status = ioread32(adapter->db +
581 SLIPORT_STATUS_OFFSET);
582 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
583 SLIPORT_STATUS_RN_MASK);
584 if (status || sliport_status)
585 status = -1;
586 } else if (err || reset_needed) {
587 status = -1;
588 }
589 }
590 /* Stop error recovery if error is not recoverable.
591 * No resource error is temporary errors and will go away
592 * when PF provisions resources.
593 */
594 resource_error = lancer_provisioning_error(adapter);
595 if (resource_error)
596 status = -EAGAIN;
597
598 return status;
599 }
600
601 int be_fw_wait_ready(struct be_adapter *adapter)
602 {
603 u16 stage;
604 int status, timeout = 0;
605 struct device *dev = &adapter->pdev->dev;
606
607 if (lancer_chip(adapter)) {
608 status = lancer_wait_ready(adapter);
609 return status;
610 }
611
612 do {
613 stage = be_POST_stage_get(adapter);
614 if (stage == POST_STAGE_ARMFW_RDY)
615 return 0;
616
617 dev_info(dev, "Waiting for POST, %ds elapsed\n",
618 timeout);
619 if (msleep_interruptible(2000)) {
620 dev_err(dev, "Waiting for POST aborted\n");
621 return -EINTR;
622 }
623 timeout += 2;
624 } while (timeout < 60);
625
626 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
627 return -1;
628 }
629
630
631 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
632 {
633 return &wrb->payload.sgl[0];
634 }
635
636
637 /* Don't touch the hdr after it's prepared */
638 /* mem will be NULL for embedded commands */
639 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
640 u8 subsystem, u8 opcode, int cmd_len,
641 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
642 {
643 struct be_sge *sge;
644 unsigned long addr = (unsigned long)req_hdr;
645 u64 req_addr = addr;
646
647 req_hdr->opcode = opcode;
648 req_hdr->subsystem = subsystem;
649 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
650 req_hdr->version = 0;
651
652 wrb->tag0 = req_addr & 0xFFFFFFFF;
653 wrb->tag1 = upper_32_bits(req_addr);
654
655 wrb->payload_length = cmd_len;
656 if (mem) {
657 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
658 MCC_WRB_SGE_CNT_SHIFT;
659 sge = nonembedded_sgl(wrb);
660 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
661 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
662 sge->len = cpu_to_le32(mem->size);
663 } else
664 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
665 be_dws_cpu_to_le(wrb, 8);
666 }
667
668 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
669 struct be_dma_mem *mem)
670 {
671 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
672 u64 dma = (u64)mem->dma;
673
674 for (i = 0; i < buf_pages; i++) {
675 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
676 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
677 dma += PAGE_SIZE_4K;
678 }
679 }
680
681 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
682 {
683 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
684 struct be_mcc_wrb *wrb
685 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
686 memset(wrb, 0, sizeof(*wrb));
687 return wrb;
688 }
689
690 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
691 {
692 struct be_queue_info *mccq = &adapter->mcc_obj.q;
693 struct be_mcc_wrb *wrb;
694
695 if (!mccq->created)
696 return NULL;
697
698 if (atomic_read(&mccq->used) >= mccq->len)
699 return NULL;
700
701 wrb = queue_head_node(mccq);
702 queue_head_inc(mccq);
703 atomic_inc(&mccq->used);
704 memset(wrb, 0, sizeof(*wrb));
705 return wrb;
706 }
707
708 /* Tell fw we're about to start firing cmds by writing a
709 * special pattern across the wrb hdr; uses mbox
710 */
711 int be_cmd_fw_init(struct be_adapter *adapter)
712 {
713 u8 *wrb;
714 int status;
715
716 if (lancer_chip(adapter))
717 return 0;
718
719 if (mutex_lock_interruptible(&adapter->mbox_lock))
720 return -1;
721
722 wrb = (u8 *)wrb_from_mbox(adapter);
723 *wrb++ = 0xFF;
724 *wrb++ = 0x12;
725 *wrb++ = 0x34;
726 *wrb++ = 0xFF;
727 *wrb++ = 0xFF;
728 *wrb++ = 0x56;
729 *wrb++ = 0x78;
730 *wrb = 0xFF;
731
732 status = be_mbox_notify_wait(adapter);
733
734 mutex_unlock(&adapter->mbox_lock);
735 return status;
736 }
737
738 /* Tell fw we're done with firing cmds by writing a
739 * special pattern across the wrb hdr; uses mbox
740 */
741 int be_cmd_fw_clean(struct be_adapter *adapter)
742 {
743 u8 *wrb;
744 int status;
745
746 if (lancer_chip(adapter))
747 return 0;
748
749 if (mutex_lock_interruptible(&adapter->mbox_lock))
750 return -1;
751
752 wrb = (u8 *)wrb_from_mbox(adapter);
753 *wrb++ = 0xFF;
754 *wrb++ = 0xAA;
755 *wrb++ = 0xBB;
756 *wrb++ = 0xFF;
757 *wrb++ = 0xFF;
758 *wrb++ = 0xCC;
759 *wrb++ = 0xDD;
760 *wrb = 0xFF;
761
762 status = be_mbox_notify_wait(adapter);
763
764 mutex_unlock(&adapter->mbox_lock);
765 return status;
766 }
767
768 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
769 {
770 struct be_mcc_wrb *wrb;
771 struct be_cmd_req_eq_create *req;
772 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
773 int status, ver = 0;
774
775 if (mutex_lock_interruptible(&adapter->mbox_lock))
776 return -1;
777
778 wrb = wrb_from_mbox(adapter);
779 req = embedded_payload(wrb);
780
781 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
782 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
783
784 /* Support for EQ_CREATEv2 available only SH-R onwards */
785 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
786 ver = 2;
787
788 req->hdr.version = ver;
789 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
790
791 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
792 /* 4byte eqe*/
793 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
794 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
795 __ilog2_u32(eqo->q.len / 256));
796 be_dws_cpu_to_le(req->context, sizeof(req->context));
797
798 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
799
800 status = be_mbox_notify_wait(adapter);
801 if (!status) {
802 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
803 eqo->q.id = le16_to_cpu(resp->eq_id);
804 eqo->msix_idx =
805 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
806 eqo->q.created = true;
807 }
808
809 mutex_unlock(&adapter->mbox_lock);
810 return status;
811 }
812
813 /* Use MCC */
814 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
815 bool permanent, u32 if_handle, u32 pmac_id)
816 {
817 struct be_mcc_wrb *wrb;
818 struct be_cmd_req_mac_query *req;
819 int status;
820
821 spin_lock_bh(&adapter->mcc_lock);
822
823 wrb = wrb_from_mccq(adapter);
824 if (!wrb) {
825 status = -EBUSY;
826 goto err;
827 }
828 req = embedded_payload(wrb);
829
830 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
831 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
832 req->type = MAC_ADDRESS_TYPE_NETWORK;
833 if (permanent) {
834 req->permanent = 1;
835 } else {
836 req->if_id = cpu_to_le16((u16) if_handle);
837 req->pmac_id = cpu_to_le32(pmac_id);
838 req->permanent = 0;
839 }
840
841 status = be_mcc_notify_wait(adapter);
842 if (!status) {
843 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
844 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
845 }
846
847 err:
848 spin_unlock_bh(&adapter->mcc_lock);
849 return status;
850 }
851
852 /* Uses synchronous MCCQ */
853 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
854 u32 if_id, u32 *pmac_id, u32 domain)
855 {
856 struct be_mcc_wrb *wrb;
857 struct be_cmd_req_pmac_add *req;
858 int status;
859
860 spin_lock_bh(&adapter->mcc_lock);
861
862 wrb = wrb_from_mccq(adapter);
863 if (!wrb) {
864 status = -EBUSY;
865 goto err;
866 }
867 req = embedded_payload(wrb);
868
869 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
870 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
871
872 req->hdr.domain = domain;
873 req->if_id = cpu_to_le32(if_id);
874 memcpy(req->mac_address, mac_addr, ETH_ALEN);
875
876 status = be_mcc_notify_wait(adapter);
877 if (!status) {
878 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
879 *pmac_id = le32_to_cpu(resp->pmac_id);
880 }
881
882 err:
883 spin_unlock_bh(&adapter->mcc_lock);
884
885 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
886 status = -EPERM;
887
888 return status;
889 }
890
891 /* Uses synchronous MCCQ */
892 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
893 {
894 struct be_mcc_wrb *wrb;
895 struct be_cmd_req_pmac_del *req;
896 int status;
897
898 if (pmac_id == -1)
899 return 0;
900
901 spin_lock_bh(&adapter->mcc_lock);
902
903 wrb = wrb_from_mccq(adapter);
904 if (!wrb) {
905 status = -EBUSY;
906 goto err;
907 }
908 req = embedded_payload(wrb);
909
910 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
911 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
912
913 req->hdr.domain = dom;
914 req->if_id = cpu_to_le32(if_id);
915 req->pmac_id = cpu_to_le32(pmac_id);
916
917 status = be_mcc_notify_wait(adapter);
918
919 err:
920 spin_unlock_bh(&adapter->mcc_lock);
921 return status;
922 }
923
924 /* Uses Mbox */
925 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
926 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
927 {
928 struct be_mcc_wrb *wrb;
929 struct be_cmd_req_cq_create *req;
930 struct be_dma_mem *q_mem = &cq->dma_mem;
931 void *ctxt;
932 int status;
933
934 if (mutex_lock_interruptible(&adapter->mbox_lock))
935 return -1;
936
937 wrb = wrb_from_mbox(adapter);
938 req = embedded_payload(wrb);
939 ctxt = &req->context;
940
941 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
942 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
943
944 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
945
946 if (BEx_chip(adapter)) {
947 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
948 coalesce_wm);
949 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
950 ctxt, no_delay);
951 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
952 __ilog2_u32(cq->len/256));
953 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
954 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
955 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
956 } else {
957 req->hdr.version = 2;
958 req->page_size = 1; /* 1 for 4K */
959 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
960 no_delay);
961 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
962 __ilog2_u32(cq->len/256));
963 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
964 AMAP_SET_BITS(struct amap_cq_context_v2, eventable,
965 ctxt, 1);
966 AMAP_SET_BITS(struct amap_cq_context_v2, eqid,
967 ctxt, eq->id);
968 }
969
970 be_dws_cpu_to_le(ctxt, sizeof(req->context));
971
972 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
973
974 status = be_mbox_notify_wait(adapter);
975 if (!status) {
976 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
977 cq->id = le16_to_cpu(resp->cq_id);
978 cq->created = true;
979 }
980
981 mutex_unlock(&adapter->mbox_lock);
982
983 return status;
984 }
985
986 static u32 be_encoded_q_len(int q_len)
987 {
988 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
989 if (len_encoded == 16)
990 len_encoded = 0;
991 return len_encoded;
992 }
993
994 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
995 struct be_queue_info *mccq,
996 struct be_queue_info *cq)
997 {
998 struct be_mcc_wrb *wrb;
999 struct be_cmd_req_mcc_ext_create *req;
1000 struct be_dma_mem *q_mem = &mccq->dma_mem;
1001 void *ctxt;
1002 int status;
1003
1004 if (mutex_lock_interruptible(&adapter->mbox_lock))
1005 return -1;
1006
1007 wrb = wrb_from_mbox(adapter);
1008 req = embedded_payload(wrb);
1009 ctxt = &req->context;
1010
1011 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1012 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
1013
1014 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1015 if (lancer_chip(adapter)) {
1016 req->hdr.version = 1;
1017 req->cq_id = cpu_to_le16(cq->id);
1018
1019 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
1020 be_encoded_q_len(mccq->len));
1021 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
1022 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
1023 ctxt, cq->id);
1024 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
1025 ctxt, 1);
1026
1027 } else {
1028 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1029 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1030 be_encoded_q_len(mccq->len));
1031 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1032 }
1033
1034 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1035 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1036 req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
1037 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1038
1039 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1040
1041 status = be_mbox_notify_wait(adapter);
1042 if (!status) {
1043 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1044 mccq->id = le16_to_cpu(resp->id);
1045 mccq->created = true;
1046 }
1047 mutex_unlock(&adapter->mbox_lock);
1048
1049 return status;
1050 }
1051
1052 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1053 struct be_queue_info *mccq,
1054 struct be_queue_info *cq)
1055 {
1056 struct be_mcc_wrb *wrb;
1057 struct be_cmd_req_mcc_create *req;
1058 struct be_dma_mem *q_mem = &mccq->dma_mem;
1059 void *ctxt;
1060 int status;
1061
1062 if (mutex_lock_interruptible(&adapter->mbox_lock))
1063 return -1;
1064
1065 wrb = wrb_from_mbox(adapter);
1066 req = embedded_payload(wrb);
1067 ctxt = &req->context;
1068
1069 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1070 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
1071
1072 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1073
1074 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1075 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1076 be_encoded_q_len(mccq->len));
1077 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1078
1079 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1080
1081 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1082
1083 status = be_mbox_notify_wait(adapter);
1084 if (!status) {
1085 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1086 mccq->id = le16_to_cpu(resp->id);
1087 mccq->created = true;
1088 }
1089
1090 mutex_unlock(&adapter->mbox_lock);
1091 return status;
1092 }
1093
1094 int be_cmd_mccq_create(struct be_adapter *adapter,
1095 struct be_queue_info *mccq,
1096 struct be_queue_info *cq)
1097 {
1098 int status;
1099
1100 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1101 if (status && !lancer_chip(adapter)) {
1102 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1103 "or newer to avoid conflicting priorities between NIC "
1104 "and FCoE traffic");
1105 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1106 }
1107 return status;
1108 }
1109
1110 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1111 {
1112 struct be_mcc_wrb *wrb;
1113 struct be_cmd_req_eth_tx_create *req;
1114 struct be_queue_info *txq = &txo->q;
1115 struct be_queue_info *cq = &txo->cq;
1116 struct be_dma_mem *q_mem = &txq->dma_mem;
1117 int status, ver = 0;
1118
1119 spin_lock_bh(&adapter->mcc_lock);
1120
1121 wrb = wrb_from_mccq(adapter);
1122 if (!wrb) {
1123 status = -EBUSY;
1124 goto err;
1125 }
1126
1127 req = embedded_payload(wrb);
1128
1129 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1130 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
1131
1132 if (lancer_chip(adapter)) {
1133 req->hdr.version = 1;
1134 req->if_id = cpu_to_le16(adapter->if_handle);
1135 } else if (BEx_chip(adapter)) {
1136 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1137 req->hdr.version = 2;
1138 } else { /* For SH */
1139 req->hdr.version = 2;
1140 }
1141
1142 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1143 req->ulp_num = BE_ULP1_NUM;
1144 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1145 req->cq_id = cpu_to_le16(cq->id);
1146 req->queue_size = be_encoded_q_len(txq->len);
1147 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1148
1149 ver = req->hdr.version;
1150
1151 status = be_mcc_notify_wait(adapter);
1152 if (!status) {
1153 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1154 txq->id = le16_to_cpu(resp->cid);
1155 if (ver == 2)
1156 txo->db_offset = le32_to_cpu(resp->db_offset);
1157 else
1158 txo->db_offset = DB_TXULP1_OFFSET;
1159 txq->created = true;
1160 }
1161
1162 err:
1163 spin_unlock_bh(&adapter->mcc_lock);
1164
1165 return status;
1166 }
1167
1168 /* Uses MCC */
1169 int be_cmd_rxq_create(struct be_adapter *adapter,
1170 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1171 u32 if_id, u32 rss, u8 *rss_id)
1172 {
1173 struct be_mcc_wrb *wrb;
1174 struct be_cmd_req_eth_rx_create *req;
1175 struct be_dma_mem *q_mem = &rxq->dma_mem;
1176 int status;
1177
1178 spin_lock_bh(&adapter->mcc_lock);
1179
1180 wrb = wrb_from_mccq(adapter);
1181 if (!wrb) {
1182 status = -EBUSY;
1183 goto err;
1184 }
1185 req = embedded_payload(wrb);
1186
1187 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1188 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1189
1190 req->cq_id = cpu_to_le16(cq_id);
1191 req->frag_size = fls(frag_size) - 1;
1192 req->num_pages = 2;
1193 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1194 req->interface_id = cpu_to_le32(if_id);
1195 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1196 req->rss_queue = cpu_to_le32(rss);
1197
1198 status = be_mcc_notify_wait(adapter);
1199 if (!status) {
1200 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1201 rxq->id = le16_to_cpu(resp->id);
1202 rxq->created = true;
1203 *rss_id = resp->rss_id;
1204 }
1205
1206 err:
1207 spin_unlock_bh(&adapter->mcc_lock);
1208 return status;
1209 }
1210
1211 /* Generic destroyer function for all types of queues
1212 * Uses Mbox
1213 */
1214 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1215 int queue_type)
1216 {
1217 struct be_mcc_wrb *wrb;
1218 struct be_cmd_req_q_destroy *req;
1219 u8 subsys = 0, opcode = 0;
1220 int status;
1221
1222 if (mutex_lock_interruptible(&adapter->mbox_lock))
1223 return -1;
1224
1225 wrb = wrb_from_mbox(adapter);
1226 req = embedded_payload(wrb);
1227
1228 switch (queue_type) {
1229 case QTYPE_EQ:
1230 subsys = CMD_SUBSYSTEM_COMMON;
1231 opcode = OPCODE_COMMON_EQ_DESTROY;
1232 break;
1233 case QTYPE_CQ:
1234 subsys = CMD_SUBSYSTEM_COMMON;
1235 opcode = OPCODE_COMMON_CQ_DESTROY;
1236 break;
1237 case QTYPE_TXQ:
1238 subsys = CMD_SUBSYSTEM_ETH;
1239 opcode = OPCODE_ETH_TX_DESTROY;
1240 break;
1241 case QTYPE_RXQ:
1242 subsys = CMD_SUBSYSTEM_ETH;
1243 opcode = OPCODE_ETH_RX_DESTROY;
1244 break;
1245 case QTYPE_MCCQ:
1246 subsys = CMD_SUBSYSTEM_COMMON;
1247 opcode = OPCODE_COMMON_MCC_DESTROY;
1248 break;
1249 default:
1250 BUG();
1251 }
1252
1253 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1254 NULL);
1255 req->id = cpu_to_le16(q->id);
1256
1257 status = be_mbox_notify_wait(adapter);
1258 q->created = false;
1259
1260 mutex_unlock(&adapter->mbox_lock);
1261 return status;
1262 }
1263
1264 /* Uses MCC */
1265 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1266 {
1267 struct be_mcc_wrb *wrb;
1268 struct be_cmd_req_q_destroy *req;
1269 int status;
1270
1271 spin_lock_bh(&adapter->mcc_lock);
1272
1273 wrb = wrb_from_mccq(adapter);
1274 if (!wrb) {
1275 status = -EBUSY;
1276 goto err;
1277 }
1278 req = embedded_payload(wrb);
1279
1280 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1281 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1282 req->id = cpu_to_le16(q->id);
1283
1284 status = be_mcc_notify_wait(adapter);
1285 q->created = false;
1286
1287 err:
1288 spin_unlock_bh(&adapter->mcc_lock);
1289 return status;
1290 }
1291
1292 /* Create an rx filtering policy configuration on an i/f
1293 * Uses MCCQ
1294 */
1295 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1296 u32 *if_handle, u32 domain)
1297 {
1298 struct be_mcc_wrb *wrb;
1299 struct be_cmd_req_if_create *req;
1300 int status;
1301
1302 spin_lock_bh(&adapter->mcc_lock);
1303
1304 wrb = wrb_from_mccq(adapter);
1305 if (!wrb) {
1306 status = -EBUSY;
1307 goto err;
1308 }
1309 req = embedded_payload(wrb);
1310
1311 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1312 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1313 req->hdr.domain = domain;
1314 req->capability_flags = cpu_to_le32(cap_flags);
1315 req->enable_flags = cpu_to_le32(en_flags);
1316
1317 req->pmac_invalid = true;
1318
1319 status = be_mcc_notify_wait(adapter);
1320 if (!status) {
1321 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1322 *if_handle = le32_to_cpu(resp->interface_id);
1323
1324 /* Hack to retrieve VF's pmac-id on BE3 */
1325 if (BE3_chip(adapter) && !be_physfn(adapter))
1326 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1327 }
1328
1329 err:
1330 spin_unlock_bh(&adapter->mcc_lock);
1331 return status;
1332 }
1333
1334 /* Uses MCCQ */
1335 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1336 {
1337 struct be_mcc_wrb *wrb;
1338 struct be_cmd_req_if_destroy *req;
1339 int status;
1340
1341 if (interface_id == -1)
1342 return 0;
1343
1344 spin_lock_bh(&adapter->mcc_lock);
1345
1346 wrb = wrb_from_mccq(adapter);
1347 if (!wrb) {
1348 status = -EBUSY;
1349 goto err;
1350 }
1351 req = embedded_payload(wrb);
1352
1353 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1354 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1355 req->hdr.domain = domain;
1356 req->interface_id = cpu_to_le32(interface_id);
1357
1358 status = be_mcc_notify_wait(adapter);
1359 err:
1360 spin_unlock_bh(&adapter->mcc_lock);
1361 return status;
1362 }
1363
1364 /* Get stats is a non embedded command: the request is not embedded inside
1365 * WRB but is a separate dma memory block
1366 * Uses asynchronous MCC
1367 */
1368 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1369 {
1370 struct be_mcc_wrb *wrb;
1371 struct be_cmd_req_hdr *hdr;
1372 int status = 0;
1373
1374 spin_lock_bh(&adapter->mcc_lock);
1375
1376 wrb = wrb_from_mccq(adapter);
1377 if (!wrb) {
1378 status = -EBUSY;
1379 goto err;
1380 }
1381 hdr = nonemb_cmd->va;
1382
1383 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1384 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1385
1386 /* version 1 of the cmd is not supported only by BE2 */
1387 if (!BE2_chip(adapter))
1388 hdr->version = 1;
1389
1390 be_mcc_notify(adapter);
1391 adapter->stats_cmd_sent = true;
1392
1393 err:
1394 spin_unlock_bh(&adapter->mcc_lock);
1395 return status;
1396 }
1397
1398 /* Lancer Stats */
1399 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1400 struct be_dma_mem *nonemb_cmd)
1401 {
1402
1403 struct be_mcc_wrb *wrb;
1404 struct lancer_cmd_req_pport_stats *req;
1405 int status = 0;
1406
1407 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1408 CMD_SUBSYSTEM_ETH))
1409 return -EPERM;
1410
1411 spin_lock_bh(&adapter->mcc_lock);
1412
1413 wrb = wrb_from_mccq(adapter);
1414 if (!wrb) {
1415 status = -EBUSY;
1416 goto err;
1417 }
1418 req = nonemb_cmd->va;
1419
1420 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1421 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1422 nonemb_cmd);
1423
1424 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1425 req->cmd_params.params.reset_stats = 0;
1426
1427 be_mcc_notify(adapter);
1428 adapter->stats_cmd_sent = true;
1429
1430 err:
1431 spin_unlock_bh(&adapter->mcc_lock);
1432 return status;
1433 }
1434
1435 static int be_mac_to_link_speed(int mac_speed)
1436 {
1437 switch (mac_speed) {
1438 case PHY_LINK_SPEED_ZERO:
1439 return 0;
1440 case PHY_LINK_SPEED_10MBPS:
1441 return 10;
1442 case PHY_LINK_SPEED_100MBPS:
1443 return 100;
1444 case PHY_LINK_SPEED_1GBPS:
1445 return 1000;
1446 case PHY_LINK_SPEED_10GBPS:
1447 return 10000;
1448 case PHY_LINK_SPEED_20GBPS:
1449 return 20000;
1450 case PHY_LINK_SPEED_25GBPS:
1451 return 25000;
1452 case PHY_LINK_SPEED_40GBPS:
1453 return 40000;
1454 }
1455 return 0;
1456 }
1457
1458 /* Uses synchronous mcc
1459 * Returns link_speed in Mbps
1460 */
1461 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1462 u8 *link_status, u32 dom)
1463 {
1464 struct be_mcc_wrb *wrb;
1465 struct be_cmd_req_link_status *req;
1466 int status;
1467
1468 spin_lock_bh(&adapter->mcc_lock);
1469
1470 if (link_status)
1471 *link_status = LINK_DOWN;
1472
1473 wrb = wrb_from_mccq(adapter);
1474 if (!wrb) {
1475 status = -EBUSY;
1476 goto err;
1477 }
1478 req = embedded_payload(wrb);
1479
1480 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1481 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1482
1483 /* version 1 of the cmd is not supported only by BE2 */
1484 if (!BE2_chip(adapter))
1485 req->hdr.version = 1;
1486
1487 req->hdr.domain = dom;
1488
1489 status = be_mcc_notify_wait(adapter);
1490 if (!status) {
1491 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1492 if (link_speed) {
1493 *link_speed = resp->link_speed ?
1494 le16_to_cpu(resp->link_speed) * 10 :
1495 be_mac_to_link_speed(resp->mac_speed);
1496
1497 if (!resp->logical_link_status)
1498 *link_speed = 0;
1499 }
1500 if (link_status)
1501 *link_status = resp->logical_link_status;
1502 }
1503
1504 err:
1505 spin_unlock_bh(&adapter->mcc_lock);
1506 return status;
1507 }
1508
1509 /* Uses synchronous mcc */
1510 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1511 {
1512 struct be_mcc_wrb *wrb;
1513 struct be_cmd_req_get_cntl_addnl_attribs *req;
1514 int status = 0;
1515
1516 spin_lock_bh(&adapter->mcc_lock);
1517
1518 wrb = wrb_from_mccq(adapter);
1519 if (!wrb) {
1520 status = -EBUSY;
1521 goto err;
1522 }
1523 req = embedded_payload(wrb);
1524
1525 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1526 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1527 wrb, NULL);
1528
1529 be_mcc_notify(adapter);
1530
1531 err:
1532 spin_unlock_bh(&adapter->mcc_lock);
1533 return status;
1534 }
1535
1536 /* Uses synchronous mcc */
1537 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1538 {
1539 struct be_mcc_wrb *wrb;
1540 struct be_cmd_req_get_fat *req;
1541 int status;
1542
1543 spin_lock_bh(&adapter->mcc_lock);
1544
1545 wrb = wrb_from_mccq(adapter);
1546 if (!wrb) {
1547 status = -EBUSY;
1548 goto err;
1549 }
1550 req = embedded_payload(wrb);
1551
1552 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1553 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1554 req->fat_operation = cpu_to_le32(QUERY_FAT);
1555 status = be_mcc_notify_wait(adapter);
1556 if (!status) {
1557 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1558 if (log_size && resp->log_size)
1559 *log_size = le32_to_cpu(resp->log_size) -
1560 sizeof(u32);
1561 }
1562 err:
1563 spin_unlock_bh(&adapter->mcc_lock);
1564 return status;
1565 }
1566
1567 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1568 {
1569 struct be_dma_mem get_fat_cmd;
1570 struct be_mcc_wrb *wrb;
1571 struct be_cmd_req_get_fat *req;
1572 u32 offset = 0, total_size, buf_size,
1573 log_offset = sizeof(u32), payload_len;
1574 int status;
1575
1576 if (buf_len == 0)
1577 return;
1578
1579 total_size = buf_len;
1580
1581 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1582 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1583 get_fat_cmd.size,
1584 &get_fat_cmd.dma);
1585 if (!get_fat_cmd.va) {
1586 status = -ENOMEM;
1587 dev_err(&adapter->pdev->dev,
1588 "Memory allocation failure while retrieving FAT data\n");
1589 return;
1590 }
1591
1592 spin_lock_bh(&adapter->mcc_lock);
1593
1594 while (total_size) {
1595 buf_size = min(total_size, (u32)60*1024);
1596 total_size -= buf_size;
1597
1598 wrb = wrb_from_mccq(adapter);
1599 if (!wrb) {
1600 status = -EBUSY;
1601 goto err;
1602 }
1603 req = get_fat_cmd.va;
1604
1605 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1606 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1607 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1608 &get_fat_cmd);
1609
1610 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1611 req->read_log_offset = cpu_to_le32(log_offset);
1612 req->read_log_length = cpu_to_le32(buf_size);
1613 req->data_buffer_size = cpu_to_le32(buf_size);
1614
1615 status = be_mcc_notify_wait(adapter);
1616 if (!status) {
1617 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1618 memcpy(buf + offset,
1619 resp->data_buffer,
1620 le32_to_cpu(resp->read_log_length));
1621 } else {
1622 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1623 goto err;
1624 }
1625 offset += buf_size;
1626 log_offset += buf_size;
1627 }
1628 err:
1629 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1630 get_fat_cmd.va,
1631 get_fat_cmd.dma);
1632 spin_unlock_bh(&adapter->mcc_lock);
1633 }
1634
1635 /* Uses synchronous mcc */
1636 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1637 char *fw_on_flash)
1638 {
1639 struct be_mcc_wrb *wrb;
1640 struct be_cmd_req_get_fw_version *req;
1641 int status;
1642
1643 spin_lock_bh(&adapter->mcc_lock);
1644
1645 wrb = wrb_from_mccq(adapter);
1646 if (!wrb) {
1647 status = -EBUSY;
1648 goto err;
1649 }
1650
1651 req = embedded_payload(wrb);
1652
1653 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1654 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1655 status = be_mcc_notify_wait(adapter);
1656 if (!status) {
1657 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1658 strcpy(fw_ver, resp->firmware_version_string);
1659 if (fw_on_flash)
1660 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1661 }
1662 err:
1663 spin_unlock_bh(&adapter->mcc_lock);
1664 return status;
1665 }
1666
1667 /* set the EQ delay interval of an EQ to specified value
1668 * Uses async mcc
1669 */
1670 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1671 {
1672 struct be_mcc_wrb *wrb;
1673 struct be_cmd_req_modify_eq_delay *req;
1674 int status = 0;
1675
1676 spin_lock_bh(&adapter->mcc_lock);
1677
1678 wrb = wrb_from_mccq(adapter);
1679 if (!wrb) {
1680 status = -EBUSY;
1681 goto err;
1682 }
1683 req = embedded_payload(wrb);
1684
1685 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1686 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1687
1688 req->num_eq = cpu_to_le32(1);
1689 req->delay[0].eq_id = cpu_to_le32(eq_id);
1690 req->delay[0].phase = 0;
1691 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1692
1693 be_mcc_notify(adapter);
1694
1695 err:
1696 spin_unlock_bh(&adapter->mcc_lock);
1697 return status;
1698 }
1699
1700 /* Uses sycnhronous mcc */
1701 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1702 u32 num, bool untagged, bool promiscuous)
1703 {
1704 struct be_mcc_wrb *wrb;
1705 struct be_cmd_req_vlan_config *req;
1706 int status;
1707
1708 spin_lock_bh(&adapter->mcc_lock);
1709
1710 wrb = wrb_from_mccq(adapter);
1711 if (!wrb) {
1712 status = -EBUSY;
1713 goto err;
1714 }
1715 req = embedded_payload(wrb);
1716
1717 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1718 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1719
1720 req->interface_id = if_id;
1721 req->promiscuous = promiscuous;
1722 req->untagged = untagged;
1723 req->num_vlan = num;
1724 if (!promiscuous) {
1725 memcpy(req->normal_vlan, vtag_array,
1726 req->num_vlan * sizeof(vtag_array[0]));
1727 }
1728
1729 status = be_mcc_notify_wait(adapter);
1730
1731 err:
1732 spin_unlock_bh(&adapter->mcc_lock);
1733 return status;
1734 }
1735
1736 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1737 {
1738 struct be_mcc_wrb *wrb;
1739 struct be_dma_mem *mem = &adapter->rx_filter;
1740 struct be_cmd_req_rx_filter *req = mem->va;
1741 int status;
1742
1743 spin_lock_bh(&adapter->mcc_lock);
1744
1745 wrb = wrb_from_mccq(adapter);
1746 if (!wrb) {
1747 status = -EBUSY;
1748 goto err;
1749 }
1750 memset(req, 0, sizeof(*req));
1751 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1752 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1753 wrb, mem);
1754
1755 req->if_id = cpu_to_le32(adapter->if_handle);
1756 if (flags & IFF_PROMISC) {
1757 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1758 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1759 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1760 if (value == ON)
1761 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1762 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1763 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1764 } else if (flags & IFF_ALLMULTI) {
1765 req->if_flags_mask = req->if_flags =
1766 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1767 } else {
1768 struct netdev_hw_addr *ha;
1769 int i = 0;
1770
1771 req->if_flags_mask = req->if_flags =
1772 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1773
1774 /* Reset mcast promisc mode if already set by setting mask
1775 * and not setting flags field
1776 */
1777 req->if_flags_mask |=
1778 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1779 adapter->if_cap_flags);
1780
1781 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1782 netdev_for_each_mc_addr(ha, adapter->netdev)
1783 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1784 }
1785
1786 status = be_mcc_notify_wait(adapter);
1787 err:
1788 spin_unlock_bh(&adapter->mcc_lock);
1789 return status;
1790 }
1791
1792 /* Uses synchrounous mcc */
1793 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1794 {
1795 struct be_mcc_wrb *wrb;
1796 struct be_cmd_req_set_flow_control *req;
1797 int status;
1798
1799 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1800 CMD_SUBSYSTEM_COMMON))
1801 return -EPERM;
1802
1803 spin_lock_bh(&adapter->mcc_lock);
1804
1805 wrb = wrb_from_mccq(adapter);
1806 if (!wrb) {
1807 status = -EBUSY;
1808 goto err;
1809 }
1810 req = embedded_payload(wrb);
1811
1812 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1813 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1814
1815 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1816 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1817
1818 status = be_mcc_notify_wait(adapter);
1819
1820 err:
1821 spin_unlock_bh(&adapter->mcc_lock);
1822 return status;
1823 }
1824
1825 /* Uses sycn mcc */
1826 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1827 {
1828 struct be_mcc_wrb *wrb;
1829 struct be_cmd_req_get_flow_control *req;
1830 int status;
1831
1832 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1833 CMD_SUBSYSTEM_COMMON))
1834 return -EPERM;
1835
1836 spin_lock_bh(&adapter->mcc_lock);
1837
1838 wrb = wrb_from_mccq(adapter);
1839 if (!wrb) {
1840 status = -EBUSY;
1841 goto err;
1842 }
1843 req = embedded_payload(wrb);
1844
1845 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1846 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1847
1848 status = be_mcc_notify_wait(adapter);
1849 if (!status) {
1850 struct be_cmd_resp_get_flow_control *resp =
1851 embedded_payload(wrb);
1852 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1853 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1854 }
1855
1856 err:
1857 spin_unlock_bh(&adapter->mcc_lock);
1858 return status;
1859 }
1860
1861 /* Uses mbox */
1862 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1863 u32 *mode, u32 *caps, u16 *asic_rev)
1864 {
1865 struct be_mcc_wrb *wrb;
1866 struct be_cmd_req_query_fw_cfg *req;
1867 int status;
1868
1869 if (mutex_lock_interruptible(&adapter->mbox_lock))
1870 return -1;
1871
1872 wrb = wrb_from_mbox(adapter);
1873 req = embedded_payload(wrb);
1874
1875 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1876 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1877
1878 status = be_mbox_notify_wait(adapter);
1879 if (!status) {
1880 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1881 *port_num = le32_to_cpu(resp->phys_port);
1882 *mode = le32_to_cpu(resp->function_mode);
1883 *caps = le32_to_cpu(resp->function_caps);
1884 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
1885 }
1886
1887 mutex_unlock(&adapter->mbox_lock);
1888 return status;
1889 }
1890
1891 /* Uses mbox */
1892 int be_cmd_reset_function(struct be_adapter *adapter)
1893 {
1894 struct be_mcc_wrb *wrb;
1895 struct be_cmd_req_hdr *req;
1896 int status;
1897
1898 if (lancer_chip(adapter)) {
1899 status = lancer_wait_ready(adapter);
1900 if (!status) {
1901 iowrite32(SLI_PORT_CONTROL_IP_MASK,
1902 adapter->db + SLIPORT_CONTROL_OFFSET);
1903 status = lancer_test_and_set_rdy_state(adapter);
1904 }
1905 if (status) {
1906 dev_err(&adapter->pdev->dev,
1907 "Adapter in non recoverable error\n");
1908 }
1909 return status;
1910 }
1911
1912 if (mutex_lock_interruptible(&adapter->mbox_lock))
1913 return -1;
1914
1915 wrb = wrb_from_mbox(adapter);
1916 req = embedded_payload(wrb);
1917
1918 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1919 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1920
1921 status = be_mbox_notify_wait(adapter);
1922
1923 mutex_unlock(&adapter->mbox_lock);
1924 return status;
1925 }
1926
1927 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1928 u32 rss_hash_opts, u16 table_size)
1929 {
1930 struct be_mcc_wrb *wrb;
1931 struct be_cmd_req_rss_config *req;
1932 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1933 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1934 0x3ea83c02, 0x4a110304};
1935 int status;
1936
1937 if (mutex_lock_interruptible(&adapter->mbox_lock))
1938 return -1;
1939
1940 wrb = wrb_from_mbox(adapter);
1941 req = embedded_payload(wrb);
1942
1943 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1944 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1945
1946 req->if_id = cpu_to_le32(adapter->if_handle);
1947 req->enable_rss = cpu_to_le16(rss_hash_opts);
1948 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1949
1950 if (lancer_chip(adapter) || skyhawk_chip(adapter))
1951 req->hdr.version = 1;
1952
1953 memcpy(req->cpu_table, rsstable, table_size);
1954 memcpy(req->hash, myhash, sizeof(myhash));
1955 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1956
1957 status = be_mbox_notify_wait(adapter);
1958
1959 mutex_unlock(&adapter->mbox_lock);
1960 return status;
1961 }
1962
1963 /* Uses sync mcc */
1964 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1965 u8 bcn, u8 sts, u8 state)
1966 {
1967 struct be_mcc_wrb *wrb;
1968 struct be_cmd_req_enable_disable_beacon *req;
1969 int status;
1970
1971 spin_lock_bh(&adapter->mcc_lock);
1972
1973 wrb = wrb_from_mccq(adapter);
1974 if (!wrb) {
1975 status = -EBUSY;
1976 goto err;
1977 }
1978 req = embedded_payload(wrb);
1979
1980 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1981 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1982
1983 req->port_num = port_num;
1984 req->beacon_state = state;
1985 req->beacon_duration = bcn;
1986 req->status_duration = sts;
1987
1988 status = be_mcc_notify_wait(adapter);
1989
1990 err:
1991 spin_unlock_bh(&adapter->mcc_lock);
1992 return status;
1993 }
1994
1995 /* Uses sync mcc */
1996 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1997 {
1998 struct be_mcc_wrb *wrb;
1999 struct be_cmd_req_get_beacon_state *req;
2000 int status;
2001
2002 spin_lock_bh(&adapter->mcc_lock);
2003
2004 wrb = wrb_from_mccq(adapter);
2005 if (!wrb) {
2006 status = -EBUSY;
2007 goto err;
2008 }
2009 req = embedded_payload(wrb);
2010
2011 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2012 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
2013
2014 req->port_num = port_num;
2015
2016 status = be_mcc_notify_wait(adapter);
2017 if (!status) {
2018 struct be_cmd_resp_get_beacon_state *resp =
2019 embedded_payload(wrb);
2020 *state = resp->beacon_state;
2021 }
2022
2023 err:
2024 spin_unlock_bh(&adapter->mcc_lock);
2025 return status;
2026 }
2027
2028 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2029 u32 data_size, u32 data_offset,
2030 const char *obj_name, u32 *data_written,
2031 u8 *change_status, u8 *addn_status)
2032 {
2033 struct be_mcc_wrb *wrb;
2034 struct lancer_cmd_req_write_object *req;
2035 struct lancer_cmd_resp_write_object *resp;
2036 void *ctxt = NULL;
2037 int status;
2038
2039 spin_lock_bh(&adapter->mcc_lock);
2040 adapter->flash_status = 0;
2041
2042 wrb = wrb_from_mccq(adapter);
2043 if (!wrb) {
2044 status = -EBUSY;
2045 goto err_unlock;
2046 }
2047
2048 req = embedded_payload(wrb);
2049
2050 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2051 OPCODE_COMMON_WRITE_OBJECT,
2052 sizeof(struct lancer_cmd_req_write_object), wrb,
2053 NULL);
2054
2055 ctxt = &req->context;
2056 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2057 write_length, ctxt, data_size);
2058
2059 if (data_size == 0)
2060 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2061 eof, ctxt, 1);
2062 else
2063 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2064 eof, ctxt, 0);
2065
2066 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2067 req->write_offset = cpu_to_le32(data_offset);
2068 strcpy(req->object_name, obj_name);
2069 req->descriptor_count = cpu_to_le32(1);
2070 req->buf_len = cpu_to_le32(data_size);
2071 req->addr_low = cpu_to_le32((cmd->dma +
2072 sizeof(struct lancer_cmd_req_write_object))
2073 & 0xFFFFFFFF);
2074 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2075 sizeof(struct lancer_cmd_req_write_object)));
2076
2077 be_mcc_notify(adapter);
2078 spin_unlock_bh(&adapter->mcc_lock);
2079
2080 if (!wait_for_completion_timeout(&adapter->flash_compl,
2081 msecs_to_jiffies(60000)))
2082 status = -1;
2083 else
2084 status = adapter->flash_status;
2085
2086 resp = embedded_payload(wrb);
2087 if (!status) {
2088 *data_written = le32_to_cpu(resp->actual_write_len);
2089 *change_status = resp->change_status;
2090 } else {
2091 *addn_status = resp->additional_status;
2092 }
2093
2094 return status;
2095
2096 err_unlock:
2097 spin_unlock_bh(&adapter->mcc_lock);
2098 return status;
2099 }
2100
2101 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2102 u32 data_size, u32 data_offset, const char *obj_name,
2103 u32 *data_read, u32 *eof, u8 *addn_status)
2104 {
2105 struct be_mcc_wrb *wrb;
2106 struct lancer_cmd_req_read_object *req;
2107 struct lancer_cmd_resp_read_object *resp;
2108 int status;
2109
2110 spin_lock_bh(&adapter->mcc_lock);
2111
2112 wrb = wrb_from_mccq(adapter);
2113 if (!wrb) {
2114 status = -EBUSY;
2115 goto err_unlock;
2116 }
2117
2118 req = embedded_payload(wrb);
2119
2120 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2121 OPCODE_COMMON_READ_OBJECT,
2122 sizeof(struct lancer_cmd_req_read_object), wrb,
2123 NULL);
2124
2125 req->desired_read_len = cpu_to_le32(data_size);
2126 req->read_offset = cpu_to_le32(data_offset);
2127 strcpy(req->object_name, obj_name);
2128 req->descriptor_count = cpu_to_le32(1);
2129 req->buf_len = cpu_to_le32(data_size);
2130 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2131 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2132
2133 status = be_mcc_notify_wait(adapter);
2134
2135 resp = embedded_payload(wrb);
2136 if (!status) {
2137 *data_read = le32_to_cpu(resp->actual_read_len);
2138 *eof = le32_to_cpu(resp->eof);
2139 } else {
2140 *addn_status = resp->additional_status;
2141 }
2142
2143 err_unlock:
2144 spin_unlock_bh(&adapter->mcc_lock);
2145 return status;
2146 }
2147
2148 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2149 u32 flash_type, u32 flash_opcode, u32 buf_size)
2150 {
2151 struct be_mcc_wrb *wrb;
2152 struct be_cmd_write_flashrom *req;
2153 int status;
2154
2155 spin_lock_bh(&adapter->mcc_lock);
2156 adapter->flash_status = 0;
2157
2158 wrb = wrb_from_mccq(adapter);
2159 if (!wrb) {
2160 status = -EBUSY;
2161 goto err_unlock;
2162 }
2163 req = cmd->va;
2164
2165 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2166 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2167
2168 req->params.op_type = cpu_to_le32(flash_type);
2169 req->params.op_code = cpu_to_le32(flash_opcode);
2170 req->params.data_buf_size = cpu_to_le32(buf_size);
2171
2172 be_mcc_notify(adapter);
2173 spin_unlock_bh(&adapter->mcc_lock);
2174
2175 if (!wait_for_completion_timeout(&adapter->flash_compl,
2176 msecs_to_jiffies(40000)))
2177 status = -1;
2178 else
2179 status = adapter->flash_status;
2180
2181 return status;
2182
2183 err_unlock:
2184 spin_unlock_bh(&adapter->mcc_lock);
2185 return status;
2186 }
2187
2188 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2189 int offset)
2190 {
2191 struct be_mcc_wrb *wrb;
2192 struct be_cmd_read_flash_crc *req;
2193 int status;
2194
2195 spin_lock_bh(&adapter->mcc_lock);
2196
2197 wrb = wrb_from_mccq(adapter);
2198 if (!wrb) {
2199 status = -EBUSY;
2200 goto err;
2201 }
2202 req = embedded_payload(wrb);
2203
2204 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2205 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2206 wrb, NULL);
2207
2208 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2209 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2210 req->params.offset = cpu_to_le32(offset);
2211 req->params.data_buf_size = cpu_to_le32(0x4);
2212
2213 status = be_mcc_notify_wait(adapter);
2214 if (!status)
2215 memcpy(flashed_crc, req->crc, 4);
2216
2217 err:
2218 spin_unlock_bh(&adapter->mcc_lock);
2219 return status;
2220 }
2221
2222 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2223 struct be_dma_mem *nonemb_cmd)
2224 {
2225 struct be_mcc_wrb *wrb;
2226 struct be_cmd_req_acpi_wol_magic_config *req;
2227 int status;
2228
2229 spin_lock_bh(&adapter->mcc_lock);
2230
2231 wrb = wrb_from_mccq(adapter);
2232 if (!wrb) {
2233 status = -EBUSY;
2234 goto err;
2235 }
2236 req = nonemb_cmd->va;
2237
2238 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2239 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2240 nonemb_cmd);
2241 memcpy(req->magic_mac, mac, ETH_ALEN);
2242
2243 status = be_mcc_notify_wait(adapter);
2244
2245 err:
2246 spin_unlock_bh(&adapter->mcc_lock);
2247 return status;
2248 }
2249
2250 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2251 u8 loopback_type, u8 enable)
2252 {
2253 struct be_mcc_wrb *wrb;
2254 struct be_cmd_req_set_lmode *req;
2255 int status;
2256
2257 spin_lock_bh(&adapter->mcc_lock);
2258
2259 wrb = wrb_from_mccq(adapter);
2260 if (!wrb) {
2261 status = -EBUSY;
2262 goto err;
2263 }
2264
2265 req = embedded_payload(wrb);
2266
2267 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2268 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2269 NULL);
2270
2271 req->src_port = port_num;
2272 req->dest_port = port_num;
2273 req->loopback_type = loopback_type;
2274 req->loopback_state = enable;
2275
2276 status = be_mcc_notify_wait(adapter);
2277 err:
2278 spin_unlock_bh(&adapter->mcc_lock);
2279 return status;
2280 }
2281
2282 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2283 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2284 {
2285 struct be_mcc_wrb *wrb;
2286 struct be_cmd_req_loopback_test *req;
2287 int status;
2288
2289 spin_lock_bh(&adapter->mcc_lock);
2290
2291 wrb = wrb_from_mccq(adapter);
2292 if (!wrb) {
2293 status = -EBUSY;
2294 goto err;
2295 }
2296
2297 req = embedded_payload(wrb);
2298
2299 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2300 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2301 req->hdr.timeout = cpu_to_le32(4);
2302
2303 req->pattern = cpu_to_le64(pattern);
2304 req->src_port = cpu_to_le32(port_num);
2305 req->dest_port = cpu_to_le32(port_num);
2306 req->pkt_size = cpu_to_le32(pkt_size);
2307 req->num_pkts = cpu_to_le32(num_pkts);
2308 req->loopback_type = cpu_to_le32(loopback_type);
2309
2310 status = be_mcc_notify_wait(adapter);
2311 if (!status) {
2312 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2313 status = le32_to_cpu(resp->status);
2314 }
2315
2316 err:
2317 spin_unlock_bh(&adapter->mcc_lock);
2318 return status;
2319 }
2320
2321 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2322 u32 byte_cnt, struct be_dma_mem *cmd)
2323 {
2324 struct be_mcc_wrb *wrb;
2325 struct be_cmd_req_ddrdma_test *req;
2326 int status;
2327 int i, j = 0;
2328
2329 spin_lock_bh(&adapter->mcc_lock);
2330
2331 wrb = wrb_from_mccq(adapter);
2332 if (!wrb) {
2333 status = -EBUSY;
2334 goto err;
2335 }
2336 req = cmd->va;
2337 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2338 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2339
2340 req->pattern = cpu_to_le64(pattern);
2341 req->byte_count = cpu_to_le32(byte_cnt);
2342 for (i = 0; i < byte_cnt; i++) {
2343 req->snd_buff[i] = (u8)(pattern >> (j*8));
2344 j++;
2345 if (j > 7)
2346 j = 0;
2347 }
2348
2349 status = be_mcc_notify_wait(adapter);
2350
2351 if (!status) {
2352 struct be_cmd_resp_ddrdma_test *resp;
2353 resp = cmd->va;
2354 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2355 resp->snd_err) {
2356 status = -1;
2357 }
2358 }
2359
2360 err:
2361 spin_unlock_bh(&adapter->mcc_lock);
2362 return status;
2363 }
2364
2365 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2366 struct be_dma_mem *nonemb_cmd)
2367 {
2368 struct be_mcc_wrb *wrb;
2369 struct be_cmd_req_seeprom_read *req;
2370 int status;
2371
2372 spin_lock_bh(&adapter->mcc_lock);
2373
2374 wrb = wrb_from_mccq(adapter);
2375 if (!wrb) {
2376 status = -EBUSY;
2377 goto err;
2378 }
2379 req = nonemb_cmd->va;
2380
2381 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2382 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2383 nonemb_cmd);
2384
2385 status = be_mcc_notify_wait(adapter);
2386
2387 err:
2388 spin_unlock_bh(&adapter->mcc_lock);
2389 return status;
2390 }
2391
2392 int be_cmd_get_phy_info(struct be_adapter *adapter)
2393 {
2394 struct be_mcc_wrb *wrb;
2395 struct be_cmd_req_get_phy_info *req;
2396 struct be_dma_mem cmd;
2397 int status;
2398
2399 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2400 CMD_SUBSYSTEM_COMMON))
2401 return -EPERM;
2402
2403 spin_lock_bh(&adapter->mcc_lock);
2404
2405 wrb = wrb_from_mccq(adapter);
2406 if (!wrb) {
2407 status = -EBUSY;
2408 goto err;
2409 }
2410 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2411 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2412 &cmd.dma);
2413 if (!cmd.va) {
2414 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2415 status = -ENOMEM;
2416 goto err;
2417 }
2418
2419 req = cmd.va;
2420
2421 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2422 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2423 wrb, &cmd);
2424
2425 status = be_mcc_notify_wait(adapter);
2426 if (!status) {
2427 struct be_phy_info *resp_phy_info =
2428 cmd.va + sizeof(struct be_cmd_req_hdr);
2429 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2430 adapter->phy.interface_type =
2431 le16_to_cpu(resp_phy_info->interface_type);
2432 adapter->phy.auto_speeds_supported =
2433 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2434 adapter->phy.fixed_speeds_supported =
2435 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2436 adapter->phy.misc_params =
2437 le32_to_cpu(resp_phy_info->misc_params);
2438
2439 if (BE2_chip(adapter)) {
2440 adapter->phy.fixed_speeds_supported =
2441 BE_SUPPORTED_SPEED_10GBPS |
2442 BE_SUPPORTED_SPEED_1GBPS;
2443 }
2444 }
2445 pci_free_consistent(adapter->pdev, cmd.size,
2446 cmd.va, cmd.dma);
2447 err:
2448 spin_unlock_bh(&adapter->mcc_lock);
2449 return status;
2450 }
2451
2452 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2453 {
2454 struct be_mcc_wrb *wrb;
2455 struct be_cmd_req_set_qos *req;
2456 int status;
2457
2458 spin_lock_bh(&adapter->mcc_lock);
2459
2460 wrb = wrb_from_mccq(adapter);
2461 if (!wrb) {
2462 status = -EBUSY;
2463 goto err;
2464 }
2465
2466 req = embedded_payload(wrb);
2467
2468 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2469 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2470
2471 req->hdr.domain = domain;
2472 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2473 req->max_bps_nic = cpu_to_le32(bps);
2474
2475 status = be_mcc_notify_wait(adapter);
2476
2477 err:
2478 spin_unlock_bh(&adapter->mcc_lock);
2479 return status;
2480 }
2481
2482 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2483 {
2484 struct be_mcc_wrb *wrb;
2485 struct be_cmd_req_cntl_attribs *req;
2486 struct be_cmd_resp_cntl_attribs *resp;
2487 int status;
2488 int payload_len = max(sizeof(*req), sizeof(*resp));
2489 struct mgmt_controller_attrib *attribs;
2490 struct be_dma_mem attribs_cmd;
2491
2492 if (mutex_lock_interruptible(&adapter->mbox_lock))
2493 return -1;
2494
2495 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2496 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2497 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2498 &attribs_cmd.dma);
2499 if (!attribs_cmd.va) {
2500 dev_err(&adapter->pdev->dev,
2501 "Memory allocation failure\n");
2502 status = -ENOMEM;
2503 goto err;
2504 }
2505
2506 wrb = wrb_from_mbox(adapter);
2507 if (!wrb) {
2508 status = -EBUSY;
2509 goto err;
2510 }
2511 req = attribs_cmd.va;
2512
2513 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2514 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2515 &attribs_cmd);
2516
2517 status = be_mbox_notify_wait(adapter);
2518 if (!status) {
2519 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2520 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2521 }
2522
2523 err:
2524 mutex_unlock(&adapter->mbox_lock);
2525 if (attribs_cmd.va)
2526 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2527 attribs_cmd.va, attribs_cmd.dma);
2528 return status;
2529 }
2530
2531 /* Uses mbox */
2532 int be_cmd_req_native_mode(struct be_adapter *adapter)
2533 {
2534 struct be_mcc_wrb *wrb;
2535 struct be_cmd_req_set_func_cap *req;
2536 int status;
2537
2538 if (mutex_lock_interruptible(&adapter->mbox_lock))
2539 return -1;
2540
2541 wrb = wrb_from_mbox(adapter);
2542 if (!wrb) {
2543 status = -EBUSY;
2544 goto err;
2545 }
2546
2547 req = embedded_payload(wrb);
2548
2549 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2550 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2551
2552 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2553 CAPABILITY_BE3_NATIVE_ERX_API);
2554 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2555
2556 status = be_mbox_notify_wait(adapter);
2557 if (!status) {
2558 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2559 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2560 CAPABILITY_BE3_NATIVE_ERX_API;
2561 if (!adapter->be3_native)
2562 dev_warn(&adapter->pdev->dev,
2563 "adapter not in advanced mode\n");
2564 }
2565 err:
2566 mutex_unlock(&adapter->mbox_lock);
2567 return status;
2568 }
2569
2570 /* Get privilege(s) for a function */
2571 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2572 u32 domain)
2573 {
2574 struct be_mcc_wrb *wrb;
2575 struct be_cmd_req_get_fn_privileges *req;
2576 int status;
2577
2578 spin_lock_bh(&adapter->mcc_lock);
2579
2580 wrb = wrb_from_mccq(adapter);
2581 if (!wrb) {
2582 status = -EBUSY;
2583 goto err;
2584 }
2585
2586 req = embedded_payload(wrb);
2587
2588 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2589 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2590 wrb, NULL);
2591
2592 req->hdr.domain = domain;
2593
2594 status = be_mcc_notify_wait(adapter);
2595 if (!status) {
2596 struct be_cmd_resp_get_fn_privileges *resp =
2597 embedded_payload(wrb);
2598 *privilege = le32_to_cpu(resp->privilege_mask);
2599 }
2600
2601 err:
2602 spin_unlock_bh(&adapter->mcc_lock);
2603 return status;
2604 }
2605
2606 /* Set privilege(s) for a function */
2607 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2608 u32 domain)
2609 {
2610 struct be_mcc_wrb *wrb;
2611 struct be_cmd_req_set_fn_privileges *req;
2612 int status;
2613
2614 spin_lock_bh(&adapter->mcc_lock);
2615
2616 wrb = wrb_from_mccq(adapter);
2617 if (!wrb) {
2618 status = -EBUSY;
2619 goto err;
2620 }
2621
2622 req = embedded_payload(wrb);
2623 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2624 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2625 wrb, NULL);
2626 req->hdr.domain = domain;
2627 if (lancer_chip(adapter))
2628 req->privileges_lancer = cpu_to_le32(privileges);
2629 else
2630 req->privileges = cpu_to_le32(privileges);
2631
2632 status = be_mcc_notify_wait(adapter);
2633 err:
2634 spin_unlock_bh(&adapter->mcc_lock);
2635 return status;
2636 }
2637
2638 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2639 * pmac_id_valid: false => pmac_id or MAC address is requested.
2640 * If pmac_id is returned, pmac_id_valid is returned as true
2641 */
2642 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2643 bool *pmac_id_valid, u32 *pmac_id, u8 domain)
2644 {
2645 struct be_mcc_wrb *wrb;
2646 struct be_cmd_req_get_mac_list *req;
2647 int status;
2648 int mac_count;
2649 struct be_dma_mem get_mac_list_cmd;
2650 int i;
2651
2652 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2653 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2654 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2655 get_mac_list_cmd.size,
2656 &get_mac_list_cmd.dma);
2657
2658 if (!get_mac_list_cmd.va) {
2659 dev_err(&adapter->pdev->dev,
2660 "Memory allocation failure during GET_MAC_LIST\n");
2661 return -ENOMEM;
2662 }
2663
2664 spin_lock_bh(&adapter->mcc_lock);
2665
2666 wrb = wrb_from_mccq(adapter);
2667 if (!wrb) {
2668 status = -EBUSY;
2669 goto out;
2670 }
2671
2672 req = get_mac_list_cmd.va;
2673
2674 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2675 OPCODE_COMMON_GET_MAC_LIST,
2676 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
2677 req->hdr.domain = domain;
2678 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2679 if (*pmac_id_valid) {
2680 req->mac_id = cpu_to_le32(*pmac_id);
2681 req->iface_id = cpu_to_le16(adapter->if_handle);
2682 req->perm_override = 0;
2683 } else {
2684 req->perm_override = 1;
2685 }
2686
2687 status = be_mcc_notify_wait(adapter);
2688 if (!status) {
2689 struct be_cmd_resp_get_mac_list *resp =
2690 get_mac_list_cmd.va;
2691
2692 if (*pmac_id_valid) {
2693 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
2694 ETH_ALEN);
2695 goto out;
2696 }
2697
2698 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2699 /* Mac list returned could contain one or more active mac_ids
2700 * or one or more true or pseudo permanant mac addresses.
2701 * If an active mac_id is present, return first active mac_id
2702 * found.
2703 */
2704 for (i = 0; i < mac_count; i++) {
2705 struct get_list_macaddr *mac_entry;
2706 u16 mac_addr_size;
2707 u32 mac_id;
2708
2709 mac_entry = &resp->macaddr_list[i];
2710 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2711 /* mac_id is a 32 bit value and mac_addr size
2712 * is 6 bytes
2713 */
2714 if (mac_addr_size == sizeof(u32)) {
2715 *pmac_id_valid = true;
2716 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2717 *pmac_id = le32_to_cpu(mac_id);
2718 goto out;
2719 }
2720 }
2721 /* If no active mac_id found, return first mac addr */
2722 *pmac_id_valid = false;
2723 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2724 ETH_ALEN);
2725 }
2726
2727 out:
2728 spin_unlock_bh(&adapter->mcc_lock);
2729 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2730 get_mac_list_cmd.va, get_mac_list_cmd.dma);
2731 return status;
2732 }
2733
2734 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id, u8 *mac)
2735 {
2736 bool active = true;
2737
2738 if (BEx_chip(adapter))
2739 return be_cmd_mac_addr_query(adapter, mac, false,
2740 adapter->if_handle, curr_pmac_id);
2741 else
2742 /* Fetch the MAC address using pmac_id */
2743 return be_cmd_get_mac_from_list(adapter, mac, &active,
2744 &curr_pmac_id, 0);
2745 }
2746
2747 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
2748 {
2749 int status;
2750 bool pmac_valid = false;
2751
2752 memset(mac, 0, ETH_ALEN);
2753
2754 if (BEx_chip(adapter)) {
2755 if (be_physfn(adapter))
2756 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
2757 0);
2758 else
2759 status = be_cmd_mac_addr_query(adapter, mac, false,
2760 adapter->if_handle, 0);
2761 } else {
2762 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
2763 NULL, 0);
2764 }
2765
2766 return status;
2767 }
2768
2769 /* Uses synchronous MCCQ */
2770 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2771 u8 mac_count, u32 domain)
2772 {
2773 struct be_mcc_wrb *wrb;
2774 struct be_cmd_req_set_mac_list *req;
2775 int status;
2776 struct be_dma_mem cmd;
2777
2778 memset(&cmd, 0, sizeof(struct be_dma_mem));
2779 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2780 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2781 &cmd.dma, GFP_KERNEL);
2782 if (!cmd.va)
2783 return -ENOMEM;
2784
2785 spin_lock_bh(&adapter->mcc_lock);
2786
2787 wrb = wrb_from_mccq(adapter);
2788 if (!wrb) {
2789 status = -EBUSY;
2790 goto err;
2791 }
2792
2793 req = cmd.va;
2794 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2795 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2796 wrb, &cmd);
2797
2798 req->hdr.domain = domain;
2799 req->mac_count = mac_count;
2800 if (mac_count)
2801 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2802
2803 status = be_mcc_notify_wait(adapter);
2804
2805 err:
2806 dma_free_coherent(&adapter->pdev->dev, cmd.size,
2807 cmd.va, cmd.dma);
2808 spin_unlock_bh(&adapter->mcc_lock);
2809 return status;
2810 }
2811
2812 /* Wrapper to delete any active MACs and provision the new mac.
2813 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
2814 * current list are active.
2815 */
2816 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
2817 {
2818 bool active_mac = false;
2819 u8 old_mac[ETH_ALEN];
2820 u32 pmac_id;
2821 int status;
2822
2823 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
2824 &pmac_id, dom);
2825 if (!status && active_mac)
2826 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
2827
2828 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
2829 }
2830
2831 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2832 u32 domain, u16 intf_id)
2833 {
2834 struct be_mcc_wrb *wrb;
2835 struct be_cmd_req_set_hsw_config *req;
2836 void *ctxt;
2837 int status;
2838
2839 spin_lock_bh(&adapter->mcc_lock);
2840
2841 wrb = wrb_from_mccq(adapter);
2842 if (!wrb) {
2843 status = -EBUSY;
2844 goto err;
2845 }
2846
2847 req = embedded_payload(wrb);
2848 ctxt = &req->context;
2849
2850 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2851 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2852
2853 req->hdr.domain = domain;
2854 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2855 if (pvid) {
2856 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2857 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2858 }
2859
2860 be_dws_cpu_to_le(req->context, sizeof(req->context));
2861 status = be_mcc_notify_wait(adapter);
2862
2863 err:
2864 spin_unlock_bh(&adapter->mcc_lock);
2865 return status;
2866 }
2867
2868 /* Get Hyper switch config */
2869 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2870 u32 domain, u16 intf_id)
2871 {
2872 struct be_mcc_wrb *wrb;
2873 struct be_cmd_req_get_hsw_config *req;
2874 void *ctxt;
2875 int status;
2876 u16 vid;
2877
2878 spin_lock_bh(&adapter->mcc_lock);
2879
2880 wrb = wrb_from_mccq(adapter);
2881 if (!wrb) {
2882 status = -EBUSY;
2883 goto err;
2884 }
2885
2886 req = embedded_payload(wrb);
2887 ctxt = &req->context;
2888
2889 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2890 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2891
2892 req->hdr.domain = domain;
2893 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2894 intf_id);
2895 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2896 be_dws_cpu_to_le(req->context, sizeof(req->context));
2897
2898 status = be_mcc_notify_wait(adapter);
2899 if (!status) {
2900 struct be_cmd_resp_get_hsw_config *resp =
2901 embedded_payload(wrb);
2902 be_dws_le_to_cpu(&resp->context,
2903 sizeof(resp->context));
2904 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2905 pvid, &resp->context);
2906 *pvid = le16_to_cpu(vid);
2907 }
2908
2909 err:
2910 spin_unlock_bh(&adapter->mcc_lock);
2911 return status;
2912 }
2913
2914 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2915 {
2916 struct be_mcc_wrb *wrb;
2917 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2918 int status;
2919 int payload_len = sizeof(*req);
2920 struct be_dma_mem cmd;
2921
2922 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2923 CMD_SUBSYSTEM_ETH))
2924 return -EPERM;
2925
2926 if (mutex_lock_interruptible(&adapter->mbox_lock))
2927 return -1;
2928
2929 memset(&cmd, 0, sizeof(struct be_dma_mem));
2930 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2931 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2932 &cmd.dma);
2933 if (!cmd.va) {
2934 dev_err(&adapter->pdev->dev,
2935 "Memory allocation failure\n");
2936 status = -ENOMEM;
2937 goto err;
2938 }
2939
2940 wrb = wrb_from_mbox(adapter);
2941 if (!wrb) {
2942 status = -EBUSY;
2943 goto err;
2944 }
2945
2946 req = cmd.va;
2947
2948 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2949 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2950 payload_len, wrb, &cmd);
2951
2952 req->hdr.version = 1;
2953 req->query_options = BE_GET_WOL_CAP;
2954
2955 status = be_mbox_notify_wait(adapter);
2956 if (!status) {
2957 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2958 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2959
2960 /* the command could succeed misleadingly on old f/w
2961 * which is not aware of the V1 version. fake an error. */
2962 if (resp->hdr.response_length < payload_len) {
2963 status = -1;
2964 goto err;
2965 }
2966 adapter->wol_cap = resp->wol_settings;
2967 }
2968 err:
2969 mutex_unlock(&adapter->mbox_lock);
2970 if (cmd.va)
2971 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2972 return status;
2973
2974 }
2975 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2976 struct be_dma_mem *cmd)
2977 {
2978 struct be_mcc_wrb *wrb;
2979 struct be_cmd_req_get_ext_fat_caps *req;
2980 int status;
2981
2982 if (mutex_lock_interruptible(&adapter->mbox_lock))
2983 return -1;
2984
2985 wrb = wrb_from_mbox(adapter);
2986 if (!wrb) {
2987 status = -EBUSY;
2988 goto err;
2989 }
2990
2991 req = cmd->va;
2992 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2993 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2994 cmd->size, wrb, cmd);
2995 req->parameter_type = cpu_to_le32(1);
2996
2997 status = be_mbox_notify_wait(adapter);
2998 err:
2999 mutex_unlock(&adapter->mbox_lock);
3000 return status;
3001 }
3002
3003 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3004 struct be_dma_mem *cmd,
3005 struct be_fat_conf_params *configs)
3006 {
3007 struct be_mcc_wrb *wrb;
3008 struct be_cmd_req_set_ext_fat_caps *req;
3009 int status;
3010
3011 spin_lock_bh(&adapter->mcc_lock);
3012
3013 wrb = wrb_from_mccq(adapter);
3014 if (!wrb) {
3015 status = -EBUSY;
3016 goto err;
3017 }
3018
3019 req = cmd->va;
3020 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3021 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3022 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3023 cmd->size, wrb, cmd);
3024
3025 status = be_mcc_notify_wait(adapter);
3026 err:
3027 spin_unlock_bh(&adapter->mcc_lock);
3028 return status;
3029 }
3030
3031 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
3032 {
3033 struct be_mcc_wrb *wrb;
3034 struct be_cmd_req_get_port_name *req;
3035 int status;
3036
3037 if (!lancer_chip(adapter)) {
3038 *port_name = adapter->hba_port_num + '0';
3039 return 0;
3040 }
3041
3042 spin_lock_bh(&adapter->mcc_lock);
3043
3044 wrb = wrb_from_mccq(adapter);
3045 if (!wrb) {
3046 status = -EBUSY;
3047 goto err;
3048 }
3049
3050 req = embedded_payload(wrb);
3051
3052 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3053 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3054 NULL);
3055 req->hdr.version = 1;
3056
3057 status = be_mcc_notify_wait(adapter);
3058 if (!status) {
3059 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3060 *port_name = resp->port_name[adapter->hba_port_num];
3061 } else {
3062 *port_name = adapter->hba_port_num + '0';
3063 }
3064 err:
3065 spin_unlock_bh(&adapter->mcc_lock);
3066 return status;
3067 }
3068
3069 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count)
3070 {
3071 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3072 int i;
3073
3074 for (i = 0; i < desc_count; i++) {
3075 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
3076 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1)
3077 return (struct be_nic_res_desc *)hdr;
3078
3079 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3080 hdr = (void *)hdr + hdr->desc_len;
3081 }
3082 return NULL;
3083 }
3084
3085 static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3086 u32 desc_count)
3087 {
3088 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3089 struct be_pcie_res_desc *pcie;
3090 int i;
3091
3092 for (i = 0; i < desc_count; i++) {
3093 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3094 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3095 pcie = (struct be_pcie_res_desc *)hdr;
3096 if (pcie->pf_num == devfn)
3097 return pcie;
3098 }
3099
3100 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3101 hdr = (void *)hdr + hdr->desc_len;
3102 }
3103 return NULL;
3104 }
3105
3106 /* Uses Mbox */
3107 int be_cmd_get_func_config(struct be_adapter *adapter)
3108 {
3109 struct be_mcc_wrb *wrb;
3110 struct be_cmd_req_get_func_config *req;
3111 int status;
3112 struct be_dma_mem cmd;
3113
3114 if (mutex_lock_interruptible(&adapter->mbox_lock))
3115 return -1;
3116
3117 memset(&cmd, 0, sizeof(struct be_dma_mem));
3118 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3119 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3120 &cmd.dma);
3121 if (!cmd.va) {
3122 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3123 status = -ENOMEM;
3124 goto err;
3125 }
3126
3127 wrb = wrb_from_mbox(adapter);
3128 if (!wrb) {
3129 status = -EBUSY;
3130 goto err;
3131 }
3132
3133 req = cmd.va;
3134
3135 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3136 OPCODE_COMMON_GET_FUNC_CONFIG,
3137 cmd.size, wrb, &cmd);
3138
3139 if (skyhawk_chip(adapter))
3140 req->hdr.version = 1;
3141
3142 status = be_mbox_notify_wait(adapter);
3143 if (!status) {
3144 struct be_cmd_resp_get_func_config *resp = cmd.va;
3145 u32 desc_count = le32_to_cpu(resp->desc_count);
3146 struct be_nic_res_desc *desc;
3147
3148 desc = be_get_nic_desc(resp->func_param, desc_count);
3149 if (!desc) {
3150 status = -EINVAL;
3151 goto err;
3152 }
3153
3154 adapter->pf_number = desc->pf_num;
3155 adapter->max_pmac_cnt = le16_to_cpu(desc->unicast_mac_count);
3156 adapter->max_vlans = le16_to_cpu(desc->vlan_count);
3157 adapter->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3158 adapter->max_tx_queues = le16_to_cpu(desc->txq_count);
3159 adapter->max_rss_queues = le16_to_cpu(desc->rssq_count);
3160 adapter->max_rx_queues = le16_to_cpu(desc->rq_count);
3161
3162 adapter->max_event_queues = le16_to_cpu(desc->eq_count);
3163 adapter->if_cap_flags = le32_to_cpu(desc->cap_flags);
3164
3165 /* Clear flags that driver is not interested in */
3166 adapter->if_cap_flags &= BE_IF_CAP_FLAGS_WANT;
3167 }
3168 err:
3169 mutex_unlock(&adapter->mbox_lock);
3170 if (cmd.va)
3171 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3172 return status;
3173 }
3174
3175 /* Uses mbox */
3176 static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3177 u8 domain, struct be_dma_mem *cmd)
3178 {
3179 struct be_mcc_wrb *wrb;
3180 struct be_cmd_req_get_profile_config *req;
3181 int status;
3182
3183 if (mutex_lock_interruptible(&adapter->mbox_lock))
3184 return -1;
3185 wrb = wrb_from_mbox(adapter);
3186
3187 req = cmd->va;
3188 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3189 OPCODE_COMMON_GET_PROFILE_CONFIG,
3190 cmd->size, wrb, cmd);
3191
3192 req->type = ACTIVE_PROFILE_TYPE;
3193 req->hdr.domain = domain;
3194 if (!lancer_chip(adapter))
3195 req->hdr.version = 1;
3196
3197 status = be_mbox_notify_wait(adapter);
3198
3199 mutex_unlock(&adapter->mbox_lock);
3200 return status;
3201 }
3202
3203 /* Uses sync mcc */
3204 static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3205 u8 domain, struct be_dma_mem *cmd)
3206 {
3207 struct be_mcc_wrb *wrb;
3208 struct be_cmd_req_get_profile_config *req;
3209 int status;
3210
3211 spin_lock_bh(&adapter->mcc_lock);
3212
3213 wrb = wrb_from_mccq(adapter);
3214 if (!wrb) {
3215 status = -EBUSY;
3216 goto err;
3217 }
3218
3219 req = cmd->va;
3220 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3221 OPCODE_COMMON_GET_PROFILE_CONFIG,
3222 cmd->size, wrb, cmd);
3223
3224 req->type = ACTIVE_PROFILE_TYPE;
3225 req->hdr.domain = domain;
3226 if (!lancer_chip(adapter))
3227 req->hdr.version = 1;
3228
3229 status = be_mcc_notify_wait(adapter);
3230
3231 err:
3232 spin_unlock_bh(&adapter->mcc_lock);
3233 return status;
3234 }
3235
3236 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3237 int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags,
3238 u16 *txq_count, u8 domain)
3239 {
3240 struct be_cmd_resp_get_profile_config *resp;
3241 struct be_pcie_res_desc *pcie;
3242 struct be_nic_res_desc *nic;
3243 struct be_queue_info *mccq = &adapter->mcc_obj.q;
3244 struct be_dma_mem cmd;
3245 u32 desc_count;
3246 int status;
3247
3248 memset(&cmd, 0, sizeof(struct be_dma_mem));
3249 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3250 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3251 if (!cmd.va)
3252 return -ENOMEM;
3253
3254 if (!mccq->created)
3255 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd);
3256 else
3257 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd);
3258 if (status)
3259 goto err;
3260
3261 resp = cmd.va;
3262 desc_count = le32_to_cpu(resp->desc_count);
3263
3264 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3265 desc_count);
3266 if (pcie)
3267 adapter->dev_num_vfs = le16_to_cpu(pcie->num_vfs);
3268
3269 nic = be_get_nic_desc(resp->func_param, desc_count);
3270 if (nic) {
3271 if (cap_flags)
3272 *cap_flags = le32_to_cpu(nic->cap_flags);
3273 if (txq_count)
3274 *txq_count = le16_to_cpu(nic->txq_count);
3275 }
3276 err:
3277 if (cmd.va)
3278 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3279 return status;
3280 }
3281
3282 /* Currently only Lancer uses this command and it supports version 0 only
3283 * Uses sync mcc
3284 */
3285 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
3286 u8 domain)
3287 {
3288 struct be_mcc_wrb *wrb;
3289 struct be_cmd_req_set_profile_config *req;
3290 int status;
3291
3292 spin_lock_bh(&adapter->mcc_lock);
3293
3294 wrb = wrb_from_mccq(adapter);
3295 if (!wrb) {
3296 status = -EBUSY;
3297 goto err;
3298 }
3299
3300 req = embedded_payload(wrb);
3301
3302 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3303 OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3304 wrb, NULL);
3305 req->hdr.domain = domain;
3306 req->desc_count = cpu_to_le32(1);
3307 req->nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3308 req->nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3309 req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV);
3310 req->nic_desc.pf_num = adapter->pf_number;
3311 req->nic_desc.vf_num = domain;
3312
3313 /* Mark fields invalid */
3314 req->nic_desc.unicast_mac_count = 0xFFFF;
3315 req->nic_desc.mcc_count = 0xFFFF;
3316 req->nic_desc.vlan_count = 0xFFFF;
3317 req->nic_desc.mcast_mac_count = 0xFFFF;
3318 req->nic_desc.txq_count = 0xFFFF;
3319 req->nic_desc.rq_count = 0xFFFF;
3320 req->nic_desc.rssq_count = 0xFFFF;
3321 req->nic_desc.lro_count = 0xFFFF;
3322 req->nic_desc.cq_count = 0xFFFF;
3323 req->nic_desc.toe_conn_count = 0xFFFF;
3324 req->nic_desc.eq_count = 0xFFFF;
3325 req->nic_desc.link_param = 0xFF;
3326 req->nic_desc.bw_min = 0xFFFFFFFF;
3327 req->nic_desc.acpi_params = 0xFF;
3328 req->nic_desc.wol_param = 0x0F;
3329
3330 /* Change BW */
3331 req->nic_desc.bw_min = cpu_to_le32(bps);
3332 req->nic_desc.bw_max = cpu_to_le32(bps);
3333 status = be_mcc_notify_wait(adapter);
3334 err:
3335 spin_unlock_bh(&adapter->mcc_lock);
3336 return status;
3337 }
3338
3339 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3340 int vf_num)
3341 {
3342 struct be_mcc_wrb *wrb;
3343 struct be_cmd_req_get_iface_list *req;
3344 struct be_cmd_resp_get_iface_list *resp;
3345 int status;
3346
3347 spin_lock_bh(&adapter->mcc_lock);
3348
3349 wrb = wrb_from_mccq(adapter);
3350 if (!wrb) {
3351 status = -EBUSY;
3352 goto err;
3353 }
3354 req = embedded_payload(wrb);
3355
3356 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3357 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3358 wrb, NULL);
3359 req->hdr.domain = vf_num + 1;
3360
3361 status = be_mcc_notify_wait(adapter);
3362 if (!status) {
3363 resp = (struct be_cmd_resp_get_iface_list *)req;
3364 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3365 }
3366
3367 err:
3368 spin_unlock_bh(&adapter->mcc_lock);
3369 return status;
3370 }
3371
3372 static int lancer_wait_idle(struct be_adapter *adapter)
3373 {
3374 #define SLIPORT_IDLE_TIMEOUT 30
3375 u32 reg_val;
3376 int status = 0, i;
3377
3378 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3379 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3380 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3381 break;
3382
3383 ssleep(1);
3384 }
3385
3386 if (i == SLIPORT_IDLE_TIMEOUT)
3387 status = -1;
3388
3389 return status;
3390 }
3391
3392 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
3393 {
3394 int status = 0;
3395
3396 status = lancer_wait_idle(adapter);
3397 if (status)
3398 return status;
3399
3400 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
3401
3402 return status;
3403 }
3404
3405 /* Routine to check whether dump image is present or not */
3406 bool dump_present(struct be_adapter *adapter)
3407 {
3408 u32 sliport_status = 0;
3409
3410 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3411 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
3412 }
3413
3414 int lancer_initiate_dump(struct be_adapter *adapter)
3415 {
3416 int status;
3417
3418 /* give firmware reset and diagnostic dump */
3419 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
3420 PHYSDEV_CONTROL_DD_MASK);
3421 if (status < 0) {
3422 dev_err(&adapter->pdev->dev, "Firmware reset failed\n");
3423 return status;
3424 }
3425
3426 status = lancer_wait_idle(adapter);
3427 if (status)
3428 return status;
3429
3430 if (!dump_present(adapter)) {
3431 dev_err(&adapter->pdev->dev, "Dump image not present\n");
3432 return -1;
3433 }
3434
3435 return 0;
3436 }
3437
3438 /* Uses sync mcc */
3439 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3440 {
3441 struct be_mcc_wrb *wrb;
3442 struct be_cmd_enable_disable_vf *req;
3443 int status;
3444
3445 if (!lancer_chip(adapter))
3446 return 0;
3447
3448 spin_lock_bh(&adapter->mcc_lock);
3449
3450 wrb = wrb_from_mccq(adapter);
3451 if (!wrb) {
3452 status = -EBUSY;
3453 goto err;
3454 }
3455
3456 req = embedded_payload(wrb);
3457
3458 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3459 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3460 wrb, NULL);
3461
3462 req->hdr.domain = domain;
3463 req->enable = 1;
3464 status = be_mcc_notify_wait(adapter);
3465 err:
3466 spin_unlock_bh(&adapter->mcc_lock);
3467 return status;
3468 }
3469
3470 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3471 {
3472 struct be_mcc_wrb *wrb;
3473 struct be_cmd_req_intr_set *req;
3474 int status;
3475
3476 if (mutex_lock_interruptible(&adapter->mbox_lock))
3477 return -1;
3478
3479 wrb = wrb_from_mbox(adapter);
3480
3481 req = embedded_payload(wrb);
3482
3483 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3484 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3485 wrb, NULL);
3486
3487 req->intr_enabled = intr_enable;
3488
3489 status = be_mbox_notify_wait(adapter);
3490
3491 mutex_unlock(&adapter->mbox_lock);
3492 return status;
3493 }
3494
3495 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3496 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3497 {
3498 struct be_adapter *adapter = netdev_priv(netdev_handle);
3499 struct be_mcc_wrb *wrb;
3500 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3501 struct be_cmd_req_hdr *req;
3502 struct be_cmd_resp_hdr *resp;
3503 int status;
3504
3505 spin_lock_bh(&adapter->mcc_lock);
3506
3507 wrb = wrb_from_mccq(adapter);
3508 if (!wrb) {
3509 status = -EBUSY;
3510 goto err;
3511 }
3512 req = embedded_payload(wrb);
3513 resp = embedded_payload(wrb);
3514
3515 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3516 hdr->opcode, wrb_payload_size, wrb, NULL);
3517 memcpy(req, wrb_payload, wrb_payload_size);
3518 be_dws_cpu_to_le(req, wrb_payload_size);
3519
3520 status = be_mcc_notify_wait(adapter);
3521 if (cmd_status)
3522 *cmd_status = (status & 0xffff);
3523 if (ext_status)
3524 *ext_status = 0;
3525 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3526 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3527 err:
3528 spin_unlock_bh(&adapter->mcc_lock);
3529 return status;
3530 }
3531 EXPORT_SYMBOL(be_roce_mcc_cmd);
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