?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
iwlwifi: pcie: alloc queues dynamically
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
blobed1034e58cb42a4fba91de33732b06fdf69b9562
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
27 * in the file called COPYING.
28 *
29 * Contact Information:
30 * Intel Linux Wireless <linuxwifi@intel.com>
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
67 #include <linux/pci.h>
68 #include <linux/pci-aspm.h>
69 #include <linux/interrupt.h>
70 #include <linux/debugfs.h>
71 #include <linux/sched.h>
72 #include <linux/bitops.h>
73 #include <linux/gfp.h>
74 #include <linux/vmalloc.h>
75 #include <linux/pm_runtime.h>
76
77 #include "iwl-drv.h"
78 #include "iwl-trans.h"
79 #include "iwl-csr.h"
80 #include "iwl-prph.h"
81 #include "iwl-scd.h"
82 #include "iwl-agn-hw.h"
83 #include "iwl-fw-error-dump.h"
84 #include "internal.h"
85 #include "iwl-fh.h"
86
87 /* extended range in FW SRAM */
88 #define IWL_FW_MEM_EXTENDED_START 0x40000
89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
92 {
93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
94
95 if (!trans_pcie->fw_mon_page)
96 return;
97
98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
100 __free_pages(trans_pcie->fw_mon_page,
101 get_order(trans_pcie->fw_mon_size));
102 trans_pcie->fw_mon_page = NULL;
103 trans_pcie->fw_mon_phys = 0;
104 trans_pcie->fw_mon_size = 0;
105 }
106
107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
108 {
109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
110 struct page *page = NULL;
111 dma_addr_t phys;
112 u32 size = 0;
113 u8 power;
114
115 if (!max_power) {
116 /* default max_power is maximum */
117 max_power = 26;
118 } else {
119 max_power += 11;
120 }
121
122 if (WARN(max_power > 26,
123 "External buffer size for monitor is too big %d, check the FW TLV\n",
124 max_power))
125 return;
126
127 if (trans_pcie->fw_mon_page) {
128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
129 trans_pcie->fw_mon_size,
130 DMA_FROM_DEVICE);
131 return;
132 }
133
134 phys = 0;
135 for (power = max_power; power >= 11; power--) {
136 int order;
137
138 size = BIT(power);
139 order = get_order(size);
140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
141 order);
142 if (!page)
143 continue;
144
145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
146 DMA_FROM_DEVICE);
147 if (dma_mapping_error(trans->dev, phys)) {
148 __free_pages(page, order);
149 page = NULL;
150 continue;
151 }
152 IWL_INFO(trans,
153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
154 size, order);
155 break;
156 }
157
158 if (WARN_ON_ONCE(!page))
159 return;
160
161 if (power != max_power)
162 IWL_ERR(trans,
163 "Sorry - debug buffer is only %luK while you requested %luK\n",
164 (unsigned long)BIT(power - 10),
165 (unsigned long)BIT(max_power - 10));
166
167 trans_pcie->fw_mon_page = page;
168 trans_pcie->fw_mon_phys = phys;
169 trans_pcie->fw_mon_size = size;
170 }
171
172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
173 {
174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
175 ((reg & 0x0000ffff) | (2 << 28)));
176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
177 }
178
179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
180 {
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
183 ((reg & 0x0000ffff) | (3 << 28)));
184 }
185
186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
187 {
188 if (trans->cfg->apmg_not_supported)
189 return;
190
191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
195 else
196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
198 ~APMG_PS_CTRL_MSK_PWR_SRC);
199 }
200
201 /* PCI registers */
202 #define PCI_CFG_RETRY_TIMEOUT 0x041
203
204 void iwl_pcie_apm_config(struct iwl_trans *trans)
205 {
206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
207 u16 lctl;
208 u16 cap;
209
210 /*
211 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
213 * If so (likely), disable L0S, so device moves directly L0->L1;
214 * costs negligible amount of power savings.
215 * If not (unlikely), enable L0S, so there is at least some
216 * power savings, even without L1.
217 */
218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
221 else
222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
224
225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
229 trans->ltr_enabled ? "En" : "Dis");
230 }
231
232 /*
233 * Start up NIC's basic functionality after it has been reset
234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
235 * NOTE: This does not load uCode nor start the embedded processor
236 */
237 static int iwl_pcie_apm_init(struct iwl_trans *trans)
238 {
239 int ret = 0;
240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
241
242 /*
243 * Use "set_bit" below rather than "write", to preserve any hardware
244 * bits already set by default after reset.
245 */
246
247 /* Disable L0S exit timer (platform NMI Work/Around) */
248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
251
252 /*
253 * Disable L0s without affecting L1;
254 * don't wait for ICH L0s (ICH bug W/A)
255 */
256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
258
259 /* Set FH wait threshold to maximum (HW error during stress W/A) */
260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
261
262 /*
263 * Enable HAP INTA (interrupt from management bus) to
264 * wake device's PCI Express link L1a -> L0s
265 */
266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
268
269 iwl_pcie_apm_config(trans);
270
271 /* Configure analog phase-lock-loop before activating to D0A */
272 if (trans->cfg->base_params->pll_cfg)
273 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
274
275 /*
276 * Set "initialization complete" bit to move adapter from
277 * D0U* --> D0A* (powered-up active) state.
278 */
279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
280
281 /*
282 * Wait for clock stabilization; once stabilized, access to
283 * device-internal resources is supported, e.g. iwl_write_prph()
284 * and accesses to uCode SRAM.
285 */
286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
289 if (ret < 0) {
290 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
291 goto out;
292 }
293
294 if (trans->cfg->host_interrupt_operation_mode) {
295 /*
296 * This is a bit of an abuse - This is needed for 7260 / 3160
297 * only check host_interrupt_operation_mode even if this is
298 * not related to host_interrupt_operation_mode.
299 *
300 * Enable the oscillator to count wake up time for L1 exit. This
301 * consumes slightly more power (100uA) - but allows to be sure
302 * that we wake up from L1 on time.
303 *
304 * This looks weird: read twice the same register, discard the
305 * value, set a bit, and yet again, read that same register
306 * just to discard the value. But that's the way the hardware
307 * seems to like it.
308 */
309 iwl_read_prph(trans, OSC_CLK);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
312 iwl_read_prph(trans, OSC_CLK);
313 iwl_read_prph(trans, OSC_CLK);
314 }
315
316 /*
317 * Enable DMA clock and wait for it to stabilize.
318 *
319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
320 * bits do not disable clocks. This preserves any hardware
321 * bits already set by default in "CLK_CTRL_REG" after reset.
322 */
323 if (!trans->cfg->apmg_not_supported) {
324 iwl_write_prph(trans, APMG_CLK_EN_REG,
325 APMG_CLK_VAL_DMA_CLK_RQT);
326 udelay(20);
327
328 /* Disable L1-Active */
329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
331
332 /* Clear the interrupt in APMG if the NIC is in RFKILL */
333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
334 APMG_RTC_INT_STT_RFKILL);
335 }
336
337 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
338
339 out:
340 return ret;
341 }
342
343 /*
344 * Enable LP XTAL to avoid HW bug where device may consume much power if
345 * FW is not loaded after device reset. LP XTAL is disabled by default
346 * after device HW reset. Do it only if XTAL is fed by internal source.
347 * Configure device's "persistence" mode to avoid resetting XTAL again when
348 * SHRD_HW_RST occurs in S3.
349 */
350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
351 {
352 int ret;
353 u32 apmg_gp1_reg;
354 u32 apmg_xtal_cfg_reg;
355 u32 dl_cfg_reg;
356
357 /* Force XTAL ON */
358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360
361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
363 usleep_range(1000, 2000);
364
365 /*
366 * Set "initialization complete" bit to move adapter from
367 * D0U* --> D0A* (powered-up active) state.
368 */
369 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
370
371 /*
372 * Wait for clock stabilization; once stabilized, access to
373 * device-internal resources is possible.
374 */
375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
378 25000);
379 if (WARN_ON(ret < 0)) {
380 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
381 /* Release XTAL ON request */
382 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
383 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
384 return;
385 }
386
387 /*
388 * Clear "disable persistence" to avoid LP XTAL resetting when
389 * SHRD_HW_RST is applied in S3.
390 */
391 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
392 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
393
394 /*
395 * Force APMG XTAL to be active to prevent its disabling by HW
396 * caused by APMG idle state.
397 */
398 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
399 SHR_APMG_XTAL_CFG_REG);
400 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
401 apmg_xtal_cfg_reg |
402 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
403
404 /*
405 * Reset entire device again - do controller reset (results in
406 * SHRD_HW_RST). Turn MAC off before proceeding.
407 */
408 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
409 usleep_range(1000, 2000);
410
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
416
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
421
422 /*
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
425 */
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
428
429 /*
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
432 */
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
435
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
439
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
443 udelay(10);
444
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
447 apmg_xtal_cfg_reg &
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
449 }
450
451 int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
452 {
453 int ret = 0;
454
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
457
458 ret = iwl_poll_bit(trans, CSR_RESET,
459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
461 if (ret < 0)
462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
463
464 IWL_DEBUG_INFO(trans, "stop master\n");
465
466 return ret;
467 }
468
469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
470 {
471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
472
473 if (op_mode_leave) {
474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
475 iwl_pcie_apm_init(trans);
476
477 /* inform ME that we are leaving */
478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
480 APMG_PCIDEV_STT_VAL_WAKE_ME);
481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
482 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
483 CSR_RESET_LINK_PWR_MGMT_DISABLED);
484 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
485 CSR_HW_IF_CONFIG_REG_PREPARE |
486 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
487 mdelay(1);
488 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
489 CSR_RESET_LINK_PWR_MGMT_DISABLED);
490 }
491 mdelay(5);
492 }
493
494 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
495
496 /* Stop device's DMA activity */
497 iwl_pcie_apm_stop_master(trans);
498
499 if (trans->cfg->lp_xtal_workaround) {
500 iwl_pcie_apm_lp_xtal_enable(trans);
501 return;
502 }
503
504 /* Reset the entire device */
505 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
506 usleep_range(1000, 2000);
507
508 /*
509 * Clear "initialization complete" bit to move adapter from
510 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
511 */
512 iwl_clear_bit(trans, CSR_GP_CNTRL,
513 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
514 }
515
516 static int iwl_pcie_nic_init(struct iwl_trans *trans)
517 {
518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
519
520 /* nic_init */
521 spin_lock(&trans_pcie->irq_lock);
522 iwl_pcie_apm_init(trans);
523
524 spin_unlock(&trans_pcie->irq_lock);
525
526 iwl_pcie_set_pwr(trans, false);
527
528 iwl_op_mode_nic_config(trans->op_mode);
529
530 /* Allocate the RX queue, or reset if it is already allocated */
531 iwl_pcie_rx_init(trans);
532
533 /* Allocate or reset and init all Tx and Command queues */
534 if (iwl_pcie_tx_init(trans))
535 return -ENOMEM;
536
537 if (trans->cfg->base_params->shadow_reg_enable) {
538 /* enable shadow regs in HW */
539 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
540 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
541 }
542
543 return 0;
544 }
545
546 #define HW_READY_TIMEOUT (50)
547
548 /* Note: returns poll_bit return value, which is >= 0 if success */
549 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
550 {
551 int ret;
552
553 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
555
556 /* See if we got it */
557 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
559 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
560 HW_READY_TIMEOUT);
561
562 if (ret >= 0)
563 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
564
565 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
566 return ret;
567 }
568
569 /* Note: returns standard 0/-ERROR code */
570 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
571 {
572 int ret;
573 int t = 0;
574 int iter;
575
576 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
577
578 ret = iwl_pcie_set_hw_ready(trans);
579 /* If the card is ready, exit 0 */
580 if (ret >= 0)
581 return 0;
582
583 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
584 CSR_RESET_LINK_PWR_MGMT_DISABLED);
585 usleep_range(1000, 2000);
586
587 for (iter = 0; iter < 10; iter++) {
588 /* If HW is not ready, prepare the conditions to check again */
589 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
590 CSR_HW_IF_CONFIG_REG_PREPARE);
591
592 do {
593 ret = iwl_pcie_set_hw_ready(trans);
594 if (ret >= 0)
595 return 0;
596
597 usleep_range(200, 1000);
598 t += 200;
599 } while (t < 150000);
600 msleep(25);
601 }
602
603 IWL_ERR(trans, "Couldn't prepare the card\n");
604
605 return ret;
606 }
607
608 /*
609 * ucode
610 */
611 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
612 u32 dst_addr, dma_addr_t phy_addr,
613 u32 byte_cnt)
614 {
615 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
616 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
617
618 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
619 dst_addr);
620
621 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
622 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
623
624 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
625 (iwl_get_dma_hi_addr(phy_addr)
626 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
627
628 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
629 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
630 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
632
633 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
634 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
636 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
637 }
638
639 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
640 u32 dst_addr, dma_addr_t phy_addr,
641 u32 byte_cnt)
642 {
643 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
644 unsigned long flags;
645 int ret;
646
647 trans_pcie->ucode_write_complete = false;
648
649 if (!iwl_trans_grab_nic_access(trans, &flags))
650 return -EIO;
651
652 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
653 byte_cnt);
654 iwl_trans_release_nic_access(trans, &flags);
655
656 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
657 trans_pcie->ucode_write_complete, 5 * HZ);
658 if (!ret) {
659 IWL_ERR(trans, "Failed to load firmware chunk!\n");
660 return -ETIMEDOUT;
661 }
662
663 return 0;
664 }
665
666 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
667 const struct fw_desc *section)
668 {
669 u8 *v_addr;
670 dma_addr_t p_addr;
671 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
672 int ret = 0;
673
674 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
675 section_num);
676
677 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
678 GFP_KERNEL | __GFP_NOWARN);
679 if (!v_addr) {
680 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
681 chunk_sz = PAGE_SIZE;
682 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
683 &p_addr, GFP_KERNEL);
684 if (!v_addr)
685 return -ENOMEM;
686 }
687
688 for (offset = 0; offset < section->len; offset += chunk_sz) {
689 u32 copy_size, dst_addr;
690 bool extended_addr = false;
691
692 copy_size = min_t(u32, chunk_sz, section->len - offset);
693 dst_addr = section->offset + offset;
694
695 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
696 dst_addr <= IWL_FW_MEM_EXTENDED_END)
697 extended_addr = true;
698
699 if (extended_addr)
700 iwl_set_bits_prph(trans, LMPM_CHICK,
701 LMPM_CHICK_EXTENDED_ADDR_SPACE);
702
703 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
704 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
705 copy_size);
706
707 if (extended_addr)
708 iwl_clear_bits_prph(trans, LMPM_CHICK,
709 LMPM_CHICK_EXTENDED_ADDR_SPACE);
710
711 if (ret) {
712 IWL_ERR(trans,
713 "Could not load the [%d] uCode section\n",
714 section_num);
715 break;
716 }
717 }
718
719 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
720 return ret;
721 }
722
723 /*
724 * Driver Takes the ownership on secure machine before FW load
725 * and prevent race with the BT load.
726 * W/A for ROM bug. (should be remove in the next Si step)
727 */
728 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
729 {
730 u32 val, loop = 1000;
731
732 /*
733 * Check the RSA semaphore is accessible.
734 * If the HW isn't locked and the rsa semaphore isn't accessible,
735 * we are in trouble.
736 */
737 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
738 if (val & (BIT(1) | BIT(17))) {
739 IWL_DEBUG_INFO(trans,
740 "can't access the RSA semaphore it is write protected\n");
741 return 0;
742 }
743
744 /* take ownership on the AUX IF */
745 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
746 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
747
748 do {
749 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
750 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
751 if (val == 0x1) {
752 iwl_write_prph(trans, RSA_ENABLE, 0);
753 return 0;
754 }
755
756 udelay(10);
757 loop--;
758 } while (loop > 0);
759
760 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
761 return -EIO;
762 }
763
764 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
765 const struct fw_img *image,
766 int cpu,
767 int *first_ucode_section)
768 {
769 int shift_param;
770 int i, ret = 0, sec_num = 0x1;
771 u32 val, last_read_idx = 0;
772
773 if (cpu == 1) {
774 shift_param = 0;
775 *first_ucode_section = 0;
776 } else {
777 shift_param = 16;
778 (*first_ucode_section)++;
779 }
780
781 for (i = *first_ucode_section; i < image->num_sec; i++) {
782 last_read_idx = i;
783
784 /*
785 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
786 * CPU1 to CPU2.
787 * PAGING_SEPARATOR_SECTION delimiter - separate between
788 * CPU2 non paged to CPU2 paging sec.
789 */
790 if (!image->sec[i].data ||
791 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
792 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
793 IWL_DEBUG_FW(trans,
794 "Break since Data not valid or Empty section, sec = %d\n",
795 i);
796 break;
797 }
798
799 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
800 if (ret)
801 return ret;
802
803 /* Notify ucode of loaded section number and status */
804 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
805 val = val | (sec_num << shift_param);
806 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
807
808 sec_num = (sec_num << 1) | 0x1;
809 }
810
811 *first_ucode_section = last_read_idx;
812
813 iwl_enable_interrupts(trans);
814
815 if (trans->cfg->use_tfh) {
816 if (cpu == 1)
817 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
818 0xFFFF);
819 else
820 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
821 0xFFFFFFFF);
822 } else {
823 if (cpu == 1)
824 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
825 0xFFFF);
826 else
827 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
828 0xFFFFFFFF);
829 }
830
831 return 0;
832 }
833
834 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
835 const struct fw_img *image,
836 int cpu,
837 int *first_ucode_section)
838 {
839 int i, ret = 0;
840 u32 last_read_idx = 0;
841
842 if (cpu == 1)
843 *first_ucode_section = 0;
844 else
845 (*first_ucode_section)++;
846
847 for (i = *first_ucode_section; i < image->num_sec; i++) {
848 last_read_idx = i;
849
850 /*
851 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
852 * CPU1 to CPU2.
853 * PAGING_SEPARATOR_SECTION delimiter - separate between
854 * CPU2 non paged to CPU2 paging sec.
855 */
856 if (!image->sec[i].data ||
857 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
858 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
859 IWL_DEBUG_FW(trans,
860 "Break since Data not valid or Empty section, sec = %d\n",
861 i);
862 break;
863 }
864
865 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
866 if (ret)
867 return ret;
868 }
869
870 *first_ucode_section = last_read_idx;
871
872 return 0;
873 }
874
875 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
876 {
877 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
878 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
879 int i;
880
881 if (dest->version)
882 IWL_ERR(trans,
883 "DBG DEST version is %d - expect issues\n",
884 dest->version);
885
886 IWL_INFO(trans, "Applying debug destination %s\n",
887 get_fw_dbg_mode_string(dest->monitor_mode));
888
889 if (dest->monitor_mode == EXTERNAL_MODE)
890 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
891 else
892 IWL_WARN(trans, "PCI should have external buffer debug\n");
893
894 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
895 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
896 u32 val = le32_to_cpu(dest->reg_ops[i].val);
897
898 switch (dest->reg_ops[i].op) {
899 case CSR_ASSIGN:
900 iwl_write32(trans, addr, val);
901 break;
902 case CSR_SETBIT:
903 iwl_set_bit(trans, addr, BIT(val));
904 break;
905 case CSR_CLEARBIT:
906 iwl_clear_bit(trans, addr, BIT(val));
907 break;
908 case PRPH_ASSIGN:
909 iwl_write_prph(trans, addr, val);
910 break;
911 case PRPH_SETBIT:
912 iwl_set_bits_prph(trans, addr, BIT(val));
913 break;
914 case PRPH_CLEARBIT:
915 iwl_clear_bits_prph(trans, addr, BIT(val));
916 break;
917 case PRPH_BLOCKBIT:
918 if (iwl_read_prph(trans, addr) & BIT(val)) {
919 IWL_ERR(trans,
920 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
921 val, addr);
922 goto monitor;
923 }
924 break;
925 default:
926 IWL_ERR(trans, "FW debug - unknown OP %d\n",
927 dest->reg_ops[i].op);
928 break;
929 }
930 }
931
932 monitor:
933 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
934 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
935 trans_pcie->fw_mon_phys >> dest->base_shift);
936 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
937 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
938 (trans_pcie->fw_mon_phys +
939 trans_pcie->fw_mon_size - 256) >>
940 dest->end_shift);
941 else
942 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
943 (trans_pcie->fw_mon_phys +
944 trans_pcie->fw_mon_size) >>
945 dest->end_shift);
946 }
947 }
948
949 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
950 const struct fw_img *image)
951 {
952 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
953 int ret = 0;
954 int first_ucode_section;
955
956 IWL_DEBUG_FW(trans, "working with %s CPU\n",
957 image->is_dual_cpus ? "Dual" : "Single");
958
959 /* load to FW the binary non secured sections of CPU1 */
960 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
961 if (ret)
962 return ret;
963
964 if (image->is_dual_cpus) {
965 /* set CPU2 header address */
966 iwl_write_prph(trans,
967 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
968 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
969
970 /* load to FW the binary sections of CPU2 */
971 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
972 &first_ucode_section);
973 if (ret)
974 return ret;
975 }
976
977 /* supported for 7000 only for the moment */
978 if (iwlwifi_mod_params.fw_monitor &&
979 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
980 iwl_pcie_alloc_fw_monitor(trans, 0);
981
982 if (trans_pcie->fw_mon_size) {
983 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
984 trans_pcie->fw_mon_phys >> 4);
985 iwl_write_prph(trans, MON_BUFF_END_ADDR,
986 (trans_pcie->fw_mon_phys +
987 trans_pcie->fw_mon_size) >> 4);
988 }
989 } else if (trans->dbg_dest_tlv) {
990 iwl_pcie_apply_destination(trans);
991 }
992
993 iwl_enable_interrupts(trans);
994
995 /* release CPU reset */
996 iwl_write32(trans, CSR_RESET, 0);
997
998 return 0;
999 }
1000
1001 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1002 const struct fw_img *image)
1003 {
1004 int ret = 0;
1005 int first_ucode_section;
1006
1007 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1008 image->is_dual_cpus ? "Dual" : "Single");
1009
1010 if (trans->dbg_dest_tlv)
1011 iwl_pcie_apply_destination(trans);
1012
1013 /* TODO: remove in the next Si step */
1014 ret = iwl_pcie_rsa_race_bug_wa(trans);
1015 if (ret)
1016 return ret;
1017
1018 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1019 iwl_read_prph(trans, WFPM_GP2));
1020
1021 /*
1022 * Set default value. On resume reading the values that were
1023 * zeored can provide debug data on the resume flow.
1024 * This is for debugging only and has no functional impact.
1025 */
1026 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1027
1028 /* configure the ucode to be ready to get the secured image */
1029 /* release CPU reset */
1030 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1031
1032 /* load to FW the binary Secured sections of CPU1 */
1033 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1034 &first_ucode_section);
1035 if (ret)
1036 return ret;
1037
1038 /* load to FW the binary sections of CPU2 */
1039 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1040 &first_ucode_section);
1041 }
1042
1043 bool iwl_trans_check_hw_rf_kill(struct iwl_trans *trans)
1044 {
1045 bool hw_rfkill = iwl_is_rfkill_set(trans);
1046
1047 if (hw_rfkill)
1048 set_bit(STATUS_RFKILL, &trans->status);
1049 else
1050 clear_bit(STATUS_RFKILL, &trans->status);
1051
1052 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1053
1054 return hw_rfkill;
1055 }
1056
1057 struct iwl_causes_list {
1058 u32 cause_num;
1059 u32 mask_reg;
1060 u8 addr;
1061 };
1062
1063 static struct iwl_causes_list causes_list[] = {
1064 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1065 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1066 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1067 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1068 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1069 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1070 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1071 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1072 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1073 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1074 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1075 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1076 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1077 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1078 };
1079
1080 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1081 {
1082 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1083 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1084 int i;
1085
1086 /*
1087 * Access all non RX causes and map them to the default irq.
1088 * In case we are missing at least one interrupt vector,
1089 * the first interrupt vector will serve non-RX and FBQ causes.
1090 */
1091 for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1092 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1093 iwl_clear_bit(trans, causes_list[i].mask_reg,
1094 causes_list[i].cause_num);
1095 }
1096 }
1097
1098 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1099 {
1100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1101 u32 offset =
1102 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1103 u32 val, idx;
1104
1105 /*
1106 * The first RX queue - fallback queue, which is designated for
1107 * management frame, command responses etc, is always mapped to the
1108 * first interrupt vector. The other RX queues are mapped to
1109 * the other (N - 2) interrupt vectors.
1110 */
1111 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1112 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1113 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1114 MSIX_FH_INT_CAUSES_Q(idx - offset));
1115 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1116 }
1117 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1118
1119 val = MSIX_FH_INT_CAUSES_Q(0);
1120 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1121 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1122 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1123
1124 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1125 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1126 }
1127
1128 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1129 {
1130 struct iwl_trans *trans = trans_pcie->trans;
1131
1132 if (!trans_pcie->msix_enabled) {
1133 if (trans->cfg->mq_rx_supported &&
1134 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1135 iwl_write_prph(trans, UREG_CHICK,
1136 UREG_CHICK_MSI_ENABLE);
1137 return;
1138 }
1139 /*
1140 * The IVAR table needs to be configured again after reset,
1141 * but if the device is disabled, we can't write to
1142 * prph.
1143 */
1144 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1145 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1146
1147 /*
1148 * Each cause from the causes list above and the RX causes is
1149 * represented as a byte in the IVAR table. The first nibble
1150 * represents the bound interrupt vector of the cause, the second
1151 * represents no auto clear for this cause. This will be set if its
1152 * interrupt vector is bound to serve other causes.
1153 */
1154 iwl_pcie_map_rx_causes(trans);
1155
1156 iwl_pcie_map_non_rx_causes(trans);
1157 }
1158
1159 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1160 {
1161 struct iwl_trans *trans = trans_pcie->trans;
1162
1163 iwl_pcie_conf_msix_hw(trans_pcie);
1164
1165 if (!trans_pcie->msix_enabled)
1166 return;
1167
1168 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1169 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1170 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1171 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1172 }
1173
1174 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1175 {
1176 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1177 bool hw_rfkill, was_hw_rfkill;
1178
1179 lockdep_assert_held(&trans_pcie->mutex);
1180
1181 if (trans_pcie->is_down)
1182 return;
1183
1184 trans_pcie->is_down = true;
1185
1186 was_hw_rfkill = iwl_is_rfkill_set(trans);
1187
1188 /* tell the device to stop sending interrupts */
1189 iwl_disable_interrupts(trans);
1190
1191 /* device going down, Stop using ICT table */
1192 iwl_pcie_disable_ict(trans);
1193
1194 /*
1195 * If a HW restart happens during firmware loading,
1196 * then the firmware loading might call this function
1197 * and later it might be called again due to the
1198 * restart. So don't process again if the device is
1199 * already dead.
1200 */
1201 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1202 IWL_DEBUG_INFO(trans,
1203 "DEVICE_ENABLED bit was set and is now cleared\n");
1204 iwl_pcie_tx_stop(trans);
1205 iwl_pcie_rx_stop(trans);
1206
1207 /* Power-down device's busmaster DMA clocks */
1208 if (!trans->cfg->apmg_not_supported) {
1209 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1210 APMG_CLK_VAL_DMA_CLK_RQT);
1211 udelay(5);
1212 }
1213 }
1214
1215 /* Make sure (redundant) we've released our request to stay awake */
1216 iwl_clear_bit(trans, CSR_GP_CNTRL,
1217 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1218
1219 /* Stop the device, and put it in low power state */
1220 iwl_pcie_apm_stop(trans, false);
1221
1222 /* stop and reset the on-board processor */
1223 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1224 usleep_range(1000, 2000);
1225
1226 /*
1227 * Upon stop, the IVAR table gets erased, so msi-x won't
1228 * work. This causes a bug in RF-KILL flows, since the interrupt
1229 * that enables radio won't fire on the correct irq, and the
1230 * driver won't be able to handle the interrupt.
1231 * Configure the IVAR table again after reset.
1232 */
1233 iwl_pcie_conf_msix_hw(trans_pcie);
1234
1235 /*
1236 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1237 * This is a bug in certain verions of the hardware.
1238 * Certain devices also keep sending HW RF kill interrupt all
1239 * the time, unless the interrupt is ACKed even if the interrupt
1240 * should be masked. Re-ACK all the interrupts here.
1241 */
1242 iwl_disable_interrupts(trans);
1243
1244 /* clear all status bits */
1245 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1246 clear_bit(STATUS_INT_ENABLED, &trans->status);
1247 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1248 clear_bit(STATUS_RFKILL, &trans->status);
1249
1250 /*
1251 * Even if we stop the HW, we still want the RF kill
1252 * interrupt
1253 */
1254 iwl_enable_rfkill_int(trans);
1255
1256 /*
1257 * Check again since the RF kill state may have changed while
1258 * all the interrupts were disabled, in this case we couldn't
1259 * receive the RF kill interrupt and update the state in the
1260 * op_mode.
1261 * Don't call the op_mode if the rkfill state hasn't changed.
1262 * This allows the op_mode to call stop_device from the rfkill
1263 * notification without endless recursion. Under very rare
1264 * circumstances, we might have a small recursion if the rfkill
1265 * state changed exactly now while we were called from stop_device.
1266 * This is very unlikely but can happen and is supported.
1267 */
1268 hw_rfkill = iwl_is_rfkill_set(trans);
1269 if (hw_rfkill)
1270 set_bit(STATUS_RFKILL, &trans->status);
1271 else
1272 clear_bit(STATUS_RFKILL, &trans->status);
1273 if (hw_rfkill != was_hw_rfkill)
1274 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1275
1276 /* re-take ownership to prevent other users from stealing the device */
1277 iwl_pcie_prepare_card_hw(trans);
1278 }
1279
1280 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1281 {
1282 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1283
1284 if (trans_pcie->msix_enabled) {
1285 int i;
1286
1287 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1288 synchronize_irq(trans_pcie->msix_entries[i].vector);
1289 } else {
1290 synchronize_irq(trans_pcie->pci_dev->irq);
1291 }
1292 }
1293
1294 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1295 const struct fw_img *fw, bool run_in_rfkill)
1296 {
1297 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1298 bool hw_rfkill;
1299 int ret;
1300
1301 /* This may fail if AMT took ownership of the device */
1302 if (iwl_pcie_prepare_card_hw(trans)) {
1303 IWL_WARN(trans, "Exit HW not ready\n");
1304 ret = -EIO;
1305 goto out;
1306 }
1307
1308 iwl_enable_rfkill_int(trans);
1309
1310 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1311
1312 /*
1313 * We enabled the RF-Kill interrupt and the handler may very
1314 * well be running. Disable the interrupts to make sure no other
1315 * interrupt can be fired.
1316 */
1317 iwl_disable_interrupts(trans);
1318
1319 /* Make sure it finished running */
1320 iwl_pcie_synchronize_irqs(trans);
1321
1322 mutex_lock(&trans_pcie->mutex);
1323
1324 /* If platform's RF_KILL switch is NOT set to KILL */
1325 hw_rfkill = iwl_trans_check_hw_rf_kill(trans);
1326 if (hw_rfkill && !run_in_rfkill) {
1327 ret = -ERFKILL;
1328 goto out;
1329 }
1330
1331 /* Someone called stop_device, don't try to start_fw */
1332 if (trans_pcie->is_down) {
1333 IWL_WARN(trans,
1334 "Can't start_fw since the HW hasn't been started\n");
1335 ret = -EIO;
1336 goto out;
1337 }
1338
1339 /* make sure rfkill handshake bits are cleared */
1340 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1341 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1342 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1343
1344 /* clear (again), then enable host interrupts */
1345 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1346
1347 ret = iwl_pcie_nic_init(trans);
1348 if (ret) {
1349 IWL_ERR(trans, "Unable to init nic\n");
1350 goto out;
1351 }
1352
1353 /*
1354 * Now, we load the firmware and don't want to be interrupted, even
1355 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1356 * FH_TX interrupt which is needed to load the firmware). If the
1357 * RF-Kill switch is toggled, we will find out after having loaded
1358 * the firmware and return the proper value to the caller.
1359 */
1360 iwl_enable_fw_load_int(trans);
1361
1362 /* really make sure rfkill handshake bits are cleared */
1363 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1364 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1365
1366 /* Load the given image to the HW */
1367 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1368 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1369 else
1370 ret = iwl_pcie_load_given_ucode(trans, fw);
1371
1372 /* re-check RF-Kill state since we may have missed the interrupt */
1373 hw_rfkill = iwl_trans_check_hw_rf_kill(trans);
1374 if (hw_rfkill && !run_in_rfkill)
1375 ret = -ERFKILL;
1376
1377 out:
1378 mutex_unlock(&trans_pcie->mutex);
1379 return ret;
1380 }
1381
1382 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1383 {
1384 iwl_pcie_reset_ict(trans);
1385 iwl_pcie_tx_start(trans, scd_addr);
1386 }
1387
1388 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1389 {
1390 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1391
1392 mutex_lock(&trans_pcie->mutex);
1393 _iwl_trans_pcie_stop_device(trans, low_power);
1394 mutex_unlock(&trans_pcie->mutex);
1395 }
1396
1397 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1398 {
1399 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1400 IWL_TRANS_GET_PCIE_TRANS(trans);
1401
1402 lockdep_assert_held(&trans_pcie->mutex);
1403
1404 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1405 if (trans->cfg->gen2)
1406 _iwl_trans_pcie_gen2_stop_device(trans, true);
1407 else
1408 _iwl_trans_pcie_stop_device(trans, true);
1409 }
1410 }
1411
1412 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1413 bool reset)
1414 {
1415 if (!reset) {
1416 /* Enable persistence mode to avoid reset */
1417 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1418 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1419 }
1420
1421 iwl_disable_interrupts(trans);
1422
1423 /*
1424 * in testing mode, the host stays awake and the
1425 * hardware won't be reset (not even partially)
1426 */
1427 if (test)
1428 return;
1429
1430 iwl_pcie_disable_ict(trans);
1431
1432 iwl_pcie_synchronize_irqs(trans);
1433
1434 iwl_clear_bit(trans, CSR_GP_CNTRL,
1435 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1436 iwl_clear_bit(trans, CSR_GP_CNTRL,
1437 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1438
1439 iwl_pcie_enable_rx_wake(trans, false);
1440
1441 if (reset) {
1442 /*
1443 * reset TX queues -- some of their registers reset during S3
1444 * so if we don't reset everything here the D3 image would try
1445 * to execute some invalid memory upon resume
1446 */
1447 iwl_trans_pcie_tx_reset(trans);
1448 }
1449
1450 iwl_pcie_set_pwr(trans, true);
1451 }
1452
1453 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1454 enum iwl_d3_status *status,
1455 bool test, bool reset)
1456 {
1457 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1458 u32 val;
1459 int ret;
1460
1461 if (test) {
1462 iwl_enable_interrupts(trans);
1463 *status = IWL_D3_STATUS_ALIVE;
1464 return 0;
1465 }
1466
1467 iwl_pcie_enable_rx_wake(trans, true);
1468
1469 /*
1470 * Reconfigure IVAR table in case of MSIX or reset ict table in
1471 * MSI mode since HW reset erased it.
1472 * Also enables interrupts - none will happen as
1473 * the device doesn't know we're waking it up, only when
1474 * the opmode actually tells it after this call.
1475 */
1476 iwl_pcie_conf_msix_hw(trans_pcie);
1477 if (!trans_pcie->msix_enabled)
1478 iwl_pcie_reset_ict(trans);
1479 iwl_enable_interrupts(trans);
1480
1481 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1482 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1483
1484 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1485 udelay(2);
1486
1487 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1488 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1489 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1490 25000);
1491 if (ret < 0) {
1492 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1493 return ret;
1494 }
1495
1496 iwl_pcie_set_pwr(trans, false);
1497
1498 if (!reset) {
1499 iwl_clear_bit(trans, CSR_GP_CNTRL,
1500 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1501 } else {
1502 iwl_trans_pcie_tx_reset(trans);
1503
1504 ret = iwl_pcie_rx_init(trans);
1505 if (ret) {
1506 IWL_ERR(trans,
1507 "Failed to resume the device (RX reset)\n");
1508 return ret;
1509 }
1510 }
1511
1512 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1513 iwl_read_prph(trans, WFPM_GP2));
1514
1515 val = iwl_read32(trans, CSR_RESET);
1516 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1517 *status = IWL_D3_STATUS_RESET;
1518 else
1519 *status = IWL_D3_STATUS_ALIVE;
1520
1521 return 0;
1522 }
1523
1524 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1525 struct iwl_trans *trans)
1526 {
1527 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1528 int max_irqs, num_irqs, i, ret, nr_online_cpus;
1529 u16 pci_cmd;
1530
1531 if (!trans->cfg->mq_rx_supported)
1532 goto enable_msi;
1533
1534 nr_online_cpus = num_online_cpus();
1535 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES);
1536 for (i = 0; i < max_irqs; i++)
1537 trans_pcie->msix_entries[i].entry = i;
1538
1539 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1540 MSIX_MIN_INTERRUPT_VECTORS,
1541 max_irqs);
1542 if (num_irqs < 0) {
1543 IWL_DEBUG_INFO(trans,
1544 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1545 num_irqs);
1546 goto enable_msi;
1547 }
1548 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1549
1550 IWL_DEBUG_INFO(trans,
1551 "MSI-X enabled. %d interrupt vectors were allocated\n",
1552 num_irqs);
1553
1554 /*
1555 * In case the OS provides fewer interrupts than requested, different
1556 * causes will share the same interrupt vector as follows:
1557 * One interrupt less: non rx causes shared with FBQ.
1558 * Two interrupts less: non rx causes shared with FBQ and RSS.
1559 * More than two interrupts: we will use fewer RSS queues.
1560 */
1561 if (num_irqs <= nr_online_cpus) {
1562 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1563 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1564 IWL_SHARED_IRQ_FIRST_RSS;
1565 } else if (num_irqs == nr_online_cpus + 1) {
1566 trans_pcie->trans->num_rx_queues = num_irqs;
1567 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1568 } else {
1569 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1570 }
1571
1572 trans_pcie->alloc_vecs = num_irqs;
1573 trans_pcie->msix_enabled = true;
1574 return;
1575
1576 enable_msi:
1577 ret = pci_enable_msi(pdev);
1578 if (ret) {
1579 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1580 /* enable rfkill interrupt: hw bug w/a */
1581 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1582 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1583 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1584 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1585 }
1586 }
1587 }
1588
1589 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1590 {
1591 int iter_rx_q, i, ret, cpu, offset;
1592 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1593
1594 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1595 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1596 offset = 1 + i;
1597 for (; i < iter_rx_q ; i++) {
1598 /*
1599 * Get the cpu prior to the place to search
1600 * (i.e. return will be > i - 1).
1601 */
1602 cpu = cpumask_next(i - offset, cpu_online_mask);
1603 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1604 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1605 &trans_pcie->affinity_mask[i]);
1606 if (ret)
1607 IWL_ERR(trans_pcie->trans,
1608 "Failed to set affinity mask for IRQ %d\n",
1609 i);
1610 }
1611 }
1612
1613 static const char *queue_name(struct device *dev,
1614 struct iwl_trans_pcie *trans_p, int i)
1615 {
1616 if (trans_p->shared_vec_mask) {
1617 int vec = trans_p->shared_vec_mask &
1618 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1619
1620 if (i == 0)
1621 return DRV_NAME ": shared IRQ";
1622
1623 return devm_kasprintf(dev, GFP_KERNEL,
1624 DRV_NAME ": queue %d", i + vec);
1625 }
1626 if (i == 0)
1627 return DRV_NAME ": default queue";
1628
1629 if (i == trans_p->alloc_vecs - 1)
1630 return DRV_NAME ": exception";
1631
1632 return devm_kasprintf(dev, GFP_KERNEL,
1633 DRV_NAME ": queue %d", i);
1634 }
1635
1636 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1637 struct iwl_trans_pcie *trans_pcie)
1638 {
1639 int i;
1640
1641 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1642 int ret;
1643 struct msix_entry *msix_entry;
1644 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1645
1646 if (!qname)
1647 return -ENOMEM;
1648
1649 msix_entry = &trans_pcie->msix_entries[i];
1650 ret = devm_request_threaded_irq(&pdev->dev,
1651 msix_entry->vector,
1652 iwl_pcie_msix_isr,
1653 (i == trans_pcie->def_irq) ?
1654 iwl_pcie_irq_msix_handler :
1655 iwl_pcie_irq_rx_msix_handler,
1656 IRQF_SHARED,
1657 qname,
1658 msix_entry);
1659 if (ret) {
1660 IWL_ERR(trans_pcie->trans,
1661 "Error allocating IRQ %d\n", i);
1662
1663 return ret;
1664 }
1665 }
1666 iwl_pcie_irq_set_affinity(trans_pcie->trans);
1667
1668 return 0;
1669 }
1670
1671 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1672 {
1673 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1674 int err;
1675
1676 lockdep_assert_held(&trans_pcie->mutex);
1677
1678 err = iwl_pcie_prepare_card_hw(trans);
1679 if (err) {
1680 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1681 return err;
1682 }
1683
1684 /* Reset the entire device */
1685 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1686 usleep_range(1000, 2000);
1687
1688 iwl_pcie_apm_init(trans);
1689
1690 iwl_pcie_init_msix(trans_pcie);
1691
1692 /* From now on, the op_mode will be kept updated about RF kill state */
1693 iwl_enable_rfkill_int(trans);
1694
1695 /* Set is_down to false here so that...*/
1696 trans_pcie->is_down = false;
1697
1698 /* ...rfkill can call stop_device and set it false if needed */
1699 iwl_trans_check_hw_rf_kill(trans);
1700
1701 /* Make sure we sync here, because we'll need full access later */
1702 if (low_power)
1703 pm_runtime_resume(trans->dev);
1704
1705 return 0;
1706 }
1707
1708 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1709 {
1710 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1711 int ret;
1712
1713 mutex_lock(&trans_pcie->mutex);
1714 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1715 mutex_unlock(&trans_pcie->mutex);
1716
1717 return ret;
1718 }
1719
1720 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1721 {
1722 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1723
1724 mutex_lock(&trans_pcie->mutex);
1725
1726 /* disable interrupts - don't enable HW RF kill interrupt */
1727 iwl_disable_interrupts(trans);
1728
1729 iwl_pcie_apm_stop(trans, true);
1730
1731 iwl_disable_interrupts(trans);
1732
1733 iwl_pcie_disable_ict(trans);
1734
1735 mutex_unlock(&trans_pcie->mutex);
1736
1737 iwl_pcie_synchronize_irqs(trans);
1738 }
1739
1740 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1741 {
1742 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1743 }
1744
1745 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1746 {
1747 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1748 }
1749
1750 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1751 {
1752 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1753 }
1754
1755 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1756 {
1757 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1758 ((reg & 0x000FFFFF) | (3 << 24)));
1759 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1760 }
1761
1762 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1763 u32 val)
1764 {
1765 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1766 ((addr & 0x000FFFFF) | (3 << 24)));
1767 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1768 }
1769
1770 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1771 const struct iwl_trans_config *trans_cfg)
1772 {
1773 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1774
1775 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1776 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1777 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1778 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1779 trans_pcie->n_no_reclaim_cmds = 0;
1780 else
1781 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1782 if (trans_pcie->n_no_reclaim_cmds)
1783 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1784 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1785
1786 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1787 trans_pcie->rx_page_order =
1788 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1789
1790 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1791 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1792 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1793
1794 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1795 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1796
1797 trans->command_groups = trans_cfg->command_groups;
1798 trans->command_groups_size = trans_cfg->command_groups_size;
1799
1800 /* Initialize NAPI here - it should be before registering to mac80211
1801 * in the opmode but after the HW struct is allocated.
1802 * As this function may be called again in some corner cases don't
1803 * do anything if NAPI was already initialized.
1804 */
1805 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1806 init_dummy_netdev(&trans_pcie->napi_dev);
1807 }
1808
1809 void iwl_trans_pcie_free(struct iwl_trans *trans)
1810 {
1811 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1812 int i;
1813
1814 iwl_pcie_synchronize_irqs(trans);
1815
1816 if (trans->cfg->gen2)
1817 iwl_pcie_gen2_tx_free(trans);
1818 else
1819 iwl_pcie_tx_free(trans);
1820 iwl_pcie_rx_free(trans);
1821
1822 if (trans_pcie->msix_enabled) {
1823 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1824 irq_set_affinity_hint(
1825 trans_pcie->msix_entries[i].vector,
1826 NULL);
1827 }
1828
1829 trans_pcie->msix_enabled = false;
1830 } else {
1831 iwl_pcie_free_ict(trans);
1832 }
1833
1834 iwl_pcie_free_fw_monitor(trans);
1835
1836 for_each_possible_cpu(i) {
1837 struct iwl_tso_hdr_page *p =
1838 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1839
1840 if (p->page)
1841 __free_page(p->page);
1842 }
1843
1844 free_percpu(trans_pcie->tso_hdr_page);
1845 mutex_destroy(&trans_pcie->mutex);
1846 iwl_trans_free(trans);
1847 }
1848
1849 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1850 {
1851 if (state)
1852 set_bit(STATUS_TPOWER_PMI, &trans->status);
1853 else
1854 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1855 }
1856
1857 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1858 unsigned long *flags)
1859 {
1860 int ret;
1861 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1862
1863 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1864
1865 if (trans_pcie->cmd_hold_nic_awake)
1866 goto out;
1867
1868 /* this bit wakes up the NIC */
1869 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1870 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1871 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1872 udelay(2);
1873
1874 /*
1875 * These bits say the device is running, and should keep running for
1876 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1877 * but they do not indicate that embedded SRAM is restored yet;
1878 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1879 * to/from host DRAM when sleeping/waking for power-saving.
1880 * Each direction takes approximately 1/4 millisecond; with this
1881 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1882 * series of register accesses are expected (e.g. reading Event Log),
1883 * to keep device from sleeping.
1884 *
1885 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1886 * SRAM is okay/restored. We don't check that here because this call
1887 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1888 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1889 *
1890 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1891 * and do not save/restore SRAM when power cycling.
1892 */
1893 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1894 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1895 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1896 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1897 if (unlikely(ret < 0)) {
1898 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1899 WARN_ONCE(1,
1900 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1901 iwl_read32(trans, CSR_GP_CNTRL));
1902 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1903 return false;
1904 }
1905
1906 out:
1907 /*
1908 * Fool sparse by faking we release the lock - sparse will
1909 * track nic_access anyway.
1910 */
1911 __release(&trans_pcie->reg_lock);
1912 return true;
1913 }
1914
1915 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1916 unsigned long *flags)
1917 {
1918 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1919
1920 lockdep_assert_held(&trans_pcie->reg_lock);
1921
1922 /*
1923 * Fool sparse by faking we acquiring the lock - sparse will
1924 * track nic_access anyway.
1925 */
1926 __acquire(&trans_pcie->reg_lock);
1927
1928 if (trans_pcie->cmd_hold_nic_awake)
1929 goto out;
1930
1931 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1932 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1933 /*
1934 * Above we read the CSR_GP_CNTRL register, which will flush
1935 * any previous writes, but we need the write that clears the
1936 * MAC_ACCESS_REQ bit to be performed before any other writes
1937 * scheduled on different CPUs (after we drop reg_lock).
1938 */
1939 mmiowb();
1940 out:
1941 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1942 }
1943
1944 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1945 void *buf, int dwords)
1946 {
1947 unsigned long flags;
1948 int offs, ret = 0;
1949 u32 *vals = buf;
1950
1951 if (iwl_trans_grab_nic_access(trans, &flags)) {
1952 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1953 for (offs = 0; offs < dwords; offs++)
1954 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1955 iwl_trans_release_nic_access(trans, &flags);
1956 } else {
1957 ret = -EBUSY;
1958 }
1959 return ret;
1960 }
1961
1962 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1963 const void *buf, int dwords)
1964 {
1965 unsigned long flags;
1966 int offs, ret = 0;
1967 const u32 *vals = buf;
1968
1969 if (iwl_trans_grab_nic_access(trans, &flags)) {
1970 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1971 for (offs = 0; offs < dwords; offs++)
1972 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1973 vals ? vals[offs] : 0);
1974 iwl_trans_release_nic_access(trans, &flags);
1975 } else {
1976 ret = -EBUSY;
1977 }
1978 return ret;
1979 }
1980
1981 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1982 unsigned long txqs,
1983 bool freeze)
1984 {
1985 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1986 int queue;
1987
1988 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1989 struct iwl_txq *txq = trans_pcie->txq[queue];
1990 unsigned long now;
1991
1992 spin_lock_bh(&txq->lock);
1993
1994 now = jiffies;
1995
1996 if (txq->frozen == freeze)
1997 goto next_queue;
1998
1999 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2000 freeze ? "Freezing" : "Waking", queue);
2001
2002 txq->frozen = freeze;
2003
2004 if (txq->read_ptr == txq->write_ptr)
2005 goto next_queue;
2006
2007 if (freeze) {
2008 if (unlikely(time_after(now,
2009 txq->stuck_timer.expires))) {
2010 /*
2011 * The timer should have fired, maybe it is
2012 * spinning right now on the lock.
2013 */
2014 goto next_queue;
2015 }
2016 /* remember how long until the timer fires */
2017 txq->frozen_expiry_remainder =
2018 txq->stuck_timer.expires - now;
2019 del_timer(&txq->stuck_timer);
2020 goto next_queue;
2021 }
2022
2023 /*
2024 * Wake a non-empty queue -> arm timer with the
2025 * remainder before it froze
2026 */
2027 mod_timer(&txq->stuck_timer,
2028 now + txq->frozen_expiry_remainder);
2029
2030 next_queue:
2031 spin_unlock_bh(&txq->lock);
2032 }
2033 }
2034
2035 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2036 {
2037 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2038 int i;
2039
2040 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2041 struct iwl_txq *txq = trans_pcie->txq[i];
2042
2043 if (i == trans_pcie->cmd_queue)
2044 continue;
2045
2046 spin_lock_bh(&txq->lock);
2047
2048 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2049 txq->block--;
2050 if (!txq->block) {
2051 iwl_write32(trans, HBUS_TARG_WRPTR,
2052 txq->write_ptr | (i << 8));
2053 }
2054 } else if (block) {
2055 txq->block++;
2056 }
2057
2058 spin_unlock_bh(&txq->lock);
2059 }
2060 }
2061
2062 #define IWL_FLUSH_WAIT_MS 2000
2063
2064 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2065 {
2066 u32 txq_id = txq->id;
2067 u32 status;
2068 bool active;
2069 u8 fifo;
2070
2071 if (trans->cfg->use_tfh) {
2072 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2073 txq->read_ptr, txq->write_ptr);
2074 /* TODO: access new SCD registers and dump them */
2075 return;
2076 }
2077
2078 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2079 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2080 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2081
2082 IWL_ERR(trans,
2083 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2084 txq_id, active ? "" : "in", fifo,
2085 jiffies_to_msecs(txq->wd_timeout),
2086 txq->read_ptr, txq->write_ptr,
2087 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2088 (TFD_QUEUE_SIZE_MAX - 1),
2089 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2090 (TFD_QUEUE_SIZE_MAX - 1),
2091 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
2092 }
2093
2094 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
2095 {
2096 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2097 struct iwl_txq *txq;
2098 int cnt;
2099 unsigned long now = jiffies;
2100 int ret = 0;
2101
2102 /* waiting for all the tx frames complete might take a while */
2103 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2104 u8 wr_ptr;
2105
2106 if (cnt == trans_pcie->cmd_queue)
2107 continue;
2108 if (!test_bit(cnt, trans_pcie->queue_used))
2109 continue;
2110 if (!(BIT(cnt) & txq_bm))
2111 continue;
2112
2113 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
2114 txq = trans_pcie->txq[cnt];
2115 wr_ptr = ACCESS_ONCE(txq->write_ptr);
2116
2117 while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) &&
2118 !time_after(jiffies,
2119 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2120 u8 write_ptr = ACCESS_ONCE(txq->write_ptr);
2121
2122 if (WARN_ONCE(wr_ptr != write_ptr,
2123 "WR pointer moved while flushing %d -> %d\n",
2124 wr_ptr, write_ptr))
2125 return -ETIMEDOUT;
2126 usleep_range(1000, 2000);
2127 }
2128
2129 if (txq->read_ptr != txq->write_ptr) {
2130 IWL_ERR(trans,
2131 "fail to flush all tx fifo queues Q %d\n", cnt);
2132 ret = -ETIMEDOUT;
2133 break;
2134 }
2135 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
2136 }
2137
2138 if (ret)
2139 iwl_trans_pcie_log_scd_error(trans, txq);
2140
2141 return ret;
2142 }
2143
2144 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2145 u32 mask, u32 value)
2146 {
2147 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2148 unsigned long flags;
2149
2150 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2151 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2152 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2153 }
2154
2155 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2156 {
2157 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2158
2159 if (iwlwifi_mod_params.d0i3_disable)
2160 return;
2161
2162 pm_runtime_get(&trans_pcie->pci_dev->dev);
2163
2164 #ifdef CONFIG_PM
2165 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2166 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2167 #endif /* CONFIG_PM */
2168 }
2169
2170 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2171 {
2172 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2173
2174 if (iwlwifi_mod_params.d0i3_disable)
2175 return;
2176
2177 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2178 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2179
2180 #ifdef CONFIG_PM
2181 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2182 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2183 #endif /* CONFIG_PM */
2184 }
2185
2186 static const char *get_csr_string(int cmd)
2187 {
2188 #define IWL_CMD(x) case x: return #x
2189 switch (cmd) {
2190 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2191 IWL_CMD(CSR_INT_COALESCING);
2192 IWL_CMD(CSR_INT);
2193 IWL_CMD(CSR_INT_MASK);
2194 IWL_CMD(CSR_FH_INT_STATUS);
2195 IWL_CMD(CSR_GPIO_IN);
2196 IWL_CMD(CSR_RESET);
2197 IWL_CMD(CSR_GP_CNTRL);
2198 IWL_CMD(CSR_HW_REV);
2199 IWL_CMD(CSR_EEPROM_REG);
2200 IWL_CMD(CSR_EEPROM_GP);
2201 IWL_CMD(CSR_OTP_GP_REG);
2202 IWL_CMD(CSR_GIO_REG);
2203 IWL_CMD(CSR_GP_UCODE_REG);
2204 IWL_CMD(CSR_GP_DRIVER_REG);
2205 IWL_CMD(CSR_UCODE_DRV_GP1);
2206 IWL_CMD(CSR_UCODE_DRV_GP2);
2207 IWL_CMD(CSR_LED_REG);
2208 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2209 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2210 IWL_CMD(CSR_ANA_PLL_CFG);
2211 IWL_CMD(CSR_HW_REV_WA_REG);
2212 IWL_CMD(CSR_MONITOR_STATUS_REG);
2213 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2214 default:
2215 return "UNKNOWN";
2216 }
2217 #undef IWL_CMD
2218 }
2219
2220 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2221 {
2222 int i;
2223 static const u32 csr_tbl[] = {
2224 CSR_HW_IF_CONFIG_REG,
2225 CSR_INT_COALESCING,
2226 CSR_INT,
2227 CSR_INT_MASK,
2228 CSR_FH_INT_STATUS,
2229 CSR_GPIO_IN,
2230 CSR_RESET,
2231 CSR_GP_CNTRL,
2232 CSR_HW_REV,
2233 CSR_EEPROM_REG,
2234 CSR_EEPROM_GP,
2235 CSR_OTP_GP_REG,
2236 CSR_GIO_REG,
2237 CSR_GP_UCODE_REG,
2238 CSR_GP_DRIVER_REG,
2239 CSR_UCODE_DRV_GP1,
2240 CSR_UCODE_DRV_GP2,
2241 CSR_LED_REG,
2242 CSR_DRAM_INT_TBL_REG,
2243 CSR_GIO_CHICKEN_BITS,
2244 CSR_ANA_PLL_CFG,
2245 CSR_MONITOR_STATUS_REG,
2246 CSR_HW_REV_WA_REG,
2247 CSR_DBG_HPET_MEM_REG
2248 };
2249 IWL_ERR(trans, "CSR values:\n");
2250 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2251 "CSR_INT_PERIODIC_REG)\n");
2252 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2253 IWL_ERR(trans, " %25s: 0X%08x\n",
2254 get_csr_string(csr_tbl[i]),
2255 iwl_read32(trans, csr_tbl[i]));
2256 }
2257 }
2258
2259 #ifdef CONFIG_IWLWIFI_DEBUGFS
2260 /* create and remove of files */
2261 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
2262 if (!debugfs_create_file(#name, mode, parent, trans, \
2263 &iwl_dbgfs_##name##_ops)) \
2264 goto err; \
2265 } while (0)
2266
2267 /* file operation */
2268 #define DEBUGFS_READ_FILE_OPS(name) \
2269 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2270 .read = iwl_dbgfs_##name##_read, \
2271 .open = simple_open, \
2272 .llseek = generic_file_llseek, \
2273 };
2274
2275 #define DEBUGFS_WRITE_FILE_OPS(name) \
2276 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2277 .write = iwl_dbgfs_##name##_write, \
2278 .open = simple_open, \
2279 .llseek = generic_file_llseek, \
2280 };
2281
2282 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
2283 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2284 .write = iwl_dbgfs_##name##_write, \
2285 .read = iwl_dbgfs_##name##_read, \
2286 .open = simple_open, \
2287 .llseek = generic_file_llseek, \
2288 };
2289
2290 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2291 char __user *user_buf,
2292 size_t count, loff_t *ppos)
2293 {
2294 struct iwl_trans *trans = file->private_data;
2295 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2296 struct iwl_txq *txq;
2297 char *buf;
2298 int pos = 0;
2299 int cnt;
2300 int ret;
2301 size_t bufsz;
2302
2303 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2304
2305 if (!trans_pcie->txq_memory)
2306 return -EAGAIN;
2307
2308 buf = kzalloc(bufsz, GFP_KERNEL);
2309 if (!buf)
2310 return -ENOMEM;
2311
2312 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2313 txq = trans_pcie->txq[cnt];
2314 pos += scnprintf(buf + pos, bufsz - pos,
2315 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2316 cnt, txq->read_ptr, txq->write_ptr,
2317 !!test_bit(cnt, trans_pcie->queue_used),
2318 !!test_bit(cnt, trans_pcie->queue_stopped),
2319 txq->need_update, txq->frozen,
2320 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2321 }
2322 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2323 kfree(buf);
2324 return ret;
2325 }
2326
2327 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2328 char __user *user_buf,
2329 size_t count, loff_t *ppos)
2330 {
2331 struct iwl_trans *trans = file->private_data;
2332 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2333 char *buf;
2334 int pos = 0, i, ret;
2335 size_t bufsz = sizeof(buf);
2336
2337 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2338
2339 if (!trans_pcie->rxq)
2340 return -EAGAIN;
2341
2342 buf = kzalloc(bufsz, GFP_KERNEL);
2343 if (!buf)
2344 return -ENOMEM;
2345
2346 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2347 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2348
2349 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2350 i);
2351 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2352 rxq->read);
2353 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2354 rxq->write);
2355 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2356 rxq->write_actual);
2357 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2358 rxq->need_update);
2359 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2360 rxq->free_count);
2361 if (rxq->rb_stts) {
2362 pos += scnprintf(buf + pos, bufsz - pos,
2363 "\tclosed_rb_num: %u\n",
2364 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2365 0x0FFF);
2366 } else {
2367 pos += scnprintf(buf + pos, bufsz - pos,
2368 "\tclosed_rb_num: Not Allocated\n");
2369 }
2370 }
2371 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2372 kfree(buf);
2373
2374 return ret;
2375 }
2376
2377 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2378 char __user *user_buf,
2379 size_t count, loff_t *ppos)
2380 {
2381 struct iwl_trans *trans = file->private_data;
2382 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2383 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2384
2385 int pos = 0;
2386 char *buf;
2387 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2388 ssize_t ret;
2389
2390 buf = kzalloc(bufsz, GFP_KERNEL);
2391 if (!buf)
2392 return -ENOMEM;
2393
2394 pos += scnprintf(buf + pos, bufsz - pos,
2395 "Interrupt Statistics Report:\n");
2396
2397 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2398 isr_stats->hw);
2399 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2400 isr_stats->sw);
2401 if (isr_stats->sw || isr_stats->hw) {
2402 pos += scnprintf(buf + pos, bufsz - pos,
2403 "\tLast Restarting Code: 0x%X\n",
2404 isr_stats->err_code);
2405 }
2406 #ifdef CONFIG_IWLWIFI_DEBUG
2407 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2408 isr_stats->sch);
2409 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2410 isr_stats->alive);
2411 #endif
2412 pos += scnprintf(buf + pos, bufsz - pos,
2413 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2414
2415 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2416 isr_stats->ctkill);
2417
2418 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2419 isr_stats->wakeup);
2420
2421 pos += scnprintf(buf + pos, bufsz - pos,
2422 "Rx command responses:\t\t %u\n", isr_stats->rx);
2423
2424 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2425 isr_stats->tx);
2426
2427 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2428 isr_stats->unhandled);
2429
2430 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2431 kfree(buf);
2432 return ret;
2433 }
2434
2435 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2436 const char __user *user_buf,
2437 size_t count, loff_t *ppos)
2438 {
2439 struct iwl_trans *trans = file->private_data;
2440 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2441 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2442
2443 char buf[8];
2444 int buf_size;
2445 u32 reset_flag;
2446
2447 memset(buf, 0, sizeof(buf));
2448 buf_size = min(count, sizeof(buf) - 1);
2449 if (copy_from_user(buf, user_buf, buf_size))
2450 return -EFAULT;
2451 if (sscanf(buf, "%x", &reset_flag) != 1)
2452 return -EFAULT;
2453 if (reset_flag == 0)
2454 memset(isr_stats, 0, sizeof(*isr_stats));
2455
2456 return count;
2457 }
2458
2459 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2460 const char __user *user_buf,
2461 size_t count, loff_t *ppos)
2462 {
2463 struct iwl_trans *trans = file->private_data;
2464 char buf[8];
2465 int buf_size;
2466 int csr;
2467
2468 memset(buf, 0, sizeof(buf));
2469 buf_size = min(count, sizeof(buf) - 1);
2470 if (copy_from_user(buf, user_buf, buf_size))
2471 return -EFAULT;
2472 if (sscanf(buf, "%d", &csr) != 1)
2473 return -EFAULT;
2474
2475 iwl_pcie_dump_csr(trans);
2476
2477 return count;
2478 }
2479
2480 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2481 char __user *user_buf,
2482 size_t count, loff_t *ppos)
2483 {
2484 struct iwl_trans *trans = file->private_data;
2485 char *buf = NULL;
2486 ssize_t ret;
2487
2488 ret = iwl_dump_fh(trans, &buf);
2489 if (ret < 0)
2490 return ret;
2491 if (!buf)
2492 return -EINVAL;
2493 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2494 kfree(buf);
2495 return ret;
2496 }
2497
2498 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2499 DEBUGFS_READ_FILE_OPS(fh_reg);
2500 DEBUGFS_READ_FILE_OPS(rx_queue);
2501 DEBUGFS_READ_FILE_OPS(tx_queue);
2502 DEBUGFS_WRITE_FILE_OPS(csr);
2503
2504 /* Create the debugfs files and directories */
2505 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2506 {
2507 struct dentry *dir = trans->dbgfs_dir;
2508
2509 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2510 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2511 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2512 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2513 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2514 return 0;
2515
2516 err:
2517 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2518 return -ENOMEM;
2519 }
2520 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2521
2522 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2523 {
2524 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2525 u32 cmdlen = 0;
2526 int i;
2527
2528 for (i = 0; i < trans_pcie->max_tbs; i++)
2529 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2530
2531 return cmdlen;
2532 }
2533
2534 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2535 struct iwl_fw_error_dump_data **data,
2536 int allocated_rb_nums)
2537 {
2538 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2539 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2540 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2541 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2542 u32 i, r, j, rb_len = 0;
2543
2544 spin_lock(&rxq->lock);
2545
2546 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2547
2548 for (i = rxq->read, j = 0;
2549 i != r && j < allocated_rb_nums;
2550 i = (i + 1) & RX_QUEUE_MASK, j++) {
2551 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2552 struct iwl_fw_error_dump_rb *rb;
2553
2554 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2555 DMA_FROM_DEVICE);
2556
2557 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2558
2559 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2560 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2561 rb = (void *)(*data)->data;
2562 rb->index = cpu_to_le32(i);
2563 memcpy(rb->data, page_address(rxb->page), max_len);
2564 /* remap the page for the free benefit */
2565 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2566 max_len,
2567 DMA_FROM_DEVICE);
2568
2569 *data = iwl_fw_error_next_data(*data);
2570 }
2571
2572 spin_unlock(&rxq->lock);
2573
2574 return rb_len;
2575 }
2576 #define IWL_CSR_TO_DUMP (0x250)
2577
2578 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2579 struct iwl_fw_error_dump_data **data)
2580 {
2581 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2582 __le32 *val;
2583 int i;
2584
2585 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2586 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2587 val = (void *)(*data)->data;
2588
2589 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2590 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2591
2592 *data = iwl_fw_error_next_data(*data);
2593
2594 return csr_len;
2595 }
2596
2597 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2598 struct iwl_fw_error_dump_data **data)
2599 {
2600 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2601 unsigned long flags;
2602 __le32 *val;
2603 int i;
2604
2605 if (!iwl_trans_grab_nic_access(trans, &flags))
2606 return 0;
2607
2608 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2609 (*data)->len = cpu_to_le32(fh_regs_len);
2610 val = (void *)(*data)->data;
2611
2612 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2613 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2614
2615 iwl_trans_release_nic_access(trans, &flags);
2616
2617 *data = iwl_fw_error_next_data(*data);
2618
2619 return sizeof(**data) + fh_regs_len;
2620 }
2621
2622 static u32
2623 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2624 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2625 u32 monitor_len)
2626 {
2627 u32 buf_size_in_dwords = (monitor_len >> 2);
2628 u32 *buffer = (u32 *)fw_mon_data->data;
2629 unsigned long flags;
2630 u32 i;
2631
2632 if (!iwl_trans_grab_nic_access(trans, &flags))
2633 return 0;
2634
2635 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2636 for (i = 0; i < buf_size_in_dwords; i++)
2637 buffer[i] = iwl_read_prph_no_grab(trans,
2638 MON_DMARB_RD_DATA_ADDR);
2639 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2640
2641 iwl_trans_release_nic_access(trans, &flags);
2642
2643 return monitor_len;
2644 }
2645
2646 static u32
2647 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2648 struct iwl_fw_error_dump_data **data,
2649 u32 monitor_len)
2650 {
2651 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2652 u32 len = 0;
2653
2654 if ((trans_pcie->fw_mon_page &&
2655 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2656 trans->dbg_dest_tlv) {
2657 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2658 u32 base, write_ptr, wrap_cnt;
2659
2660 /* If there was a dest TLV - use the values from there */
2661 if (trans->dbg_dest_tlv) {
2662 write_ptr =
2663 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2664 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2665 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2666 } else {
2667 base = MON_BUFF_BASE_ADDR;
2668 write_ptr = MON_BUFF_WRPTR;
2669 wrap_cnt = MON_BUFF_CYCLE_CNT;
2670 }
2671
2672 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2673 fw_mon_data = (void *)(*data)->data;
2674 fw_mon_data->fw_mon_wr_ptr =
2675 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2676 fw_mon_data->fw_mon_cycle_cnt =
2677 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2678 fw_mon_data->fw_mon_base_ptr =
2679 cpu_to_le32(iwl_read_prph(trans, base));
2680
2681 len += sizeof(**data) + sizeof(*fw_mon_data);
2682 if (trans_pcie->fw_mon_page) {
2683 /*
2684 * The firmware is now asserted, it won't write anything
2685 * to the buffer. CPU can take ownership to fetch the
2686 * data. The buffer will be handed back to the device
2687 * before the firmware will be restarted.
2688 */
2689 dma_sync_single_for_cpu(trans->dev,
2690 trans_pcie->fw_mon_phys,
2691 trans_pcie->fw_mon_size,
2692 DMA_FROM_DEVICE);
2693 memcpy(fw_mon_data->data,
2694 page_address(trans_pcie->fw_mon_page),
2695 trans_pcie->fw_mon_size);
2696
2697 monitor_len = trans_pcie->fw_mon_size;
2698 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2699 /*
2700 * Update pointers to reflect actual values after
2701 * shifting
2702 */
2703 base = iwl_read_prph(trans, base) <<
2704 trans->dbg_dest_tlv->base_shift;
2705 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2706 monitor_len / sizeof(u32));
2707 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2708 monitor_len =
2709 iwl_trans_pci_dump_marbh_monitor(trans,
2710 fw_mon_data,
2711 monitor_len);
2712 } else {
2713 /* Didn't match anything - output no monitor data */
2714 monitor_len = 0;
2715 }
2716
2717 len += monitor_len;
2718 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2719 }
2720
2721 return len;
2722 }
2723
2724 static struct iwl_trans_dump_data
2725 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2726 const struct iwl_fw_dbg_trigger_tlv *trigger)
2727 {
2728 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2729 struct iwl_fw_error_dump_data *data;
2730 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
2731 struct iwl_fw_error_dump_txcmd *txcmd;
2732 struct iwl_trans_dump_data *dump_data;
2733 u32 len, num_rbs;
2734 u32 monitor_len;
2735 int i, ptr;
2736 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2737 !trans->cfg->mq_rx_supported;
2738
2739 /* transport dump header */
2740 len = sizeof(*dump_data);
2741
2742 /* host commands */
2743 len += sizeof(*data) +
2744 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2745
2746 /* FW monitor */
2747 if (trans_pcie->fw_mon_page) {
2748 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2749 trans_pcie->fw_mon_size;
2750 monitor_len = trans_pcie->fw_mon_size;
2751 } else if (trans->dbg_dest_tlv) {
2752 u32 base, end;
2753
2754 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2755 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2756
2757 base = iwl_read_prph(trans, base) <<
2758 trans->dbg_dest_tlv->base_shift;
2759 end = iwl_read_prph(trans, end) <<
2760 trans->dbg_dest_tlv->end_shift;
2761
2762 /* Make "end" point to the actual end */
2763 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2764 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2765 end += (1 << trans->dbg_dest_tlv->end_shift);
2766 monitor_len = end - base;
2767 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2768 monitor_len;
2769 } else {
2770 monitor_len = 0;
2771 }
2772
2773 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2774 dump_data = vzalloc(len);
2775 if (!dump_data)
2776 return NULL;
2777
2778 data = (void *)dump_data->data;
2779 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2780 dump_data->len = len;
2781
2782 return dump_data;
2783 }
2784
2785 /* CSR registers */
2786 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2787
2788 /* FH registers */
2789 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2790
2791 if (dump_rbs) {
2792 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2793 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2794 /* RBs */
2795 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
2796 & 0x0FFF;
2797 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2798 len += num_rbs * (sizeof(*data) +
2799 sizeof(struct iwl_fw_error_dump_rb) +
2800 (PAGE_SIZE << trans_pcie->rx_page_order));
2801 }
2802
2803 dump_data = vzalloc(len);
2804 if (!dump_data)
2805 return NULL;
2806
2807 len = 0;
2808 data = (void *)dump_data->data;
2809 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2810 txcmd = (void *)data->data;
2811 spin_lock_bh(&cmdq->lock);
2812 ptr = cmdq->write_ptr;
2813 for (i = 0; i < cmdq->n_window; i++) {
2814 u8 idx = get_cmd_index(cmdq, ptr);
2815 u32 caplen, cmdlen;
2816
2817 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2818 trans_pcie->tfd_size * ptr);
2819 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2820
2821 if (cmdlen) {
2822 len += sizeof(*txcmd) + caplen;
2823 txcmd->cmdlen = cpu_to_le32(cmdlen);
2824 txcmd->caplen = cpu_to_le32(caplen);
2825 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2826 txcmd = (void *)((u8 *)txcmd->data + caplen);
2827 }
2828
2829 ptr = iwl_queue_dec_wrap(ptr);
2830 }
2831 spin_unlock_bh(&cmdq->lock);
2832
2833 data->len = cpu_to_le32(len);
2834 len += sizeof(*data);
2835 data = iwl_fw_error_next_data(data);
2836
2837 len += iwl_trans_pcie_dump_csr(trans, &data);
2838 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2839 if (dump_rbs)
2840 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2841
2842 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2843
2844 dump_data->len = len;
2845
2846 return dump_data;
2847 }
2848
2849 #ifdef CONFIG_PM_SLEEP
2850 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2851 {
2852 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2853 return iwl_pci_fw_enter_d0i3(trans);
2854
2855 return 0;
2856 }
2857
2858 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2859 {
2860 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2861 iwl_pci_fw_exit_d0i3(trans);
2862 }
2863 #endif /* CONFIG_PM_SLEEP */
2864
2865 #define IWL_TRANS_COMMON_OPS \
2866 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
2867 .write8 = iwl_trans_pcie_write8, \
2868 .write32 = iwl_trans_pcie_write32, \
2869 .read32 = iwl_trans_pcie_read32, \
2870 .read_prph = iwl_trans_pcie_read_prph, \
2871 .write_prph = iwl_trans_pcie_write_prph, \
2872 .read_mem = iwl_trans_pcie_read_mem, \
2873 .write_mem = iwl_trans_pcie_write_mem, \
2874 .configure = iwl_trans_pcie_configure, \
2875 .set_pmi = iwl_trans_pcie_set_pmi, \
2876 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
2877 .release_nic_access = iwl_trans_pcie_release_nic_access, \
2878 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
2879 .ref = iwl_trans_pcie_ref, \
2880 .unref = iwl_trans_pcie_unref, \
2881 .dump_data = iwl_trans_pcie_dump_data, \
2882 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, \
2883 .d3_suspend = iwl_trans_pcie_d3_suspend, \
2884 .d3_resume = iwl_trans_pcie_d3_resume
2885
2886 #ifdef CONFIG_PM_SLEEP
2887 #define IWL_TRANS_PM_OPS \
2888 .suspend = iwl_trans_pcie_suspend, \
2889 .resume = iwl_trans_pcie_resume,
2890 #else
2891 #define IWL_TRANS_PM_OPS
2892 #endif /* CONFIG_PM_SLEEP */
2893
2894 static const struct iwl_trans_ops trans_ops_pcie = {
2895 IWL_TRANS_COMMON_OPS,
2896 IWL_TRANS_PM_OPS
2897 .start_hw = iwl_trans_pcie_start_hw,
2898 .fw_alive = iwl_trans_pcie_fw_alive,
2899 .start_fw = iwl_trans_pcie_start_fw,
2900 .stop_device = iwl_trans_pcie_stop_device,
2901
2902 .send_cmd = iwl_trans_pcie_send_hcmd,
2903
2904 .tx = iwl_trans_pcie_tx,
2905 .reclaim = iwl_trans_pcie_reclaim,
2906
2907 .txq_disable = iwl_trans_pcie_txq_disable,
2908 .txq_enable = iwl_trans_pcie_txq_enable,
2909
2910 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
2911
2912 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2913 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2914 };
2915
2916 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
2917 IWL_TRANS_COMMON_OPS,
2918 IWL_TRANS_PM_OPS
2919 .start_hw = iwl_trans_pcie_start_hw,
2920 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
2921 .start_fw = iwl_trans_pcie_gen2_start_fw,
2922 .stop_device = iwl_trans_pcie_gen2_stop_device,
2923
2924 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
2925
2926 .tx = iwl_trans_pcie_gen2_tx,
2927 .reclaim = iwl_trans_pcie_reclaim,
2928
2929 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
2930 .txq_free = iwl_trans_pcie_dyn_txq_free,
2931 };
2932
2933 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2934 const struct pci_device_id *ent,
2935 const struct iwl_cfg *cfg)
2936 {
2937 struct iwl_trans_pcie *trans_pcie;
2938 struct iwl_trans *trans;
2939 int ret, addr_size;
2940
2941 ret = pcim_enable_device(pdev);
2942 if (ret)
2943 return ERR_PTR(ret);
2944
2945 if (cfg->gen2)
2946 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2947 &pdev->dev, cfg, &trans_ops_pcie_gen2);
2948 else
2949 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2950 &pdev->dev, cfg, &trans_ops_pcie);
2951 if (!trans)
2952 return ERR_PTR(-ENOMEM);
2953
2954 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2955
2956 trans_pcie->trans = trans;
2957 spin_lock_init(&trans_pcie->irq_lock);
2958 spin_lock_init(&trans_pcie->reg_lock);
2959 mutex_init(&trans_pcie->mutex);
2960 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2961 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2962 if (!trans_pcie->tso_hdr_page) {
2963 ret = -ENOMEM;
2964 goto out_no_pci;
2965 }
2966
2967
2968 if (!cfg->base_params->pcie_l1_allowed) {
2969 /*
2970 * W/A - seems to solve weird behavior. We need to remove this
2971 * if we don't want to stay in L1 all the time. This wastes a
2972 * lot of power.
2973 */
2974 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2975 PCIE_LINK_STATE_L1 |
2976 PCIE_LINK_STATE_CLKPM);
2977 }
2978
2979 if (cfg->use_tfh) {
2980 addr_size = 64;
2981 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
2982 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
2983 } else {
2984 addr_size = 36;
2985 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
2986 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
2987 }
2988 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
2989
2990 pci_set_master(pdev);
2991
2992 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
2993 if (!ret)
2994 ret = pci_set_consistent_dma_mask(pdev,
2995 DMA_BIT_MASK(addr_size));
2996 if (ret) {
2997 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2998 if (!ret)
2999 ret = pci_set_consistent_dma_mask(pdev,
3000 DMA_BIT_MASK(32));
3001 /* both attempts failed: */
3002 if (ret) {
3003 dev_err(&pdev->dev, "No suitable DMA available\n");
3004 goto out_no_pci;
3005 }
3006 }
3007
3008 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3009 if (ret) {
3010 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3011 goto out_no_pci;
3012 }
3013
3014 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
3015 if (!trans_pcie->hw_base) {
3016 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3017 ret = -ENODEV;
3018 goto out_no_pci;
3019 }
3020
3021 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3022 * PCI Tx retries from interfering with C3 CPU state */
3023 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3024
3025 trans->dev = &pdev->dev;
3026 trans_pcie->pci_dev = pdev;
3027 iwl_disable_interrupts(trans);
3028
3029 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3030 /*
3031 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3032 * changed, and now the revision step also includes bit 0-1 (no more
3033 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3034 * in the old format.
3035 */
3036 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
3037 unsigned long flags;
3038
3039 trans->hw_rev = (trans->hw_rev & 0xfff0) |
3040 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3041
3042 ret = iwl_pcie_prepare_card_hw(trans);
3043 if (ret) {
3044 IWL_WARN(trans, "Exit HW not ready\n");
3045 goto out_no_pci;
3046 }
3047
3048 /*
3049 * in-order to recognize C step driver should read chip version
3050 * id located at the AUX bus MISC address space.
3051 */
3052 iwl_set_bit(trans, CSR_GP_CNTRL,
3053 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3054 udelay(2);
3055
3056 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3057 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3058 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3059 25000);
3060 if (ret < 0) {
3061 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
3062 goto out_no_pci;
3063 }
3064
3065 if (iwl_trans_grab_nic_access(trans, &flags)) {
3066 u32 hw_step;
3067
3068 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
3069 hw_step |= ENABLE_WFPM;
3070 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3071 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
3072 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3073 if (hw_step == 0x3)
3074 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3075 (SILICON_C_STEP << 2);
3076 iwl_trans_release_nic_access(trans, &flags);
3077 }
3078 }
3079
3080 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3081
3082 iwl_pcie_set_interrupt_capa(pdev, trans);
3083 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3084 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3085 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3086
3087 /* Initialize the wait queue for commands */
3088 init_waitqueue_head(&trans_pcie->wait_command_queue);
3089
3090 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3091
3092 if (trans_pcie->msix_enabled) {
3093 if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
3094 goto out_no_pci;
3095 } else {
3096 ret = iwl_pcie_alloc_ict(trans);
3097 if (ret)
3098 goto out_no_pci;
3099
3100 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3101 iwl_pcie_isr,
3102 iwl_pcie_irq_handler,
3103 IRQF_SHARED, DRV_NAME, trans);
3104 if (ret) {
3105 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3106 goto out_free_ict;
3107 }
3108 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3109 }
3110
3111 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
3112 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3113 #else
3114 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3115 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3116
3117 return trans;
3118
3119 out_free_ict:
3120 iwl_pcie_free_ict(trans);
3121 out_no_pci:
3122 free_percpu(trans_pcie->tso_hdr_page);
3123 iwl_trans_free(trans);
3124 return ERR_PTR(ret);
3125 }
(deprecated) Btrfs devel tree