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[media] s5h1420: fix a buffer overflow when checking userspace params
[linux-2.6/btrfs-unstable.git] / drivers / dma / at_xdmac.c
blob933e4b338459284465d7970e3ff7dbf0f37314b8
1 /*
2 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
3 *
4 * Copyright (C) 2014 Atmel Corporation
5 *
6 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include <asm/barrier.h>
22 #include <dt-bindings/dma/at91.h>
23 #include <linux/clk.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dmapool.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/kernel.h>
29 #include <linux/list.h>
30 #include <linux/module.h>
31 #include <linux/of_dma.h>
32 #include <linux/of_platform.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm.h>
35
36 #include "dmaengine.h"
37
38 /* Global registers */
39 #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */
40 #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
41 #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
42 #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
43 #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
44 #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
45 #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
46 #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
47 #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
48 #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */
49 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
50 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
51 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
52 #define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */
53 #define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */
54 #define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */
55 #define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */
56 #define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */
57 #define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */
58 #define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */
59 #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
60
61 /* Channel relative registers offsets */
62 #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
63 #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */
64 #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
65 #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */
66 #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
67 #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */
68 #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */
69 #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */
70 #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
71 #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */
72 #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
73 #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */
74 #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
75 #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */
76 #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */
77 #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */
78 #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */
79 #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */
80 #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
81 #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */
82 #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
83 #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */
84 #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */
85 #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */
86 #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */
87 #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */
88 #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
89 #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */
90 #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
91 #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */
92 #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */
93 #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */
94 #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */
95 #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */
96 #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */
97 #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */
98 #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */
99 #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */
100 #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
101 #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
102 #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
103 #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
104 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
105 #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
106 #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
107 #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */
108 #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */
109 #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */
110 #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */
111 #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */
112 #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */
113 #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
114 #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
115 #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1)
116 #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1)
117 #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1)
118 #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */
119 #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4)
120 #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4)
121 #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */
122 #define AT_XDMAC_CC_PROT_SEC (0x0 << 5)
123 #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5)
124 #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */
125 #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
126 #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
127 #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */
128 #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7)
129 #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7)
130 #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */
131 #define AT_XDMAC_CC_DWIDTH_OFFSET 11
132 #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
133 #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */
134 #define AT_XDMAC_CC_DWIDTH_BYTE 0x0
135 #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1
136 #define AT_XDMAC_CC_DWIDTH_WORD 0x2
137 #define AT_XDMAC_CC_DWIDTH_DWORD 0x3
138 #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */
139 #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */
140 #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
141 #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16)
142 #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16)
143 #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16)
144 #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16)
145 #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
146 #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18)
147 #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18)
148 #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18)
149 #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18)
150 #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */
151 #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21)
152 #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21)
153 #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */
154 #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22)
155 #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22)
156 #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
157 #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
158 #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
159 #define AT_XDMAC_CC_PERID(i) (0x7f & (h) << 24) /* Channel Peripheral Identifier */
160 #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
161 #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
162 #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
163
164 #define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */
165
166 /* Microblock control members */
167 #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
168 #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
169 #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */
170 #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */
171 #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */
172 #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */
173 #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */
174 #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
175
176 #define AT_XDMAC_MAX_CHAN 0x20
177
178 #define AT_XDMAC_DMA_BUSWIDTHS\
179 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
180 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
181 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
182 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\
183 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
184
185 enum atc_status {
186 AT_XDMAC_CHAN_IS_CYCLIC = 0,
187 AT_XDMAC_CHAN_IS_PAUSED,
188 };
189
190 /* ----- Channels ----- */
191 struct at_xdmac_chan {
192 struct dma_chan chan;
193 void __iomem *ch_regs;
194 u32 mask; /* Channel Mask */
195 u32 cfg[2]; /* Channel Configuration Register */
196 #define AT_XDMAC_DEV_TO_MEM_CFG 0 /* Predifined dev to mem channel conf */
197 #define AT_XDMAC_MEM_TO_DEV_CFG 1 /* Predifined mem to dev channel conf */
198 u8 perid; /* Peripheral ID */
199 u8 perif; /* Peripheral Interface */
200 u8 memif; /* Memory Interface */
201 u32 per_src_addr;
202 u32 per_dst_addr;
203 u32 save_cc;
204 u32 save_cim;
205 u32 save_cnda;
206 u32 save_cndc;
207 unsigned long status;
208 struct tasklet_struct tasklet;
209
210 spinlock_t lock;
211
212 struct list_head xfers_list;
213 struct list_head free_descs_list;
214 };
215
216
217 /* ----- Controller ----- */
218 struct at_xdmac {
219 struct dma_device dma;
220 void __iomem *regs;
221 int irq;
222 struct clk *clk;
223 u32 save_gim;
224 u32 save_gs;
225 struct dma_pool *at_xdmac_desc_pool;
226 struct at_xdmac_chan chan[0];
227 };
228
229
230 /* ----- Descriptors ----- */
231
232 /* Linked List Descriptor */
233 struct at_xdmac_lld {
234 dma_addr_t mbr_nda; /* Next Descriptor Member */
235 u32 mbr_ubc; /* Microblock Control Member */
236 dma_addr_t mbr_sa; /* Source Address Member */
237 dma_addr_t mbr_da; /* Destination Address Member */
238 u32 mbr_cfg; /* Configuration Register */
239 };
240
241
242 struct at_xdmac_desc {
243 struct at_xdmac_lld lld;
244 enum dma_transfer_direction direction;
245 struct dma_async_tx_descriptor tx_dma_desc;
246 struct list_head desc_node;
247 /* Following members are only used by the first descriptor */
248 bool active_xfer;
249 unsigned int xfer_size;
250 struct list_head descs_list;
251 struct list_head xfer_node;
252 };
253
254 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
255 {
256 return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);
257 }
258
259 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
260 #define at_xdmac_write(atxdmac, reg, value) \
261 writel_relaxed((value), (atxdmac)->regs + (reg))
262
263 #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg))
264 #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
265
266 static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan)
267 {
268 return container_of(dchan, struct at_xdmac_chan, chan);
269 }
270
271 static struct device *chan2dev(struct dma_chan *chan)
272 {
273 return &chan->dev->device;
274 }
275
276 static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev)
277 {
278 return container_of(ddev, struct at_xdmac, dma);
279 }
280
281 static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd)
282 {
283 return container_of(txd, struct at_xdmac_desc, tx_dma_desc);
284 }
285
286 static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan)
287 {
288 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
289 }
290
291 static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan)
292 {
293 return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
294 }
295
296 static inline int at_xdmac_csize(u32 maxburst)
297 {
298 int csize;
299
300 csize = ffs(maxburst) - 1;
301 if (csize > 4)
302 csize = -EINVAL;
303
304 return csize;
305 };
306
307 static inline u8 at_xdmac_get_dwidth(u32 cfg)
308 {
309 return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET;
310 };
311
312 static unsigned int init_nr_desc_per_channel = 64;
313 module_param(init_nr_desc_per_channel, uint, 0644);
314 MODULE_PARM_DESC(init_nr_desc_per_channel,
315 "initial descriptors per channel (default: 64)");
316
317
318 static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan)
319 {
320 return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask;
321 }
322
323 static void at_xdmac_off(struct at_xdmac *atxdmac)
324 {
325 at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L);
326
327 /* Wait that all chans are disabled. */
328 while (at_xdmac_read(atxdmac, AT_XDMAC_GS))
329 cpu_relax();
330
331 at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L);
332 }
333
334 /* Call with lock hold. */
335 static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
336 struct at_xdmac_desc *first)
337 {
338 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
339 u32 reg;
340
341 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first);
342
343 if (at_xdmac_chan_is_enabled(atchan))
344 return;
345
346 /* Set transfer as active to not try to start it again. */
347 first->active_xfer = true;
348
349 /* Tell xdmac where to get the first descriptor. */
350 reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)
351 | AT_XDMAC_CNDA_NDAIF(atchan->memif);
352 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
353
354 /*
355 * When doing non cyclic transfer we need to use the next
356 * descriptor view 2 since some fields of the configuration register
357 * depend on transfer size and src/dest addresses.
358 */
359 if (at_xdmac_chan_is_cyclic(atchan)) {
360 reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
361 at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
362 } else {
363 /*
364 * No need to write AT_XDMAC_CC reg, it will be done when the
365 * descriptor is fecthed.
366 */
367 reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
368 }
369
370 reg |= AT_XDMAC_CNDC_NDDUP
371 | AT_XDMAC_CNDC_NDSUP
372 | AT_XDMAC_CNDC_NDE;
373 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg);
374
375 dev_vdbg(chan2dev(&atchan->chan),
376 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
377 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
378 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
379 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
380 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
381 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
382 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
383
384 at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff);
385 reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE | AT_XDMAC_CIE_ROIE;
386 /*
387 * There is no end of list when doing cyclic dma, we need to get
388 * an interrupt after each periods.
389 */
390 if (at_xdmac_chan_is_cyclic(atchan))
391 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
392 reg | AT_XDMAC_CIE_BIE);
393 else
394 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
395 reg | AT_XDMAC_CIE_LIE);
396 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask);
397 dev_vdbg(chan2dev(&atchan->chan),
398 "%s: enable channel (0x%08x)\n", __func__, atchan->mask);
399 wmb();
400 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
401
402 dev_vdbg(chan2dev(&atchan->chan),
403 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
404 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
405 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
406 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
407 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
408 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
409 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
410
411 }
412
413 static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx)
414 {
415 struct at_xdmac_desc *desc = txd_to_at_desc(tx);
416 struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan);
417 dma_cookie_t cookie;
418
419 spin_lock_bh(&atchan->lock);
420 cookie = dma_cookie_assign(tx);
421
422 dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n",
423 __func__, atchan, desc);
424 list_add_tail(&desc->xfer_node, &atchan->xfers_list);
425 if (list_is_singular(&atchan->xfers_list))
426 at_xdmac_start_xfer(atchan, desc);
427
428 spin_unlock_bh(&atchan->lock);
429 return cookie;
430 }
431
432 static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan,
433 gfp_t gfp_flags)
434 {
435 struct at_xdmac_desc *desc;
436 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
437 dma_addr_t phys;
438
439 desc = dma_pool_alloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys);
440 if (desc) {
441 memset(desc, 0, sizeof(*desc));
442 INIT_LIST_HEAD(&desc->descs_list);
443 dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan);
444 desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit;
445 desc->tx_dma_desc.phys = phys;
446 }
447
448 return desc;
449 }
450
451 /* Call must be protected by lock. */
452 static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan)
453 {
454 struct at_xdmac_desc *desc;
455
456 if (list_empty(&atchan->free_descs_list)) {
457 desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT);
458 } else {
459 desc = list_first_entry(&atchan->free_descs_list,
460 struct at_xdmac_desc, desc_node);
461 list_del(&desc->desc_node);
462 desc->active_xfer = false;
463 }
464
465 return desc;
466 }
467
468 static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
469 struct of_dma *of_dma)
470 {
471 struct at_xdmac *atxdmac = of_dma->of_dma_data;
472 struct at_xdmac_chan *atchan;
473 struct dma_chan *chan;
474 struct device *dev = atxdmac->dma.dev;
475
476 if (dma_spec->args_count != 1) {
477 dev_err(dev, "dma phandler args: bad number of args\n");
478 return NULL;
479 }
480
481 chan = dma_get_any_slave_channel(&atxdmac->dma);
482 if (!chan) {
483 dev_err(dev, "can't get a dma channel\n");
484 return NULL;
485 }
486
487 atchan = to_at_xdmac_chan(chan);
488 atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]);
489 atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]);
490 atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]);
491 dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n",
492 atchan->memif, atchan->perif, atchan->perid);
493
494 return chan;
495 }
496
497 static int at_xdmac_set_slave_config(struct dma_chan *chan,
498 struct dma_slave_config *sconfig)
499 {
500 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
501 u8 dwidth;
502 int csize;
503
504 atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] =
505 AT91_XDMAC_DT_PERID(atchan->perid)
506 | AT_XDMAC_CC_DAM_INCREMENTED_AM
507 | AT_XDMAC_CC_SAM_FIXED_AM
508 | AT_XDMAC_CC_DIF(atchan->memif)
509 | AT_XDMAC_CC_SIF(atchan->perif)
510 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
511 | AT_XDMAC_CC_DSYNC_PER2MEM
512 | AT_XDMAC_CC_MBSIZE_SIXTEEN
513 | AT_XDMAC_CC_TYPE_PER_TRAN;
514 csize = at_xdmac_csize(sconfig->src_maxburst);
515 if (csize < 0) {
516 dev_err(chan2dev(chan), "invalid src maxburst value\n");
517 return -EINVAL;
518 }
519 atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] |= AT_XDMAC_CC_CSIZE(csize);
520 dwidth = ffs(sconfig->src_addr_width) - 1;
521 atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] |= AT_XDMAC_CC_DWIDTH(dwidth);
522
523
524 atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] =
525 AT91_XDMAC_DT_PERID(atchan->perid)
526 | AT_XDMAC_CC_DAM_FIXED_AM
527 | AT_XDMAC_CC_SAM_INCREMENTED_AM
528 | AT_XDMAC_CC_DIF(atchan->perif)
529 | AT_XDMAC_CC_SIF(atchan->memif)
530 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
531 | AT_XDMAC_CC_DSYNC_MEM2PER
532 | AT_XDMAC_CC_MBSIZE_SIXTEEN
533 | AT_XDMAC_CC_TYPE_PER_TRAN;
534 csize = at_xdmac_csize(sconfig->dst_maxburst);
535 if (csize < 0) {
536 dev_err(chan2dev(chan), "invalid src maxburst value\n");
537 return -EINVAL;
538 }
539 atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] |= AT_XDMAC_CC_CSIZE(csize);
540 dwidth = ffs(sconfig->dst_addr_width) - 1;
541 atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] |= AT_XDMAC_CC_DWIDTH(dwidth);
542
543 /* Src and dst addr are needed to configure the link list descriptor. */
544 atchan->per_src_addr = sconfig->src_addr;
545 atchan->per_dst_addr = sconfig->dst_addr;
546
547 dev_dbg(chan2dev(chan),
548 "%s: cfg[dev2mem]=0x%08x, cfg[mem2dev]=0x%08x, per_src_addr=0x%08x, per_dst_addr=0x%08x\n",
549 __func__, atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG],
550 atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG],
551 atchan->per_src_addr, atchan->per_dst_addr);
552
553 return 0;
554 }
555
556 static struct dma_async_tx_descriptor *
557 at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
558 unsigned int sg_len, enum dma_transfer_direction direction,
559 unsigned long flags, void *context)
560 {
561 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
562 struct at_xdmac_desc *first = NULL, *prev = NULL;
563 struct scatterlist *sg;
564 int i;
565 unsigned int xfer_size = 0;
566
567 if (!sgl)
568 return NULL;
569
570 if (!is_slave_direction(direction)) {
571 dev_err(chan2dev(chan), "invalid DMA direction\n");
572 return NULL;
573 }
574
575 dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n",
576 __func__, sg_len,
577 direction == DMA_MEM_TO_DEV ? "to device" : "from device",
578 flags);
579
580 /* Protect dma_sconfig field that can be modified by set_slave_conf. */
581 spin_lock_bh(&atchan->lock);
582
583 /* Prepare descriptors. */
584 for_each_sg(sgl, sg, sg_len, i) {
585 struct at_xdmac_desc *desc = NULL;
586 u32 len, mem, dwidth, fixed_dwidth;
587
588 len = sg_dma_len(sg);
589 mem = sg_dma_address(sg);
590 if (unlikely(!len)) {
591 dev_err(chan2dev(chan), "sg data length is zero\n");
592 spin_unlock_bh(&atchan->lock);
593 return NULL;
594 }
595 dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n",
596 __func__, i, len, mem);
597
598 desc = at_xdmac_get_desc(atchan);
599 if (!desc) {
600 dev_err(chan2dev(chan), "can't get descriptor\n");
601 if (first)
602 list_splice_init(&first->descs_list, &atchan->free_descs_list);
603 spin_unlock_bh(&atchan->lock);
604 return NULL;
605 }
606
607 /* Linked list descriptor setup. */
608 if (direction == DMA_DEV_TO_MEM) {
609 desc->lld.mbr_sa = atchan->per_src_addr;
610 desc->lld.mbr_da = mem;
611 desc->lld.mbr_cfg = atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG];
612 } else {
613 desc->lld.mbr_sa = mem;
614 desc->lld.mbr_da = atchan->per_dst_addr;
615 desc->lld.mbr_cfg = atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG];
616 }
617 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
618 fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
619 ? at_xdmac_get_dwidth(desc->lld.mbr_cfg)
620 : AT_XDMAC_CC_DWIDTH_BYTE;
621 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */
622 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */
623 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */
624 | (i == sg_len - 1 ? 0 : AT_XDMAC_MBR_UBC_NDE) /* descriptor fetch */
625 | (len >> fixed_dwidth); /* microblock length */
626 dev_dbg(chan2dev(chan),
627 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
628 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
629
630 /* Chain lld. */
631 if (prev) {
632 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
633 dev_dbg(chan2dev(chan),
634 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
635 __func__, prev, &prev->lld.mbr_nda);
636 }
637
638 prev = desc;
639 if (!first)
640 first = desc;
641
642 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
643 __func__, desc, first);
644 list_add_tail(&desc->desc_node, &first->descs_list);
645 xfer_size += len;
646 }
647
648 spin_unlock_bh(&atchan->lock);
649
650 first->tx_dma_desc.flags = flags;
651 first->xfer_size = xfer_size;
652 first->direction = direction;
653
654 return &first->tx_dma_desc;
655 }
656
657 static struct dma_async_tx_descriptor *
658 at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
659 size_t buf_len, size_t period_len,
660 enum dma_transfer_direction direction,
661 unsigned long flags)
662 {
663 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
664 struct at_xdmac_desc *first = NULL, *prev = NULL;
665 unsigned int periods = buf_len / period_len;
666 int i;
667
668 dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
669 __func__, &buf_addr, buf_len, period_len,
670 direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags);
671
672 if (!is_slave_direction(direction)) {
673 dev_err(chan2dev(chan), "invalid DMA direction\n");
674 return NULL;
675 }
676
677 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) {
678 dev_err(chan2dev(chan), "channel currently used\n");
679 return NULL;
680 }
681
682 for (i = 0; i < periods; i++) {
683 struct at_xdmac_desc *desc = NULL;
684
685 spin_lock_bh(&atchan->lock);
686 desc = at_xdmac_get_desc(atchan);
687 if (!desc) {
688 dev_err(chan2dev(chan), "can't get descriptor\n");
689 if (first)
690 list_splice_init(&first->descs_list, &atchan->free_descs_list);
691 spin_unlock_bh(&atchan->lock);
692 return NULL;
693 }
694 spin_unlock_bh(&atchan->lock);
695 dev_dbg(chan2dev(chan),
696 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
697 __func__, desc, &desc->tx_dma_desc.phys);
698
699 if (direction == DMA_DEV_TO_MEM) {
700 desc->lld.mbr_sa = atchan->per_src_addr;
701 desc->lld.mbr_da = buf_addr + i * period_len;
702 desc->lld.mbr_cfg = atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG];
703 } else {
704 desc->lld.mbr_sa = buf_addr + i * period_len;
705 desc->lld.mbr_da = atchan->per_dst_addr;
706 desc->lld.mbr_cfg = atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG];
707 }
708 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
709 | AT_XDMAC_MBR_UBC_NDEN
710 | AT_XDMAC_MBR_UBC_NSEN
711 | AT_XDMAC_MBR_UBC_NDE
712 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg);
713
714 dev_dbg(chan2dev(chan),
715 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
716 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
717
718 /* Chain lld. */
719 if (prev) {
720 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
721 dev_dbg(chan2dev(chan),
722 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
723 __func__, prev, &prev->lld.mbr_nda);
724 }
725
726 prev = desc;
727 if (!first)
728 first = desc;
729
730 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
731 __func__, desc, first);
732 list_add_tail(&desc->desc_node, &first->descs_list);
733 }
734
735 prev->lld.mbr_nda = first->tx_dma_desc.phys;
736 dev_dbg(chan2dev(chan),
737 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
738 __func__, prev, &prev->lld.mbr_nda);
739 first->tx_dma_desc.flags = flags;
740 first->xfer_size = buf_len;
741 first->direction = direction;
742
743 return &first->tx_dma_desc;
744 }
745
746 static struct dma_async_tx_descriptor *
747 at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
748 size_t len, unsigned long flags)
749 {
750 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
751 struct at_xdmac_desc *first = NULL, *prev = NULL;
752 size_t remaining_size = len, xfer_size = 0, ublen;
753 dma_addr_t src_addr = src, dst_addr = dest;
754 u32 dwidth;
755 /*
756 * WARNING: We don't know the direction, it involves we can't
757 * dynamically set the source and dest interface so we have to use the
758 * same one. Only interface 0 allows EBI access. Hopefully we can
759 * access DDR through both ports (at least on SAMA5D4x), so we can use
760 * the same interface for source and dest, that solves the fact we
761 * don't know the direction.
762 */
763 u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
764 | AT_XDMAC_CC_SAM_INCREMENTED_AM
765 | AT_XDMAC_CC_DIF(0)
766 | AT_XDMAC_CC_SIF(0)
767 | AT_XDMAC_CC_MBSIZE_SIXTEEN
768 | AT_XDMAC_CC_TYPE_MEM_TRAN;
769
770 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
771 __func__, &src, &dest, len, flags);
772
773 if (unlikely(!len))
774 return NULL;
775
776 /*
777 * Check address alignment to select the greater data width we can use.
778 * Some XDMAC implementations don't provide dword transfer, in this
779 * case selecting dword has the same behavior as selecting word transfers.
780 */
781 if (!((src_addr | dst_addr) & 7)) {
782 dwidth = AT_XDMAC_CC_DWIDTH_DWORD;
783 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
784 } else if (!((src_addr | dst_addr) & 3)) {
785 dwidth = AT_XDMAC_CC_DWIDTH_WORD;
786 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
787 } else if (!((src_addr | dst_addr) & 1)) {
788 dwidth = AT_XDMAC_CC_DWIDTH_HALFWORD;
789 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
790 } else {
791 dwidth = AT_XDMAC_CC_DWIDTH_BYTE;
792 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
793 }
794
795 /* Prepare descriptors. */
796 while (remaining_size) {
797 struct at_xdmac_desc *desc = NULL;
798
799 dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size);
800
801 spin_lock_bh(&atchan->lock);
802 desc = at_xdmac_get_desc(atchan);
803 spin_unlock_bh(&atchan->lock);
804 if (!desc) {
805 dev_err(chan2dev(chan), "can't get descriptor\n");
806 if (first)
807 list_splice_init(&first->descs_list, &atchan->free_descs_list);
808 return NULL;
809 }
810
811 /* Update src and dest addresses. */
812 src_addr += xfer_size;
813 dst_addr += xfer_size;
814
815 if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)
816 xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth;
817 else
818 xfer_size = remaining_size;
819
820 dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size);
821
822 /* Check remaining length and change data width if needed. */
823 if (!((src_addr | dst_addr | xfer_size) & 7)) {
824 dwidth = AT_XDMAC_CC_DWIDTH_DWORD;
825 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
826 } else if (!((src_addr | dst_addr | xfer_size) & 3)) {
827 dwidth = AT_XDMAC_CC_DWIDTH_WORD;
828 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
829 } else if (!((src_addr | dst_addr | xfer_size) & 1)) {
830 dwidth = AT_XDMAC_CC_DWIDTH_HALFWORD;
831 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
832 } else if ((src_addr | dst_addr | xfer_size) & 1) {
833 dwidth = AT_XDMAC_CC_DWIDTH_BYTE;
834 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
835 }
836 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
837
838 ublen = xfer_size >> dwidth;
839 remaining_size -= xfer_size;
840
841 desc->lld.mbr_sa = src_addr;
842 desc->lld.mbr_da = dst_addr;
843 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2
844 | AT_XDMAC_MBR_UBC_NDEN
845 | AT_XDMAC_MBR_UBC_NSEN
846 | (remaining_size ? AT_XDMAC_MBR_UBC_NDE : 0)
847 | ublen;
848 desc->lld.mbr_cfg = chan_cc;
849
850 dev_dbg(chan2dev(chan),
851 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
852 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
853
854 /* Chain lld. */
855 if (prev) {
856 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
857 dev_dbg(chan2dev(chan),
858 "%s: chain lld: prev=0x%p, mbr_nda=0x%08x\n",
859 __func__, prev, prev->lld.mbr_nda);
860 }
861
862 prev = desc;
863 if (!first)
864 first = desc;
865
866 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
867 __func__, desc, first);
868 list_add_tail(&desc->desc_node, &first->descs_list);
869 }
870
871 first->tx_dma_desc.flags = flags;
872 first->xfer_size = len;
873
874 return &first->tx_dma_desc;
875 }
876
877 static enum dma_status
878 at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
879 struct dma_tx_state *txstate)
880 {
881 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
882 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
883 struct at_xdmac_desc *desc, *_desc;
884 struct list_head *descs_list;
885 enum dma_status ret;
886 int residue;
887 u32 cur_nda, mask, value;
888 u8 dwidth = 0;
889
890 ret = dma_cookie_status(chan, cookie, txstate);
891 if (ret == DMA_COMPLETE)
892 return ret;
893
894 if (!txstate)
895 return ret;
896
897 spin_lock_bh(&atchan->lock);
898
899 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
900
901 /*
902 * If the transfer has not been started yet, don't need to compute the
903 * residue, it's the transfer length.
904 */
905 if (!desc->active_xfer) {
906 dma_set_residue(txstate, desc->xfer_size);
907 spin_unlock_bh(&atchan->lock);
908 return ret;
909 }
910
911 residue = desc->xfer_size;
912 /*
913 * Flush FIFO: only relevant when the transfer is source peripheral
914 * synchronized.
915 */
916 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
917 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
918 if ((desc->lld.mbr_cfg & mask) == value) {
919 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
920 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
921 cpu_relax();
922 }
923
924 cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
925 /*
926 * Remove size of all microblocks already transferred and the current
927 * one. Then add the remaining size to transfer of the current
928 * microblock.
929 */
930 descs_list = &desc->descs_list;
931 list_for_each_entry_safe(desc, _desc, descs_list, desc_node) {
932 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
933 residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth;
934 if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda)
935 break;
936 }
937 residue += at_xdmac_chan_read(atchan, AT_XDMAC_CUBC) << dwidth;
938
939 spin_unlock_bh(&atchan->lock);
940
941 dma_set_residue(txstate, residue);
942
943 dev_dbg(chan2dev(chan),
944 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
945 __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue);
946
947 return ret;
948 }
949
950 /* Call must be protected by lock. */
951 static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan,
952 struct at_xdmac_desc *desc)
953 {
954 dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
955
956 /*
957 * Remove the transfer from the transfer list then move the transfer
958 * descriptors into the free descriptors list.
959 */
960 list_del(&desc->xfer_node);
961 list_splice_init(&desc->descs_list, &atchan->free_descs_list);
962 }
963
964 static void at_xdmac_advance_work(struct at_xdmac_chan *atchan)
965 {
966 struct at_xdmac_desc *desc;
967
968 spin_lock_bh(&atchan->lock);
969
970 /*
971 * If channel is enabled, do nothing, advance_work will be triggered
972 * after the interruption.
973 */
974 if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) {
975 desc = list_first_entry(&atchan->xfers_list,
976 struct at_xdmac_desc,
977 xfer_node);
978 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
979 if (!desc->active_xfer)
980 at_xdmac_start_xfer(atchan, desc);
981 }
982
983 spin_unlock_bh(&atchan->lock);
984 }
985
986 static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan)
987 {
988 struct at_xdmac_desc *desc;
989 struct dma_async_tx_descriptor *txd;
990
991 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
992 txd = &desc->tx_dma_desc;
993
994 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
995 txd->callback(txd->callback_param);
996 }
997
998 static void at_xdmac_tasklet(unsigned long data)
999 {
1000 struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data;
1001 struct at_xdmac_desc *desc;
1002 u32 error_mask;
1003
1004 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08lx\n",
1005 __func__, atchan->status);
1006
1007 error_mask = AT_XDMAC_CIS_RBEIS
1008 | AT_XDMAC_CIS_WBEIS
1009 | AT_XDMAC_CIS_ROIS;
1010
1011 if (at_xdmac_chan_is_cyclic(atchan)) {
1012 at_xdmac_handle_cyclic(atchan);
1013 } else if ((atchan->status & AT_XDMAC_CIS_LIS)
1014 || (atchan->status & error_mask)) {
1015 struct dma_async_tx_descriptor *txd;
1016
1017 if (atchan->status & AT_XDMAC_CIS_RBEIS)
1018 dev_err(chan2dev(&atchan->chan), "read bus error!!!");
1019 if (atchan->status & AT_XDMAC_CIS_WBEIS)
1020 dev_err(chan2dev(&atchan->chan), "write bus error!!!");
1021 if (atchan->status & AT_XDMAC_CIS_ROIS)
1022 dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
1023
1024 spin_lock_bh(&atchan->lock);
1025 desc = list_first_entry(&atchan->xfers_list,
1026 struct at_xdmac_desc,
1027 xfer_node);
1028 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1029 BUG_ON(!desc->active_xfer);
1030
1031 txd = &desc->tx_dma_desc;
1032
1033 at_xdmac_remove_xfer(atchan, desc);
1034 spin_unlock_bh(&atchan->lock);
1035
1036 if (!at_xdmac_chan_is_cyclic(atchan)) {
1037 dma_cookie_complete(txd);
1038 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1039 txd->callback(txd->callback_param);
1040 }
1041
1042 dma_run_dependencies(txd);
1043
1044 at_xdmac_advance_work(atchan);
1045 }
1046 }
1047
1048 static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)
1049 {
1050 struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id;
1051 struct at_xdmac_chan *atchan;
1052 u32 imr, status, pending;
1053 u32 chan_imr, chan_status;
1054 int i, ret = IRQ_NONE;
1055
1056 do {
1057 imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1058 status = at_xdmac_read(atxdmac, AT_XDMAC_GIS);
1059 pending = status & imr;
1060
1061 dev_vdbg(atxdmac->dma.dev,
1062 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n",
1063 __func__, status, imr, pending);
1064
1065 if (!pending)
1066 break;
1067
1068 /* We have to find which channel has generated the interrupt. */
1069 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1070 if (!((1 << i) & pending))
1071 continue;
1072
1073 atchan = &atxdmac->chan[i];
1074 chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1075 chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS);
1076 atchan->status = chan_status & chan_imr;
1077 dev_vdbg(atxdmac->dma.dev,
1078 "%s: chan%d: imr=0x%x, status=0x%x\n",
1079 __func__, i, chan_imr, chan_status);
1080 dev_vdbg(chan2dev(&atchan->chan),
1081 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
1082 __func__,
1083 at_xdmac_chan_read(atchan, AT_XDMAC_CC),
1084 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
1085 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
1086 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
1087 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
1088 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
1089
1090 if (atchan->status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS))
1091 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1092
1093 tasklet_schedule(&atchan->tasklet);
1094 ret = IRQ_HANDLED;
1095 }
1096
1097 } while (pending);
1098
1099 return ret;
1100 }
1101
1102 static void at_xdmac_issue_pending(struct dma_chan *chan)
1103 {
1104 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1105
1106 dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__);
1107
1108 if (!at_xdmac_chan_is_cyclic(atchan))
1109 at_xdmac_advance_work(atchan);
1110
1111 return;
1112 }
1113
1114 static int at_xdmac_device_config(struct dma_chan *chan,
1115 struct dma_slave_config *config)
1116 {
1117 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1118 int ret;
1119
1120 dev_dbg(chan2dev(chan), "%s\n", __func__);
1121
1122 spin_lock_bh(&atchan->lock);
1123 ret = at_xdmac_set_slave_config(chan, config);
1124 spin_unlock_bh(&atchan->lock);
1125
1126 return ret;
1127 }
1128
1129 static int at_xdmac_device_pause(struct dma_chan *chan)
1130 {
1131 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1132 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1133
1134 dev_dbg(chan2dev(chan), "%s\n", __func__);
1135
1136 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status))
1137 return 0;
1138
1139 spin_lock_bh(&atchan->lock);
1140 at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);
1141 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
1142 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
1143 cpu_relax();
1144 spin_unlock_bh(&atchan->lock);
1145
1146 return 0;
1147 }
1148
1149 static int at_xdmac_device_resume(struct dma_chan *chan)
1150 {
1151 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1152 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1153
1154 dev_dbg(chan2dev(chan), "%s\n", __func__);
1155
1156 spin_lock_bh(&atchan->lock);
1157 if (!at_xdmac_chan_is_paused(atchan)) {
1158 spin_unlock_bh(&atchan->lock);
1159 return 0;
1160 }
1161
1162 at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);
1163 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1164 spin_unlock_bh(&atchan->lock);
1165
1166 return 0;
1167 }
1168
1169 static int at_xdmac_device_terminate_all(struct dma_chan *chan)
1170 {
1171 struct at_xdmac_desc *desc, *_desc;
1172 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1173 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1174
1175 dev_dbg(chan2dev(chan), "%s\n", __func__);
1176
1177 spin_lock_bh(&atchan->lock);
1178 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1179 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1180 cpu_relax();
1181
1182 /* Cancel all pending transfers. */
1183 list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node)
1184 at_xdmac_remove_xfer(atchan, desc);
1185
1186 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
1187 spin_unlock_bh(&atchan->lock);
1188
1189 return 0;
1190 }
1191
1192 static int at_xdmac_alloc_chan_resources(struct dma_chan *chan)
1193 {
1194 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1195 struct at_xdmac_desc *desc;
1196 int i;
1197
1198 spin_lock_bh(&atchan->lock);
1199
1200 if (at_xdmac_chan_is_enabled(atchan)) {
1201 dev_err(chan2dev(chan),
1202 "can't allocate channel resources (channel enabled)\n");
1203 i = -EIO;
1204 goto spin_unlock;
1205 }
1206
1207 if (!list_empty(&atchan->free_descs_list)) {
1208 dev_err(chan2dev(chan),
1209 "can't allocate channel resources (channel not free from a previous use)\n");
1210 i = -EIO;
1211 goto spin_unlock;
1212 }
1213
1214 for (i = 0; i < init_nr_desc_per_channel; i++) {
1215 desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC);
1216 if (!desc) {
1217 dev_warn(chan2dev(chan),
1218 "only %d descriptors have been allocated\n", i);
1219 break;
1220 }
1221 list_add_tail(&desc->desc_node, &atchan->free_descs_list);
1222 }
1223
1224 dma_cookie_init(chan);
1225
1226 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1227
1228 spin_unlock:
1229 spin_unlock_bh(&atchan->lock);
1230 return i;
1231 }
1232
1233 static void at_xdmac_free_chan_resources(struct dma_chan *chan)
1234 {
1235 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1236 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
1237 struct at_xdmac_desc *desc, *_desc;
1238
1239 list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) {
1240 dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc);
1241 list_del(&desc->desc_node);
1242 dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys);
1243 }
1244
1245 return;
1246 }
1247
1248 #ifdef CONFIG_PM
1249 static int atmel_xdmac_prepare(struct device *dev)
1250 {
1251 struct platform_device *pdev = to_platform_device(dev);
1252 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1253 struct dma_chan *chan, *_chan;
1254
1255 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1256 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1257
1258 /* Wait for transfer completion, except in cyclic case. */
1259 if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan))
1260 return -EAGAIN;
1261 }
1262 return 0;
1263 }
1264 #else
1265 # define atmel_xdmac_prepare NULL
1266 #endif
1267
1268 #ifdef CONFIG_PM_SLEEP
1269 static int atmel_xdmac_suspend(struct device *dev)
1270 {
1271 struct platform_device *pdev = to_platform_device(dev);
1272 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1273 struct dma_chan *chan, *_chan;
1274
1275 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1276 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1277
1278 atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC);
1279 if (at_xdmac_chan_is_cyclic(atchan)) {
1280 if (!at_xdmac_chan_is_paused(atchan))
1281 at_xdmac_device_pause(chan);
1282 atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1283 atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA);
1284 atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC);
1285 }
1286 }
1287 atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1288
1289 at_xdmac_off(atxdmac);
1290 clk_disable_unprepare(atxdmac->clk);
1291 return 0;
1292 }
1293
1294 static int atmel_xdmac_resume(struct device *dev)
1295 {
1296 struct platform_device *pdev = to_platform_device(dev);
1297 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1298 struct at_xdmac_chan *atchan;
1299 struct dma_chan *chan, *_chan;
1300 int i;
1301
1302 clk_prepare_enable(atxdmac->clk);
1303
1304 /* Clear pending interrupts. */
1305 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1306 atchan = &atxdmac->chan[i];
1307 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1308 cpu_relax();
1309 }
1310
1311 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim);
1312 at_xdmac_write(atxdmac, AT_XDMAC_GE, atxdmac->save_gs);
1313 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1314 atchan = to_at_xdmac_chan(chan);
1315 at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc);
1316 if (at_xdmac_chan_is_cyclic(atchan)) {
1317 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda);
1318 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc);
1319 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim);
1320 wmb();
1321 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
1322 }
1323 }
1324 return 0;
1325 }
1326 #endif /* CONFIG_PM_SLEEP */
1327
1328 static int at_xdmac_probe(struct platform_device *pdev)
1329 {
1330 struct resource *res;
1331 struct at_xdmac *atxdmac;
1332 int irq, size, nr_channels, i, ret;
1333 void __iomem *base;
1334 u32 reg;
1335
1336 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1337 if (!res)
1338 return -EINVAL;
1339
1340 irq = platform_get_irq(pdev, 0);
1341 if (irq < 0)
1342 return irq;
1343
1344 base = devm_ioremap_resource(&pdev->dev, res);
1345 if (IS_ERR(base))
1346 return PTR_ERR(base);
1347
1348 /*
1349 * Read number of xdmac channels, read helper function can't be used
1350 * since atxdmac is not yet allocated and we need to know the number
1351 * of channels to do the allocation.
1352 */
1353 reg = readl_relaxed(base + AT_XDMAC_GTYPE);
1354 nr_channels = AT_XDMAC_NB_CH(reg);
1355 if (nr_channels > AT_XDMAC_MAX_CHAN) {
1356 dev_err(&pdev->dev, "invalid number of channels (%u)\n",
1357 nr_channels);
1358 return -EINVAL;
1359 }
1360
1361 size = sizeof(*atxdmac);
1362 size += nr_channels * sizeof(struct at_xdmac_chan);
1363 atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1364 if (!atxdmac) {
1365 dev_err(&pdev->dev, "can't allocate at_xdmac structure\n");
1366 return -ENOMEM;
1367 }
1368
1369 atxdmac->regs = base;
1370 atxdmac->irq = irq;
1371
1372 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
1373 if (IS_ERR(atxdmac->clk)) {
1374 dev_err(&pdev->dev, "can't get dma_clk\n");
1375 return PTR_ERR(atxdmac->clk);
1376 }
1377
1378 /* Do not use dev res to prevent races with tasklet */
1379 ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac);
1380 if (ret) {
1381 dev_err(&pdev->dev, "can't request irq\n");
1382 return ret;
1383 }
1384
1385 ret = clk_prepare_enable(atxdmac->clk);
1386 if (ret) {
1387 dev_err(&pdev->dev, "can't prepare or enable clock\n");
1388 goto err_free_irq;
1389 }
1390
1391 atxdmac->at_xdmac_desc_pool =
1392 dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
1393 sizeof(struct at_xdmac_desc), 4, 0);
1394 if (!atxdmac->at_xdmac_desc_pool) {
1395 dev_err(&pdev->dev, "no memory for descriptors dma pool\n");
1396 ret = -ENOMEM;
1397 goto err_clk_disable;
1398 }
1399
1400 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
1401 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
1402 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
1403 /*
1404 * Without DMA_PRIVATE the driver is not able to allocate more than
1405 * one channel, second allocation fails in private_candidate.
1406 */
1407 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
1408 atxdmac->dma.dev = &pdev->dev;
1409 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
1410 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
1411 atxdmac->dma.device_tx_status = at_xdmac_tx_status;
1412 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
1413 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
1414 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
1415 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
1416 atxdmac->dma.device_config = at_xdmac_device_config;
1417 atxdmac->dma.device_pause = at_xdmac_device_pause;
1418 atxdmac->dma.device_resume = at_xdmac_device_resume;
1419 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all;
1420 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1421 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1422 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1423 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1424
1425 /* Disable all chans and interrupts. */
1426 at_xdmac_off(atxdmac);
1427
1428 /* Init channels. */
1429 INIT_LIST_HEAD(&atxdmac->dma.channels);
1430 for (i = 0; i < nr_channels; i++) {
1431 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1432
1433 atchan->chan.device = &atxdmac->dma;
1434 list_add_tail(&atchan->chan.device_node,
1435 &atxdmac->dma.channels);
1436
1437 atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i);
1438 atchan->mask = 1 << i;
1439
1440 spin_lock_init(&atchan->lock);
1441 INIT_LIST_HEAD(&atchan->xfers_list);
1442 INIT_LIST_HEAD(&atchan->free_descs_list);
1443 tasklet_init(&atchan->tasklet, at_xdmac_tasklet,
1444 (unsigned long)atchan);
1445
1446 /* Clear pending interrupts. */
1447 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1448 cpu_relax();
1449 }
1450 platform_set_drvdata(pdev, atxdmac);
1451
1452 ret = dma_async_device_register(&atxdmac->dma);
1453 if (ret) {
1454 dev_err(&pdev->dev, "fail to register DMA engine device\n");
1455 goto err_clk_disable;
1456 }
1457
1458 ret = of_dma_controller_register(pdev->dev.of_node,
1459 at_xdmac_xlate, atxdmac);
1460 if (ret) {
1461 dev_err(&pdev->dev, "could not register of dma controller\n");
1462 goto err_dma_unregister;
1463 }
1464
1465 dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
1466 nr_channels, atxdmac->regs);
1467
1468 return 0;
1469
1470 err_dma_unregister:
1471 dma_async_device_unregister(&atxdmac->dma);
1472 err_clk_disable:
1473 clk_disable_unprepare(atxdmac->clk);
1474 err_free_irq:
1475 free_irq(atxdmac->irq, atxdmac->dma.dev);
1476 return ret;
1477 }
1478
1479 static int at_xdmac_remove(struct platform_device *pdev)
1480 {
1481 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
1482 int i;
1483
1484 at_xdmac_off(atxdmac);
1485 of_dma_controller_free(pdev->dev.of_node);
1486 dma_async_device_unregister(&atxdmac->dma);
1487 clk_disable_unprepare(atxdmac->clk);
1488
1489 synchronize_irq(atxdmac->irq);
1490
1491 free_irq(atxdmac->irq, atxdmac->dma.dev);
1492
1493 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1494 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1495
1496 tasklet_kill(&atchan->tasklet);
1497 at_xdmac_free_chan_resources(&atchan->chan);
1498 }
1499
1500 return 0;
1501 }
1502
1503 static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = {
1504 .prepare = atmel_xdmac_prepare,
1505 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume)
1506 };
1507
1508 static const struct of_device_id atmel_xdmac_dt_ids[] = {
1509 {
1510 .compatible = "atmel,sama5d4-dma",
1511 }, {
1512 /* sentinel */
1513 }
1514 };
1515 MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids);
1516
1517 static struct platform_driver at_xdmac_driver = {
1518 .probe = at_xdmac_probe,
1519 .remove = at_xdmac_remove,
1520 .driver = {
1521 .name = "at_xdmac",
1522 .of_match_table = of_match_ptr(atmel_xdmac_dt_ids),
1523 .pm = &atmel_xdmac_dev_pm_ops,
1524 }
1525 };
1526
1527 static int __init at_xdmac_init(void)
1528 {
1529 return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe);
1530 }
1531 subsys_initcall(at_xdmac_init);
1532
1533 MODULE_DESCRIPTION("Atmel Extended DMA Controller driver");
1534 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
1535 MODULE_LICENSE("GPL");
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