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lockstat: Report avg wait and hold times
[linux-2.6/btrfs-unstable.git] / drivers / staging / winbond / wb35reg.c
bloba5e255bb0f8b1c2865d856820d0a30195830aae4
1 #include "wb35reg_f.h"
2 #include "phy_calibration.h"
3
4 #include <linux/usb.h>
5 #include <linux/slab.h>
6
7 /*
8 * true : read command process successfully
9 * false : register not support
10 * RegisterNo : start base
11 * pRegisterData : data point
12 * NumberOfData : number of register data
13 * Flag : AUTO_INCREMENT - RegisterNo will auto increment 4
14 * NO_INCREMENT - Function will write data into the same register
15 */
16 unsigned char Wb35Reg_BurstWrite(struct hw_data *pHwData, u16 RegisterNo,
17 u32 *pRegisterData, u8 NumberOfData, u8 Flag)
18 {
19 struct wb35_reg *reg = &pHwData->reg;
20 struct urb *urb = NULL;
21 struct wb35_reg_queue *reg_queue = NULL;
22 u16 UrbSize;
23 struct usb_ctrlrequest *dr;
24 u16 i, DataSize = NumberOfData * 4;
25
26 /* Module shutdown */
27 if (pHwData->SurpriseRemove)
28 return false;
29
30 /* Trying to use burst write function if use new hardware */
31 UrbSize = sizeof(struct wb35_reg_queue) + DataSize + sizeof(struct usb_ctrlrequest);
32 reg_queue = kzalloc(UrbSize, GFP_ATOMIC);
33 if (reg_queue == NULL)
34 return false;
35
36 urb = usb_alloc_urb(0, GFP_ATOMIC);
37 if (urb == NULL) {
38 kfree(reg_queue);
39 return false;
40 }
41
42 reg_queue->DIRECT = 2; /* burst write register */
43 reg_queue->INDEX = RegisterNo;
44 reg_queue->pBuffer = (u32 *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue));
45 memcpy(reg_queue->pBuffer, pRegisterData, DataSize);
46 /* the function for reversing register data from little endian to big endian */
47 for (i = 0; i < NumberOfData; i++)
48 reg_queue->pBuffer[i] = cpu_to_le32(reg_queue->pBuffer[i]);
49
50 dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue) + DataSize);
51 dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE;
52 dr->bRequest = 0x04; /* USB or vendor-defined request code, burst mode */
53 dr->wValue = cpu_to_le16(Flag); /* 0: Register number auto-increment, 1: No auto increment */
54 dr->wIndex = cpu_to_le16(RegisterNo);
55 dr->wLength = cpu_to_le16(DataSize);
56 reg_queue->Next = NULL;
57 reg_queue->pUsbReq = dr;
58 reg_queue->urb = urb;
59
60 spin_lock_irq(&reg->EP0VM_spin_lock);
61 if (reg->reg_first == NULL)
62 reg->reg_first = reg_queue;
63 else
64 reg->reg_last->Next = reg_queue;
65 reg->reg_last = reg_queue;
66
67 spin_unlock_irq(&reg->EP0VM_spin_lock);
68
69 /* Start EP0VM */
70 Wb35Reg_EP0VM_start(pHwData);
71
72 return true;
73 }
74
75 void Wb35Reg_Update(struct hw_data *pHwData, u16 RegisterNo, u32 RegisterValue)
76 {
77 struct wb35_reg *reg = &pHwData->reg;
78 switch (RegisterNo) {
79 case 0x3b0: reg->U1B0 = RegisterValue; break;
80 case 0x3bc: reg->U1BC_LEDConfigure = RegisterValue; break;
81 case 0x400: reg->D00_DmaControl = RegisterValue; break;
82 case 0x800: reg->M00_MacControl = RegisterValue; break;
83 case 0x804: reg->M04_MulticastAddress1 = RegisterValue; break;
84 case 0x808: reg->M08_MulticastAddress2 = RegisterValue; break;
85 case 0x824: reg->M24_MacControl = RegisterValue; break;
86 case 0x828: reg->M28_MacControl = RegisterValue; break;
87 case 0x82c: reg->M2C_MacControl = RegisterValue; break;
88 case 0x838: reg->M38_MacControl = RegisterValue; break;
89 case 0x840: reg->M40_MacControl = RegisterValue; break;
90 case 0x844: reg->M44_MacControl = RegisterValue; break;
91 case 0x848: reg->M48_MacControl = RegisterValue; break;
92 case 0x84c: reg->M4C_MacStatus = RegisterValue; break;
93 case 0x860: reg->M60_MacControl = RegisterValue; break;
94 case 0x868: reg->M68_MacControl = RegisterValue; break;
95 case 0x870: reg->M70_MacControl = RegisterValue; break;
96 case 0x874: reg->M74_MacControl = RegisterValue; break;
97 case 0x878: reg->M78_ERPInformation = RegisterValue; break;
98 case 0x87C: reg->M7C_MacControl = RegisterValue; break;
99 case 0x880: reg->M80_MacControl = RegisterValue; break;
100 case 0x884: reg->M84_MacControl = RegisterValue; break;
101 case 0x888: reg->M88_MacControl = RegisterValue; break;
102 case 0x898: reg->M98_MacControl = RegisterValue; break;
103 case 0x100c: reg->BB0C = RegisterValue; break;
104 case 0x102c: reg->BB2C = RegisterValue; break;
105 case 0x1030: reg->BB30 = RegisterValue; break;
106 case 0x103c: reg->BB3C = RegisterValue; break;
107 case 0x1048: reg->BB48 = RegisterValue; break;
108 case 0x104c: reg->BB4C = RegisterValue; break;
109 case 0x1050: reg->BB50 = RegisterValue; break;
110 case 0x1054: reg->BB54 = RegisterValue; break;
111 case 0x1058: reg->BB58 = RegisterValue; break;
112 case 0x105c: reg->BB5C = RegisterValue; break;
113 case 0x1060: reg->BB60 = RegisterValue; break;
114 }
115 }
116
117 /*
118 * true : read command process successfully
119 * false : register not support
120 */
121 unsigned char Wb35Reg_WriteSync(struct hw_data *pHwData, u16 RegisterNo,
122 u32 RegisterValue)
123 {
124 struct wb35_reg *reg = &pHwData->reg;
125 int ret = -1;
126
127 /* Module shutdown */
128 if (pHwData->SurpriseRemove)
129 return false;
130
131 RegisterValue = cpu_to_le32(RegisterValue);
132
133 /* update the register by send usb message */
134 reg->SyncIoPause = 1;
135
136 /* Wait until EP0VM stop */
137 while (reg->EP0vm_state != VM_STOP)
138 msleep(10);
139
140 /* Sync IoCallDriver */
141 reg->EP0vm_state = VM_RUNNING;
142 ret = usb_control_msg(pHwData->udev,
143 usb_sndctrlpipe(pHwData->udev, 0),
144 0x03,
145 USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
146 0x0, RegisterNo, &RegisterValue, 4, HZ * 100);
147 reg->EP0vm_state = VM_STOP;
148 reg->SyncIoPause = 0;
149
150 Wb35Reg_EP0VM_start(pHwData);
151
152 if (ret < 0) {
153 pr_debug("EP0 Write register usb message sending error\n");
154 pHwData->SurpriseRemove = 1;
155 return false;
156 }
157 return true;
158 }
159
160 /*
161 * true : read command process successfully
162 * false : register not support
163 */
164 unsigned char Wb35Reg_Write(struct hw_data *pHwData, u16 RegisterNo,
165 u32 RegisterValue)
166 {
167 struct wb35_reg *reg = &pHwData->reg;
168 struct usb_ctrlrequest *dr;
169 struct urb *urb = NULL;
170 struct wb35_reg_queue *reg_queue = NULL;
171 u16 UrbSize;
172
173 /* Module shutdown */
174 if (pHwData->SurpriseRemove)
175 return false;
176
177 /* update the register by send urb request */
178 UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest);
179 reg_queue = kzalloc(UrbSize, GFP_ATOMIC);
180 if (reg_queue == NULL)
181 return false;
182
183 urb = usb_alloc_urb(0, GFP_ATOMIC);
184 if (urb == NULL) {
185 kfree(reg_queue);
186 return false;
187 }
188
189 reg_queue->DIRECT = 1; /* burst write register */
190 reg_queue->INDEX = RegisterNo;
191 reg_queue->VALUE = cpu_to_le32(RegisterValue);
192 reg_queue->RESERVED_VALID = false;
193 dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue));
194 dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE;
195 dr->bRequest = 0x03; /* USB or vendor-defined request code, burst mode */
196 dr->wValue = cpu_to_le16(0x0);
197 dr->wIndex = cpu_to_le16(RegisterNo);
198 dr->wLength = cpu_to_le16(4);
199
200 /* Enter the sending queue */
201 reg_queue->Next = NULL;
202 reg_queue->pUsbReq = dr;
203 reg_queue->urb = urb;
204
205 spin_lock_irq(&reg->EP0VM_spin_lock);
206 if (reg->reg_first == NULL)
207 reg->reg_first = reg_queue;
208 else
209 reg->reg_last->Next = reg_queue;
210 reg->reg_last = reg_queue;
211
212 spin_unlock_irq(&reg->EP0VM_spin_lock);
213
214 /* Start EP0VM */
215 Wb35Reg_EP0VM_start(pHwData);
216
217 return true;
218 }
219
220 /*
221 * This command will be executed with a user defined value. When it completes,
222 * this value is useful. For example, hal_set_current_channel will use it.
223 * true : read command process successfully
224 * false : register not supported
225 */
226 unsigned char Wb35Reg_WriteWithCallbackValue(struct hw_data *pHwData,
227 u16 RegisterNo,
228 u32 RegisterValue,
229 s8 *pValue,
230 s8 Len)
231 {
232 struct wb35_reg *reg = &pHwData->reg;
233 struct usb_ctrlrequest *dr;
234 struct urb *urb = NULL;
235 struct wb35_reg_queue *reg_queue = NULL;
236 u16 UrbSize;
237
238 /* Module shutdown */
239 if (pHwData->SurpriseRemove)
240 return false;
241
242 /* update the register by send urb request */
243 UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest);
244 reg_queue = kzalloc(UrbSize, GFP_ATOMIC);
245 if (reg_queue == NULL)
246 return false;
247
248 urb = usb_alloc_urb(0, GFP_ATOMIC);
249 if (urb == NULL) {
250 kfree(reg_queue);
251 return false;
252 }
253
254 reg_queue->DIRECT = 1; /* burst write register */
255 reg_queue->INDEX = RegisterNo;
256 reg_queue->VALUE = cpu_to_le32(RegisterValue);
257 /* NOTE : Users must guarantee the size of value will not exceed the buffer size. */
258 memcpy(reg_queue->RESERVED, pValue, Len);
259 reg_queue->RESERVED_VALID = true;
260 dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue));
261 dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE;
262 dr->bRequest = 0x03; /* USB or vendor-defined request code, burst mode */
263 dr->wValue = cpu_to_le16(0x0);
264 dr->wIndex = cpu_to_le16(RegisterNo);
265 dr->wLength = cpu_to_le16(4);
266
267 /* Enter the sending queue */
268 reg_queue->Next = NULL;
269 reg_queue->pUsbReq = dr;
270 reg_queue->urb = urb;
271 spin_lock_irq(&reg->EP0VM_spin_lock);
272 if (reg->reg_first == NULL)
273 reg->reg_first = reg_queue;
274 else
275 reg->reg_last->Next = reg_queue;
276 reg->reg_last = reg_queue;
277
278 spin_unlock_irq(&reg->EP0VM_spin_lock);
279
280 /* Start EP0VM */
281 Wb35Reg_EP0VM_start(pHwData);
282
283 return true;
284 }
285
286 /*
287 * true : read command process successfully
288 * false : register not support
289 * pRegisterValue : It must be a resident buffer due to
290 * asynchronous read register.
291 */
292 unsigned char Wb35Reg_ReadSync(struct hw_data *pHwData, u16 RegisterNo,
293 u32 *pRegisterValue)
294 {
295 struct wb35_reg *reg = &pHwData->reg;
296 u32 *pltmp = pRegisterValue;
297 int ret = -1;
298
299 /* Module shutdown */
300 if (pHwData->SurpriseRemove)
301 return false;
302
303 /* Read the register by send usb message */
304 reg->SyncIoPause = 1;
305
306 /* Wait until EP0VM stop */
307 while (reg->EP0vm_state != VM_STOP)
308 msleep(10);
309
310 reg->EP0vm_state = VM_RUNNING;
311 ret = usb_control_msg(pHwData->udev,
312 usb_rcvctrlpipe(pHwData->udev, 0),
313 0x01,
314 USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN,
315 0x0, RegisterNo, pltmp, 4, HZ * 100);
316
317 *pRegisterValue = cpu_to_le32(*pltmp);
318
319 reg->EP0vm_state = VM_STOP;
320
321 Wb35Reg_Update(pHwData, RegisterNo, *pRegisterValue);
322 reg->SyncIoPause = 0;
323
324 Wb35Reg_EP0VM_start(pHwData);
325
326 if (ret < 0) {
327 pr_debug("EP0 Read register usb message sending error\n");
328 pHwData->SurpriseRemove = 1;
329 return false;
330 }
331 return true;
332 }
333
334 /*
335 * true : read command process successfully
336 * false : register not support
337 * pRegisterValue : It must be a resident buffer due to
338 * asynchronous read register.
339 */
340 unsigned char Wb35Reg_Read(struct hw_data *pHwData, u16 RegisterNo,
341 u32 *pRegisterValue)
342 {
343 struct wb35_reg *reg = &pHwData->reg;
344 struct usb_ctrlrequest *dr;
345 struct urb *urb;
346 struct wb35_reg_queue *reg_queue;
347 u16 UrbSize;
348
349 /* Module shutdown */
350 if (pHwData->SurpriseRemove)
351 return false;
352
353 /* update the variable by send Urb to read register */
354 UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest);
355 reg_queue = kzalloc(UrbSize, GFP_ATOMIC);
356 if (reg_queue == NULL)
357 return false;
358
359 urb = usb_alloc_urb(0, GFP_ATOMIC);
360 if (urb == NULL) {
361 kfree(reg_queue);
362 return false;
363 }
364 reg_queue->DIRECT = 0; /* read register */
365 reg_queue->INDEX = RegisterNo;
366 reg_queue->pBuffer = pRegisterValue;
367 dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue));
368 dr->bRequestType = USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN;
369 dr->bRequest = 0x01; /* USB or vendor-defined request code, burst mode */
370 dr->wValue = cpu_to_le16(0x0);
371 dr->wIndex = cpu_to_le16(RegisterNo);
372 dr->wLength = cpu_to_le16(4);
373
374 /* Enter the sending queue */
375 reg_queue->Next = NULL;
376 reg_queue->pUsbReq = dr;
377 reg_queue->urb = urb;
378 spin_lock_irq(&reg->EP0VM_spin_lock);
379 if (reg->reg_first == NULL)
380 reg->reg_first = reg_queue;
381 else
382 reg->reg_last->Next = reg_queue;
383 reg->reg_last = reg_queue;
384
385 spin_unlock_irq(&reg->EP0VM_spin_lock);
386
387 /* Start EP0VM */
388 Wb35Reg_EP0VM_start(pHwData);
389
390 return true;
391 }
392
393
394 void Wb35Reg_EP0VM_start(struct hw_data *pHwData)
395 {
396 struct wb35_reg *reg = &pHwData->reg;
397
398 if (atomic_inc_return(&reg->RegFireCount) == 1) {
399 reg->EP0vm_state = VM_RUNNING;
400 Wb35Reg_EP0VM(pHwData);
401 } else
402 atomic_dec(&reg->RegFireCount);
403 }
404
405 void Wb35Reg_EP0VM(struct hw_data *pHwData)
406 {
407 struct wb35_reg *reg = &pHwData->reg;
408 struct urb *urb;
409 struct usb_ctrlrequest *dr;
410 u32 *pBuffer;
411 int ret = -1;
412 struct wb35_reg_queue *reg_queue;
413
414
415 if (reg->SyncIoPause)
416 goto cleanup;
417
418 if (pHwData->SurpriseRemove)
419 goto cleanup;
420
421 /* Get the register data and send to USB through Irp */
422 spin_lock_irq(&reg->EP0VM_spin_lock);
423 reg_queue = reg->reg_first;
424 spin_unlock_irq(&reg->EP0VM_spin_lock);
425
426 if (!reg_queue)
427 goto cleanup;
428
429 /* Get an Urb, send it */
430 urb = (struct urb *)reg_queue->urb;
431
432 dr = reg_queue->pUsbReq;
433 urb = reg_queue->urb;
434 pBuffer = reg_queue->pBuffer;
435 if (reg_queue->DIRECT == 1) /* output */
436 pBuffer = &reg_queue->VALUE;
437
438 usb_fill_control_urb(urb, pHwData->udev,
439 REG_DIRECTION(pHwData->udev, reg_queue),
440 (u8 *)dr, pBuffer, cpu_to_le16(dr->wLength),
441 Wb35Reg_EP0VM_complete, (void *)pHwData);
442
443 reg->EP0vm_state = VM_RUNNING;
444
445 ret = usb_submit_urb(urb, GFP_ATOMIC);
446
447 if (ret < 0) {
448 pr_debug("EP0 Irp sending error\n");
449 goto cleanup;
450 }
451 return;
452
453 cleanup:
454 reg->EP0vm_state = VM_STOP;
455 atomic_dec(&reg->RegFireCount);
456 }
457
458
459 void Wb35Reg_EP0VM_complete(struct urb *urb)
460 {
461 struct hw_data *pHwData = (struct hw_data *)urb->context;
462 struct wb35_reg *reg = &pHwData->reg;
463 struct wb35_reg_queue *reg_queue;
464
465
466 /* Variable setting */
467 reg->EP0vm_state = VM_COMPLETED;
468 reg->EP0VM_status = urb->status;
469
470 if (pHwData->SurpriseRemove) { /* Let WbWlanHalt to handle surprise remove */
471 reg->EP0vm_state = VM_STOP;
472 atomic_dec(&reg->RegFireCount);
473 } else {
474 /* Complete to send, remove the URB from the first */
475 spin_lock_irq(&reg->EP0VM_spin_lock);
476 reg_queue = reg->reg_first;
477 if (reg_queue == reg->reg_last)
478 reg->reg_last = NULL;
479 reg->reg_first = reg->reg_first->Next;
480 spin_unlock_irq(&reg->EP0VM_spin_lock);
481
482 if (reg->EP0VM_status) {
483 pr_debug("EP0 IoCompleteRoutine return error\n");
484 reg->EP0vm_state = VM_STOP;
485 pHwData->SurpriseRemove = 1;
486 } else {
487 /* Success. Update the result */
488
489 /* Start the next send */
490 Wb35Reg_EP0VM(pHwData);
491 }
492
493 kfree(reg_queue);
494 }
495
496 usb_free_urb(urb);
497 }
498
499
500 void Wb35Reg_destroy(struct hw_data *pHwData)
501 {
502 struct wb35_reg *reg = &pHwData->reg;
503 struct urb *urb;
504 struct wb35_reg_queue *reg_queue;
505
506 Uxx_power_off_procedure(pHwData);
507
508 /* Wait for Reg operation completed */
509 do {
510 msleep(10); /* Delay for waiting function enter */
511 } while (reg->EP0vm_state != VM_STOP);
512 msleep(10); /* Delay for waiting function enter */
513
514 /* Release all the data in RegQueue */
515 spin_lock_irq(&reg->EP0VM_spin_lock);
516 reg_queue = reg->reg_first;
517 while (reg_queue) {
518 if (reg_queue == reg->reg_last)
519 reg->reg_last = NULL;
520 reg->reg_first = reg->reg_first->Next;
521
522 urb = reg_queue->urb;
523 spin_unlock_irq(&reg->EP0VM_spin_lock);
524 if (urb) {
525 usb_free_urb(urb);
526 kfree(reg_queue);
527 } else {
528 pr_debug("EP0 queue release error\n");
529 }
530 spin_lock_irq(&reg->EP0VM_spin_lock);
531
532 reg_queue = reg->reg_first;
533 }
534 spin_unlock_irq(&reg->EP0VM_spin_lock);
535 }
536
537 /*
538 * =======================================================================
539 * The function can be run in passive-level only.
540 * =========================================================================
541 */
542 unsigned char Wb35Reg_initial(struct hw_data *pHwData)
543 {
544 struct wb35_reg *reg = &pHwData->reg;
545 u32 ltmp;
546 u32 SoftwareSet, VCO_trim, TxVga, Region_ScanInterval;
547
548 /* Spin lock is acquired for read and write IRP command */
549 spin_lock_init(&reg->EP0VM_spin_lock);
550
551 /* Getting RF module type from EEPROM */
552 Wb35Reg_WriteSync(pHwData, 0x03b4, 0x080d0000); /* Start EEPROM access + Read + address(0x0d) */
553 Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp);
554
555 /* Update RF module type and determine the PHY type by inf or EEPROM */
556 reg->EEPROMPhyType = (u8)(ltmp & 0xff);
557 /*
558 * 0 V MAX2825, 1 V MAX2827, 2 V MAX2828, 3 V MAX2829
559 * 16V AL2230, 17 - AL7230, 18 - AL2230S
560 * 32 Reserved
561 * 33 - W89RF242(TxVGA 0~19), 34 - W89RF242(TxVGA 0~34)
562 */
563 if (reg->EEPROMPhyType != RF_DECIDE_BY_INF) {
564 if ((reg->EEPROMPhyType == RF_MAXIM_2825) ||
565 (reg->EEPROMPhyType == RF_MAXIM_2827) ||
566 (reg->EEPROMPhyType == RF_MAXIM_2828) ||
567 (reg->EEPROMPhyType == RF_MAXIM_2829) ||
568 (reg->EEPROMPhyType == RF_MAXIM_V1) ||
569 (reg->EEPROMPhyType == RF_AIROHA_2230) ||
570 (reg->EEPROMPhyType == RF_AIROHA_2230S) ||
571 (reg->EEPROMPhyType == RF_AIROHA_7230) ||
572 (reg->EEPROMPhyType == RF_WB_242) ||
573 (reg->EEPROMPhyType == RF_WB_242_1))
574 pHwData->phy_type = reg->EEPROMPhyType;
575 }
576
577 /* Power On procedure running. The relative parameter will be set according to phy_type */
578 Uxx_power_on_procedure(pHwData);
579
580 /* Reading MAC address */
581 Uxx_ReadEthernetAddress(pHwData);
582
583 /* Read VCO trim for RF parameter */
584 Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08200000);
585 Wb35Reg_ReadSync(pHwData, 0x03b4, &VCO_trim);
586
587 /* Read Antenna On/Off of software flag */
588 Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08210000);
589 Wb35Reg_ReadSync(pHwData, 0x03b4, &SoftwareSet);
590
591 /* Read TXVGA */
592 Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08100000);
593 Wb35Reg_ReadSync(pHwData, 0x03b4, &TxVga);
594
595 /* Get Scan interval setting from EEPROM offset 0x1c */
596 Wb35Reg_WriteSync(pHwData, 0x03b4, 0x081d0000);
597 Wb35Reg_ReadSync(pHwData, 0x03b4, &Region_ScanInterval);
598
599 /* Update Ethernet address */
600 memcpy(pHwData->CurrentMacAddress, pHwData->PermanentMacAddress, ETH_ALEN);
601
602 /* Update software variable */
603 pHwData->SoftwareSet = (u16)(SoftwareSet & 0xffff);
604 TxVga &= 0x000000ff;
605 pHwData->PowerIndexFromEEPROM = (u8)TxVga;
606 pHwData->VCO_trim = (u8)VCO_trim & 0xff;
607 if (pHwData->VCO_trim == 0xff)
608 pHwData->VCO_trim = 0x28;
609
610 reg->EEPROMRegion = (u8)(Region_ScanInterval >> 8);
611 if (reg->EEPROMRegion < 1 || reg->EEPROMRegion > 6)
612 reg->EEPROMRegion = REGION_AUTO;
613
614 /* For Get Tx VGA from EEPROM */
615 GetTxVgaFromEEPROM(pHwData);
616
617 /* Set Scan Interval */
618 pHwData->Scan_Interval = (u8)(Region_ScanInterval & 0xff) * 10;
619 if ((pHwData->Scan_Interval == 2550) || (pHwData->Scan_Interval < 10)) /* Is default setting 0xff * 10 */
620 pHwData->Scan_Interval = SCAN_MAX_CHNL_TIME;
621
622 /* Initial register */
623 RFSynthesizer_initial(pHwData);
624
625 BBProcessor_initial(pHwData); /* Async write, must wait until complete */
626
627 Wb35Reg_phy_calibration(pHwData);
628
629 Mxx_initial(pHwData);
630 Dxx_initial(pHwData);
631
632 if (pHwData->SurpriseRemove)
633 return false;
634 else
635 return true; /* Initial fail */
636 }
637
638 /*
639 * ================================================================
640 * CardComputeCrc --
641 *
642 * Description:
643 * Runs the AUTODIN II CRC algorithm on the buffers Buffer length.
644 *
645 * Arguments:
646 * Buffer - the input buffer
647 * Length - the length of Buffer
648 *
649 * Return Value:
650 * The 32-bit CRC value.
651 * ===================================================================
652 */
653 u32 CardComputeCrc(u8 *Buffer, u32 Length)
654 {
655 u32 Crc, Carry;
656 u32 i, j;
657 u8 CurByte;
658
659 Crc = 0xffffffff;
660
661 for (i = 0; i < Length; i++) {
662 CurByte = Buffer[i];
663 for (j = 0; j < 8; j++) {
664 Carry = ((Crc & 0x80000000) ? 1 : 0) ^ (CurByte & 0x01);
665 Crc <<= 1;
666 CurByte >>= 1;
667 if (Carry)
668 Crc = (Crc ^ 0x04c11db6) | Carry;
669 }
670 }
671 return Crc;
672 }
673
674
675 /*
676 * ==================================================================
677 * BitReverse --
678 * Reverse the bits in the input argument, dwData, which is
679 * regarded as a string of bits with the length, DataLength.
680 *
681 * Arguments:
682 * dwData :
683 * DataLength :
684 *
685 * Return:
686 * The converted value.
687 * ==================================================================
688 */
689 u32 BitReverse(u32 dwData, u32 DataLength)
690 {
691 u32 HalfLength, i, j;
692 u32 BitA, BitB;
693
694 if (DataLength <= 0)
695 return 0; /* No conversion is done. */
696 dwData = dwData & (0xffffffff >> (32 - DataLength));
697
698 HalfLength = DataLength / 2;
699 for (i = 0, j = DataLength - 1; i < HalfLength; i++, j--) {
700 BitA = GetBit(dwData, i);
701 BitB = GetBit(dwData, j);
702 if (BitA && !BitB) {
703 dwData = ClearBit(dwData, i);
704 dwData = SetBit(dwData, j);
705 } else if (!BitA && BitB) {
706 dwData = SetBit(dwData, i);
707 dwData = ClearBit(dwData, j);
708 } else {
709 /* Do nothing since these two bits are of the save values. */
710 }
711 }
712 return dwData;
713 }
714
715 void Wb35Reg_phy_calibration(struct hw_data *pHwData)
716 {
717 u32 BB3c, BB54;
718
719 if ((pHwData->phy_type == RF_WB_242) ||
720 (pHwData->phy_type == RF_WB_242_1)) {
721 phy_calibration_winbond(pHwData, 2412); /* Sync operation */
722 Wb35Reg_ReadSync(pHwData, 0x103c, &BB3c);
723 Wb35Reg_ReadSync(pHwData, 0x1054, &BB54);
724
725 pHwData->BB3c_cal = BB3c;
726 pHwData->BB54_cal = BB54;
727
728 RFSynthesizer_initial(pHwData);
729 BBProcessor_initial(pHwData); /* Async operation */
730
731 Wb35Reg_WriteSync(pHwData, 0x103c, BB3c);
732 Wb35Reg_WriteSync(pHwData, 0x1054, BB54);
733 }
734 }
735
736
(deprecated) Btrfs devel tree