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serial: tegra: Add delay after enabling FIFO mode
[linux-2.6/btrfs-unstable.git] / drivers / tty / serial / serial-tegra.c
blob0d9d7ceb1dbbbfb872bd8e5c27d92d5d8a95c8a6
1 /*
2 * serial_tegra.c
3 *
4 * High-speed serial driver for NVIDIA Tegra SoCs
5 *
6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author: Laxman Dewangan <ldewangan@nvidia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include <linux/clk.h>
24 #include <linux/debugfs.h>
25 #include <linux/delay.h>
26 #include <linux/dmaengine.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmapool.h>
29 #include <linux/err.h>
30 #include <linux/io.h>
31 #include <linux/irq.h>
32 #include <linux/module.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/pagemap.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/serial.h>
39 #include <linux/serial_8250.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial_reg.h>
42 #include <linux/slab.h>
43 #include <linux/string.h>
44 #include <linux/termios.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47
48 #define TEGRA_UART_TYPE "TEGRA_UART"
49 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
50 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
51
52 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096
53 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100
54 #define TEGRA_UART_IER_EORD 0x20
55 #define TEGRA_UART_MCR_RTS_EN 0x40
56 #define TEGRA_UART_MCR_CTS_EN 0x20
57 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
58 UART_LSR_PE | UART_LSR_FE)
59 #define TEGRA_UART_IRDA_CSR 0x08
60 #define TEGRA_UART_SIR_ENABLED 0x80
61
62 #define TEGRA_UART_TX_PIO 1
63 #define TEGRA_UART_TX_DMA 2
64 #define TEGRA_UART_MIN_DMA 16
65 #define TEGRA_UART_FIFO_SIZE 32
66
67 /*
68 * Tx fifo trigger level setting in tegra uart is in
69 * reverse way then conventional uart.
70 */
71 #define TEGRA_UART_TX_TRIG_16B 0x00
72 #define TEGRA_UART_TX_TRIG_8B 0x10
73 #define TEGRA_UART_TX_TRIG_4B 0x20
74 #define TEGRA_UART_TX_TRIG_1B 0x30
75
76 #define TEGRA_UART_MAXIMUM 5
77
78 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
79 #define TEGRA_UART_DEFAULT_BAUD 115200
80 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
81
82 /* Tx transfer mode */
83 #define TEGRA_TX_PIO 1
84 #define TEGRA_TX_DMA 2
85
86 /**
87 * tegra_uart_chip_data: SOC specific data.
88 *
89 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
90 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
91 * Tegra30 does not allow this.
92 * @support_clk_src_div: Clock source support the clock divider.
93 */
94 struct tegra_uart_chip_data {
95 bool tx_fifo_full_status;
96 bool allow_txfifo_reset_fifo_mode;
97 bool support_clk_src_div;
98 };
99
100 struct tegra_uart_port {
101 struct uart_port uport;
102 const struct tegra_uart_chip_data *cdata;
103
104 struct clk *uart_clk;
105 struct reset_control *rst;
106 unsigned int current_baud;
107
108 /* Register shadow */
109 unsigned long fcr_shadow;
110 unsigned long mcr_shadow;
111 unsigned long lcr_shadow;
112 unsigned long ier_shadow;
113 bool rts_active;
114
115 int tx_in_progress;
116 unsigned int tx_bytes;
117
118 bool enable_modem_interrupt;
119
120 bool rx_timeout;
121 int rx_in_progress;
122 int symb_bit;
123
124 struct dma_chan *rx_dma_chan;
125 struct dma_chan *tx_dma_chan;
126 dma_addr_t rx_dma_buf_phys;
127 dma_addr_t tx_dma_buf_phys;
128 unsigned char *rx_dma_buf_virt;
129 unsigned char *tx_dma_buf_virt;
130 struct dma_async_tx_descriptor *tx_dma_desc;
131 struct dma_async_tx_descriptor *rx_dma_desc;
132 dma_cookie_t tx_cookie;
133 dma_cookie_t rx_cookie;
134 int tx_bytes_requested;
135 int rx_bytes_requested;
136 };
137
138 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
139 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
140
141 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
142 unsigned long reg)
143 {
144 return readl(tup->uport.membase + (reg << tup->uport.regshift));
145 }
146
147 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
148 unsigned long reg)
149 {
150 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
151 }
152
153 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
154 {
155 return container_of(u, struct tegra_uart_port, uport);
156 }
157
158 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
159 {
160 struct tegra_uart_port *tup = to_tegra_uport(u);
161
162 /*
163 * RI - Ring detector is active
164 * CD/DCD/CAR - Carrier detect is always active. For some reason
165 * linux has different names for carrier detect.
166 * DSR - Data Set ready is active as the hardware doesn't support it.
167 * Don't know if the linux support this yet?
168 * CTS - Clear to send. Always set to active, as the hardware handles
169 * CTS automatically.
170 */
171 if (tup->enable_modem_interrupt)
172 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
173 return TIOCM_CTS;
174 }
175
176 static void set_rts(struct tegra_uart_port *tup, bool active)
177 {
178 unsigned long mcr;
179
180 mcr = tup->mcr_shadow;
181 if (active)
182 mcr |= TEGRA_UART_MCR_RTS_EN;
183 else
184 mcr &= ~TEGRA_UART_MCR_RTS_EN;
185 if (mcr != tup->mcr_shadow) {
186 tegra_uart_write(tup, mcr, UART_MCR);
187 tup->mcr_shadow = mcr;
188 }
189 return;
190 }
191
192 static void set_dtr(struct tegra_uart_port *tup, bool active)
193 {
194 unsigned long mcr;
195
196 mcr = tup->mcr_shadow;
197 if (active)
198 mcr |= UART_MCR_DTR;
199 else
200 mcr &= ~UART_MCR_DTR;
201 if (mcr != tup->mcr_shadow) {
202 tegra_uart_write(tup, mcr, UART_MCR);
203 tup->mcr_shadow = mcr;
204 }
205 return;
206 }
207
208 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
209 {
210 struct tegra_uart_port *tup = to_tegra_uport(u);
211 unsigned long mcr;
212 int dtr_enable;
213
214 mcr = tup->mcr_shadow;
215 tup->rts_active = !!(mctrl & TIOCM_RTS);
216 set_rts(tup, tup->rts_active);
217
218 dtr_enable = !!(mctrl & TIOCM_DTR);
219 set_dtr(tup, dtr_enable);
220 return;
221 }
222
223 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
224 {
225 struct tegra_uart_port *tup = to_tegra_uport(u);
226 unsigned long lcr;
227
228 lcr = tup->lcr_shadow;
229 if (break_ctl)
230 lcr |= UART_LCR_SBC;
231 else
232 lcr &= ~UART_LCR_SBC;
233 tegra_uart_write(tup, lcr, UART_LCR);
234 tup->lcr_shadow = lcr;
235 }
236
237 /**
238 * tegra_uart_wait_cycle_time: Wait for N UART clock periods
239 *
240 * @tup: Tegra serial port data structure.
241 * @cycles: Number of clock periods to wait.
242 *
243 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART
244 * clock speed is 16X the current baud rate.
245 */
246 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
247 unsigned int cycles)
248 {
249 if (tup->current_baud)
250 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
251 }
252
253 /* Wait for a symbol-time. */
254 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
255 unsigned int syms)
256 {
257 if (tup->current_baud)
258 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
259 tup->current_baud));
260 }
261
262 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
263 {
264 unsigned long fcr = tup->fcr_shadow;
265
266 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
267 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
268 tegra_uart_write(tup, fcr, UART_FCR);
269 } else {
270 fcr &= ~UART_FCR_ENABLE_FIFO;
271 tegra_uart_write(tup, fcr, UART_FCR);
272 udelay(60);
273 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
274 tegra_uart_write(tup, fcr, UART_FCR);
275 fcr |= UART_FCR_ENABLE_FIFO;
276 tegra_uart_write(tup, fcr, UART_FCR);
277 }
278
279 /* Dummy read to ensure the write is posted */
280 tegra_uart_read(tup, UART_SCR);
281
282 /*
283 * For all tegra devices (up to t210), there is a hardware issue that
284 * requires software to wait for 32 UART clock periods for the flush
285 * to propagate, otherwise data could be lost.
286 */
287 tegra_uart_wait_cycle_time(tup, 32);
288 }
289
290 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
291 {
292 unsigned long rate;
293 unsigned int divisor;
294 unsigned long lcr;
295 int ret;
296
297 if (tup->current_baud == baud)
298 return 0;
299
300 if (tup->cdata->support_clk_src_div) {
301 rate = baud * 16;
302 ret = clk_set_rate(tup->uart_clk, rate);
303 if (ret < 0) {
304 dev_err(tup->uport.dev,
305 "clk_set_rate() failed for rate %lu\n", rate);
306 return ret;
307 }
308 divisor = 1;
309 } else {
310 rate = clk_get_rate(tup->uart_clk);
311 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
312 }
313
314 lcr = tup->lcr_shadow;
315 lcr |= UART_LCR_DLAB;
316 tegra_uart_write(tup, lcr, UART_LCR);
317
318 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
319 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
320
321 lcr &= ~UART_LCR_DLAB;
322 tegra_uart_write(tup, lcr, UART_LCR);
323
324 /* Dummy read to ensure the write is posted */
325 tegra_uart_read(tup, UART_SCR);
326
327 tup->current_baud = baud;
328
329 /* wait two character intervals at new rate */
330 tegra_uart_wait_sym_time(tup, 2);
331 return 0;
332 }
333
334 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
335 unsigned long lsr)
336 {
337 char flag = TTY_NORMAL;
338
339 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
340 if (lsr & UART_LSR_OE) {
341 /* Overrrun error */
342 flag = TTY_OVERRUN;
343 tup->uport.icount.overrun++;
344 dev_err(tup->uport.dev, "Got overrun errors\n");
345 } else if (lsr & UART_LSR_PE) {
346 /* Parity error */
347 flag = TTY_PARITY;
348 tup->uport.icount.parity++;
349 dev_err(tup->uport.dev, "Got Parity errors\n");
350 } else if (lsr & UART_LSR_FE) {
351 flag = TTY_FRAME;
352 tup->uport.icount.frame++;
353 dev_err(tup->uport.dev, "Got frame errors\n");
354 } else if (lsr & UART_LSR_BI) {
355 dev_err(tup->uport.dev, "Got Break\n");
356 tup->uport.icount.brk++;
357 /* If FIFO read error without any data, reset Rx FIFO */
358 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
359 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
360 }
361 }
362 return flag;
363 }
364
365 static int tegra_uart_request_port(struct uart_port *u)
366 {
367 return 0;
368 }
369
370 static void tegra_uart_release_port(struct uart_port *u)
371 {
372 /* Nothing to do here */
373 }
374
375 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
376 {
377 struct circ_buf *xmit = &tup->uport.state->xmit;
378 int i;
379
380 for (i = 0; i < max_bytes; i++) {
381 BUG_ON(uart_circ_empty(xmit));
382 if (tup->cdata->tx_fifo_full_status) {
383 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
384 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
385 break;
386 }
387 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
388 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
389 tup->uport.icount.tx++;
390 }
391 }
392
393 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
394 unsigned int bytes)
395 {
396 if (bytes > TEGRA_UART_MIN_DMA)
397 bytes = TEGRA_UART_MIN_DMA;
398
399 tup->tx_in_progress = TEGRA_UART_TX_PIO;
400 tup->tx_bytes = bytes;
401 tup->ier_shadow |= UART_IER_THRI;
402 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
403 }
404
405 static void tegra_uart_tx_dma_complete(void *args)
406 {
407 struct tegra_uart_port *tup = args;
408 struct circ_buf *xmit = &tup->uport.state->xmit;
409 struct dma_tx_state state;
410 unsigned long flags;
411 int count;
412
413 dmaengine_tx_status(tup->tx_dma_chan, tup->rx_cookie, &state);
414 count = tup->tx_bytes_requested - state.residue;
415 async_tx_ack(tup->tx_dma_desc);
416 spin_lock_irqsave(&tup->uport.lock, flags);
417 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
418 tup->tx_in_progress = 0;
419 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
420 uart_write_wakeup(&tup->uport);
421 tegra_uart_start_next_tx(tup);
422 spin_unlock_irqrestore(&tup->uport.lock, flags);
423 }
424
425 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
426 unsigned long count)
427 {
428 struct circ_buf *xmit = &tup->uport.state->xmit;
429 dma_addr_t tx_phys_addr;
430
431 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
432 UART_XMIT_SIZE, DMA_TO_DEVICE);
433
434 tup->tx_bytes = count & ~(0xF);
435 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
436 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
437 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
438 DMA_PREP_INTERRUPT);
439 if (!tup->tx_dma_desc) {
440 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
441 return -EIO;
442 }
443
444 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
445 tup->tx_dma_desc->callback_param = tup;
446 tup->tx_in_progress = TEGRA_UART_TX_DMA;
447 tup->tx_bytes_requested = tup->tx_bytes;
448 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
449 dma_async_issue_pending(tup->tx_dma_chan);
450 return 0;
451 }
452
453 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
454 {
455 unsigned long tail;
456 unsigned long count;
457 struct circ_buf *xmit = &tup->uport.state->xmit;
458
459 tail = (unsigned long)&xmit->buf[xmit->tail];
460 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
461 if (!count)
462 return;
463
464 if (count < TEGRA_UART_MIN_DMA)
465 tegra_uart_start_pio_tx(tup, count);
466 else if (BYTES_TO_ALIGN(tail) > 0)
467 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
468 else
469 tegra_uart_start_tx_dma(tup, count);
470 }
471
472 /* Called by serial core driver with u->lock taken. */
473 static void tegra_uart_start_tx(struct uart_port *u)
474 {
475 struct tegra_uart_port *tup = to_tegra_uport(u);
476 struct circ_buf *xmit = &u->state->xmit;
477
478 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
479 tegra_uart_start_next_tx(tup);
480 }
481
482 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
483 {
484 struct tegra_uart_port *tup = to_tegra_uport(u);
485 unsigned int ret = 0;
486 unsigned long flags;
487
488 spin_lock_irqsave(&u->lock, flags);
489 if (!tup->tx_in_progress) {
490 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
491 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
492 ret = TIOCSER_TEMT;
493 }
494 spin_unlock_irqrestore(&u->lock, flags);
495 return ret;
496 }
497
498 static void tegra_uart_stop_tx(struct uart_port *u)
499 {
500 struct tegra_uart_port *tup = to_tegra_uport(u);
501 struct circ_buf *xmit = &tup->uport.state->xmit;
502 struct dma_tx_state state;
503 int count;
504
505 if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
506 return;
507
508 dmaengine_terminate_all(tup->tx_dma_chan);
509 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
510 count = tup->tx_bytes_requested - state.residue;
511 async_tx_ack(tup->tx_dma_desc);
512 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
513 tup->tx_in_progress = 0;
514 return;
515 }
516
517 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
518 {
519 struct circ_buf *xmit = &tup->uport.state->xmit;
520
521 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
522 tup->tx_in_progress = 0;
523 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
524 uart_write_wakeup(&tup->uport);
525 tegra_uart_start_next_tx(tup);
526 return;
527 }
528
529 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
530 struct tty_port *tty)
531 {
532 do {
533 char flag = TTY_NORMAL;
534 unsigned long lsr = 0;
535 unsigned char ch;
536
537 lsr = tegra_uart_read(tup, UART_LSR);
538 if (!(lsr & UART_LSR_DR))
539 break;
540
541 flag = tegra_uart_decode_rx_error(tup, lsr);
542 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
543 tup->uport.icount.rx++;
544
545 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty)
546 tty_insert_flip_char(tty, ch, flag);
547 } while (1);
548
549 return;
550 }
551
552 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
553 struct tty_port *tty, int count)
554 {
555 int copied;
556
557 tup->uport.icount.rx += count;
558 if (!tty) {
559 dev_err(tup->uport.dev, "No tty port\n");
560 return;
561 }
562 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
563 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
564 copied = tty_insert_flip_string(tty,
565 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
566 if (copied != count) {
567 WARN_ON(1);
568 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
569 }
570 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
571 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
572 }
573
574 static void tegra_uart_rx_dma_complete(void *args)
575 {
576 struct tegra_uart_port *tup = args;
577 struct uart_port *u = &tup->uport;
578 int count = tup->rx_bytes_requested;
579 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
580 struct tty_port *port = &u->state->port;
581 unsigned long flags;
582
583 async_tx_ack(tup->rx_dma_desc);
584 spin_lock_irqsave(&u->lock, flags);
585
586 /* Deactivate flow control to stop sender */
587 if (tup->rts_active)
588 set_rts(tup, false);
589
590 /* If we are here, DMA is stopped */
591 if (count)
592 tegra_uart_copy_rx_to_tty(tup, port, count);
593
594 tegra_uart_handle_rx_pio(tup, port);
595 if (tty) {
596 spin_unlock_irqrestore(&u->lock, flags);
597 tty_flip_buffer_push(port);
598 spin_lock_irqsave(&u->lock, flags);
599 tty_kref_put(tty);
600 }
601 tegra_uart_start_rx_dma(tup);
602
603 /* Activate flow control to start transfer */
604 if (tup->rts_active)
605 set_rts(tup, true);
606
607 spin_unlock_irqrestore(&u->lock, flags);
608 }
609
610 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup,
611 unsigned long *flags)
612 {
613 struct dma_tx_state state;
614 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
615 struct tty_port *port = &tup->uport.state->port;
616 struct uart_port *u = &tup->uport;
617 int count;
618
619 /* Deactivate flow control to stop sender */
620 if (tup->rts_active)
621 set_rts(tup, false);
622
623 dmaengine_terminate_all(tup->rx_dma_chan);
624 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
625 async_tx_ack(tup->rx_dma_desc);
626 count = tup->rx_bytes_requested - state.residue;
627
628 /* If we are here, DMA is stopped */
629 if (count)
630 tegra_uart_copy_rx_to_tty(tup, port, count);
631
632 tegra_uart_handle_rx_pio(tup, port);
633 if (tty) {
634 spin_unlock_irqrestore(&u->lock, *flags);
635 tty_flip_buffer_push(port);
636 spin_lock_irqsave(&u->lock, *flags);
637 tty_kref_put(tty);
638 }
639 tegra_uart_start_rx_dma(tup);
640
641 if (tup->rts_active)
642 set_rts(tup, true);
643 }
644
645 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
646 {
647 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
648
649 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
650 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
651 DMA_PREP_INTERRUPT);
652 if (!tup->rx_dma_desc) {
653 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
654 return -EIO;
655 }
656
657 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
658 tup->rx_dma_desc->callback_param = tup;
659 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
660 count, DMA_TO_DEVICE);
661 tup->rx_bytes_requested = count;
662 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
663 dma_async_issue_pending(tup->rx_dma_chan);
664 return 0;
665 }
666
667 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
668 {
669 struct tegra_uart_port *tup = to_tegra_uport(u);
670 unsigned long msr;
671
672 msr = tegra_uart_read(tup, UART_MSR);
673 if (!(msr & UART_MSR_ANY_DELTA))
674 return;
675
676 if (msr & UART_MSR_TERI)
677 tup->uport.icount.rng++;
678 if (msr & UART_MSR_DDSR)
679 tup->uport.icount.dsr++;
680 /* We may only get DDCD when HW init and reset */
681 if (msr & UART_MSR_DDCD)
682 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
683 /* Will start/stop_tx accordingly */
684 if (msr & UART_MSR_DCTS)
685 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
686 return;
687 }
688
689 static irqreturn_t tegra_uart_isr(int irq, void *data)
690 {
691 struct tegra_uart_port *tup = data;
692 struct uart_port *u = &tup->uport;
693 unsigned long iir;
694 unsigned long ier;
695 bool is_rx_int = false;
696 unsigned long flags;
697
698 spin_lock_irqsave(&u->lock, flags);
699 while (1) {
700 iir = tegra_uart_read(tup, UART_IIR);
701 if (iir & UART_IIR_NO_INT) {
702 if (is_rx_int) {
703 tegra_uart_handle_rx_dma(tup, &flags);
704 if (tup->rx_in_progress) {
705 ier = tup->ier_shadow;
706 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
707 TEGRA_UART_IER_EORD);
708 tup->ier_shadow = ier;
709 tegra_uart_write(tup, ier, UART_IER);
710 }
711 }
712 spin_unlock_irqrestore(&u->lock, flags);
713 return IRQ_HANDLED;
714 }
715
716 switch ((iir >> 1) & 0x7) {
717 case 0: /* Modem signal change interrupt */
718 tegra_uart_handle_modem_signal_change(u);
719 break;
720
721 case 1: /* Transmit interrupt only triggered when using PIO */
722 tup->ier_shadow &= ~UART_IER_THRI;
723 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
724 tegra_uart_handle_tx_pio(tup);
725 break;
726
727 case 4: /* End of data */
728 case 6: /* Rx timeout */
729 case 2: /* Receive */
730 if (!is_rx_int) {
731 is_rx_int = true;
732 /* Disable Rx interrupts */
733 ier = tup->ier_shadow;
734 ier |= UART_IER_RDI;
735 tegra_uart_write(tup, ier, UART_IER);
736 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
737 UART_IER_RTOIE | TEGRA_UART_IER_EORD);
738 tup->ier_shadow = ier;
739 tegra_uart_write(tup, ier, UART_IER);
740 }
741 break;
742
743 case 3: /* Receive error */
744 tegra_uart_decode_rx_error(tup,
745 tegra_uart_read(tup, UART_LSR));
746 break;
747
748 case 5: /* break nothing to handle */
749 case 7: /* break nothing to handle */
750 break;
751 }
752 }
753 }
754
755 static void tegra_uart_stop_rx(struct uart_port *u)
756 {
757 struct tegra_uart_port *tup = to_tegra_uport(u);
758 struct tty_struct *tty;
759 struct tty_port *port = &u->state->port;
760 struct dma_tx_state state;
761 unsigned long ier;
762 int count;
763
764 if (tup->rts_active)
765 set_rts(tup, false);
766
767 if (!tup->rx_in_progress)
768 return;
769
770 tty = tty_port_tty_get(&tup->uport.state->port);
771
772 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */
773
774 ier = tup->ier_shadow;
775 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
776 TEGRA_UART_IER_EORD);
777 tup->ier_shadow = ier;
778 tegra_uart_write(tup, ier, UART_IER);
779 tup->rx_in_progress = 0;
780 if (tup->rx_dma_chan) {
781 dmaengine_terminate_all(tup->rx_dma_chan);
782 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
783 async_tx_ack(tup->rx_dma_desc);
784 count = tup->rx_bytes_requested - state.residue;
785 tegra_uart_copy_rx_to_tty(tup, port, count);
786 tegra_uart_handle_rx_pio(tup, port);
787 } else {
788 tegra_uart_handle_rx_pio(tup, port);
789 }
790 if (tty) {
791 tty_flip_buffer_push(port);
792 tty_kref_put(tty);
793 }
794 return;
795 }
796
797 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
798 {
799 unsigned long flags;
800 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
801 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
802 unsigned long wait_time;
803 unsigned long lsr;
804 unsigned long msr;
805 unsigned long mcr;
806
807 /* Disable interrupts */
808 tegra_uart_write(tup, 0, UART_IER);
809
810 lsr = tegra_uart_read(tup, UART_LSR);
811 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
812 msr = tegra_uart_read(tup, UART_MSR);
813 mcr = tegra_uart_read(tup, UART_MCR);
814 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
815 dev_err(tup->uport.dev,
816 "Tx Fifo not empty, CTS disabled, waiting\n");
817
818 /* Wait for Tx fifo to be empty */
819 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
820 wait_time = min(fifo_empty_time, 100lu);
821 udelay(wait_time);
822 fifo_empty_time -= wait_time;
823 if (!fifo_empty_time) {
824 msr = tegra_uart_read(tup, UART_MSR);
825 mcr = tegra_uart_read(tup, UART_MCR);
826 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
827 (msr & UART_MSR_CTS))
828 dev_err(tup->uport.dev,
829 "Slave not ready\n");
830 break;
831 }
832 lsr = tegra_uart_read(tup, UART_LSR);
833 }
834 }
835
836 spin_lock_irqsave(&tup->uport.lock, flags);
837 /* Reset the Rx and Tx FIFOs */
838 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
839 tup->current_baud = 0;
840 spin_unlock_irqrestore(&tup->uport.lock, flags);
841
842 clk_disable_unprepare(tup->uart_clk);
843 }
844
845 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
846 {
847 int ret;
848
849 tup->fcr_shadow = 0;
850 tup->mcr_shadow = 0;
851 tup->lcr_shadow = 0;
852 tup->ier_shadow = 0;
853 tup->current_baud = 0;
854
855 clk_prepare_enable(tup->uart_clk);
856
857 /* Reset the UART controller to clear all previous status.*/
858 reset_control_assert(tup->rst);
859 udelay(10);
860 reset_control_deassert(tup->rst);
861
862 tup->rx_in_progress = 0;
863 tup->tx_in_progress = 0;
864
865 /*
866 * Set the trigger level
867 *
868 * For PIO mode:
869 *
870 * For receive, this will interrupt the CPU after that many number of
871 * bytes are received, for the remaining bytes the receive timeout
872 * interrupt is received. Rx high watermark is set to 4.
873 *
874 * For transmit, if the trasnmit interrupt is enabled, this will
875 * interrupt the CPU when the number of entries in the FIFO reaches the
876 * low watermark. Tx low watermark is set to 16 bytes.
877 *
878 * For DMA mode:
879 *
880 * Set the Tx trigger to 16. This should match the DMA burst size that
881 * programmed in the DMA registers.
882 */
883 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
884 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
885 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
886 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
887
888 /* Dummy read to ensure the write is posted */
889 tegra_uart_read(tup, UART_SCR);
890
891 /*
892 * For all tegra devices (up to t210), there is a hardware issue that
893 * requires software to wait for 3 UART clock periods after enabling
894 * the TX fifo, otherwise data could be lost.
895 */
896 tegra_uart_wait_cycle_time(tup, 3);
897
898 /*
899 * Initialize the UART with default configuration
900 * (115200, N, 8, 1) so that the receive DMA buffer may be
901 * enqueued
902 */
903 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
904 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
905 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
906 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
907
908 ret = tegra_uart_start_rx_dma(tup);
909 if (ret < 0) {
910 dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
911 return ret;
912 }
913 tup->rx_in_progress = 1;
914
915 /*
916 * Enable IE_RXS for the receive status interrupts like line errros.
917 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
918 *
919 * If using DMA mode, enable EORD instead of receive interrupt which
920 * will interrupt after the UART is done with the receive instead of
921 * the interrupt when the FIFO "threshold" is reached.
922 *
923 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
924 * the DATA is sitting in the FIFO and couldn't be transferred to the
925 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
926 * triggered when there is a pause of the incomming data stream for 4
927 * characters long.
928 *
929 * For pauses in the data which is not aligned to 4 bytes, we get
930 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
931 * then the EORD.
932 */
933 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD;
934 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
935 return 0;
936 }
937
938 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
939 bool dma_to_memory)
940 {
941 struct dma_chan *dma_chan;
942 unsigned char *dma_buf;
943 dma_addr_t dma_phys;
944 int ret;
945 struct dma_slave_config dma_sconfig;
946
947 dma_chan = dma_request_slave_channel_reason(tup->uport.dev,
948 dma_to_memory ? "rx" : "tx");
949 if (IS_ERR(dma_chan)) {
950 ret = PTR_ERR(dma_chan);
951 dev_err(tup->uport.dev,
952 "DMA channel alloc failed: %d\n", ret);
953 return ret;
954 }
955
956 if (dma_to_memory) {
957 dma_buf = dma_alloc_coherent(tup->uport.dev,
958 TEGRA_UART_RX_DMA_BUFFER_SIZE,
959 &dma_phys, GFP_KERNEL);
960 if (!dma_buf) {
961 dev_err(tup->uport.dev,
962 "Not able to allocate the dma buffer\n");
963 dma_release_channel(dma_chan);
964 return -ENOMEM;
965 }
966 } else {
967 dma_phys = dma_map_single(tup->uport.dev,
968 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
969 DMA_TO_DEVICE);
970 dma_buf = tup->uport.state->xmit.buf;
971 }
972
973 if (dma_to_memory) {
974 dma_sconfig.src_addr = tup->uport.mapbase;
975 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
976 dma_sconfig.src_maxburst = 4;
977 } else {
978 dma_sconfig.dst_addr = tup->uport.mapbase;
979 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
980 dma_sconfig.dst_maxburst = 16;
981 }
982
983 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
984 if (ret < 0) {
985 dev_err(tup->uport.dev,
986 "Dma slave config failed, err = %d\n", ret);
987 goto scrub;
988 }
989
990 if (dma_to_memory) {
991 tup->rx_dma_chan = dma_chan;
992 tup->rx_dma_buf_virt = dma_buf;
993 tup->rx_dma_buf_phys = dma_phys;
994 } else {
995 tup->tx_dma_chan = dma_chan;
996 tup->tx_dma_buf_virt = dma_buf;
997 tup->tx_dma_buf_phys = dma_phys;
998 }
999 return 0;
1000
1001 scrub:
1002 dma_release_channel(dma_chan);
1003 return ret;
1004 }
1005
1006 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
1007 bool dma_to_memory)
1008 {
1009 struct dma_chan *dma_chan;
1010
1011 if (dma_to_memory) {
1012 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
1013 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
1014 dma_chan = tup->rx_dma_chan;
1015 tup->rx_dma_chan = NULL;
1016 tup->rx_dma_buf_phys = 0;
1017 tup->rx_dma_buf_virt = NULL;
1018 } else {
1019 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
1020 UART_XMIT_SIZE, DMA_TO_DEVICE);
1021 dma_chan = tup->tx_dma_chan;
1022 tup->tx_dma_chan = NULL;
1023 tup->tx_dma_buf_phys = 0;
1024 tup->tx_dma_buf_virt = NULL;
1025 }
1026 dma_release_channel(dma_chan);
1027 }
1028
1029 static int tegra_uart_startup(struct uart_port *u)
1030 {
1031 struct tegra_uart_port *tup = to_tegra_uport(u);
1032 int ret;
1033
1034 ret = tegra_uart_dma_channel_allocate(tup, false);
1035 if (ret < 0) {
1036 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret);
1037 return ret;
1038 }
1039
1040 ret = tegra_uart_dma_channel_allocate(tup, true);
1041 if (ret < 0) {
1042 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret);
1043 goto fail_rx_dma;
1044 }
1045
1046 ret = tegra_uart_hw_init(tup);
1047 if (ret < 0) {
1048 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1049 goto fail_hw_init;
1050 }
1051
1052 ret = request_irq(u->irq, tegra_uart_isr, 0,
1053 dev_name(u->dev), tup);
1054 if (ret < 0) {
1055 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1056 goto fail_hw_init;
1057 }
1058 return 0;
1059
1060 fail_hw_init:
1061 tegra_uart_dma_channel_free(tup, true);
1062 fail_rx_dma:
1063 tegra_uart_dma_channel_free(tup, false);
1064 return ret;
1065 }
1066
1067 /*
1068 * Flush any TX data submitted for DMA and PIO. Called when the
1069 * TX circular buffer is reset.
1070 */
1071 static void tegra_uart_flush_buffer(struct uart_port *u)
1072 {
1073 struct tegra_uart_port *tup = to_tegra_uport(u);
1074
1075 tup->tx_bytes = 0;
1076 if (tup->tx_dma_chan)
1077 dmaengine_terminate_all(tup->tx_dma_chan);
1078 return;
1079 }
1080
1081 static void tegra_uart_shutdown(struct uart_port *u)
1082 {
1083 struct tegra_uart_port *tup = to_tegra_uport(u);
1084
1085 tegra_uart_hw_deinit(tup);
1086
1087 tup->rx_in_progress = 0;
1088 tup->tx_in_progress = 0;
1089
1090 tegra_uart_dma_channel_free(tup, true);
1091 tegra_uart_dma_channel_free(tup, false);
1092 free_irq(u->irq, tup);
1093
1094 tegra_uart_flush_buffer(u);
1095 }
1096
1097 static void tegra_uart_enable_ms(struct uart_port *u)
1098 {
1099 struct tegra_uart_port *tup = to_tegra_uport(u);
1100
1101 if (tup->enable_modem_interrupt) {
1102 tup->ier_shadow |= UART_IER_MSI;
1103 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1104 }
1105 }
1106
1107 static void tegra_uart_set_termios(struct uart_port *u,
1108 struct ktermios *termios, struct ktermios *oldtermios)
1109 {
1110 struct tegra_uart_port *tup = to_tegra_uport(u);
1111 unsigned int baud;
1112 unsigned long flags;
1113 unsigned int lcr;
1114 int symb_bit = 1;
1115 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1116 unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1117 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1118
1119 max_divider *= 16;
1120 spin_lock_irqsave(&u->lock, flags);
1121
1122 /* Changing configuration, it is safe to stop any rx now */
1123 if (tup->rts_active)
1124 set_rts(tup, false);
1125
1126 /* Clear all interrupts as configuration is going to be change */
1127 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1128 tegra_uart_read(tup, UART_IER);
1129 tegra_uart_write(tup, 0, UART_IER);
1130 tegra_uart_read(tup, UART_IER);
1131
1132 /* Parity */
1133 lcr = tup->lcr_shadow;
1134 lcr &= ~UART_LCR_PARITY;
1135
1136 /* CMSPAR isn't supported by this driver */
1137 termios->c_cflag &= ~CMSPAR;
1138
1139 if ((termios->c_cflag & PARENB) == PARENB) {
1140 symb_bit++;
1141 if (termios->c_cflag & PARODD) {
1142 lcr |= UART_LCR_PARITY;
1143 lcr &= ~UART_LCR_EPAR;
1144 lcr &= ~UART_LCR_SPAR;
1145 } else {
1146 lcr |= UART_LCR_PARITY;
1147 lcr |= UART_LCR_EPAR;
1148 lcr &= ~UART_LCR_SPAR;
1149 }
1150 }
1151
1152 lcr &= ~UART_LCR_WLEN8;
1153 switch (termios->c_cflag & CSIZE) {
1154 case CS5:
1155 lcr |= UART_LCR_WLEN5;
1156 symb_bit += 5;
1157 break;
1158 case CS6:
1159 lcr |= UART_LCR_WLEN6;
1160 symb_bit += 6;
1161 break;
1162 case CS7:
1163 lcr |= UART_LCR_WLEN7;
1164 symb_bit += 7;
1165 break;
1166 default:
1167 lcr |= UART_LCR_WLEN8;
1168 symb_bit += 8;
1169 break;
1170 }
1171
1172 /* Stop bits */
1173 if (termios->c_cflag & CSTOPB) {
1174 lcr |= UART_LCR_STOP;
1175 symb_bit += 2;
1176 } else {
1177 lcr &= ~UART_LCR_STOP;
1178 symb_bit++;
1179 }
1180
1181 tegra_uart_write(tup, lcr, UART_LCR);
1182 tup->lcr_shadow = lcr;
1183 tup->symb_bit = symb_bit;
1184
1185 /* Baud rate. */
1186 baud = uart_get_baud_rate(u, termios, oldtermios,
1187 parent_clk_rate/max_divider,
1188 parent_clk_rate/16);
1189 spin_unlock_irqrestore(&u->lock, flags);
1190 tegra_set_baudrate(tup, baud);
1191 if (tty_termios_baud_rate(termios))
1192 tty_termios_encode_baud_rate(termios, baud, baud);
1193 spin_lock_irqsave(&u->lock, flags);
1194
1195 /* Flow control */
1196 if (termios->c_cflag & CRTSCTS) {
1197 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1198 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1199 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1200 /* if top layer has asked to set rts active then do so here */
1201 if (tup->rts_active)
1202 set_rts(tup, true);
1203 } else {
1204 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1205 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1206 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1207 }
1208
1209 /* update the port timeout based on new settings */
1210 uart_update_timeout(u, termios->c_cflag, baud);
1211
1212 /* Make sure all write has completed */
1213 tegra_uart_read(tup, UART_IER);
1214
1215 /* Reenable interrupt */
1216 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1217 tegra_uart_read(tup, UART_IER);
1218
1219 spin_unlock_irqrestore(&u->lock, flags);
1220 return;
1221 }
1222
1223 static const char *tegra_uart_type(struct uart_port *u)
1224 {
1225 return TEGRA_UART_TYPE;
1226 }
1227
1228 static struct uart_ops tegra_uart_ops = {
1229 .tx_empty = tegra_uart_tx_empty,
1230 .set_mctrl = tegra_uart_set_mctrl,
1231 .get_mctrl = tegra_uart_get_mctrl,
1232 .stop_tx = tegra_uart_stop_tx,
1233 .start_tx = tegra_uart_start_tx,
1234 .stop_rx = tegra_uart_stop_rx,
1235 .flush_buffer = tegra_uart_flush_buffer,
1236 .enable_ms = tegra_uart_enable_ms,
1237 .break_ctl = tegra_uart_break_ctl,
1238 .startup = tegra_uart_startup,
1239 .shutdown = tegra_uart_shutdown,
1240 .set_termios = tegra_uart_set_termios,
1241 .type = tegra_uart_type,
1242 .request_port = tegra_uart_request_port,
1243 .release_port = tegra_uart_release_port,
1244 };
1245
1246 static struct uart_driver tegra_uart_driver = {
1247 .owner = THIS_MODULE,
1248 .driver_name = "tegra_hsuart",
1249 .dev_name = "ttyTHS",
1250 .cons = NULL,
1251 .nr = TEGRA_UART_MAXIMUM,
1252 };
1253
1254 static int tegra_uart_parse_dt(struct platform_device *pdev,
1255 struct tegra_uart_port *tup)
1256 {
1257 struct device_node *np = pdev->dev.of_node;
1258 int port;
1259
1260 port = of_alias_get_id(np, "serial");
1261 if (port < 0) {
1262 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1263 return port;
1264 }
1265 tup->uport.line = port;
1266
1267 tup->enable_modem_interrupt = of_property_read_bool(np,
1268 "nvidia,enable-modem-interrupt");
1269 return 0;
1270 }
1271
1272 static struct tegra_uart_chip_data tegra20_uart_chip_data = {
1273 .tx_fifo_full_status = false,
1274 .allow_txfifo_reset_fifo_mode = true,
1275 .support_clk_src_div = false,
1276 };
1277
1278 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1279 .tx_fifo_full_status = true,
1280 .allow_txfifo_reset_fifo_mode = false,
1281 .support_clk_src_div = true,
1282 };
1283
1284 static const struct of_device_id tegra_uart_of_match[] = {
1285 {
1286 .compatible = "nvidia,tegra30-hsuart",
1287 .data = &tegra30_uart_chip_data,
1288 }, {
1289 .compatible = "nvidia,tegra20-hsuart",
1290 .data = &tegra20_uart_chip_data,
1291 }, {
1292 },
1293 };
1294 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1295
1296 static int tegra_uart_probe(struct platform_device *pdev)
1297 {
1298 struct tegra_uart_port *tup;
1299 struct uart_port *u;
1300 struct resource *resource;
1301 int ret;
1302 const struct tegra_uart_chip_data *cdata;
1303 const struct of_device_id *match;
1304
1305 match = of_match_device(tegra_uart_of_match, &pdev->dev);
1306 if (!match) {
1307 dev_err(&pdev->dev, "Error: No device match found\n");
1308 return -ENODEV;
1309 }
1310 cdata = match->data;
1311
1312 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1313 if (!tup) {
1314 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1315 return -ENOMEM;
1316 }
1317
1318 ret = tegra_uart_parse_dt(pdev, tup);
1319 if (ret < 0)
1320 return ret;
1321
1322 u = &tup->uport;
1323 u->dev = &pdev->dev;
1324 u->ops = &tegra_uart_ops;
1325 u->type = PORT_TEGRA;
1326 u->fifosize = 32;
1327 tup->cdata = cdata;
1328
1329 platform_set_drvdata(pdev, tup);
1330 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1331 if (!resource) {
1332 dev_err(&pdev->dev, "No IO memory resource\n");
1333 return -ENODEV;
1334 }
1335
1336 u->mapbase = resource->start;
1337 u->membase = devm_ioremap_resource(&pdev->dev, resource);
1338 if (IS_ERR(u->membase))
1339 return PTR_ERR(u->membase);
1340
1341 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1342 if (IS_ERR(tup->uart_clk)) {
1343 dev_err(&pdev->dev, "Couldn't get the clock\n");
1344 return PTR_ERR(tup->uart_clk);
1345 }
1346
1347 tup->rst = devm_reset_control_get(&pdev->dev, "serial");
1348 if (IS_ERR(tup->rst)) {
1349 dev_err(&pdev->dev, "Couldn't get the reset\n");
1350 return PTR_ERR(tup->rst);
1351 }
1352
1353 u->iotype = UPIO_MEM32;
1354 u->irq = platform_get_irq(pdev, 0);
1355 u->regshift = 2;
1356 ret = uart_add_one_port(&tegra_uart_driver, u);
1357 if (ret < 0) {
1358 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1359 return ret;
1360 }
1361 return ret;
1362 }
1363
1364 static int tegra_uart_remove(struct platform_device *pdev)
1365 {
1366 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1367 struct uart_port *u = &tup->uport;
1368
1369 uart_remove_one_port(&tegra_uart_driver, u);
1370 return 0;
1371 }
1372
1373 #ifdef CONFIG_PM_SLEEP
1374 static int tegra_uart_suspend(struct device *dev)
1375 {
1376 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1377 struct uart_port *u = &tup->uport;
1378
1379 return uart_suspend_port(&tegra_uart_driver, u);
1380 }
1381
1382 static int tegra_uart_resume(struct device *dev)
1383 {
1384 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1385 struct uart_port *u = &tup->uport;
1386
1387 return uart_resume_port(&tegra_uart_driver, u);
1388 }
1389 #endif
1390
1391 static const struct dev_pm_ops tegra_uart_pm_ops = {
1392 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1393 };
1394
1395 static struct platform_driver tegra_uart_platform_driver = {
1396 .probe = tegra_uart_probe,
1397 .remove = tegra_uart_remove,
1398 .driver = {
1399 .name = "serial-tegra",
1400 .of_match_table = tegra_uart_of_match,
1401 .pm = &tegra_uart_pm_ops,
1402 },
1403 };
1404
1405 static int __init tegra_uart_init(void)
1406 {
1407 int ret;
1408
1409 ret = uart_register_driver(&tegra_uart_driver);
1410 if (ret < 0) {
1411 pr_err("Could not register %s driver\n",
1412 tegra_uart_driver.driver_name);
1413 return ret;
1414 }
1415
1416 ret = platform_driver_register(&tegra_uart_platform_driver);
1417 if (ret < 0) {
1418 pr_err("Uart platform driver register failed, e = %d\n", ret);
1419 uart_unregister_driver(&tegra_uart_driver);
1420 return ret;
1421 }
1422 return 0;
1423 }
1424
1425 static void __exit tegra_uart_exit(void)
1426 {
1427 pr_info("Unloading tegra uart driver\n");
1428 platform_driver_unregister(&tegra_uart_platform_driver);
1429 uart_unregister_driver(&tegra_uart_driver);
1430 }
1431
1432 module_init(tegra_uart_init);
1433 module_exit(tegra_uart_exit);
1434
1435 MODULE_ALIAS("platform:serial-tegra");
1436 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1437 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1438 MODULE_LICENSE("GPL v2");
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