sound/soc/atmel/atmel_ssc_dai.c

   1 /*
   2  * atmel_ssc_dai.c  --  ALSA SoC ATMEL SSC Audio Layer Platform driver
   3  *
   4  * Copyright (C) 2005 SAN People
   5  * Copyright (C) 2008 Atmel
   6  *
   7  * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
   8  *         ATMEL CORP.
   9  *
  10  * Based on at91-ssc.c by
  11  * Frank Mandarino <fmandarino@endrelia.com>
  12  * Based on pxa2xx Platform drivers by
  13  * Liam Girdwood <lrg@slimlogic.co.uk>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  28  */
  29
  30 #include <linux/init.h>
  31 #include <linux/module.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/device.h>
  34 #include <linux/delay.h>
  35 #include <linux/clk.h>
  36 #include <linux/atmel_pdc.h>
  37
  38 #include <linux/atmel-ssc.h>
  39 #include <sound/core.h>
  40 #include <sound/pcm.h>
  41 #include <sound/pcm_params.h>
  42 #include <sound/initval.h>
  43 #include <sound/soc.h>
  44
  45 #include "atmel-pcm.h"
  46 #include "atmel_ssc_dai.h"
  47
  48
  49 #define NUM_SSC_DEVICES         3
  50
  51 /*
  52  * SSC PDC registers required by the PCM DMA engine.
  53  */
  54 static struct atmel_pdc_regs pdc_tx_reg = {
  55         .xpr            = ATMEL_PDC_TPR,
  56         .xcr            = ATMEL_PDC_TCR,
  57         .xnpr           = ATMEL_PDC_TNPR,
  58         .xncr           = ATMEL_PDC_TNCR,
  59 };
  60
  61 static struct atmel_pdc_regs pdc_rx_reg = {
  62         .xpr            = ATMEL_PDC_RPR,
  63         .xcr            = ATMEL_PDC_RCR,
  64         .xnpr           = ATMEL_PDC_RNPR,
  65         .xncr           = ATMEL_PDC_RNCR,
  66 };
  67
  68 /*
  69  * SSC & PDC status bits for transmit and receive.
  70  */
  71 static struct atmel_ssc_mask ssc_tx_mask = {
  72         .ssc_enable     = SSC_BIT(CR_TXEN),
  73         .ssc_disable    = SSC_BIT(CR_TXDIS),
  74         .ssc_endx       = SSC_BIT(SR_ENDTX),
  75         .ssc_endbuf     = SSC_BIT(SR_TXBUFE),
  76         .ssc_error      = SSC_BIT(SR_OVRUN),
  77         .pdc_enable     = ATMEL_PDC_TXTEN,
  78         .pdc_disable    = ATMEL_PDC_TXTDIS,
  79 };
  80
  81 static struct atmel_ssc_mask ssc_rx_mask = {
  82         .ssc_enable     = SSC_BIT(CR_RXEN),
  83         .ssc_disable    = SSC_BIT(CR_RXDIS),
  84         .ssc_endx       = SSC_BIT(SR_ENDRX),
  85         .ssc_endbuf     = SSC_BIT(SR_RXBUFF),
  86         .ssc_error      = SSC_BIT(SR_OVRUN),
  87         .pdc_enable     = ATMEL_PDC_RXTEN,
  88         .pdc_disable    = ATMEL_PDC_RXTDIS,
  89 };
  90
  91
  92 /*
  93  * DMA parameters.
  94  */
  95 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
  96         {{
  97         .name           = "SSC0 PCM out",
  98         .pdc            = &pdc_tx_reg,
  99         .mask           = &ssc_tx_mask,
 100         },
 101         {
 102         .name           = "SSC0 PCM in",
 103         .pdc            = &pdc_rx_reg,
 104         .mask           = &ssc_rx_mask,
 105         } },
 106         {{
 107         .name           = "SSC1 PCM out",
 108         .pdc            = &pdc_tx_reg,
 109         .mask           = &ssc_tx_mask,
 110         },
 111         {
 112         .name           = "SSC1 PCM in",
 113         .pdc            = &pdc_rx_reg,
 114         .mask           = &ssc_rx_mask,
 115         } },
 116         {{
 117         .name           = "SSC2 PCM out",
 118         .pdc            = &pdc_tx_reg,
 119         .mask           = &ssc_tx_mask,
 120         },
 121         {
 122         .name           = "SSC2 PCM in",
 123         .pdc            = &pdc_rx_reg,
 124         .mask           = &ssc_rx_mask,
 125         } },
 126 };
 127
 128
 129 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
 130         {
 131         .name           = "ssc0",
 132         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
 133         .dir_mask       = SSC_DIR_MASK_UNUSED,
 134         .initialized    = 0,
 135         },
 136         {
 137         .name           = "ssc1",
 138         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
 139         .dir_mask       = SSC_DIR_MASK_UNUSED,
 140         .initialized    = 0,
 141         },
 142         {
 143         .name           = "ssc2",
 144         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
 145         .dir_mask       = SSC_DIR_MASK_UNUSED,
 146         .initialized    = 0,
 147         },
 148 };
 149
 150
 151 /*
 152  * SSC interrupt handler.  Passes PDC interrupts to the DMA
 153  * interrupt handler in the PCM driver.
 154  */
 155 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
 156 {
 157         struct atmel_ssc_info *ssc_p = dev_id;
 158         struct atmel_pcm_dma_params *dma_params;
 159         u32 ssc_sr;
 160         u32 ssc_substream_mask;
 161         int i;
 162
 163         ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
 164                         & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
 165
 166         /*
 167          * Loop through the substreams attached to this SSC.  If
 168          * a DMA-related interrupt occurred on that substream, call
 169          * the DMA interrupt handler function, if one has been
 170          * registered in the dma_params structure by the PCM driver.
 171          */
 172         for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
 173                 dma_params = ssc_p->dma_params[i];
 174
 175                 if ((dma_params != NULL) &&
 176                         (dma_params->dma_intr_handler != NULL)) {
 177                         ssc_substream_mask = (dma_params->mask->ssc_endx |
 178                                         dma_params->mask->ssc_endbuf);
 179                         if (ssc_sr & ssc_substream_mask) {
 180                                 dma_params->dma_intr_handler(ssc_sr,
 181                                                 dma_params->
 182                                                 substream);
 183                         }
 184                 }
 185         }
 186
 187         return IRQ_HANDLED;
 188 }
 189
 190
 191 /*-------------------------------------------------------------------------*\
 192  * DAI functions
 193 \*-------------------------------------------------------------------------*/
 194 /*
 195  * Startup.  Only that one substream allowed in each direction.
 196  */
 197 static int atmel_ssc_startup(struct snd_pcm_substream *substream,
 198                              struct snd_soc_dai *dai)
 199 {
 200         struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
 201         struct atmel_pcm_dma_params *dma_params;
 202         int dir, dir_mask;
 203
 204         pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n",
 205                 ssc_readl(ssc_p->ssc->regs, SR));
 206
 207         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 208                 dir = 0;
 209                 dir_mask = SSC_DIR_MASK_PLAYBACK;
 210         } else {
 211                 dir = 1;
 212                 dir_mask = SSC_DIR_MASK_CAPTURE;
 213         }
 214
 215         dma_params = &ssc_dma_params[dai->id][dir];
 216         dma_params->ssc = ssc_p->ssc;
 217         dma_params->substream = substream;
 218
 219         ssc_p->dma_params[dir] = dma_params;
 220
 221         snd_soc_dai_set_dma_data(dai, substream, dma_params);
 222
 223         spin_lock_irq(&ssc_p->lock);
 224         if (ssc_p->dir_mask & dir_mask) {
 225                 spin_unlock_irq(&ssc_p->lock);
 226                 return -EBUSY;
 227         }
 228         ssc_p->dir_mask |= dir_mask;
 229         spin_unlock_irq(&ssc_p->lock);
 230
 231         return 0;
 232 }
 233
 234 /*
 235  * Shutdown.  Clear DMA parameters and shutdown the SSC if there
 236  * are no other substreams open.
 237  */
 238 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
 239                                struct snd_soc_dai *dai)
 240 {
 241         struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
 242         struct atmel_pcm_dma_params *dma_params;
 243         int dir, dir_mask;
 244
 245         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 246                 dir = 0;
 247         else
 248                 dir = 1;
 249
 250         dma_params = ssc_p->dma_params[dir];
 251
 252         if (dma_params != NULL) {
 253                 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
 254                 pr_debug("atmel_ssc_shutdown: %s disabled SSC_SR=0x%08x\n",
 255                         (dir ? "receive" : "transmit"),
 256                         ssc_readl(ssc_p->ssc->regs, SR));
 257
 258                 dma_params->ssc = NULL;
 259                 dma_params->substream = NULL;
 260                 ssc_p->dma_params[dir] = NULL;
 261         }
 262
 263         dir_mask = 1 << dir;
 264
 265         spin_lock_irq(&ssc_p->lock);
 266         ssc_p->dir_mask &= ~dir_mask;
 267         if (!ssc_p->dir_mask) {
 268                 if (ssc_p->initialized) {
 269                         /* Shutdown the SSC clock. */
 270                         pr_debug("atmel_ssc_dau: Stopping clock\n");
 271                         clk_disable(ssc_p->ssc->clk);
 272
 273                         free_irq(ssc_p->ssc->irq, ssc_p);
 274                         ssc_p->initialized = 0;
 275                 }
 276
 277                 /* Reset the SSC */
 278                 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
 279                 /* Clear the SSC dividers */
 280                 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
 281         }
 282         spin_unlock_irq(&ssc_p->lock);
 283 }
 284
 285
 286 /*
 287  * Record the DAI format for use in hw_params().
 288  */
 289 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 290                 unsigned int fmt)
 291 {
 292         struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
 293
 294         ssc_p->daifmt = fmt;
 295         return 0;
 296 }
 297
 298 /*
 299  * Record SSC clock dividers for use in hw_params().
 300  */
 301 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
 302         int div_id, int div)
 303 {
 304         struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
 305
 306         switch (div_id) {
 307         case ATMEL_SSC_CMR_DIV:
 308                 /*
 309                  * The same master clock divider is used for both
 310                  * transmit and receive, so if a value has already
 311                  * been set, it must match this value.
 312                  */
 313                 if (ssc_p->cmr_div == 0)
 314                         ssc_p->cmr_div = div;
 315                 else
 316                         if (div != ssc_p->cmr_div)
 317                                 return -EBUSY;
 318                 break;
 319
 320         case ATMEL_SSC_TCMR_PERIOD:
 321                 ssc_p->tcmr_period = div;
 322                 break;
 323
 324         case ATMEL_SSC_RCMR_PERIOD:
 325                 ssc_p->rcmr_period = div;
 326                 break;
 327
 328         default:
 329                 return -EINVAL;
 330         }
 331
 332         return 0;
 333 }
 334
 335 /*
 336  * Configure the SSC.
 337  */
 338 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
 339         struct snd_pcm_hw_params *params,
 340         struct snd_soc_dai *dai)
 341 {
 342         int id = dai->id;
 343         struct atmel_ssc_info *ssc_p = &ssc_info[id];
 344         struct ssc_device *ssc = ssc_p->ssc;
 345         struct atmel_pcm_dma_params *dma_params;
 346         int dir, channels, bits;
 347         u32 tfmr, rfmr, tcmr, rcmr;
 348         int start_event;
 349         int ret;
 350
 351         /*
 352          * Currently, there is only one set of dma params for
 353          * each direction.  If more are added, this code will
 354          * have to be changed to select the proper set.
 355          */
 356         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 357                 dir = 0;
 358         else
 359                 dir = 1;
 360
 361         dma_params = ssc_p->dma_params[dir];
 362
 363         channels = params_channels(params);
 364
 365         /*
 366          * Determine sample size in bits and the PDC increment.
 367          */
 368         switch (params_format(params)) {
 369         case SNDRV_PCM_FORMAT_S8:
 370                 bits = 8;
 371                 dma_params->pdc_xfer_size = 1;
 372                 break;
 373         case SNDRV_PCM_FORMAT_S16_LE:
 374                 bits = 16;
 375                 dma_params->pdc_xfer_size = 2;
 376                 break;
 377         case SNDRV_PCM_FORMAT_S24_LE:
 378                 bits = 24;
 379                 dma_params->pdc_xfer_size = 4;
 380                 break;
 381         case SNDRV_PCM_FORMAT_S32_LE:
 382                 bits = 32;
 383                 dma_params->pdc_xfer_size = 4;
 384                 break;
 385         default:
 386                 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
 387                 return -EINVAL;
 388         }
 389
 390         /*
 391          * The SSC only supports up to 16-bit samples in I2S format, due
 392          * to the size of the Frame Mode Register FSLEN field.
 393          */
 394         if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S
 395                 && bits > 16) {
 396                 printk(KERN_WARNING
 397                                 "atmel_ssc_dai: sample size %d "
 398                                 "is too large for I2S\n", bits);
 399                 return -EINVAL;
 400         }
 401
 402         /*
 403          * Compute SSC register settings.
 404          */
 405         switch (ssc_p->daifmt
 406                 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
 407
 408         case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
 409                 /*
 410                  * I2S format, SSC provides BCLK and LRC clocks.
 411                  *
 412                  * The SSC transmit and receive clocks are generated
 413                  * from the MCK divider, and the BCLK signal
 414                  * is output on the SSC TK line.
 415                  */
 416                 rcmr =    SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
 417                         | SSC_BF(RCMR_STTDLY, START_DELAY)
 418                         | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
 419                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
 420                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 421                         | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
 422
 423                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 424                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
 425                         | SSC_BF(RFMR_FSLEN, (bits - 1))
 426                         | SSC_BF(RFMR_DATNB, (channels - 1))
 427                         | SSC_BIT(RFMR_MSBF)
 428                         | SSC_BF(RFMR_LOOP, 0)
 429                         | SSC_BF(RFMR_DATLEN, (bits - 1));
 430
 431                 tcmr =    SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
 432                         | SSC_BF(TCMR_STTDLY, START_DELAY)
 433                         | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
 434                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
 435                         | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
 436                         | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
 437
 438                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 439                         | SSC_BF(TFMR_FSDEN, 0)
 440                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
 441                         | SSC_BF(TFMR_FSLEN, (bits - 1))
 442                         | SSC_BF(TFMR_DATNB, (channels - 1))
 443                         | SSC_BIT(TFMR_MSBF)
 444                         | SSC_BF(TFMR_DATDEF, 0)
 445                         | SSC_BF(TFMR_DATLEN, (bits - 1));
 446                 break;
 447
 448         case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
 449                 /*
 450                  * I2S format, CODEC supplies BCLK and LRC clocks.
 451                  *
 452                  * The SSC transmit clock is obtained from the BCLK signal on
 453                  * on the TK line, and the SSC receive clock is
 454                  * generated from the transmit clock.
 455                  *
 456                  *  For single channel data, one sample is transferred
 457                  * on the falling edge of the LRC clock.
 458                  * For two channel data, one sample is
 459                  * transferred on both edges of the LRC clock.
 460                  */
 461                 start_event = ((channels == 1)
 462                                 ? SSC_START_FALLING_RF
 463                                 : SSC_START_EDGE_RF);
 464
 465                 rcmr =    SSC_BF(RCMR_PERIOD, 0)
 466                         | SSC_BF(RCMR_STTDLY, START_DELAY)
 467                         | SSC_BF(RCMR_START, start_event)
 468                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
 469                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 470                         | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
 471                                            SSC_CKS_PIN : SSC_CKS_CLOCK);
 472
 473                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 474                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
 475                         | SSC_BF(RFMR_FSLEN, 0)
 476                         | SSC_BF(RFMR_DATNB, 0)
 477                         | SSC_BIT(RFMR_MSBF)
 478                         | SSC_BF(RFMR_LOOP, 0)
 479                         | SSC_BF(RFMR_DATLEN, (bits - 1));
 480
 481                 tcmr =    SSC_BF(TCMR_PERIOD, 0)
 482                         | SSC_BF(TCMR_STTDLY, START_DELAY)
 483                         | SSC_BF(TCMR_START, start_event)
 484                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
 485                         | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
 486                         | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
 487                                            SSC_CKS_CLOCK : SSC_CKS_PIN);
 488
 489                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 490                         | SSC_BF(TFMR_FSDEN, 0)
 491                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
 492                         | SSC_BF(TFMR_FSLEN, 0)
 493                         | SSC_BF(TFMR_DATNB, 0)
 494                         | SSC_BIT(TFMR_MSBF)
 495                         | SSC_BF(TFMR_DATDEF, 0)
 496                         | SSC_BF(TFMR_DATLEN, (bits - 1));
 497                 break;
 498
 499         case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
 500                 /*
 501                  * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
 502                  *
 503                  * The SSC transmit and receive clocks are generated from the
 504                  * MCK divider, and the BCLK signal is output
 505                  * on the SSC TK line.
 506                  */
 507                 rcmr =    SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
 508                         | SSC_BF(RCMR_STTDLY, 1)
 509                         | SSC_BF(RCMR_START, SSC_START_RISING_RF)
 510                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
 511                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 512                         | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
 513
 514                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 515                         | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
 516                         | SSC_BF(RFMR_FSLEN, 0)
 517                         | SSC_BF(RFMR_DATNB, (channels - 1))
 518                         | SSC_BIT(RFMR_MSBF)
 519                         | SSC_BF(RFMR_LOOP, 0)
 520                         | SSC_BF(RFMR_DATLEN, (bits - 1));
 521
 522                 tcmr =    SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
 523                         | SSC_BF(TCMR_STTDLY, 1)
 524                         | SSC_BF(TCMR_START, SSC_START_RISING_RF)
 525                         | SSC_BF(TCMR_CKI, SSC_CKI_RISING)
 526                         | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
 527                         | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
 528
 529                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 530                         | SSC_BF(TFMR_FSDEN, 0)
 531                         | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
 532                         | SSC_BF(TFMR_FSLEN, 0)
 533                         | SSC_BF(TFMR_DATNB, (channels - 1))
 534                         | SSC_BIT(TFMR_MSBF)
 535                         | SSC_BF(TFMR_DATDEF, 0)
 536                         | SSC_BF(TFMR_DATLEN, (bits - 1));
 537                 break;
 538
 539         case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
 540                 /*
 541                  * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
 542                  *
 543                  * The SSC transmit clock is obtained from the BCLK signal on
 544                  * on the TK line, and the SSC receive clock is
 545                  * generated from the transmit clock.
 546                  *
 547                  * Data is transferred on first BCLK after LRC pulse rising
 548                  * edge.If stereo, the right channel data is contiguous with
 549                  * the left channel data.
 550                  */
 551                 rcmr =    SSC_BF(RCMR_PERIOD, 0)
 552                         | SSC_BF(RCMR_STTDLY, START_DELAY)
 553                         | SSC_BF(RCMR_START, SSC_START_RISING_RF)
 554                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
 555                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 556                         | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
 557                                            SSC_CKS_PIN : SSC_CKS_CLOCK);
 558
 559                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 560                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
 561                         | SSC_BF(RFMR_FSLEN, 0)
 562                         | SSC_BF(RFMR_DATNB, (channels - 1))
 563                         | SSC_BIT(RFMR_MSBF)
 564                         | SSC_BF(RFMR_LOOP, 0)
 565                         | SSC_BF(RFMR_DATLEN, (bits - 1));
 566
 567                 tcmr =    SSC_BF(TCMR_PERIOD, 0)
 568                         | SSC_BF(TCMR_STTDLY, START_DELAY)
 569                         | SSC_BF(TCMR_START, SSC_START_RISING_RF)
 570                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
 571                         | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
 572                         | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
 573                                            SSC_CKS_CLOCK : SSC_CKS_PIN);
 574
 575                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 576                         | SSC_BF(TFMR_FSDEN, 0)
 577                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
 578                         | SSC_BF(TFMR_FSLEN, 0)
 579                         | SSC_BF(TFMR_DATNB, (channels - 1))
 580                         | SSC_BIT(TFMR_MSBF)
 581                         | SSC_BF(TFMR_DATDEF, 0)
 582                         | SSC_BF(TFMR_DATLEN, (bits - 1));
 583                 break;
 584
 585         default:
 586                 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
 587                         ssc_p->daifmt);
 588                 return -EINVAL;
 589         }
 590         pr_debug("atmel_ssc_hw_params: "
 591                         "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
 592                         rcmr, rfmr, tcmr, tfmr);
 593
 594         if (!ssc_p->initialized) {
 595
 596                 /* Enable PMC peripheral clock for this SSC */
 597                 pr_debug("atmel_ssc_dai: Starting clock\n");
 598                 clk_enable(ssc_p->ssc->clk);
 599
 600                 /* Reset the SSC and its PDC registers */
 601                 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
 602
 603                 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
 604                 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
 605                 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
 606                 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
 607
 608                 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
 609                 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
 610                 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
 611                 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
 612
 613                 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
 614                                 ssc_p->name, ssc_p);
 615                 if (ret < 0) {
 616                         printk(KERN_WARNING
 617                                         "atmel_ssc_dai: request_irq failure\n");
 618                         pr_debug("Atmel_ssc_dai: Stoping clock\n");
 619                         clk_disable(ssc_p->ssc->clk);
 620                         return ret;
 621                 }
 622
 623                 ssc_p->initialized = 1;
 624         }
 625
 626         /* set SSC clock mode register */
 627         ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
 628
 629         /* set receive clock mode and format */
 630         ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
 631         ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
 632
 633         /* set transmit clock mode and format */
 634         ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
 635         ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
 636
 637         pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
 638         return 0;
 639 }
 640
 641
 642 static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
 643                              struct snd_soc_dai *dai)
 644 {
 645         struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
 646         struct atmel_pcm_dma_params *dma_params;
 647         int dir;
 648
 649         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 650                 dir = 0;
 651         else
 652                 dir = 1;
 653
 654         dma_params = ssc_p->dma_params[dir];
 655
 656         ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
 657         ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error);
 658
 659         pr_debug("%s enabled SSC_SR=0x%08x\n",
 660                         dir ? "receive" : "transmit",
 661                         ssc_readl(ssc_p->ssc->regs, SR));
 662         return 0;
 663 }
 664
 665 static int atmel_ssc_trigger(struct snd_pcm_substream *substream,
 666                              int cmd, struct snd_soc_dai *dai)
 667 {
 668         struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
 669         struct atmel_pcm_dma_params *dma_params;
 670         int dir;
 671
 672         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 673                 dir = 0;
 674         else
 675                 dir = 1;
 676
 677         dma_params = ssc_p->dma_params[dir];
 678
 679         switch (cmd) {
 680         case SNDRV_PCM_TRIGGER_START:
 681         case SNDRV_PCM_TRIGGER_RESUME:
 682         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 683                 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
 684                 break;
 685         default:
 686                 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
 687                 break;
 688         }
 689
 690         return 0;
 691 }
 692
 693 #ifdef CONFIG_PM
 694 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
 695 {
 696         struct atmel_ssc_info *ssc_p;
 697
 698         if (!cpu_dai->active)
 699                 return 0;
 700
 701         ssc_p = &ssc_info[cpu_dai->id];
 702
 703         /* Save the status register before disabling transmit and receive */
 704         ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
 705         ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
 706
 707         /* Save the current interrupt mask, then disable unmasked interrupts */
 708         ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
 709         ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
 710
 711         ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
 712         ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
 713         ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
 714         ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
 715         ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
 716
 717         return 0;
 718 }
 719
 720
 721
 722 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
 723 {
 724         struct atmel_ssc_info *ssc_p;
 725         u32 cr;
 726
 727         if (!cpu_dai->active)
 728                 return 0;
 729
 730         ssc_p = &ssc_info[cpu_dai->id];
 731
 732         /* restore SSC register settings */
 733         ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
 734         ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
 735         ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
 736         ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
 737         ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
 738
 739         /* re-enable interrupts */
 740         ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
 741
 742         /* Re-enable receive and transmit as appropriate */
 743         cr = 0;
 744         cr |=
 745             (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
 746         cr |=
 747             (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
 748         ssc_writel(ssc_p->ssc->regs, CR, cr);
 749
 750         return 0;
 751 }
 752 #else /* CONFIG_PM */
 753 #  define atmel_ssc_suspend     NULL
 754 #  define atmel_ssc_resume      NULL
 755 #endif /* CONFIG_PM */
 756
 757 #define ATMEL_SSC_RATES (SNDRV_PCM_RATE_8000_96000)
 758
 759 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8     | SNDRV_PCM_FMTBIT_S16_LE |\
 760                           SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 761
 762 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
 763         .startup        = atmel_ssc_startup,
 764         .shutdown       = atmel_ssc_shutdown,
 765         .prepare        = atmel_ssc_prepare,
 766         .trigger        = atmel_ssc_trigger,
 767         .hw_params      = atmel_ssc_hw_params,
 768         .set_fmt        = atmel_ssc_set_dai_fmt,
 769         .set_clkdiv     = atmel_ssc_set_dai_clkdiv,
 770 };
 771
 772 static struct snd_soc_dai_driver atmel_ssc_dai = {
 773                 .suspend = atmel_ssc_suspend,
 774                 .resume = atmel_ssc_resume,
 775                 .playback = {
 776                         .channels_min = 1,
 777                         .channels_max = 2,
 778                         .rates = ATMEL_SSC_RATES,
 779                         .formats = ATMEL_SSC_FORMATS,},
 780                 .capture = {
 781                         .channels_min = 1,
 782                         .channels_max = 2,
 783                         .rates = ATMEL_SSC_RATES,
 784                         .formats = ATMEL_SSC_FORMATS,},
 785                 .ops = &atmel_ssc_dai_ops,
 786 };
 787
 788 static const struct snd_soc_component_driver atmel_ssc_component = {
 789         .name           = "atmel-ssc",
 790 };
 791
 792 static int asoc_ssc_init(struct device *dev)
 793 {
 794         struct platform_device *pdev = to_platform_device(dev);
 795         struct ssc_device *ssc = platform_get_drvdata(pdev);
 796         int ret;
 797
 798         ret = snd_soc_register_component(dev, &atmel_ssc_component,
 799                                          &atmel_ssc_dai, 1);
 800         if (ret) {
 801                 dev_err(dev, "Could not register DAI: %d\n", ret);
 802                 goto err;
 803         }
 804
 805         if (ssc->pdata->use_dma)
 806                 ret = atmel_pcm_dma_platform_register(dev);
 807         else
 808                 ret = atmel_pcm_pdc_platform_register(dev);
 809
 810         if (ret) {
 811                 dev_err(dev, "Could not register PCM: %d\n", ret);
 812                 goto err_unregister_dai;
 813         }
 814
 815         return 0;
 816
 817 err_unregister_dai:
 818         snd_soc_unregister_component(dev);
 819 err:
 820         return ret;
 821 }
 822
 823 static void asoc_ssc_exit(struct device *dev)
 824 {
 825         struct platform_device *pdev = to_platform_device(dev);
 826         struct ssc_device *ssc = platform_get_drvdata(pdev);
 827
 828         if (ssc->pdata->use_dma)
 829                 atmel_pcm_dma_platform_unregister(dev);
 830         else
 831                 atmel_pcm_pdc_platform_unregister(dev);
 832
 833         snd_soc_unregister_component(dev);
 834 }
 835
 836 /**
 837  * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
 838  */
 839 int atmel_ssc_set_audio(int ssc_id)
 840 {
 841         struct ssc_device *ssc;
 842         int ret;
 843
 844         /* If we can grab the SSC briefly to parent the DAI device off it */
 845         ssc = ssc_request(ssc_id);
 846         if (IS_ERR(ssc)) {
 847                 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
 848                         PTR_ERR(ssc));
 849                 return PTR_ERR(ssc);
 850         } else {
 851                 ssc_info[ssc_id].ssc = ssc;
 852         }
 853
 854         ret = asoc_ssc_init(&ssc->pdev->dev);
 855
 856         return ret;
 857 }
 858 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
 859
 860 void atmel_ssc_put_audio(int ssc_id)
 861 {
 862         struct ssc_device *ssc = ssc_info[ssc_id].ssc;
 863
 864         asoc_ssc_exit(&ssc->pdev->dev);
 865         ssc_free(ssc);
 866 }
 867 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
 868
 869 /* Module information */
 870 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
 871 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
 872 MODULE_LICENSE("GPL");