arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39 #include <linux/of.h>
  40 #include <linux/of_address.h>
  41 #include <linux/of_irq.h>
  42
  43 #include <asm/mach/time.h>
  44 #include <asm/smp_twd.h>
  45 #include <asm/sched_clock.h>
  46
  47 #include <asm/arch_timer.h>
  48 #include "omap_hwmod.h"
  49 #include "omap_device.h"
  50 #include <plat/counter-32k.h>
  51 #include <plat/dmtimer.h>
  52 #include "omap-pm.h"
  53
  54 #include "soc.h"
  55 #include "common.h"
  56 #include "powerdomain.h"
  57
  58 /* Parent clocks, eventually these will come from the clock framework */
  59
  60 #define OMAP2_MPU_SOURCE        "sys_ck"
  61 #define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
  62 #define OMAP4_MPU_SOURCE        "sys_clkin_ck"
  63 #define OMAP2_32K_SOURCE        "func_32k_ck"
  64 #define OMAP3_32K_SOURCE        "omap_32k_fck"
  65 #define OMAP4_32K_SOURCE        "sys_32k_ck"
  66
  67 #ifdef CONFIG_OMAP_32K_TIMER
  68 #define OMAP2_CLKEV_SOURCE      OMAP2_32K_SOURCE
  69 #define OMAP3_CLKEV_SOURCE      OMAP3_32K_SOURCE
  70 #define OMAP4_CLKEV_SOURCE      OMAP4_32K_SOURCE
  71 #define OMAP3_SECURE_TIMER      12
  72 #define TIMER_PROP_SECURE       "ti,timer-secure"
  73 #else
  74 #define OMAP2_CLKEV_SOURCE      OMAP2_MPU_SOURCE
  75 #define OMAP3_CLKEV_SOURCE      OMAP3_MPU_SOURCE
  76 #define OMAP4_CLKEV_SOURCE      OMAP4_MPU_SOURCE
  77 #define OMAP3_SECURE_TIMER      1
  78 #define TIMER_PROP_SECURE       "ti,timer-alwon"
  79 #endif
  80
  81 #define REALTIME_COUNTER_BASE                           0x48243200
  82 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
  83 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
  84 #define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
  85
  86 /* Clockevent code */
  87
  88 static struct omap_dm_timer clkev;
  89 static struct clock_event_device clockevent_gpt;
  90
  91 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  92 {
  93         struct clock_event_device *evt = &clockevent_gpt;
  94
  95         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
  96
  97         evt->event_handler(evt);
  98         return IRQ_HANDLED;
  99 }
 100
 101 static struct irqaction omap2_gp_timer_irq = {
 102         .name           = "gp_timer",
 103         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 104         .handler        = omap2_gp_timer_interrupt,
 105 };
 106
 107 static int omap2_gp_timer_set_next_event(unsigned long cycles,
 108                                          struct clock_event_device *evt)
 109 {
 110         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
 111                                    0xffffffff - cycles, OMAP_TIMER_POSTED);
 112
 113         return 0;
 114 }
 115
 116 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 117                                     struct clock_event_device *evt)
 118 {
 119         u32 period;
 120
 121         __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
 122
 123         switch (mode) {
 124         case CLOCK_EVT_MODE_PERIODIC:
 125                 period = clkev.rate / HZ;
 126                 period -= 1;
 127                 /* Looks like we need to first set the load value separately */
 128                 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
 129                                       0xffffffff - period, OMAP_TIMER_POSTED);
 130                 __omap_dm_timer_load_start(&clkev,
 131                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 132                                         0xffffffff - period, OMAP_TIMER_POSTED);
 133                 break;
 134         case CLOCK_EVT_MODE_ONESHOT:
 135                 break;
 136         case CLOCK_EVT_MODE_UNUSED:
 137         case CLOCK_EVT_MODE_SHUTDOWN:
 138         case CLOCK_EVT_MODE_RESUME:
 139                 break;
 140         }
 141 }
 142
 143 static struct clock_event_device clockevent_gpt = {
 144         .name           = "gp_timer",
 145         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 146         .shift          = 32,
 147         .rating         = 300,
 148         .set_next_event = omap2_gp_timer_set_next_event,
 149         .set_mode       = omap2_gp_timer_set_mode,
 150 };
 151
 152 static struct property device_disabled = {
 153         .name = "status",
 154         .length = sizeof("disabled"),
 155         .value = "disabled",
 156 };
 157
 158 static struct of_device_id omap_timer_match[] __initdata = {
 159         { .compatible = "ti,omap2-timer", },
 160         { }
 161 };
 162
 163 static struct of_device_id omap_counter_match[] __initdata = {
 164         { .compatible = "ti,omap-counter32k", },
 165         { }
 166 };
 167
 168 /**
 169  * omap_get_timer_dt - get a timer using device-tree
 170  * @match       - device-tree match structure for matching a device type
 171  * @property    - optional timer property to match
 172  *
 173  * Helper function to get a timer during early boot using device-tree for use
 174  * as kernel system timer. Optionally, the property argument can be used to
 175  * select a timer with a specific property. Once a timer is found then mark
 176  * the timer node in device-tree as disabled, to prevent the kernel from
 177  * registering this timer as a platform device and so no one else can use it.
 178  */
 179 static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
 180                                                      const char *property)
 181 {
 182         struct device_node *np;
 183
 184         for_each_matching_node(np, match) {
 185                 if (!of_device_is_available(np)) {
 186                         of_node_put(np);
 187                         continue;
 188                 }
 189
 190                 if (property && !of_get_property(np, property, NULL)) {
 191                         of_node_put(np);
 192                         continue;
 193                 }
 194
 195                 prom_add_property(np, &device_disabled);
 196                 return np;
 197         }
 198
 199         return NULL;
 200 }
 201
 202 /**
 203  * omap_dmtimer_init - initialisation function when device tree is used
 204  *
 205  * For secure OMAP3 devices, timers with device type "timer-secure" cannot
 206  * be used by the kernel as they are reserved. Therefore, to prevent the
 207  * kernel registering these devices remove them dynamically from the device
 208  * tree on boot.
 209  */
 210 void __init omap_dmtimer_init(void)
 211 {
 212         struct device_node *np;
 213
 214         if (!cpu_is_omap34xx())
 215                 return;
 216
 217         /* If we are a secure device, remove any secure timer nodes */
 218         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
 219                 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
 220                 if (np)
 221                         of_node_put(np);
 222         }
 223 }
 224
 225 /**
 226  * omap_dm_timer_get_errata - get errata flags for a timer
 227  *
 228  * Get the timer errata flags that are specific to the OMAP device being used.
 229  */
 230 u32 __init omap_dm_timer_get_errata(void)
 231 {
 232         if (cpu_is_omap24xx())
 233                 return 0;
 234
 235         return OMAP_TIMER_ERRATA_I103_I767;
 236 }
 237
 238 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 239                                                 int gptimer_id,
 240                                                 const char *fck_source,
 241                                                 const char *property,
 242                                                 int posted)
 243 {
 244         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
 245         const char *oh_name;
 246         struct device_node *np;
 247         struct omap_hwmod *oh;
 248         struct resource irq_rsrc, mem_rsrc;
 249         size_t size;
 250         int res = 0;
 251         int r;
 252
 253         if (of_have_populated_dt()) {
 254                 np = omap_get_timer_dt(omap_timer_match, NULL);
 255                 if (!np)
 256                         return -ENODEV;
 257
 258                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 259                 if (!oh_name)
 260                         return -ENODEV;
 261
 262                 timer->irq = irq_of_parse_and_map(np, 0);
 263                 if (!timer->irq)
 264                         return -ENXIO;
 265
 266                 timer->io_base = of_iomap(np, 0);
 267
 268                 of_node_put(np);
 269         } else {
 270                 if (omap_dm_timer_reserve_systimer(gptimer_id))
 271                         return -ENODEV;
 272
 273                 sprintf(name, "timer%d", gptimer_id);
 274                 oh_name = name;
 275         }
 276
 277         omap_hwmod_setup_one(oh_name);
 278         oh = omap_hwmod_lookup(oh_name);
 279
 280         if (!oh)
 281                 return -ENODEV;
 282
 283         if (!of_have_populated_dt()) {
 284                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
 285                                                    &irq_rsrc);
 286                 if (r)
 287                         return -ENXIO;
 288                 timer->irq = irq_rsrc.start;
 289
 290                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
 291                                                    &mem_rsrc);
 292                 if (r)
 293                         return -ENXIO;
 294                 timer->phys_base = mem_rsrc.start;
 295                 size = mem_rsrc.end - mem_rsrc.start;
 296
 297                 /* Static mapping, never released */
 298                 timer->io_base = ioremap(timer->phys_base, size);
 299         }
 300
 301         if (!timer->io_base)
 302                 return -ENXIO;
 303
 304         /* After the dmtimer is using hwmod these clocks won't be needed */
 305         timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
 306         if (IS_ERR(timer->fclk))
 307                 return -ENODEV;
 308
 309         omap_hwmod_enable(oh);
 310
 311         /* FIXME: Need to remove hard-coded test on timer ID */
 312         if (gptimer_id != 12) {
 313                 struct clk *src;
 314
 315                 src = clk_get(NULL, fck_source);
 316                 if (IS_ERR(src)) {
 317                         res = -EINVAL;
 318                 } else {
 319                         res = __omap_dm_timer_set_source(timer->fclk, src);
 320                         if (IS_ERR_VALUE(res))
 321                                 pr_warn("%s: %s cannot set source\n",
 322                                         __func__, oh->name);
 323                         clk_put(src);
 324                 }
 325         }
 326         __omap_dm_timer_init_regs(timer);
 327
 328         if (posted)
 329                 __omap_dm_timer_enable_posted(timer);
 330
 331         /* Check that the intended posted configuration matches the actual */
 332         if (posted != timer->posted)
 333                 return -EINVAL;
 334
 335         timer->rate = clk_get_rate(timer->fclk);
 336         timer->reserved = 1;
 337
 338         return res;
 339 }
 340
 341 static void __init omap2_gp_clockevent_init(int gptimer_id,
 342                                                 const char *fck_source,
 343                                                 const char *property)
 344 {
 345         int res;
 346
 347         clkev.errata = omap_dm_timer_get_errata();
 348
 349         /*
 350          * For clock-event timers we never read the timer counter and
 351          * so we are not impacted by errata i103 and i767. Therefore,
 352          * we can safely ignore this errata for clock-event timers.
 353          */
 354         __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
 355
 356         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
 357                                      OMAP_TIMER_POSTED);
 358         BUG_ON(res);
 359
 360         omap2_gp_timer_irq.dev_id = &clkev;
 361         setup_irq(clkev.irq, &omap2_gp_timer_irq);
 362
 363         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 364
 365         clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
 366                                      clockevent_gpt.shift);
 367         clockevent_gpt.max_delta_ns =
 368                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
 369         clockevent_gpt.min_delta_ns =
 370                 clockevent_delta2ns(3, &clockevent_gpt);
 371                 /* Timer internal resynch latency. */
 372
 373         clockevent_gpt.cpumask = cpu_possible_mask;
 374         clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
 375         clockevents_register_device(&clockevent_gpt);
 376
 377         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
 378                 gptimer_id, clkev.rate);
 379 }
 380
 381 /* Clocksource code */
 382 static struct omap_dm_timer clksrc;
 383 static bool use_gptimer_clksrc;
 384
 385 /*
 386  * clocksource
 387  */
 388 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 389 {
 390         return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
 391                                                      OMAP_TIMER_NONPOSTED);
 392 }
 393
 394 static struct clocksource clocksource_gpt = {
 395         .name           = "gp_timer",
 396         .rating         = 300,
 397         .read           = clocksource_read_cycles,
 398         .mask           = CLOCKSOURCE_MASK(32),
 399         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 400 };
 401
 402 static u32 notrace dmtimer_read_sched_clock(void)
 403 {
 404         if (clksrc.reserved)
 405                 return __omap_dm_timer_read_counter(&clksrc,
 406                                                     OMAP_TIMER_NONPOSTED);
 407
 408         return 0;
 409 }
 410
 411 #ifdef CONFIG_OMAP_32K_TIMER
 412 /* Setup free-running counter for clocksource */
 413 static int __init omap2_sync32k_clocksource_init(void)
 414 {
 415         int ret;
 416         struct device_node *np = NULL;
 417         struct omap_hwmod *oh;
 418         void __iomem *vbase;
 419         const char *oh_name = "counter_32k";
 420
 421         /*
 422          * If device-tree is present, then search the DT blob
 423          * to see if the 32kHz counter is supported.
 424          */
 425         if (of_have_populated_dt()) {
 426                 np = omap_get_timer_dt(omap_counter_match, NULL);
 427                 if (!np)
 428                         return -ENODEV;
 429
 430                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 431                 if (!oh_name)
 432                         return -ENODEV;
 433         }
 434
 435         /*
 436          * First check hwmod data is available for sync32k counter
 437          */
 438         oh = omap_hwmod_lookup(oh_name);
 439         if (!oh || oh->slaves_cnt == 0)
 440                 return -ENODEV;
 441
 442         omap_hwmod_setup_one(oh_name);
 443
 444         if (np) {
 445                 vbase = of_iomap(np, 0);
 446                 of_node_put(np);
 447         } else {
 448                 vbase = omap_hwmod_get_mpu_rt_va(oh);
 449         }
 450
 451         if (!vbase) {
 452                 pr_warn("%s: failed to get counter_32k resource\n", __func__);
 453                 return -ENXIO;
 454         }
 455
 456         ret = omap_hwmod_enable(oh);
 457         if (ret) {
 458                 pr_warn("%s: failed to enable counter_32k module (%d)\n",
 459                                                         __func__, ret);
 460                 return ret;
 461         }
 462
 463         ret = omap_init_clocksource_32k(vbase);
 464         if (ret) {
 465                 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
 466                                                         __func__, ret);
 467                 omap_hwmod_idle(oh);
 468         }
 469
 470         return ret;
 471 }
 472 #else
 473 static inline int omap2_sync32k_clocksource_init(void)
 474 {
 475         return -ENODEV;
 476 }
 477 #endif
 478
 479 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 480                                                 const char *fck_source)
 481 {
 482         int res;
 483
 484         clksrc.errata = omap_dm_timer_get_errata();
 485
 486         res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
 487                                      OMAP_TIMER_NONPOSTED);
 488         BUG_ON(res);
 489
 490         __omap_dm_timer_load_start(&clksrc,
 491                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
 492                                    OMAP_TIMER_NONPOSTED);
 493         setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
 494
 495         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 496                 pr_err("Could not register clocksource %s\n",
 497                         clocksource_gpt.name);
 498         else
 499                 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
 500                         gptimer_id, clksrc.rate);
 501 }
 502
 503 static void __init omap2_clocksource_init(int gptimer_id,
 504                                                 const char *fck_source)
 505 {
 506         /*
 507          * First give preference to kernel parameter configuration
 508          * by user (clocksource="gp_timer").
 509          *
 510          * In case of missing kernel parameter for clocksource,
 511          * first check for availability for 32k-sync timer, in case
 512          * of failure in finding 32k_counter module or registering
 513          * it as clocksource, execution will fallback to gp-timer.
 514          */
 515         if (use_gptimer_clksrc == true)
 516                 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 517         else if (omap2_sync32k_clocksource_init())
 518                 /* Fall back to gp-timer code */
 519                 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 520 }
 521
 522 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 523 /*
 524  * The realtime counter also called master counter, is a free-running
 525  * counter, which is related to real time. It produces the count used
 526  * by the CPU local timer peripherals in the MPU cluster. The timer counts
 527  * at a rate of 6.144 MHz. Because the device operates on different clocks
 528  * in different power modes, the master counter shifts operation between
 529  * clocks, adjusting the increment per clock in hardware accordingly to
 530  * maintain a constant count rate.
 531  */
 532 static void __init realtime_counter_init(void)
 533 {
 534         void __iomem *base;
 535         static struct clk *sys_clk;
 536         unsigned long rate;
 537         unsigned int reg, num, den;
 538
 539         base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
 540         if (!base) {
 541                 pr_err("%s: ioremap failed\n", __func__);
 542                 return;
 543         }
 544         sys_clk = clk_get(NULL, "sys_clkin_ck");
 545         if (IS_ERR(sys_clk)) {
 546                 pr_err("%s: failed to get system clock handle\n", __func__);
 547                 iounmap(base);
 548                 return;
 549         }
 550
 551         rate = clk_get_rate(sys_clk);
 552         /* Numerator/denumerator values refer TRM Realtime Counter section */
 553         switch (rate) {
 554         case 1200000:
 555                 num = 64;
 556                 den = 125;
 557                 break;
 558         case 1300000:
 559                 num = 768;
 560                 den = 1625;
 561                 break;
 562         case 19200000:
 563                 num = 8;
 564                 den = 25;
 565                 break;
 566         case 2600000:
 567                 num = 384;
 568                 den = 1625;
 569                 break;
 570         case 2700000:
 571                 num = 256;
 572                 den = 1125;
 573                 break;
 574         case 38400000:
 575         default:
 576                 /* Program it for 38.4 MHz */
 577                 num = 4;
 578                 den = 25;
 579                 break;
 580         }
 581
 582         /* Program numerator and denumerator registers */
 583         reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
 584                         NUMERATOR_DENUMERATOR_MASK;
 585         reg |= num;
 586         __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
 587
 588         reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
 589                         NUMERATOR_DENUMERATOR_MASK;
 590         reg |= den;
 591         __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 592
 593         iounmap(base);
 594 }
 595 #else
 596 static inline void __init realtime_counter_init(void)
 597 {}
 598 #endif
 599
 600 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,      \
 601                                 clksrc_nr, clksrc_src)                  \
 602 static void __init omap##name##_timer_init(void)                        \
 603 {                                                                       \
 604         omap_dmtimer_init();                                            \
 605         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
 606         omap2_clocksource_init((clksrc_nr), clksrc_src);                \
 607 }
 608
 609 #define OMAP_SYS_TIMER(name)                                            \
 610 struct sys_timer omap##name##_timer = {                                 \
 611         .init   = omap##name##_timer_init,                              \
 612 };
 613
 614 #ifdef CONFIG_ARCH_OMAP2
 615 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, "ti,timer-alwon",
 616                     2, OMAP2_MPU_SOURCE)
 617 OMAP_SYS_TIMER(2)
 618 #endif
 619
 620 #ifdef CONFIG_ARCH_OMAP3
 621 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, "ti,timer-alwon",
 622                     2, OMAP3_MPU_SOURCE)
 623 OMAP_SYS_TIMER(3)
 624 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
 625                         TIMER_PROP_SECURE, 2, OMAP3_MPU_SOURCE)
 626 OMAP_SYS_TIMER(3_secure)
 627 #endif
 628
 629 #ifdef CONFIG_SOC_AM33XX
 630 OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
 631                     2, OMAP4_MPU_SOURCE)
 632 OMAP_SYS_TIMER(3_am33xx)
 633 #endif
 634
 635 #ifdef CONFIG_ARCH_OMAP4
 636 #ifdef CONFIG_LOCAL_TIMERS
 637 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
 638                               OMAP44XX_LOCAL_TWD_BASE, 29);
 639 #endif
 640
 641 static void __init omap4_timer_init(void)
 642 {
 643         omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon");
 644         omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
 645 #ifdef CONFIG_LOCAL_TIMERS
 646         /* Local timers are not supprted on OMAP4430 ES1.0 */
 647         if (omap_rev() != OMAP4430_REV_ES1_0) {
 648                 int err;
 649
 650                 if (of_have_populated_dt()) {
 651                         twd_local_timer_of_register();
 652                         return;
 653                 }
 654
 655                 err = twd_local_timer_register(&twd_local_timer);
 656                 if (err)
 657                         pr_err("twd_local_timer_register failed %d\n", err);
 658         }
 659 #endif
 660 }
 661 OMAP_SYS_TIMER(4)
 662 #endif
 663
 664 #ifdef CONFIG_SOC_OMAP5
 665 static void __init omap5_timer_init(void)
 666 {
 667         int err;
 668
 669         omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon");
 670         omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
 671         realtime_counter_init();
 672
 673         err = arch_timer_of_register();
 674         if (err)
 675                 pr_err("%s: arch_timer_register failed %d\n", __func__, err);
 676 }
 677 OMAP_SYS_TIMER(5)
 678 #endif
 679
 680 /**
 681  * omap_timer_init - build and register timer device with an
 682  * associated timer hwmod
 683  * @oh: timer hwmod pointer to be used to build timer device
 684  * @user:       parameter that can be passed from calling hwmod API
 685  *
 686  * Called by omap_hwmod_for_each_by_class to register each of the timer
 687  * devices present in the system. The number of timer devices is known
 688  * by parsing through the hwmod database for a given class name. At the
 689  * end of function call memory is allocated for timer device and it is
 690  * registered to the framework ready to be proved by the driver.
 691  */
 692 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
 693 {
 694         int id;
 695         int ret = 0;
 696         char *name = "omap_timer";
 697         struct dmtimer_platform_data *pdata;
 698         struct platform_device *pdev;
 699         struct omap_timer_capability_dev_attr *timer_dev_attr;
 700
 701         pr_debug("%s: %s\n", __func__, oh->name);
 702
 703         /* on secure device, do not register secure timer */
 704         timer_dev_attr = oh->dev_attr;
 705         if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
 706                 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
 707                         return ret;
 708
 709         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 710         if (!pdata) {
 711                 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
 712                 return -ENOMEM;
 713         }
 714
 715         /*
 716          * Extract the IDs from name field in hwmod database
 717          * and use the same for constructing ids' for the
 718          * timer devices. In a way, we are avoiding usage of
 719          * static variable witin the function to do the same.
 720          * CAUTION: We have to be careful and make sure the
 721          * name in hwmod database does not change in which case
 722          * we might either make corresponding change here or
 723          * switch back static variable mechanism.
 724          */
 725         sscanf(oh->name, "timer%2d", &id);
 726
 727         if (timer_dev_attr)
 728                 pdata->timer_capability = timer_dev_attr->timer_capability;
 729
 730         pdata->timer_errata = omap_dm_timer_get_errata();
 731         pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
 732
 733         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
 734                                  NULL, 0, 0);
 735
 736         if (IS_ERR(pdev)) {
 737                 pr_err("%s: Can't build omap_device for %s: %s.\n",
 738                         __func__, name, oh->name);
 739                 ret = -EINVAL;
 740         }
 741
 742         kfree(pdata);
 743
 744         return ret;
 745 }
 746
 747 /**
 748  * omap2_dm_timer_init - top level regular device initialization
 749  *
 750  * Uses dedicated hwmod api to parse through hwmod database for
 751  * given class name and then build and register the timer device.
 752  */
 753 static int __init omap2_dm_timer_init(void)
 754 {
 755         int ret;
 756
 757         /* If dtb is there, the devices will be created dynamically */
 758         if (of_have_populated_dt())
 759                 return -ENODEV;
 760
 761         ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
 762         if (unlikely(ret)) {
 763                 pr_err("%s: device registration failed.\n", __func__);
 764                 return -EINVAL;
 765         }
 766
 767         return 0;
 768 }
 769 arch_initcall(omap2_dm_timer_init);
 770
 771 /**
 772  * omap2_override_clocksource - clocksource override with user configuration
 773  *
 774  * Allows user to override default clocksource, using kernel parameter
 775  *   clocksource="gp_timer"     (For all OMAP2PLUS architectures)
 776  *
 777  * Note that, here we are using same standard kernel parameter "clocksource=",
 778  * and not introducing any OMAP specific interface.
 779  */
 780 static int __init omap2_override_clocksource(char *str)
 781 {
 782         if (!str)
 783                 return 0;
 784         /*
 785          * For OMAP architecture, we only have two options
 786          *    - sync_32k (default)
 787          *    - gp_timer (sys_clk based)
 788          */
 789         if (!strcmp(str, "gp_timer"))
 790                 use_gptimer_clksrc = true;
 791
 792         return 0;
 793 }
 794 early_param("clocksource", omap2_override_clocksource);