2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/platform_data/gpio-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/i2c-omap.h>
26 #include <plat-omap/dma-omap.h>
28 #include <linux/platform_data/spi-omap2-mcspi.h>
29 #include <linux/platform_data/asoc-ti-mcbsp.h>
30 #include <plat/dmtimer.h>
31 #include <plat/iommu.h>
33 #include "omap_hwmod.h"
34 #include "omap_hwmod_common_data.h"
38 #include "prm-regbits-44xx.h"
43 /* Base offset for all OMAP4 interrupts external to MPUSS */
44 #define OMAP44XX_IRQ_GIC_START 32
46 /* Base offset for all OMAP4 dma requests */
47 #define OMAP44XX_DMA_REQ_START 1
54 * 'c2c_target_fw' class
55 * instance(s): c2c_target_fw
57 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class
= {
58 .name
= "c2c_target_fw",
62 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod
= {
63 .name
= "c2c_target_fw",
64 .class = &omap44xx_c2c_target_fw_hwmod_class
,
65 .clkdm_name
= "d2d_clkdm",
68 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET
,
69 .context_offs
= OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET
,
78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class
= {
83 static struct omap_hwmod_irq_info omap44xx_dmm_irqs
[] = {
84 { .irq
= 113 + OMAP44XX_IRQ_GIC_START
},
88 static struct omap_hwmod omap44xx_dmm_hwmod
= {
90 .class = &omap44xx_dmm_hwmod_class
,
91 .clkdm_name
= "l3_emif_clkdm",
92 .mpu_irqs
= omap44xx_dmm_irqs
,
95 .clkctrl_offs
= OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET
,
96 .context_offs
= OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET
,
103 * instance(s): emif_fw
105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class
= {
110 static struct omap_hwmod omap44xx_emif_fw_hwmod
= {
112 .class = &omap44xx_emif_fw_hwmod_class
,
113 .clkdm_name
= "l3_emif_clkdm",
116 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET
,
117 .context_offs
= OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET
,
124 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
126 static struct omap_hwmod_class omap44xx_l3_hwmod_class
= {
131 static struct omap_hwmod omap44xx_l3_instr_hwmod
= {
133 .class = &omap44xx_l3_hwmod_class
,
134 .clkdm_name
= "l3_instr_clkdm",
137 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
138 .context_offs
= OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
139 .modulemode
= MODULEMODE_HWCTRL
,
145 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs
[] = {
146 { .name
= "dbg_err", .irq
= 9 + OMAP44XX_IRQ_GIC_START
},
147 { .name
= "app_err", .irq
= 10 + OMAP44XX_IRQ_GIC_START
},
151 static struct omap_hwmod omap44xx_l3_main_1_hwmod
= {
153 .class = &omap44xx_l3_hwmod_class
,
154 .clkdm_name
= "l3_1_clkdm",
155 .mpu_irqs
= omap44xx_l3_main_1_irqs
,
158 .clkctrl_offs
= OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET
,
159 .context_offs
= OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET
,
165 static struct omap_hwmod omap44xx_l3_main_2_hwmod
= {
167 .class = &omap44xx_l3_hwmod_class
,
168 .clkdm_name
= "l3_2_clkdm",
171 .clkctrl_offs
= OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET
,
172 .context_offs
= OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET
,
178 static struct omap_hwmod omap44xx_l3_main_3_hwmod
= {
180 .class = &omap44xx_l3_hwmod_class
,
181 .clkdm_name
= "l3_instr_clkdm",
184 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET
,
185 .context_offs
= OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET
,
186 .modulemode
= MODULEMODE_HWCTRL
,
193 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
195 static struct omap_hwmod_class omap44xx_l4_hwmod_class
= {
200 static struct omap_hwmod omap44xx_l4_abe_hwmod
= {
202 .class = &omap44xx_l4_hwmod_class
,
203 .clkdm_name
= "abe_clkdm",
206 .clkctrl_offs
= OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET
,
207 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
208 .lostcontext_mask
= OMAP4430_LOSTMEM_AESSMEM_MASK
,
209 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
215 static struct omap_hwmod omap44xx_l4_cfg_hwmod
= {
217 .class = &omap44xx_l4_hwmod_class
,
218 .clkdm_name
= "l4_cfg_clkdm",
221 .clkctrl_offs
= OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
222 .context_offs
= OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
228 static struct omap_hwmod omap44xx_l4_per_hwmod
= {
230 .class = &omap44xx_l4_hwmod_class
,
231 .clkdm_name
= "l4_per_clkdm",
234 .clkctrl_offs
= OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET
,
235 .context_offs
= OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET
,
241 static struct omap_hwmod omap44xx_l4_wkup_hwmod
= {
243 .class = &omap44xx_l4_hwmod_class
,
244 .clkdm_name
= "l4_wkup_clkdm",
247 .clkctrl_offs
= OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
,
248 .context_offs
= OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET
,
255 * instance(s): mpu_private
257 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class
= {
262 static struct omap_hwmod omap44xx_mpu_private_hwmod
= {
263 .name
= "mpu_private",
264 .class = &omap44xx_mpu_bus_hwmod_class
,
265 .clkdm_name
= "mpuss_clkdm",
268 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
275 * instance(s): ocp_wp_noc
277 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class
= {
278 .name
= "ocp_wp_noc",
282 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod
= {
283 .name
= "ocp_wp_noc",
284 .class = &omap44xx_ocp_wp_noc_hwmod_class
,
285 .clkdm_name
= "l3_instr_clkdm",
288 .clkctrl_offs
= OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET
,
289 .context_offs
= OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET
,
290 .modulemode
= MODULEMODE_HWCTRL
,
296 * Modules omap_hwmod structures
298 * The following IPs are excluded for the moment because:
299 * - They do not need an explicit SW control using omap_hwmod API.
300 * - They still need to be validated with the driver
301 * properly adapted to omap_hwmod / omap_device
308 * audio engine sub system
311 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc
= {
314 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
315 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
316 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
|
317 MSTANDBY_SMART_WKUP
),
318 .sysc_fields
= &omap_hwmod_sysc_type2
,
321 static struct omap_hwmod_class omap44xx_aess_hwmod_class
= {
323 .sysc
= &omap44xx_aess_sysc
,
327 static struct omap_hwmod_irq_info omap44xx_aess_irqs
[] = {
328 { .irq
= 99 + OMAP44XX_IRQ_GIC_START
},
332 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs
[] = {
333 { .name
= "fifo0", .dma_req
= 100 + OMAP44XX_DMA_REQ_START
},
334 { .name
= "fifo1", .dma_req
= 101 + OMAP44XX_DMA_REQ_START
},
335 { .name
= "fifo2", .dma_req
= 102 + OMAP44XX_DMA_REQ_START
},
336 { .name
= "fifo3", .dma_req
= 103 + OMAP44XX_DMA_REQ_START
},
337 { .name
= "fifo4", .dma_req
= 104 + OMAP44XX_DMA_REQ_START
},
338 { .name
= "fifo5", .dma_req
= 105 + OMAP44XX_DMA_REQ_START
},
339 { .name
= "fifo6", .dma_req
= 106 + OMAP44XX_DMA_REQ_START
},
340 { .name
= "fifo7", .dma_req
= 107 + OMAP44XX_DMA_REQ_START
},
344 static struct omap_hwmod omap44xx_aess_hwmod
= {
346 .class = &omap44xx_aess_hwmod_class
,
347 .clkdm_name
= "abe_clkdm",
348 .mpu_irqs
= omap44xx_aess_irqs
,
349 .sdma_reqs
= omap44xx_aess_sdma_reqs
,
350 .main_clk
= "aess_fck",
353 .clkctrl_offs
= OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET
,
354 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
355 .lostcontext_mask
= OMAP4430_LOSTCONTEXT_DFF_MASK
,
356 .modulemode
= MODULEMODE_SWCTRL
,
363 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
367 static struct omap_hwmod_class omap44xx_c2c_hwmod_class
= {
372 static struct omap_hwmod_irq_info omap44xx_c2c_irqs
[] = {
373 { .irq
= 88 + OMAP44XX_IRQ_GIC_START
},
377 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs
[] = {
378 { .dma_req
= 68 + OMAP44XX_DMA_REQ_START
},
382 static struct omap_hwmod omap44xx_c2c_hwmod
= {
384 .class = &omap44xx_c2c_hwmod_class
,
385 .clkdm_name
= "d2d_clkdm",
386 .mpu_irqs
= omap44xx_c2c_irqs
,
387 .sdma_reqs
= omap44xx_c2c_sdma_reqs
,
390 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET
,
391 .context_offs
= OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET
,
398 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
401 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc
= {
404 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
405 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
),
406 .sysc_fields
= &omap_hwmod_sysc_type1
,
409 static struct omap_hwmod_class omap44xx_counter_hwmod_class
= {
411 .sysc
= &omap44xx_counter_sysc
,
415 static struct omap_hwmod omap44xx_counter_32k_hwmod
= {
416 .name
= "counter_32k",
417 .class = &omap44xx_counter_hwmod_class
,
418 .clkdm_name
= "l4_wkup_clkdm",
419 .flags
= HWMOD_SWSUP_SIDLE
,
420 .main_clk
= "sys_32k_ck",
423 .clkctrl_offs
= OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET
,
424 .context_offs
= OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET
,
430 * 'ctrl_module' class
431 * attila core control module + core pad control module + wkup pad control
432 * module + attila wkup control module
435 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc
= {
438 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
439 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
441 .sysc_fields
= &omap_hwmod_sysc_type2
,
444 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class
= {
445 .name
= "ctrl_module",
446 .sysc
= &omap44xx_ctrl_module_sysc
,
449 /* ctrl_module_core */
450 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs
[] = {
451 { .irq
= 8 + OMAP44XX_IRQ_GIC_START
},
455 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod
= {
456 .name
= "ctrl_module_core",
457 .class = &omap44xx_ctrl_module_hwmod_class
,
458 .clkdm_name
= "l4_cfg_clkdm",
459 .mpu_irqs
= omap44xx_ctrl_module_core_irqs
,
462 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
467 /* ctrl_module_pad_core */
468 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod
= {
469 .name
= "ctrl_module_pad_core",
470 .class = &omap44xx_ctrl_module_hwmod_class
,
471 .clkdm_name
= "l4_cfg_clkdm",
474 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
479 /* ctrl_module_wkup */
480 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod
= {
481 .name
= "ctrl_module_wkup",
482 .class = &omap44xx_ctrl_module_hwmod_class
,
483 .clkdm_name
= "l4_wkup_clkdm",
486 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
491 /* ctrl_module_pad_wkup */
492 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod
= {
493 .name
= "ctrl_module_pad_wkup",
494 .class = &omap44xx_ctrl_module_hwmod_class
,
495 .clkdm_name
= "l4_wkup_clkdm",
498 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
505 * debug and emulation sub system
508 static struct omap_hwmod_class omap44xx_debugss_hwmod_class
= {
513 static struct omap_hwmod omap44xx_debugss_hwmod
= {
515 .class = &omap44xx_debugss_hwmod_class
,
516 .clkdm_name
= "emu_sys_clkdm",
517 .main_clk
= "trace_clk_div_ck",
520 .clkctrl_offs
= OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET
,
521 .context_offs
= OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET
,
528 * dma controller for data exchange between memory to memory (i.e. internal or
529 * external memory) and gp peripherals to memory or memory to gp peripherals
532 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc
= {
536 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
537 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
538 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
539 SYSS_HAS_RESET_STATUS
),
540 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
541 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
542 .sysc_fields
= &omap_hwmod_sysc_type1
,
545 static struct omap_hwmod_class omap44xx_dma_hwmod_class
= {
547 .sysc
= &omap44xx_dma_sysc
,
551 static struct omap_dma_dev_attr dma_dev_attr
= {
552 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
553 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
558 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs
[] = {
559 { .name
= "0", .irq
= 12 + OMAP44XX_IRQ_GIC_START
},
560 { .name
= "1", .irq
= 13 + OMAP44XX_IRQ_GIC_START
},
561 { .name
= "2", .irq
= 14 + OMAP44XX_IRQ_GIC_START
},
562 { .name
= "3", .irq
= 15 + OMAP44XX_IRQ_GIC_START
},
566 static struct omap_hwmod omap44xx_dma_system_hwmod
= {
567 .name
= "dma_system",
568 .class = &omap44xx_dma_hwmod_class
,
569 .clkdm_name
= "l3_dma_clkdm",
570 .mpu_irqs
= omap44xx_dma_system_irqs
,
571 .main_clk
= "l3_div_ck",
574 .clkctrl_offs
= OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET
,
575 .context_offs
= OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET
,
578 .dev_attr
= &dma_dev_attr
,
583 * digital microphone controller
586 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc
= {
589 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
590 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
591 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
593 .sysc_fields
= &omap_hwmod_sysc_type2
,
596 static struct omap_hwmod_class omap44xx_dmic_hwmod_class
= {
598 .sysc
= &omap44xx_dmic_sysc
,
602 static struct omap_hwmod_irq_info omap44xx_dmic_irqs
[] = {
603 { .irq
= 114 + OMAP44XX_IRQ_GIC_START
},
607 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs
[] = {
608 { .dma_req
= 66 + OMAP44XX_DMA_REQ_START
},
612 static struct omap_hwmod omap44xx_dmic_hwmod
= {
614 .class = &omap44xx_dmic_hwmod_class
,
615 .clkdm_name
= "abe_clkdm",
616 .mpu_irqs
= omap44xx_dmic_irqs
,
617 .sdma_reqs
= omap44xx_dmic_sdma_reqs
,
618 .main_clk
= "dmic_fck",
621 .clkctrl_offs
= OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET
,
622 .context_offs
= OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET
,
623 .modulemode
= MODULEMODE_SWCTRL
,
633 static struct omap_hwmod_class omap44xx_dsp_hwmod_class
= {
638 static struct omap_hwmod_irq_info omap44xx_dsp_irqs
[] = {
639 { .irq
= 28 + OMAP44XX_IRQ_GIC_START
},
643 static struct omap_hwmod_rst_info omap44xx_dsp_resets
[] = {
644 { .name
= "dsp", .rst_shift
= 0 },
647 static struct omap_hwmod omap44xx_dsp_hwmod
= {
649 .class = &omap44xx_dsp_hwmod_class
,
650 .clkdm_name
= "tesla_clkdm",
651 .mpu_irqs
= omap44xx_dsp_irqs
,
652 .rst_lines
= omap44xx_dsp_resets
,
653 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_dsp_resets
),
654 .main_clk
= "dsp_fck",
657 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
658 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
659 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
660 .modulemode
= MODULEMODE_HWCTRL
,
670 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc
= {
673 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
676 static struct omap_hwmod_class omap44xx_dss_hwmod_class
= {
678 .sysc
= &omap44xx_dss_sysc
,
679 .reset
= omap_dss_reset
,
683 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
684 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
685 { .role
= "tv_clk", .clk
= "dss_tv_clk" },
686 { .role
= "hdmi_clk", .clk
= "dss_48mhz_clk" },
689 static struct omap_hwmod omap44xx_dss_hwmod
= {
691 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
692 .class = &omap44xx_dss_hwmod_class
,
693 .clkdm_name
= "l3_dss_clkdm",
694 .main_clk
= "dss_dss_clk",
697 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
698 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
701 .opt_clks
= dss_opt_clks
,
702 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
710 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc
= {
714 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
715 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_MIDLEMODE
|
716 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
717 SYSS_HAS_RESET_STATUS
),
718 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
719 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
720 .sysc_fields
= &omap_hwmod_sysc_type1
,
723 static struct omap_hwmod_class omap44xx_dispc_hwmod_class
= {
725 .sysc
= &omap44xx_dispc_sysc
,
729 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs
[] = {
730 { .irq
= 25 + OMAP44XX_IRQ_GIC_START
},
734 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs
[] = {
735 { .dma_req
= 5 + OMAP44XX_DMA_REQ_START
},
739 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr
= {
741 .has_framedonetv_irq
= 1
744 static struct omap_hwmod omap44xx_dss_dispc_hwmod
= {
746 .class = &omap44xx_dispc_hwmod_class
,
747 .clkdm_name
= "l3_dss_clkdm",
748 .mpu_irqs
= omap44xx_dss_dispc_irqs
,
749 .sdma_reqs
= omap44xx_dss_dispc_sdma_reqs
,
750 .main_clk
= "dss_dss_clk",
753 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
754 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
757 .dev_attr
= &omap44xx_dss_dispc_dev_attr
762 * display serial interface controller
765 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc
= {
769 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
770 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
771 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
772 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
773 .sysc_fields
= &omap_hwmod_sysc_type1
,
776 static struct omap_hwmod_class omap44xx_dsi_hwmod_class
= {
778 .sysc
= &omap44xx_dsi_sysc
,
782 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs
[] = {
783 { .irq
= 53 + OMAP44XX_IRQ_GIC_START
},
787 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs
[] = {
788 { .dma_req
= 74 + OMAP44XX_DMA_REQ_START
},
792 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks
[] = {
793 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
796 static struct omap_hwmod omap44xx_dss_dsi1_hwmod
= {
798 .class = &omap44xx_dsi_hwmod_class
,
799 .clkdm_name
= "l3_dss_clkdm",
800 .mpu_irqs
= omap44xx_dss_dsi1_irqs
,
801 .sdma_reqs
= omap44xx_dss_dsi1_sdma_reqs
,
802 .main_clk
= "dss_dss_clk",
805 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
806 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
809 .opt_clks
= dss_dsi1_opt_clks
,
810 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi1_opt_clks
),
814 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs
[] = {
815 { .irq
= 84 + OMAP44XX_IRQ_GIC_START
},
819 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs
[] = {
820 { .dma_req
= 83 + OMAP44XX_DMA_REQ_START
},
824 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks
[] = {
825 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
828 static struct omap_hwmod omap44xx_dss_dsi2_hwmod
= {
830 .class = &omap44xx_dsi_hwmod_class
,
831 .clkdm_name
= "l3_dss_clkdm",
832 .mpu_irqs
= omap44xx_dss_dsi2_irqs
,
833 .sdma_reqs
= omap44xx_dss_dsi2_sdma_reqs
,
834 .main_clk
= "dss_dss_clk",
837 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
838 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
841 .opt_clks
= dss_dsi2_opt_clks
,
842 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi2_opt_clks
),
850 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc
= {
853 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
855 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
857 .sysc_fields
= &omap_hwmod_sysc_type2
,
860 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class
= {
862 .sysc
= &omap44xx_hdmi_sysc
,
866 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs
[] = {
867 { .irq
= 101 + OMAP44XX_IRQ_GIC_START
},
871 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs
[] = {
872 { .dma_req
= 75 + OMAP44XX_DMA_REQ_START
},
876 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks
[] = {
877 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
880 static struct omap_hwmod omap44xx_dss_hdmi_hwmod
= {
882 .class = &omap44xx_hdmi_hwmod_class
,
883 .clkdm_name
= "l3_dss_clkdm",
885 * HDMI audio requires to use no-idle mode. Hence,
886 * set idle mode by software.
888 .flags
= HWMOD_SWSUP_SIDLE
,
889 .mpu_irqs
= omap44xx_dss_hdmi_irqs
,
890 .sdma_reqs
= omap44xx_dss_hdmi_sdma_reqs
,
891 .main_clk
= "dss_48mhz_clk",
894 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
895 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
898 .opt_clks
= dss_hdmi_opt_clks
,
899 .opt_clks_cnt
= ARRAY_SIZE(dss_hdmi_opt_clks
),
904 * remote frame buffer interface
907 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc
= {
911 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
912 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
913 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
914 .sysc_fields
= &omap_hwmod_sysc_type1
,
917 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class
= {
919 .sysc
= &omap44xx_rfbi_sysc
,
923 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs
[] = {
924 { .dma_req
= 13 + OMAP44XX_DMA_REQ_START
},
928 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks
[] = {
929 { .role
= "ick", .clk
= "dss_fck" },
932 static struct omap_hwmod omap44xx_dss_rfbi_hwmod
= {
934 .class = &omap44xx_rfbi_hwmod_class
,
935 .clkdm_name
= "l3_dss_clkdm",
936 .sdma_reqs
= omap44xx_dss_rfbi_sdma_reqs
,
937 .main_clk
= "dss_dss_clk",
940 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
941 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
944 .opt_clks
= dss_rfbi_opt_clks
,
945 .opt_clks_cnt
= ARRAY_SIZE(dss_rfbi_opt_clks
),
953 static struct omap_hwmod_class omap44xx_venc_hwmod_class
= {
958 static struct omap_hwmod omap44xx_dss_venc_hwmod
= {
960 .class = &omap44xx_venc_hwmod_class
,
961 .clkdm_name
= "l3_dss_clkdm",
962 .main_clk
= "dss_tv_clk",
965 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
966 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
973 * bch error location module
976 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc
= {
980 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
981 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
982 SYSS_HAS_RESET_STATUS
),
983 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
984 .sysc_fields
= &omap_hwmod_sysc_type1
,
987 static struct omap_hwmod_class omap44xx_elm_hwmod_class
= {
989 .sysc
= &omap44xx_elm_sysc
,
993 static struct omap_hwmod_irq_info omap44xx_elm_irqs
[] = {
994 { .irq
= 4 + OMAP44XX_IRQ_GIC_START
},
998 static struct omap_hwmod omap44xx_elm_hwmod
= {
1000 .class = &omap44xx_elm_hwmod_class
,
1001 .clkdm_name
= "l4_per_clkdm",
1002 .mpu_irqs
= omap44xx_elm_irqs
,
1005 .clkctrl_offs
= OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET
,
1006 .context_offs
= OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET
,
1013 * external memory interface no1
1016 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc
= {
1020 static struct omap_hwmod_class omap44xx_emif_hwmod_class
= {
1022 .sysc
= &omap44xx_emif_sysc
,
1026 static struct omap_hwmod_irq_info omap44xx_emif1_irqs
[] = {
1027 { .irq
= 110 + OMAP44XX_IRQ_GIC_START
},
1031 static struct omap_hwmod omap44xx_emif1_hwmod
= {
1033 .class = &omap44xx_emif_hwmod_class
,
1034 .clkdm_name
= "l3_emif_clkdm",
1035 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1036 .mpu_irqs
= omap44xx_emif1_irqs
,
1037 .main_clk
= "ddrphy_ck",
1040 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET
,
1041 .context_offs
= OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET
,
1042 .modulemode
= MODULEMODE_HWCTRL
,
1048 static struct omap_hwmod_irq_info omap44xx_emif2_irqs
[] = {
1049 { .irq
= 111 + OMAP44XX_IRQ_GIC_START
},
1053 static struct omap_hwmod omap44xx_emif2_hwmod
= {
1055 .class = &omap44xx_emif_hwmod_class
,
1056 .clkdm_name
= "l3_emif_clkdm",
1057 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1058 .mpu_irqs
= omap44xx_emif2_irqs
,
1059 .main_clk
= "ddrphy_ck",
1062 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET
,
1063 .context_offs
= OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET
,
1064 .modulemode
= MODULEMODE_HWCTRL
,
1071 * face detection hw accelerator module
1074 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc
= {
1076 .sysc_offs
= 0x0010,
1078 * FDIF needs 100 OCP clk cycles delay after a softreset before
1079 * accessing sysconfig again.
1080 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1081 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1083 * TODO: Indicate errata when available.
1086 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1087 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1088 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1089 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1090 .sysc_fields
= &omap_hwmod_sysc_type2
,
1093 static struct omap_hwmod_class omap44xx_fdif_hwmod_class
= {
1095 .sysc
= &omap44xx_fdif_sysc
,
1099 static struct omap_hwmod_irq_info omap44xx_fdif_irqs
[] = {
1100 { .irq
= 69 + OMAP44XX_IRQ_GIC_START
},
1104 static struct omap_hwmod omap44xx_fdif_hwmod
= {
1106 .class = &omap44xx_fdif_hwmod_class
,
1107 .clkdm_name
= "iss_clkdm",
1108 .mpu_irqs
= omap44xx_fdif_irqs
,
1109 .main_clk
= "fdif_fck",
1112 .clkctrl_offs
= OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET
,
1113 .context_offs
= OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET
,
1114 .modulemode
= MODULEMODE_SWCTRL
,
1121 * general purpose io module
1124 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc
= {
1126 .sysc_offs
= 0x0010,
1127 .syss_offs
= 0x0114,
1128 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1129 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1130 SYSS_HAS_RESET_STATUS
),
1131 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1133 .sysc_fields
= &omap_hwmod_sysc_type1
,
1136 static struct omap_hwmod_class omap44xx_gpio_hwmod_class
= {
1138 .sysc
= &omap44xx_gpio_sysc
,
1143 static struct omap_gpio_dev_attr gpio_dev_attr
= {
1149 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs
[] = {
1150 { .irq
= 29 + OMAP44XX_IRQ_GIC_START
},
1154 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
1155 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
1158 static struct omap_hwmod omap44xx_gpio1_hwmod
= {
1160 .class = &omap44xx_gpio_hwmod_class
,
1161 .clkdm_name
= "l4_wkup_clkdm",
1162 .mpu_irqs
= omap44xx_gpio1_irqs
,
1163 .main_clk
= "gpio1_ick",
1166 .clkctrl_offs
= OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET
,
1167 .context_offs
= OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET
,
1168 .modulemode
= MODULEMODE_HWCTRL
,
1171 .opt_clks
= gpio1_opt_clks
,
1172 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
1173 .dev_attr
= &gpio_dev_attr
,
1177 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs
[] = {
1178 { .irq
= 30 + OMAP44XX_IRQ_GIC_START
},
1182 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
1183 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
1186 static struct omap_hwmod omap44xx_gpio2_hwmod
= {
1188 .class = &omap44xx_gpio_hwmod_class
,
1189 .clkdm_name
= "l4_per_clkdm",
1190 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1191 .mpu_irqs
= omap44xx_gpio2_irqs
,
1192 .main_clk
= "gpio2_ick",
1195 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
1196 .context_offs
= OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
1197 .modulemode
= MODULEMODE_HWCTRL
,
1200 .opt_clks
= gpio2_opt_clks
,
1201 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
1202 .dev_attr
= &gpio_dev_attr
,
1206 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs
[] = {
1207 { .irq
= 31 + OMAP44XX_IRQ_GIC_START
},
1211 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
1212 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
1215 static struct omap_hwmod omap44xx_gpio3_hwmod
= {
1217 .class = &omap44xx_gpio_hwmod_class
,
1218 .clkdm_name
= "l4_per_clkdm",
1219 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1220 .mpu_irqs
= omap44xx_gpio3_irqs
,
1221 .main_clk
= "gpio3_ick",
1224 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
1225 .context_offs
= OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
1226 .modulemode
= MODULEMODE_HWCTRL
,
1229 .opt_clks
= gpio3_opt_clks
,
1230 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
1231 .dev_attr
= &gpio_dev_attr
,
1235 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs
[] = {
1236 { .irq
= 32 + OMAP44XX_IRQ_GIC_START
},
1240 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
1241 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
1244 static struct omap_hwmod omap44xx_gpio4_hwmod
= {
1246 .class = &omap44xx_gpio_hwmod_class
,
1247 .clkdm_name
= "l4_per_clkdm",
1248 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1249 .mpu_irqs
= omap44xx_gpio4_irqs
,
1250 .main_clk
= "gpio4_ick",
1253 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
1254 .context_offs
= OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
1255 .modulemode
= MODULEMODE_HWCTRL
,
1258 .opt_clks
= gpio4_opt_clks
,
1259 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
1260 .dev_attr
= &gpio_dev_attr
,
1264 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs
[] = {
1265 { .irq
= 33 + OMAP44XX_IRQ_GIC_START
},
1269 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
1270 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
1273 static struct omap_hwmod omap44xx_gpio5_hwmod
= {
1275 .class = &omap44xx_gpio_hwmod_class
,
1276 .clkdm_name
= "l4_per_clkdm",
1277 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1278 .mpu_irqs
= omap44xx_gpio5_irqs
,
1279 .main_clk
= "gpio5_ick",
1282 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
1283 .context_offs
= OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
1284 .modulemode
= MODULEMODE_HWCTRL
,
1287 .opt_clks
= gpio5_opt_clks
,
1288 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
1289 .dev_attr
= &gpio_dev_attr
,
1293 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs
[] = {
1294 { .irq
= 34 + OMAP44XX_IRQ_GIC_START
},
1298 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
1299 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
1302 static struct omap_hwmod omap44xx_gpio6_hwmod
= {
1304 .class = &omap44xx_gpio_hwmod_class
,
1305 .clkdm_name
= "l4_per_clkdm",
1306 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1307 .mpu_irqs
= omap44xx_gpio6_irqs
,
1308 .main_clk
= "gpio6_ick",
1311 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
1312 .context_offs
= OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
1313 .modulemode
= MODULEMODE_HWCTRL
,
1316 .opt_clks
= gpio6_opt_clks
,
1317 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
1318 .dev_attr
= &gpio_dev_attr
,
1323 * general purpose memory controller
1326 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc
= {
1328 .sysc_offs
= 0x0010,
1329 .syss_offs
= 0x0014,
1330 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1331 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1332 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1333 .sysc_fields
= &omap_hwmod_sysc_type1
,
1336 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class
= {
1338 .sysc
= &omap44xx_gpmc_sysc
,
1342 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs
[] = {
1343 { .irq
= 20 + OMAP44XX_IRQ_GIC_START
},
1347 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs
[] = {
1348 { .dma_req
= 3 + OMAP44XX_DMA_REQ_START
},
1352 static struct omap_hwmod omap44xx_gpmc_hwmod
= {
1354 .class = &omap44xx_gpmc_hwmod_class
,
1355 .clkdm_name
= "l3_2_clkdm",
1357 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1358 * block. It is not being added due to any known bugs with
1359 * resetting the GPMC IP block, but rather because any timings
1360 * set by the bootloader are not being correctly programmed by
1361 * the kernel from the board file or DT data.
1362 * HWMOD_INIT_NO_RESET should be removed ASAP.
1364 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1365 .mpu_irqs
= omap44xx_gpmc_irqs
,
1366 .sdma_reqs
= omap44xx_gpmc_sdma_reqs
,
1369 .clkctrl_offs
= OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET
,
1370 .context_offs
= OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET
,
1371 .modulemode
= MODULEMODE_HWCTRL
,
1378 * 2d/3d graphics accelerator
1381 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc
= {
1382 .rev_offs
= 0x1fc00,
1383 .sysc_offs
= 0x1fc10,
1384 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
1385 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1386 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1387 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1388 .sysc_fields
= &omap_hwmod_sysc_type2
,
1391 static struct omap_hwmod_class omap44xx_gpu_hwmod_class
= {
1393 .sysc
= &omap44xx_gpu_sysc
,
1397 static struct omap_hwmod_irq_info omap44xx_gpu_irqs
[] = {
1398 { .irq
= 21 + OMAP44XX_IRQ_GIC_START
},
1402 static struct omap_hwmod omap44xx_gpu_hwmod
= {
1404 .class = &omap44xx_gpu_hwmod_class
,
1405 .clkdm_name
= "l3_gfx_clkdm",
1406 .mpu_irqs
= omap44xx_gpu_irqs
,
1407 .main_clk
= "gpu_fck",
1410 .clkctrl_offs
= OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET
,
1411 .context_offs
= OMAP4_RM_GFX_GFX_CONTEXT_OFFSET
,
1412 .modulemode
= MODULEMODE_SWCTRL
,
1419 * hdq / 1-wire serial interface controller
1422 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc
= {
1424 .sysc_offs
= 0x0014,
1425 .syss_offs
= 0x0018,
1426 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SOFTRESET
|
1427 SYSS_HAS_RESET_STATUS
),
1428 .sysc_fields
= &omap_hwmod_sysc_type1
,
1431 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class
= {
1433 .sysc
= &omap44xx_hdq1w_sysc
,
1437 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs
[] = {
1438 { .irq
= 58 + OMAP44XX_IRQ_GIC_START
},
1442 static struct omap_hwmod omap44xx_hdq1w_hwmod
= {
1444 .class = &omap44xx_hdq1w_hwmod_class
,
1445 .clkdm_name
= "l4_per_clkdm",
1446 .flags
= HWMOD_INIT_NO_RESET
, /* XXX temporary */
1447 .mpu_irqs
= omap44xx_hdq1w_irqs
,
1448 .main_clk
= "hdq1w_fck",
1451 .clkctrl_offs
= OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
,
1452 .context_offs
= OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET
,
1453 .modulemode
= MODULEMODE_SWCTRL
,
1460 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1464 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc
= {
1466 .sysc_offs
= 0x0010,
1467 .syss_offs
= 0x0014,
1468 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_EMUFREE
|
1469 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
1470 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1471 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1472 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1473 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1474 .sysc_fields
= &omap_hwmod_sysc_type1
,
1477 static struct omap_hwmod_class omap44xx_hsi_hwmod_class
= {
1479 .sysc
= &omap44xx_hsi_sysc
,
1483 static struct omap_hwmod_irq_info omap44xx_hsi_irqs
[] = {
1484 { .name
= "mpu_p1", .irq
= 67 + OMAP44XX_IRQ_GIC_START
},
1485 { .name
= "mpu_p2", .irq
= 68 + OMAP44XX_IRQ_GIC_START
},
1486 { .name
= "mpu_dma", .irq
= 71 + OMAP44XX_IRQ_GIC_START
},
1490 static struct omap_hwmod omap44xx_hsi_hwmod
= {
1492 .class = &omap44xx_hsi_hwmod_class
,
1493 .clkdm_name
= "l3_init_clkdm",
1494 .mpu_irqs
= omap44xx_hsi_irqs
,
1495 .main_clk
= "hsi_fck",
1498 .clkctrl_offs
= OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET
,
1499 .context_offs
= OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET
,
1500 .modulemode
= MODULEMODE_HWCTRL
,
1507 * multimaster high-speed i2c controller
1510 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc
= {
1511 .sysc_offs
= 0x0010,
1512 .syss_offs
= 0x0090,
1513 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1514 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1515 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1516 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1518 .clockact
= CLOCKACT_TEST_ICLK
,
1519 .sysc_fields
= &omap_hwmod_sysc_type1
,
1522 static struct omap_hwmod_class omap44xx_i2c_hwmod_class
= {
1524 .sysc
= &omap44xx_i2c_sysc
,
1525 .rev
= OMAP_I2C_IP_VERSION_2
,
1526 .reset
= &omap_i2c_reset
,
1529 static struct omap_i2c_dev_attr i2c_dev_attr
= {
1530 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
|
1531 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE
,
1535 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs
[] = {
1536 { .irq
= 56 + OMAP44XX_IRQ_GIC_START
},
1540 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs
[] = {
1541 { .name
= "tx", .dma_req
= 26 + OMAP44XX_DMA_REQ_START
},
1542 { .name
= "rx", .dma_req
= 27 + OMAP44XX_DMA_REQ_START
},
1546 static struct omap_hwmod omap44xx_i2c1_hwmod
= {
1548 .class = &omap44xx_i2c_hwmod_class
,
1549 .clkdm_name
= "l4_per_clkdm",
1550 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1551 .mpu_irqs
= omap44xx_i2c1_irqs
,
1552 .sdma_reqs
= omap44xx_i2c1_sdma_reqs
,
1553 .main_clk
= "i2c1_fck",
1556 .clkctrl_offs
= OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
1557 .context_offs
= OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET
,
1558 .modulemode
= MODULEMODE_SWCTRL
,
1561 .dev_attr
= &i2c_dev_attr
,
1565 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs
[] = {
1566 { .irq
= 57 + OMAP44XX_IRQ_GIC_START
},
1570 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs
[] = {
1571 { .name
= "tx", .dma_req
= 28 + OMAP44XX_DMA_REQ_START
},
1572 { .name
= "rx", .dma_req
= 29 + OMAP44XX_DMA_REQ_START
},
1576 static struct omap_hwmod omap44xx_i2c2_hwmod
= {
1578 .class = &omap44xx_i2c_hwmod_class
,
1579 .clkdm_name
= "l4_per_clkdm",
1580 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1581 .mpu_irqs
= omap44xx_i2c2_irqs
,
1582 .sdma_reqs
= omap44xx_i2c2_sdma_reqs
,
1583 .main_clk
= "i2c2_fck",
1586 .clkctrl_offs
= OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
1587 .context_offs
= OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET
,
1588 .modulemode
= MODULEMODE_SWCTRL
,
1591 .dev_attr
= &i2c_dev_attr
,
1595 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs
[] = {
1596 { .irq
= 61 + OMAP44XX_IRQ_GIC_START
},
1600 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs
[] = {
1601 { .name
= "tx", .dma_req
= 24 + OMAP44XX_DMA_REQ_START
},
1602 { .name
= "rx", .dma_req
= 25 + OMAP44XX_DMA_REQ_START
},
1606 static struct omap_hwmod omap44xx_i2c3_hwmod
= {
1608 .class = &omap44xx_i2c_hwmod_class
,
1609 .clkdm_name
= "l4_per_clkdm",
1610 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1611 .mpu_irqs
= omap44xx_i2c3_irqs
,
1612 .sdma_reqs
= omap44xx_i2c3_sdma_reqs
,
1613 .main_clk
= "i2c3_fck",
1616 .clkctrl_offs
= OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
1617 .context_offs
= OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET
,
1618 .modulemode
= MODULEMODE_SWCTRL
,
1621 .dev_attr
= &i2c_dev_attr
,
1625 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs
[] = {
1626 { .irq
= 62 + OMAP44XX_IRQ_GIC_START
},
1630 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs
[] = {
1631 { .name
= "tx", .dma_req
= 123 + OMAP44XX_DMA_REQ_START
},
1632 { .name
= "rx", .dma_req
= 124 + OMAP44XX_DMA_REQ_START
},
1636 static struct omap_hwmod omap44xx_i2c4_hwmod
= {
1638 .class = &omap44xx_i2c_hwmod_class
,
1639 .clkdm_name
= "l4_per_clkdm",
1640 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1641 .mpu_irqs
= omap44xx_i2c4_irqs
,
1642 .sdma_reqs
= omap44xx_i2c4_sdma_reqs
,
1643 .main_clk
= "i2c4_fck",
1646 .clkctrl_offs
= OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
1647 .context_offs
= OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET
,
1648 .modulemode
= MODULEMODE_SWCTRL
,
1651 .dev_attr
= &i2c_dev_attr
,
1656 * imaging processor unit
1659 static struct omap_hwmod_class omap44xx_ipu_hwmod_class
= {
1664 static struct omap_hwmod_irq_info omap44xx_ipu_irqs
[] = {
1665 { .irq
= 100 + OMAP44XX_IRQ_GIC_START
},
1669 static struct omap_hwmod_rst_info omap44xx_ipu_resets
[] = {
1670 { .name
= "cpu0", .rst_shift
= 0 },
1671 { .name
= "cpu1", .rst_shift
= 1 },
1674 static struct omap_hwmod omap44xx_ipu_hwmod
= {
1676 .class = &omap44xx_ipu_hwmod_class
,
1677 .clkdm_name
= "ducati_clkdm",
1678 .mpu_irqs
= omap44xx_ipu_irqs
,
1679 .rst_lines
= omap44xx_ipu_resets
,
1680 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_ipu_resets
),
1681 .main_clk
= "ipu_fck",
1684 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
1685 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
1686 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
1687 .modulemode
= MODULEMODE_HWCTRL
,
1694 * external images sensor pixel data processor
1697 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc
= {
1699 .sysc_offs
= 0x0010,
1701 * ISS needs 100 OCP clk cycles delay after a softreset before
1702 * accessing sysconfig again.
1703 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1704 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1706 * TODO: Indicate errata when available.
1709 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1710 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1711 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1712 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1713 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1714 .sysc_fields
= &omap_hwmod_sysc_type2
,
1717 static struct omap_hwmod_class omap44xx_iss_hwmod_class
= {
1719 .sysc
= &omap44xx_iss_sysc
,
1723 static struct omap_hwmod_irq_info omap44xx_iss_irqs
[] = {
1724 { .irq
= 24 + OMAP44XX_IRQ_GIC_START
},
1728 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs
[] = {
1729 { .name
= "1", .dma_req
= 8 + OMAP44XX_DMA_REQ_START
},
1730 { .name
= "2", .dma_req
= 9 + OMAP44XX_DMA_REQ_START
},
1731 { .name
= "3", .dma_req
= 11 + OMAP44XX_DMA_REQ_START
},
1732 { .name
= "4", .dma_req
= 12 + OMAP44XX_DMA_REQ_START
},
1736 static struct omap_hwmod_opt_clk iss_opt_clks
[] = {
1737 { .role
= "ctrlclk", .clk
= "iss_ctrlclk" },
1740 static struct omap_hwmod omap44xx_iss_hwmod
= {
1742 .class = &omap44xx_iss_hwmod_class
,
1743 .clkdm_name
= "iss_clkdm",
1744 .mpu_irqs
= omap44xx_iss_irqs
,
1745 .sdma_reqs
= omap44xx_iss_sdma_reqs
,
1746 .main_clk
= "iss_fck",
1749 .clkctrl_offs
= OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET
,
1750 .context_offs
= OMAP4_RM_CAM_ISS_CONTEXT_OFFSET
,
1751 .modulemode
= MODULEMODE_SWCTRL
,
1754 .opt_clks
= iss_opt_clks
,
1755 .opt_clks_cnt
= ARRAY_SIZE(iss_opt_clks
),
1760 * multi-standard video encoder/decoder hardware accelerator
1763 static struct omap_hwmod_class omap44xx_iva_hwmod_class
= {
1768 static struct omap_hwmod_irq_info omap44xx_iva_irqs
[] = {
1769 { .name
= "sync_1", .irq
= 103 + OMAP44XX_IRQ_GIC_START
},
1770 { .name
= "sync_0", .irq
= 104 + OMAP44XX_IRQ_GIC_START
},
1771 { .name
= "mailbox_0", .irq
= 107 + OMAP44XX_IRQ_GIC_START
},
1775 static struct omap_hwmod_rst_info omap44xx_iva_resets
[] = {
1776 { .name
= "seq0", .rst_shift
= 0 },
1777 { .name
= "seq1", .rst_shift
= 1 },
1778 { .name
= "logic", .rst_shift
= 2 },
1781 static struct omap_hwmod omap44xx_iva_hwmod
= {
1783 .class = &omap44xx_iva_hwmod_class
,
1784 .clkdm_name
= "ivahd_clkdm",
1785 .mpu_irqs
= omap44xx_iva_irqs
,
1786 .rst_lines
= omap44xx_iva_resets
,
1787 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_iva_resets
),
1788 .main_clk
= "iva_fck",
1791 .clkctrl_offs
= OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET
,
1792 .rstctrl_offs
= OMAP4_RM_IVAHD_RSTCTRL_OFFSET
,
1793 .context_offs
= OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET
,
1794 .modulemode
= MODULEMODE_HWCTRL
,
1801 * keyboard controller
1804 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc
= {
1806 .sysc_offs
= 0x0010,
1807 .syss_offs
= 0x0014,
1808 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1809 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
1810 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1811 SYSS_HAS_RESET_STATUS
),
1812 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1813 .sysc_fields
= &omap_hwmod_sysc_type1
,
1816 static struct omap_hwmod_class omap44xx_kbd_hwmod_class
= {
1818 .sysc
= &omap44xx_kbd_sysc
,
1822 static struct omap_hwmod_irq_info omap44xx_kbd_irqs
[] = {
1823 { .irq
= 120 + OMAP44XX_IRQ_GIC_START
},
1827 static struct omap_hwmod omap44xx_kbd_hwmod
= {
1829 .class = &omap44xx_kbd_hwmod_class
,
1830 .clkdm_name
= "l4_wkup_clkdm",
1831 .mpu_irqs
= omap44xx_kbd_irqs
,
1832 .main_clk
= "kbd_fck",
1835 .clkctrl_offs
= OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET
,
1836 .context_offs
= OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET
,
1837 .modulemode
= MODULEMODE_SWCTRL
,
1844 * mailbox module allowing communication between the on-chip processors using a
1845 * queued mailbox-interrupt mechanism.
1848 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc
= {
1850 .sysc_offs
= 0x0010,
1851 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1852 SYSC_HAS_SOFTRESET
),
1853 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1854 .sysc_fields
= &omap_hwmod_sysc_type2
,
1857 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class
= {
1859 .sysc
= &omap44xx_mailbox_sysc
,
1863 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs
[] = {
1864 { .irq
= 26 + OMAP44XX_IRQ_GIC_START
},
1868 static struct omap_hwmod omap44xx_mailbox_hwmod
= {
1870 .class = &omap44xx_mailbox_hwmod_class
,
1871 .clkdm_name
= "l4_cfg_clkdm",
1872 .mpu_irqs
= omap44xx_mailbox_irqs
,
1875 .clkctrl_offs
= OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET
,
1876 .context_offs
= OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET
,
1883 * multi-channel audio serial port controller
1886 /* The IP is not compliant to type1 / type2 scheme */
1887 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp
= {
1891 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc
= {
1892 .sysc_offs
= 0x0004,
1893 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1894 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1896 .sysc_fields
= &omap_hwmod_sysc_type_mcasp
,
1899 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class
= {
1901 .sysc
= &omap44xx_mcasp_sysc
,
1905 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs
[] = {
1906 { .name
= "arevt", .irq
= 108 + OMAP44XX_IRQ_GIC_START
},
1907 { .name
= "axevt", .irq
= 109 + OMAP44XX_IRQ_GIC_START
},
1911 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs
[] = {
1912 { .name
= "axevt", .dma_req
= 7 + OMAP44XX_DMA_REQ_START
},
1913 { .name
= "arevt", .dma_req
= 10 + OMAP44XX_DMA_REQ_START
},
1917 static struct omap_hwmod omap44xx_mcasp_hwmod
= {
1919 .class = &omap44xx_mcasp_hwmod_class
,
1920 .clkdm_name
= "abe_clkdm",
1921 .mpu_irqs
= omap44xx_mcasp_irqs
,
1922 .sdma_reqs
= omap44xx_mcasp_sdma_reqs
,
1923 .main_clk
= "mcasp_fck",
1926 .clkctrl_offs
= OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET
,
1927 .context_offs
= OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET
,
1928 .modulemode
= MODULEMODE_SWCTRL
,
1935 * multi channel buffered serial port controller
1938 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc
= {
1939 .sysc_offs
= 0x008c,
1940 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
1941 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1942 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1943 .sysc_fields
= &omap_hwmod_sysc_type1
,
1946 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class
= {
1948 .sysc
= &omap44xx_mcbsp_sysc
,
1949 .rev
= MCBSP_CONFIG_TYPE4
,
1953 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs
[] = {
1954 { .name
= "common", .irq
= 17 + OMAP44XX_IRQ_GIC_START
},
1958 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs
[] = {
1959 { .name
= "tx", .dma_req
= 32 + OMAP44XX_DMA_REQ_START
},
1960 { .name
= "rx", .dma_req
= 33 + OMAP44XX_DMA_REQ_START
},
1964 static struct omap_hwmod_opt_clk mcbsp1_opt_clks
[] = {
1965 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1966 { .role
= "prcm_fck", .clk
= "mcbsp1_sync_mux_ck" },
1969 static struct omap_hwmod omap44xx_mcbsp1_hwmod
= {
1971 .class = &omap44xx_mcbsp_hwmod_class
,
1972 .clkdm_name
= "abe_clkdm",
1973 .mpu_irqs
= omap44xx_mcbsp1_irqs
,
1974 .sdma_reqs
= omap44xx_mcbsp1_sdma_reqs
,
1975 .main_clk
= "mcbsp1_fck",
1978 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET
,
1979 .context_offs
= OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET
,
1980 .modulemode
= MODULEMODE_SWCTRL
,
1983 .opt_clks
= mcbsp1_opt_clks
,
1984 .opt_clks_cnt
= ARRAY_SIZE(mcbsp1_opt_clks
),
1988 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs
[] = {
1989 { .name
= "common", .irq
= 22 + OMAP44XX_IRQ_GIC_START
},
1993 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs
[] = {
1994 { .name
= "tx", .dma_req
= 16 + OMAP44XX_DMA_REQ_START
},
1995 { .name
= "rx", .dma_req
= 17 + OMAP44XX_DMA_REQ_START
},
1999 static struct omap_hwmod_opt_clk mcbsp2_opt_clks
[] = {
2000 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2001 { .role
= "prcm_fck", .clk
= "mcbsp2_sync_mux_ck" },
2004 static struct omap_hwmod omap44xx_mcbsp2_hwmod
= {
2006 .class = &omap44xx_mcbsp_hwmod_class
,
2007 .clkdm_name
= "abe_clkdm",
2008 .mpu_irqs
= omap44xx_mcbsp2_irqs
,
2009 .sdma_reqs
= omap44xx_mcbsp2_sdma_reqs
,
2010 .main_clk
= "mcbsp2_fck",
2013 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET
,
2014 .context_offs
= OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET
,
2015 .modulemode
= MODULEMODE_SWCTRL
,
2018 .opt_clks
= mcbsp2_opt_clks
,
2019 .opt_clks_cnt
= ARRAY_SIZE(mcbsp2_opt_clks
),
2023 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs
[] = {
2024 { .name
= "common", .irq
= 23 + OMAP44XX_IRQ_GIC_START
},
2028 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs
[] = {
2029 { .name
= "tx", .dma_req
= 18 + OMAP44XX_DMA_REQ_START
},
2030 { .name
= "rx", .dma_req
= 19 + OMAP44XX_DMA_REQ_START
},
2034 static struct omap_hwmod_opt_clk mcbsp3_opt_clks
[] = {
2035 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2036 { .role
= "prcm_fck", .clk
= "mcbsp3_sync_mux_ck" },
2039 static struct omap_hwmod omap44xx_mcbsp3_hwmod
= {
2041 .class = &omap44xx_mcbsp_hwmod_class
,
2042 .clkdm_name
= "abe_clkdm",
2043 .mpu_irqs
= omap44xx_mcbsp3_irqs
,
2044 .sdma_reqs
= omap44xx_mcbsp3_sdma_reqs
,
2045 .main_clk
= "mcbsp3_fck",
2048 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET
,
2049 .context_offs
= OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET
,
2050 .modulemode
= MODULEMODE_SWCTRL
,
2053 .opt_clks
= mcbsp3_opt_clks
,
2054 .opt_clks_cnt
= ARRAY_SIZE(mcbsp3_opt_clks
),
2058 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs
[] = {
2059 { .name
= "common", .irq
= 16 + OMAP44XX_IRQ_GIC_START
},
2063 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs
[] = {
2064 { .name
= "tx", .dma_req
= 30 + OMAP44XX_DMA_REQ_START
},
2065 { .name
= "rx", .dma_req
= 31 + OMAP44XX_DMA_REQ_START
},
2069 static struct omap_hwmod_opt_clk mcbsp4_opt_clks
[] = {
2070 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2071 { .role
= "prcm_fck", .clk
= "mcbsp4_sync_mux_ck" },
2074 static struct omap_hwmod omap44xx_mcbsp4_hwmod
= {
2076 .class = &omap44xx_mcbsp_hwmod_class
,
2077 .clkdm_name
= "l4_per_clkdm",
2078 .mpu_irqs
= omap44xx_mcbsp4_irqs
,
2079 .sdma_reqs
= omap44xx_mcbsp4_sdma_reqs
,
2080 .main_clk
= "mcbsp4_fck",
2083 .clkctrl_offs
= OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET
,
2084 .context_offs
= OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET
,
2085 .modulemode
= MODULEMODE_SWCTRL
,
2088 .opt_clks
= mcbsp4_opt_clks
,
2089 .opt_clks_cnt
= ARRAY_SIZE(mcbsp4_opt_clks
),
2094 * multi channel pdm controller (proprietary interface with phoenix power
2098 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc
= {
2100 .sysc_offs
= 0x0010,
2101 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2102 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2103 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2105 .sysc_fields
= &omap_hwmod_sysc_type2
,
2108 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class
= {
2110 .sysc
= &omap44xx_mcpdm_sysc
,
2114 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs
[] = {
2115 { .irq
= 112 + OMAP44XX_IRQ_GIC_START
},
2119 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs
[] = {
2120 { .name
= "up_link", .dma_req
= 64 + OMAP44XX_DMA_REQ_START
},
2121 { .name
= "dn_link", .dma_req
= 65 + OMAP44XX_DMA_REQ_START
},
2125 static struct omap_hwmod omap44xx_mcpdm_hwmod
= {
2127 .class = &omap44xx_mcpdm_hwmod_class
,
2128 .clkdm_name
= "abe_clkdm",
2129 .mpu_irqs
= omap44xx_mcpdm_irqs
,
2130 .sdma_reqs
= omap44xx_mcpdm_sdma_reqs
,
2131 .main_clk
= "mcpdm_fck",
2134 .clkctrl_offs
= OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET
,
2135 .context_offs
= OMAP4_RM_ABE_PDM_CONTEXT_OFFSET
,
2136 .modulemode
= MODULEMODE_SWCTRL
,
2143 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2147 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc
= {
2149 .sysc_offs
= 0x0010,
2150 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2151 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2152 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2154 .sysc_fields
= &omap_hwmod_sysc_type2
,
2157 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class
= {
2159 .sysc
= &omap44xx_mcspi_sysc
,
2160 .rev
= OMAP4_MCSPI_REV
,
2164 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs
[] = {
2165 { .irq
= 65 + OMAP44XX_IRQ_GIC_START
},
2169 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs
[] = {
2170 { .name
= "tx0", .dma_req
= 34 + OMAP44XX_DMA_REQ_START
},
2171 { .name
= "rx0", .dma_req
= 35 + OMAP44XX_DMA_REQ_START
},
2172 { .name
= "tx1", .dma_req
= 36 + OMAP44XX_DMA_REQ_START
},
2173 { .name
= "rx1", .dma_req
= 37 + OMAP44XX_DMA_REQ_START
},
2174 { .name
= "tx2", .dma_req
= 38 + OMAP44XX_DMA_REQ_START
},
2175 { .name
= "rx2", .dma_req
= 39 + OMAP44XX_DMA_REQ_START
},
2176 { .name
= "tx3", .dma_req
= 40 + OMAP44XX_DMA_REQ_START
},
2177 { .name
= "rx3", .dma_req
= 41 + OMAP44XX_DMA_REQ_START
},
2181 /* mcspi1 dev_attr */
2182 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
2183 .num_chipselect
= 4,
2186 static struct omap_hwmod omap44xx_mcspi1_hwmod
= {
2188 .class = &omap44xx_mcspi_hwmod_class
,
2189 .clkdm_name
= "l4_per_clkdm",
2190 .mpu_irqs
= omap44xx_mcspi1_irqs
,
2191 .sdma_reqs
= omap44xx_mcspi1_sdma_reqs
,
2192 .main_clk
= "mcspi1_fck",
2195 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
2196 .context_offs
= OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
2197 .modulemode
= MODULEMODE_SWCTRL
,
2200 .dev_attr
= &mcspi1_dev_attr
,
2204 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs
[] = {
2205 { .irq
= 66 + OMAP44XX_IRQ_GIC_START
},
2209 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs
[] = {
2210 { .name
= "tx0", .dma_req
= 42 + OMAP44XX_DMA_REQ_START
},
2211 { .name
= "rx0", .dma_req
= 43 + OMAP44XX_DMA_REQ_START
},
2212 { .name
= "tx1", .dma_req
= 44 + OMAP44XX_DMA_REQ_START
},
2213 { .name
= "rx1", .dma_req
= 45 + OMAP44XX_DMA_REQ_START
},
2217 /* mcspi2 dev_attr */
2218 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
2219 .num_chipselect
= 2,
2222 static struct omap_hwmod omap44xx_mcspi2_hwmod
= {
2224 .class = &omap44xx_mcspi_hwmod_class
,
2225 .clkdm_name
= "l4_per_clkdm",
2226 .mpu_irqs
= omap44xx_mcspi2_irqs
,
2227 .sdma_reqs
= omap44xx_mcspi2_sdma_reqs
,
2228 .main_clk
= "mcspi2_fck",
2231 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
2232 .context_offs
= OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
2233 .modulemode
= MODULEMODE_SWCTRL
,
2236 .dev_attr
= &mcspi2_dev_attr
,
2240 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs
[] = {
2241 { .irq
= 91 + OMAP44XX_IRQ_GIC_START
},
2245 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs
[] = {
2246 { .name
= "tx0", .dma_req
= 14 + OMAP44XX_DMA_REQ_START
},
2247 { .name
= "rx0", .dma_req
= 15 + OMAP44XX_DMA_REQ_START
},
2248 { .name
= "tx1", .dma_req
= 22 + OMAP44XX_DMA_REQ_START
},
2249 { .name
= "rx1", .dma_req
= 23 + OMAP44XX_DMA_REQ_START
},
2253 /* mcspi3 dev_attr */
2254 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
2255 .num_chipselect
= 2,
2258 static struct omap_hwmod omap44xx_mcspi3_hwmod
= {
2260 .class = &omap44xx_mcspi_hwmod_class
,
2261 .clkdm_name
= "l4_per_clkdm",
2262 .mpu_irqs
= omap44xx_mcspi3_irqs
,
2263 .sdma_reqs
= omap44xx_mcspi3_sdma_reqs
,
2264 .main_clk
= "mcspi3_fck",
2267 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
2268 .context_offs
= OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
2269 .modulemode
= MODULEMODE_SWCTRL
,
2272 .dev_attr
= &mcspi3_dev_attr
,
2276 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs
[] = {
2277 { .irq
= 48 + OMAP44XX_IRQ_GIC_START
},
2281 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs
[] = {
2282 { .name
= "tx0", .dma_req
= 69 + OMAP44XX_DMA_REQ_START
},
2283 { .name
= "rx0", .dma_req
= 70 + OMAP44XX_DMA_REQ_START
},
2287 /* mcspi4 dev_attr */
2288 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
2289 .num_chipselect
= 1,
2292 static struct omap_hwmod omap44xx_mcspi4_hwmod
= {
2294 .class = &omap44xx_mcspi_hwmod_class
,
2295 .clkdm_name
= "l4_per_clkdm",
2296 .mpu_irqs
= omap44xx_mcspi4_irqs
,
2297 .sdma_reqs
= omap44xx_mcspi4_sdma_reqs
,
2298 .main_clk
= "mcspi4_fck",
2301 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
2302 .context_offs
= OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
2303 .modulemode
= MODULEMODE_SWCTRL
,
2306 .dev_attr
= &mcspi4_dev_attr
,
2311 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2314 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc
= {
2316 .sysc_offs
= 0x0010,
2317 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
2318 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2319 SYSC_HAS_SOFTRESET
),
2320 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2321 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
2322 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
2323 .sysc_fields
= &omap_hwmod_sysc_type2
,
2326 static struct omap_hwmod_class omap44xx_mmc_hwmod_class
= {
2328 .sysc
= &omap44xx_mmc_sysc
,
2332 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs
[] = {
2333 { .irq
= 83 + OMAP44XX_IRQ_GIC_START
},
2337 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs
[] = {
2338 { .name
= "tx", .dma_req
= 60 + OMAP44XX_DMA_REQ_START
},
2339 { .name
= "rx", .dma_req
= 61 + OMAP44XX_DMA_REQ_START
},
2344 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
2345 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
2348 static struct omap_hwmod omap44xx_mmc1_hwmod
= {
2350 .class = &omap44xx_mmc_hwmod_class
,
2351 .clkdm_name
= "l3_init_clkdm",
2352 .mpu_irqs
= omap44xx_mmc1_irqs
,
2353 .sdma_reqs
= omap44xx_mmc1_sdma_reqs
,
2354 .main_clk
= "mmc1_fck",
2357 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
2358 .context_offs
= OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
2359 .modulemode
= MODULEMODE_SWCTRL
,
2362 .dev_attr
= &mmc1_dev_attr
,
2366 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs
[] = {
2367 { .irq
= 86 + OMAP44XX_IRQ_GIC_START
},
2371 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs
[] = {
2372 { .name
= "tx", .dma_req
= 46 + OMAP44XX_DMA_REQ_START
},
2373 { .name
= "rx", .dma_req
= 47 + OMAP44XX_DMA_REQ_START
},
2377 static struct omap_hwmod omap44xx_mmc2_hwmod
= {
2379 .class = &omap44xx_mmc_hwmod_class
,
2380 .clkdm_name
= "l3_init_clkdm",
2381 .mpu_irqs
= omap44xx_mmc2_irqs
,
2382 .sdma_reqs
= omap44xx_mmc2_sdma_reqs
,
2383 .main_clk
= "mmc2_fck",
2386 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
2387 .context_offs
= OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
2388 .modulemode
= MODULEMODE_SWCTRL
,
2394 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs
[] = {
2395 { .irq
= 94 + OMAP44XX_IRQ_GIC_START
},
2399 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs
[] = {
2400 { .name
= "tx", .dma_req
= 76 + OMAP44XX_DMA_REQ_START
},
2401 { .name
= "rx", .dma_req
= 77 + OMAP44XX_DMA_REQ_START
},
2405 static struct omap_hwmod omap44xx_mmc3_hwmod
= {
2407 .class = &omap44xx_mmc_hwmod_class
,
2408 .clkdm_name
= "l4_per_clkdm",
2409 .mpu_irqs
= omap44xx_mmc3_irqs
,
2410 .sdma_reqs
= omap44xx_mmc3_sdma_reqs
,
2411 .main_clk
= "mmc3_fck",
2414 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET
,
2415 .context_offs
= OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET
,
2416 .modulemode
= MODULEMODE_SWCTRL
,
2422 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs
[] = {
2423 { .irq
= 96 + OMAP44XX_IRQ_GIC_START
},
2427 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs
[] = {
2428 { .name
= "tx", .dma_req
= 56 + OMAP44XX_DMA_REQ_START
},
2429 { .name
= "rx", .dma_req
= 57 + OMAP44XX_DMA_REQ_START
},
2433 static struct omap_hwmod omap44xx_mmc4_hwmod
= {
2435 .class = &omap44xx_mmc_hwmod_class
,
2436 .clkdm_name
= "l4_per_clkdm",
2437 .mpu_irqs
= omap44xx_mmc4_irqs
,
2438 .sdma_reqs
= omap44xx_mmc4_sdma_reqs
,
2439 .main_clk
= "mmc4_fck",
2442 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET
,
2443 .context_offs
= OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET
,
2444 .modulemode
= MODULEMODE_SWCTRL
,
2450 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs
[] = {
2451 { .irq
= 59 + OMAP44XX_IRQ_GIC_START
},
2455 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs
[] = {
2456 { .name
= "tx", .dma_req
= 58 + OMAP44XX_DMA_REQ_START
},
2457 { .name
= "rx", .dma_req
= 59 + OMAP44XX_DMA_REQ_START
},
2461 static struct omap_hwmod omap44xx_mmc5_hwmod
= {
2463 .class = &omap44xx_mmc_hwmod_class
,
2464 .clkdm_name
= "l4_per_clkdm",
2465 .mpu_irqs
= omap44xx_mmc5_irqs
,
2466 .sdma_reqs
= omap44xx_mmc5_sdma_reqs
,
2467 .main_clk
= "mmc5_fck",
2470 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET
,
2471 .context_offs
= OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET
,
2472 .modulemode
= MODULEMODE_SWCTRL
,
2479 * The memory management unit performs virtual to physical address translation
2480 * for its requestors.
2483 static struct omap_hwmod_class_sysconfig mmu_sysc
= {
2487 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
2488 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
2489 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2490 .sysc_fields
= &omap_hwmod_sysc_type1
,
2493 static struct omap_hwmod_class omap44xx_mmu_hwmod_class
= {
2500 static struct omap_mmu_dev_attr mmu_ipu_dev_attr
= {
2502 .da_end
= 0xfffff000,
2503 .nr_tlb_entries
= 32,
2506 static struct omap_hwmod omap44xx_mmu_ipu_hwmod
;
2507 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs
[] = {
2508 { .irq
= 100 + OMAP44XX_IRQ_GIC_START
, },
2512 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets
[] = {
2513 { .name
= "mmu_cache", .rst_shift
= 2 },
2516 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs
[] = {
2518 .pa_start
= 0x55082000,
2519 .pa_end
= 0x550820ff,
2520 .flags
= ADDR_TYPE_RT
,
2525 /* l3_main_2 -> mmu_ipu */
2526 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu
= {
2527 .master
= &omap44xx_l3_main_2_hwmod
,
2528 .slave
= &omap44xx_mmu_ipu_hwmod
,
2530 .addr
= omap44xx_mmu_ipu_addrs
,
2531 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2534 static struct omap_hwmod omap44xx_mmu_ipu_hwmod
= {
2536 .class = &omap44xx_mmu_hwmod_class
,
2537 .clkdm_name
= "ducati_clkdm",
2538 .mpu_irqs
= omap44xx_mmu_ipu_irqs
,
2539 .rst_lines
= omap44xx_mmu_ipu_resets
,
2540 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_mmu_ipu_resets
),
2541 .main_clk
= "ducati_clk_mux_ck",
2544 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
2545 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
2546 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
2547 .modulemode
= MODULEMODE_HWCTRL
,
2550 .dev_attr
= &mmu_ipu_dev_attr
,
2555 static struct omap_mmu_dev_attr mmu_dsp_dev_attr
= {
2557 .da_end
= 0xfffff000,
2558 .nr_tlb_entries
= 32,
2561 static struct omap_hwmod omap44xx_mmu_dsp_hwmod
;
2562 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs
[] = {
2563 { .irq
= 28 + OMAP44XX_IRQ_GIC_START
},
2567 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets
[] = {
2568 { .name
= "mmu_cache", .rst_shift
= 1 },
2571 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs
[] = {
2573 .pa_start
= 0x4a066000,
2574 .pa_end
= 0x4a0660ff,
2575 .flags
= ADDR_TYPE_RT
,
2581 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp
= {
2582 .master
= &omap44xx_l4_cfg_hwmod
,
2583 .slave
= &omap44xx_mmu_dsp_hwmod
,
2585 .addr
= omap44xx_mmu_dsp_addrs
,
2586 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2589 static struct omap_hwmod omap44xx_mmu_dsp_hwmod
= {
2591 .class = &omap44xx_mmu_hwmod_class
,
2592 .clkdm_name
= "tesla_clkdm",
2593 .mpu_irqs
= omap44xx_mmu_dsp_irqs
,
2594 .rst_lines
= omap44xx_mmu_dsp_resets
,
2595 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_mmu_dsp_resets
),
2596 .main_clk
= "dpll_iva_m4x2_ck",
2599 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
2600 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
2601 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
2602 .modulemode
= MODULEMODE_HWCTRL
,
2605 .dev_attr
= &mmu_dsp_dev_attr
,
2613 static struct omap_hwmod_class omap44xx_mpu_hwmod_class
= {
2618 static struct omap_hwmod_irq_info omap44xx_mpu_irqs
[] = {
2619 { .name
= "pmu0", .irq
= 54 + OMAP44XX_IRQ_GIC_START
},
2620 { .name
= "pmu1", .irq
= 55 + OMAP44XX_IRQ_GIC_START
},
2621 { .name
= "pl310", .irq
= 0 + OMAP44XX_IRQ_GIC_START
},
2622 { .name
= "cti0", .irq
= 1 + OMAP44XX_IRQ_GIC_START
},
2623 { .name
= "cti1", .irq
= 2 + OMAP44XX_IRQ_GIC_START
},
2627 static struct omap_hwmod omap44xx_mpu_hwmod
= {
2629 .class = &omap44xx_mpu_hwmod_class
,
2630 .clkdm_name
= "mpuss_clkdm",
2631 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
2632 .mpu_irqs
= omap44xx_mpu_irqs
,
2633 .main_clk
= "dpll_mpu_m2_ck",
2636 .clkctrl_offs
= OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET
,
2637 .context_offs
= OMAP4_RM_MPU_MPU_CONTEXT_OFFSET
,
2644 * top-level core on-chip ram
2647 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class
= {
2652 static struct omap_hwmod omap44xx_ocmc_ram_hwmod
= {
2654 .class = &omap44xx_ocmc_ram_hwmod_class
,
2655 .clkdm_name
= "l3_2_clkdm",
2658 .clkctrl_offs
= OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET
,
2659 .context_offs
= OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET
,
2666 * bridge to transform ocp interface protocol to scp (serial control port)
2670 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc
= {
2672 .sysc_offs
= 0x0010,
2673 .syss_offs
= 0x0014,
2674 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
2675 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2676 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2677 .sysc_fields
= &omap_hwmod_sysc_type1
,
2680 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class
= {
2682 .sysc
= &omap44xx_ocp2scp_sysc
,
2685 /* ocp2scp_usb_phy */
2686 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod
= {
2687 .name
= "ocp2scp_usb_phy",
2688 .class = &omap44xx_ocp2scp_hwmod_class
,
2689 .clkdm_name
= "l3_init_clkdm",
2690 .main_clk
= "ocp2scp_usb_phy_phy_48m",
2693 .clkctrl_offs
= OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET
,
2694 .context_offs
= OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET
,
2695 .modulemode
= MODULEMODE_HWCTRL
,
2702 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2703 * + clock manager 1 (in always on power domain) + local prm in mpu
2706 static struct omap_hwmod_class omap44xx_prcm_hwmod_class
= {
2711 static struct omap_hwmod omap44xx_prcm_mpu_hwmod
= {
2713 .class = &omap44xx_prcm_hwmod_class
,
2714 .clkdm_name
= "l4_wkup_clkdm",
2715 .flags
= HWMOD_NO_IDLEST
,
2718 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2724 static struct omap_hwmod omap44xx_cm_core_aon_hwmod
= {
2725 .name
= "cm_core_aon",
2726 .class = &omap44xx_prcm_hwmod_class
,
2727 .flags
= HWMOD_NO_IDLEST
,
2730 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2736 static struct omap_hwmod omap44xx_cm_core_hwmod
= {
2738 .class = &omap44xx_prcm_hwmod_class
,
2739 .flags
= HWMOD_NO_IDLEST
,
2742 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2748 static struct omap_hwmod_irq_info omap44xx_prm_irqs
[] = {
2749 { .irq
= 11 + OMAP44XX_IRQ_GIC_START
},
2753 static struct omap_hwmod_rst_info omap44xx_prm_resets
[] = {
2754 { .name
= "rst_global_warm_sw", .rst_shift
= 0 },
2755 { .name
= "rst_global_cold_sw", .rst_shift
= 1 },
2758 static struct omap_hwmod omap44xx_prm_hwmod
= {
2760 .class = &omap44xx_prcm_hwmod_class
,
2761 .mpu_irqs
= omap44xx_prm_irqs
,
2762 .rst_lines
= omap44xx_prm_resets
,
2763 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_prm_resets
),
2768 * system clock and reset manager
2771 static struct omap_hwmod_class omap44xx_scrm_hwmod_class
= {
2776 static struct omap_hwmod omap44xx_scrm_hwmod
= {
2778 .class = &omap44xx_scrm_hwmod_class
,
2779 .clkdm_name
= "l4_wkup_clkdm",
2782 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2789 * shared level 2 memory interface
2792 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class
= {
2797 static struct omap_hwmod omap44xx_sl2if_hwmod
= {
2799 .class = &omap44xx_sl2if_hwmod_class
,
2800 .clkdm_name
= "ivahd_clkdm",
2803 .clkctrl_offs
= OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET
,
2804 .context_offs
= OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET
,
2805 .modulemode
= MODULEMODE_HWCTRL
,
2812 * bidirectional, multi-drop, multi-channel two-line serial interface between
2813 * the device and external components
2816 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc
= {
2818 .sysc_offs
= 0x0010,
2819 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2820 SYSC_HAS_SOFTRESET
),
2821 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2823 .sysc_fields
= &omap_hwmod_sysc_type2
,
2826 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class
= {
2828 .sysc
= &omap44xx_slimbus_sysc
,
2832 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs
[] = {
2833 { .irq
= 97 + OMAP44XX_IRQ_GIC_START
},
2837 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs
[] = {
2838 { .name
= "tx0", .dma_req
= 84 + OMAP44XX_DMA_REQ_START
},
2839 { .name
= "tx1", .dma_req
= 85 + OMAP44XX_DMA_REQ_START
},
2840 { .name
= "tx2", .dma_req
= 86 + OMAP44XX_DMA_REQ_START
},
2841 { .name
= "tx3", .dma_req
= 87 + OMAP44XX_DMA_REQ_START
},
2842 { .name
= "rx0", .dma_req
= 88 + OMAP44XX_DMA_REQ_START
},
2843 { .name
= "rx1", .dma_req
= 89 + OMAP44XX_DMA_REQ_START
},
2844 { .name
= "rx2", .dma_req
= 90 + OMAP44XX_DMA_REQ_START
},
2845 { .name
= "rx3", .dma_req
= 91 + OMAP44XX_DMA_REQ_START
},
2849 static struct omap_hwmod_opt_clk slimbus1_opt_clks
[] = {
2850 { .role
= "fclk_1", .clk
= "slimbus1_fclk_1" },
2851 { .role
= "fclk_0", .clk
= "slimbus1_fclk_0" },
2852 { .role
= "fclk_2", .clk
= "slimbus1_fclk_2" },
2853 { .role
= "slimbus_clk", .clk
= "slimbus1_slimbus_clk" },
2856 static struct omap_hwmod omap44xx_slimbus1_hwmod
= {
2858 .class = &omap44xx_slimbus_hwmod_class
,
2859 .clkdm_name
= "abe_clkdm",
2860 .mpu_irqs
= omap44xx_slimbus1_irqs
,
2861 .sdma_reqs
= omap44xx_slimbus1_sdma_reqs
,
2864 .clkctrl_offs
= OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET
,
2865 .context_offs
= OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET
,
2866 .modulemode
= MODULEMODE_SWCTRL
,
2869 .opt_clks
= slimbus1_opt_clks
,
2870 .opt_clks_cnt
= ARRAY_SIZE(slimbus1_opt_clks
),
2874 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs
[] = {
2875 { .irq
= 98 + OMAP44XX_IRQ_GIC_START
},
2879 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs
[] = {
2880 { .name
= "tx0", .dma_req
= 92 + OMAP44XX_DMA_REQ_START
},
2881 { .name
= "tx1", .dma_req
= 93 + OMAP44XX_DMA_REQ_START
},
2882 { .name
= "tx2", .dma_req
= 94 + OMAP44XX_DMA_REQ_START
},
2883 { .name
= "tx3", .dma_req
= 95 + OMAP44XX_DMA_REQ_START
},
2884 { .name
= "rx0", .dma_req
= 96 + OMAP44XX_DMA_REQ_START
},
2885 { .name
= "rx1", .dma_req
= 97 + OMAP44XX_DMA_REQ_START
},
2886 { .name
= "rx2", .dma_req
= 98 + OMAP44XX_DMA_REQ_START
},
2887 { .name
= "rx3", .dma_req
= 99 + OMAP44XX_DMA_REQ_START
},
2891 static struct omap_hwmod_opt_clk slimbus2_opt_clks
[] = {
2892 { .role
= "fclk_1", .clk
= "slimbus2_fclk_1" },
2893 { .role
= "fclk_0", .clk
= "slimbus2_fclk_0" },
2894 { .role
= "slimbus_clk", .clk
= "slimbus2_slimbus_clk" },
2897 static struct omap_hwmod omap44xx_slimbus2_hwmod
= {
2899 .class = &omap44xx_slimbus_hwmod_class
,
2900 .clkdm_name
= "l4_per_clkdm",
2901 .mpu_irqs
= omap44xx_slimbus2_irqs
,
2902 .sdma_reqs
= omap44xx_slimbus2_sdma_reqs
,
2905 .clkctrl_offs
= OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET
,
2906 .context_offs
= OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET
,
2907 .modulemode
= MODULEMODE_SWCTRL
,
2910 .opt_clks
= slimbus2_opt_clks
,
2911 .opt_clks_cnt
= ARRAY_SIZE(slimbus2_opt_clks
),
2915 * 'smartreflex' class
2916 * smartreflex module (monitor silicon performance and outputs a measure of
2917 * performance error)
2920 /* The IP is not compliant to type1 / type2 scheme */
2921 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex
= {
2926 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc
= {
2927 .sysc_offs
= 0x0038,
2928 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
),
2929 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2931 .sysc_fields
= &omap_hwmod_sysc_type_smartreflex
,
2934 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class
= {
2935 .name
= "smartreflex",
2936 .sysc
= &omap44xx_smartreflex_sysc
,
2940 /* smartreflex_core */
2941 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr
= {
2942 .sensor_voltdm_name
= "core",
2945 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs
[] = {
2946 { .irq
= 19 + OMAP44XX_IRQ_GIC_START
},
2950 static struct omap_hwmod omap44xx_smartreflex_core_hwmod
= {
2951 .name
= "smartreflex_core",
2952 .class = &omap44xx_smartreflex_hwmod_class
,
2953 .clkdm_name
= "l4_ao_clkdm",
2954 .mpu_irqs
= omap44xx_smartreflex_core_irqs
,
2956 .main_clk
= "smartreflex_core_fck",
2959 .clkctrl_offs
= OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET
,
2960 .context_offs
= OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET
,
2961 .modulemode
= MODULEMODE_SWCTRL
,
2964 .dev_attr
= &smartreflex_core_dev_attr
,
2967 /* smartreflex_iva */
2968 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr
= {
2969 .sensor_voltdm_name
= "iva",
2972 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs
[] = {
2973 { .irq
= 102 + OMAP44XX_IRQ_GIC_START
},
2977 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod
= {
2978 .name
= "smartreflex_iva",
2979 .class = &omap44xx_smartreflex_hwmod_class
,
2980 .clkdm_name
= "l4_ao_clkdm",
2981 .mpu_irqs
= omap44xx_smartreflex_iva_irqs
,
2982 .main_clk
= "smartreflex_iva_fck",
2985 .clkctrl_offs
= OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET
,
2986 .context_offs
= OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET
,
2987 .modulemode
= MODULEMODE_SWCTRL
,
2990 .dev_attr
= &smartreflex_iva_dev_attr
,
2993 /* smartreflex_mpu */
2994 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr
= {
2995 .sensor_voltdm_name
= "mpu",
2998 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs
[] = {
2999 { .irq
= 18 + OMAP44XX_IRQ_GIC_START
},
3003 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod
= {
3004 .name
= "smartreflex_mpu",
3005 .class = &omap44xx_smartreflex_hwmod_class
,
3006 .clkdm_name
= "l4_ao_clkdm",
3007 .mpu_irqs
= omap44xx_smartreflex_mpu_irqs
,
3008 .main_clk
= "smartreflex_mpu_fck",
3011 .clkctrl_offs
= OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET
,
3012 .context_offs
= OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET
,
3013 .modulemode
= MODULEMODE_SWCTRL
,
3016 .dev_attr
= &smartreflex_mpu_dev_attr
,
3021 * spinlock provides hardware assistance for synchronizing the processes
3022 * running on multiple processors
3025 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc
= {
3027 .sysc_offs
= 0x0010,
3028 .syss_offs
= 0x0014,
3029 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
3030 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
3031 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3032 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3034 .sysc_fields
= &omap_hwmod_sysc_type1
,
3037 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class
= {
3039 .sysc
= &omap44xx_spinlock_sysc
,
3043 static struct omap_hwmod omap44xx_spinlock_hwmod
= {
3045 .class = &omap44xx_spinlock_hwmod_class
,
3046 .clkdm_name
= "l4_cfg_clkdm",
3049 .clkctrl_offs
= OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET
,
3050 .context_offs
= OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET
,
3057 * general purpose timer module with accurate 1ms tick
3058 * This class contains several variants: ['timer_1ms', 'timer']
3061 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc
= {
3063 .sysc_offs
= 0x0010,
3064 .syss_offs
= 0x0014,
3065 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
3066 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
3067 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
3068 SYSS_HAS_RESET_STATUS
),
3069 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3070 .clockact
= CLOCKACT_TEST_ICLK
,
3071 .sysc_fields
= &omap_hwmod_sysc_type1
,
3074 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class
= {
3076 .sysc
= &omap44xx_timer_1ms_sysc
,
3079 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc
= {
3081 .sysc_offs
= 0x0010,
3082 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
3083 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
3084 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3086 .sysc_fields
= &omap_hwmod_sysc_type2
,
3089 static struct omap_hwmod_class omap44xx_timer_hwmod_class
= {
3091 .sysc
= &omap44xx_timer_sysc
,
3094 /* always-on timers dev attribute */
3095 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr
= {
3096 .timer_capability
= OMAP_TIMER_ALWON
,
3099 /* pwm timers dev attribute */
3100 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr
= {
3101 .timer_capability
= OMAP_TIMER_HAS_PWM
,
3104 /* timers with DSP interrupt dev attribute */
3105 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr
= {
3106 .timer_capability
= OMAP_TIMER_HAS_DSP_IRQ
,
3109 /* pwm timers with DSP interrupt dev attribute */
3110 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr
= {
3111 .timer_capability
= OMAP_TIMER_HAS_DSP_IRQ
| OMAP_TIMER_HAS_PWM
,
3115 static struct omap_hwmod_irq_info omap44xx_timer1_irqs
[] = {
3116 { .irq
= 37 + OMAP44XX_IRQ_GIC_START
},
3120 static struct omap_hwmod omap44xx_timer1_hwmod
= {
3122 .class = &omap44xx_timer_1ms_hwmod_class
,
3123 .clkdm_name
= "l4_wkup_clkdm",
3124 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
3125 .mpu_irqs
= omap44xx_timer1_irqs
,
3126 .main_clk
= "timer1_fck",
3129 .clkctrl_offs
= OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET
,
3130 .context_offs
= OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET
,
3131 .modulemode
= MODULEMODE_SWCTRL
,
3134 .dev_attr
= &capability_alwon_dev_attr
,
3138 static struct omap_hwmod_irq_info omap44xx_timer2_irqs
[] = {
3139 { .irq
= 38 + OMAP44XX_IRQ_GIC_START
},
3143 static struct omap_hwmod omap44xx_timer2_hwmod
= {
3145 .class = &omap44xx_timer_1ms_hwmod_class
,
3146 .clkdm_name
= "l4_per_clkdm",
3147 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
3148 .mpu_irqs
= omap44xx_timer2_irqs
,
3149 .main_clk
= "timer2_fck",
3152 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET
,
3153 .context_offs
= OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET
,
3154 .modulemode
= MODULEMODE_SWCTRL
,
3160 static struct omap_hwmod_irq_info omap44xx_timer3_irqs
[] = {
3161 { .irq
= 39 + OMAP44XX_IRQ_GIC_START
},
3165 static struct omap_hwmod omap44xx_timer3_hwmod
= {
3167 .class = &omap44xx_timer_hwmod_class
,
3168 .clkdm_name
= "l4_per_clkdm",
3169 .mpu_irqs
= omap44xx_timer3_irqs
,
3170 .main_clk
= "timer3_fck",
3173 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET
,
3174 .context_offs
= OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET
,
3175 .modulemode
= MODULEMODE_SWCTRL
,
3181 static struct omap_hwmod_irq_info omap44xx_timer4_irqs
[] = {
3182 { .irq
= 40 + OMAP44XX_IRQ_GIC_START
},
3186 static struct omap_hwmod omap44xx_timer4_hwmod
= {
3188 .class = &omap44xx_timer_hwmod_class
,
3189 .clkdm_name
= "l4_per_clkdm",
3190 .mpu_irqs
= omap44xx_timer4_irqs
,
3191 .main_clk
= "timer4_fck",
3194 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET
,
3195 .context_offs
= OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET
,
3196 .modulemode
= MODULEMODE_SWCTRL
,
3202 static struct omap_hwmod_irq_info omap44xx_timer5_irqs
[] = {
3203 { .irq
= 41 + OMAP44XX_IRQ_GIC_START
},
3207 static struct omap_hwmod omap44xx_timer5_hwmod
= {
3209 .class = &omap44xx_timer_hwmod_class
,
3210 .clkdm_name
= "abe_clkdm",
3211 .mpu_irqs
= omap44xx_timer5_irqs
,
3212 .main_clk
= "timer5_fck",
3215 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET
,
3216 .context_offs
= OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET
,
3217 .modulemode
= MODULEMODE_SWCTRL
,
3220 .dev_attr
= &capability_dsp_dev_attr
,
3224 static struct omap_hwmod_irq_info omap44xx_timer6_irqs
[] = {
3225 { .irq
= 42 + OMAP44XX_IRQ_GIC_START
},
3229 static struct omap_hwmod omap44xx_timer6_hwmod
= {
3231 .class = &omap44xx_timer_hwmod_class
,
3232 .clkdm_name
= "abe_clkdm",
3233 .mpu_irqs
= omap44xx_timer6_irqs
,
3235 .main_clk
= "timer6_fck",
3238 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET
,
3239 .context_offs
= OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET
,
3240 .modulemode
= MODULEMODE_SWCTRL
,
3243 .dev_attr
= &capability_dsp_dev_attr
,
3247 static struct omap_hwmod_irq_info omap44xx_timer7_irqs
[] = {
3248 { .irq
= 43 + OMAP44XX_IRQ_GIC_START
},
3252 static struct omap_hwmod omap44xx_timer7_hwmod
= {
3254 .class = &omap44xx_timer_hwmod_class
,
3255 .clkdm_name
= "abe_clkdm",
3256 .mpu_irqs
= omap44xx_timer7_irqs
,
3257 .main_clk
= "timer7_fck",
3260 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET
,
3261 .context_offs
= OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET
,
3262 .modulemode
= MODULEMODE_SWCTRL
,
3265 .dev_attr
= &capability_dsp_dev_attr
,
3269 static struct omap_hwmod_irq_info omap44xx_timer8_irqs
[] = {
3270 { .irq
= 44 + OMAP44XX_IRQ_GIC_START
},
3274 static struct omap_hwmod omap44xx_timer8_hwmod
= {
3276 .class = &omap44xx_timer_hwmod_class
,
3277 .clkdm_name
= "abe_clkdm",
3278 .mpu_irqs
= omap44xx_timer8_irqs
,
3279 .main_clk
= "timer8_fck",
3282 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET
,
3283 .context_offs
= OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET
,
3284 .modulemode
= MODULEMODE_SWCTRL
,
3287 .dev_attr
= &capability_dsp_pwm_dev_attr
,
3291 static struct omap_hwmod_irq_info omap44xx_timer9_irqs
[] = {
3292 { .irq
= 45 + OMAP44XX_IRQ_GIC_START
},
3296 static struct omap_hwmod omap44xx_timer9_hwmod
= {
3298 .class = &omap44xx_timer_hwmod_class
,
3299 .clkdm_name
= "l4_per_clkdm",
3300 .mpu_irqs
= omap44xx_timer9_irqs
,
3301 .main_clk
= "timer9_fck",
3304 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET
,
3305 .context_offs
= OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET
,
3306 .modulemode
= MODULEMODE_SWCTRL
,
3309 .dev_attr
= &capability_pwm_dev_attr
,
3313 static struct omap_hwmod_irq_info omap44xx_timer10_irqs
[] = {
3314 { .irq
= 46 + OMAP44XX_IRQ_GIC_START
},
3318 static struct omap_hwmod omap44xx_timer10_hwmod
= {
3320 .class = &omap44xx_timer_1ms_hwmod_class
,
3321 .clkdm_name
= "l4_per_clkdm",
3322 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
3323 .mpu_irqs
= omap44xx_timer10_irqs
,
3324 .main_clk
= "timer10_fck",
3327 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET
,
3328 .context_offs
= OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET
,
3329 .modulemode
= MODULEMODE_SWCTRL
,
3332 .dev_attr
= &capability_pwm_dev_attr
,
3336 static struct omap_hwmod_irq_info omap44xx_timer11_irqs
[] = {
3337 { .irq
= 47 + OMAP44XX_IRQ_GIC_START
},
3341 static struct omap_hwmod omap44xx_timer11_hwmod
= {
3343 .class = &omap44xx_timer_hwmod_class
,
3344 .clkdm_name
= "l4_per_clkdm",
3345 .mpu_irqs
= omap44xx_timer11_irqs
,
3346 .main_clk
= "timer11_fck",
3349 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET
,
3350 .context_offs
= OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET
,
3351 .modulemode
= MODULEMODE_SWCTRL
,
3354 .dev_attr
= &capability_pwm_dev_attr
,
3359 * universal asynchronous receiver/transmitter (uart)
3362 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc
= {
3364 .sysc_offs
= 0x0054,
3365 .syss_offs
= 0x0058,
3366 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3367 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
3368 SYSS_HAS_RESET_STATUS
),
3369 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3371 .sysc_fields
= &omap_hwmod_sysc_type1
,
3374 static struct omap_hwmod_class omap44xx_uart_hwmod_class
= {
3376 .sysc
= &omap44xx_uart_sysc
,
3380 static struct omap_hwmod_irq_info omap44xx_uart1_irqs
[] = {
3381 { .irq
= 72 + OMAP44XX_IRQ_GIC_START
},
3385 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs
[] = {
3386 { .name
= "tx", .dma_req
= 48 + OMAP44XX_DMA_REQ_START
},
3387 { .name
= "rx", .dma_req
= 49 + OMAP44XX_DMA_REQ_START
},
3391 static struct omap_hwmod omap44xx_uart1_hwmod
= {
3393 .class = &omap44xx_uart_hwmod_class
,
3394 .clkdm_name
= "l4_per_clkdm",
3395 .mpu_irqs
= omap44xx_uart1_irqs
,
3396 .sdma_reqs
= omap44xx_uart1_sdma_reqs
,
3397 .main_clk
= "uart1_fck",
3400 .clkctrl_offs
= OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET
,
3401 .context_offs
= OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET
,
3402 .modulemode
= MODULEMODE_SWCTRL
,
3408 static struct omap_hwmod_irq_info omap44xx_uart2_irqs
[] = {
3409 { .irq
= 73 + OMAP44XX_IRQ_GIC_START
},
3413 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs
[] = {
3414 { .name
= "tx", .dma_req
= 50 + OMAP44XX_DMA_REQ_START
},
3415 { .name
= "rx", .dma_req
= 51 + OMAP44XX_DMA_REQ_START
},
3419 static struct omap_hwmod omap44xx_uart2_hwmod
= {
3421 .class = &omap44xx_uart_hwmod_class
,
3422 .clkdm_name
= "l4_per_clkdm",
3423 .mpu_irqs
= omap44xx_uart2_irqs
,
3424 .sdma_reqs
= omap44xx_uart2_sdma_reqs
,
3425 .main_clk
= "uart2_fck",
3428 .clkctrl_offs
= OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET
,
3429 .context_offs
= OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET
,
3430 .modulemode
= MODULEMODE_SWCTRL
,
3436 static struct omap_hwmod_irq_info omap44xx_uart3_irqs
[] = {
3437 { .irq
= 74 + OMAP44XX_IRQ_GIC_START
},
3441 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs
[] = {
3442 { .name
= "tx", .dma_req
= 52 + OMAP44XX_DMA_REQ_START
},
3443 { .name
= "rx", .dma_req
= 53 + OMAP44XX_DMA_REQ_START
},
3447 static struct omap_hwmod omap44xx_uart3_hwmod
= {
3449 .class = &omap44xx_uart_hwmod_class
,
3450 .clkdm_name
= "l4_per_clkdm",
3451 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
3452 .mpu_irqs
= omap44xx_uart3_irqs
,
3453 .sdma_reqs
= omap44xx_uart3_sdma_reqs
,
3454 .main_clk
= "uart3_fck",
3457 .clkctrl_offs
= OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET
,
3458 .context_offs
= OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET
,
3459 .modulemode
= MODULEMODE_SWCTRL
,
3465 static struct omap_hwmod_irq_info omap44xx_uart4_irqs
[] = {
3466 { .irq
= 70 + OMAP44XX_IRQ_GIC_START
},
3470 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs
[] = {
3471 { .name
= "tx", .dma_req
= 54 + OMAP44XX_DMA_REQ_START
},
3472 { .name
= "rx", .dma_req
= 55 + OMAP44XX_DMA_REQ_START
},
3476 static struct omap_hwmod omap44xx_uart4_hwmod
= {
3478 .class = &omap44xx_uart_hwmod_class
,
3479 .clkdm_name
= "l4_per_clkdm",
3480 .mpu_irqs
= omap44xx_uart4_irqs
,
3481 .sdma_reqs
= omap44xx_uart4_sdma_reqs
,
3482 .main_clk
= "uart4_fck",
3485 .clkctrl_offs
= OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET
,
3486 .context_offs
= OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET
,
3487 .modulemode
= MODULEMODE_SWCTRL
,
3493 * 'usb_host_fs' class
3494 * full-speed usb host controller
3497 /* The IP is not compliant to type1 / type2 scheme */
3498 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs
= {
3504 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc
= {
3506 .sysc_offs
= 0x0210,
3507 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3508 SYSC_HAS_SOFTRESET
),
3509 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3511 .sysc_fields
= &omap_hwmod_sysc_type_usb_host_fs
,
3514 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class
= {
3515 .name
= "usb_host_fs",
3516 .sysc
= &omap44xx_usb_host_fs_sysc
,
3520 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs
[] = {
3521 { .name
= "std", .irq
= 89 + OMAP44XX_IRQ_GIC_START
},
3522 { .name
= "smi", .irq
= 90 + OMAP44XX_IRQ_GIC_START
},
3526 static struct omap_hwmod omap44xx_usb_host_fs_hwmod
= {
3527 .name
= "usb_host_fs",
3528 .class = &omap44xx_usb_host_fs_hwmod_class
,
3529 .clkdm_name
= "l3_init_clkdm",
3530 .mpu_irqs
= omap44xx_usb_host_fs_irqs
,
3531 .main_clk
= "usb_host_fs_fck",
3534 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET
,
3535 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET
,
3536 .modulemode
= MODULEMODE_SWCTRL
,
3542 * 'usb_host_hs' class
3543 * high-speed multi-port usb host controller
3546 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc
= {
3548 .sysc_offs
= 0x0010,
3549 .syss_offs
= 0x0014,
3550 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3551 SYSC_HAS_SOFTRESET
),
3552 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3553 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3554 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
3555 .sysc_fields
= &omap_hwmod_sysc_type2
,
3558 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class
= {
3559 .name
= "usb_host_hs",
3560 .sysc
= &omap44xx_usb_host_hs_sysc
,
3564 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs
[] = {
3565 { .name
= "ohci-irq", .irq
= 76 + OMAP44XX_IRQ_GIC_START
},
3566 { .name
= "ehci-irq", .irq
= 77 + OMAP44XX_IRQ_GIC_START
},
3570 static struct omap_hwmod omap44xx_usb_host_hs_hwmod
= {
3571 .name
= "usb_host_hs",
3572 .class = &omap44xx_usb_host_hs_hwmod_class
,
3573 .clkdm_name
= "l3_init_clkdm",
3574 .main_clk
= "usb_host_hs_fck",
3577 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET
,
3578 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET
,
3579 .modulemode
= MODULEMODE_SWCTRL
,
3582 .mpu_irqs
= omap44xx_usb_host_hs_irqs
,
3585 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3589 * In the following configuration :
3590 * - USBHOST module is set to smart-idle mode
3591 * - PRCM asserts idle_req to the USBHOST module ( This typically
3592 * happens when the system is going to a low power mode : all ports
3593 * have been suspended, the master part of the USBHOST module has
3594 * entered the standby state, and SW has cut the functional clocks)
3595 * - an USBHOST interrupt occurs before the module is able to answer
3596 * idle_ack, typically a remote wakeup IRQ.
3597 * Then the USB HOST module will enter a deadlock situation where it
3598 * is no more accessible nor functional.
3601 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3605 * Errata: USB host EHCI may stall when entering smart-standby mode
3609 * When the USBHOST module is set to smart-standby mode, and when it is
3610 * ready to enter the standby state (i.e. all ports are suspended and
3611 * all attached devices are in suspend mode), then it can wrongly assert
3612 * the Mstandby signal too early while there are still some residual OCP
3613 * transactions ongoing. If this condition occurs, the internal state
3614 * machine may go to an undefined state and the USB link may be stuck
3615 * upon the next resume.
3618 * Don't use smart standby; use only force standby,
3619 * hence HWMOD_SWSUP_MSTANDBY
3623 * During system boot; If the hwmod framework resets the module
3624 * the module will have smart idle settings; which can lead to deadlock
3625 * (above Errata Id:i660); so, dont reset the module during boot;
3626 * Use HWMOD_INIT_NO_RESET.
3629 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
|
3630 HWMOD_INIT_NO_RESET
,
3634 * 'usb_otg_hs' class
3635 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3638 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc
= {
3640 .sysc_offs
= 0x0404,
3641 .syss_offs
= 0x0408,
3642 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3643 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3644 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3645 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3646 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3648 .sysc_fields
= &omap_hwmod_sysc_type1
,
3651 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class
= {
3652 .name
= "usb_otg_hs",
3653 .sysc
= &omap44xx_usb_otg_hs_sysc
,
3657 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs
[] = {
3658 { .name
= "mc", .irq
= 92 + OMAP44XX_IRQ_GIC_START
},
3659 { .name
= "dma", .irq
= 93 + OMAP44XX_IRQ_GIC_START
},
3663 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks
[] = {
3664 { .role
= "xclk", .clk
= "usb_otg_hs_xclk" },
3667 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod
= {
3668 .name
= "usb_otg_hs",
3669 .class = &omap44xx_usb_otg_hs_hwmod_class
,
3670 .clkdm_name
= "l3_init_clkdm",
3671 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
3672 .mpu_irqs
= omap44xx_usb_otg_hs_irqs
,
3673 .main_clk
= "usb_otg_hs_ick",
3676 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET
,
3677 .context_offs
= OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET
,
3678 .modulemode
= MODULEMODE_HWCTRL
,
3681 .opt_clks
= usb_otg_hs_opt_clks
,
3682 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_hs_opt_clks
),
3686 * 'usb_tll_hs' class
3687 * usb_tll_hs module is the adapter on the usb_host_hs ports
3690 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc
= {
3692 .sysc_offs
= 0x0010,
3693 .syss_offs
= 0x0014,
3694 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3695 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3697 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3698 .sysc_fields
= &omap_hwmod_sysc_type1
,
3701 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class
= {
3702 .name
= "usb_tll_hs",
3703 .sysc
= &omap44xx_usb_tll_hs_sysc
,
3706 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs
[] = {
3707 { .name
= "tll-irq", .irq
= 78 + OMAP44XX_IRQ_GIC_START
},
3711 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod
= {
3712 .name
= "usb_tll_hs",
3713 .class = &omap44xx_usb_tll_hs_hwmod_class
,
3714 .clkdm_name
= "l3_init_clkdm",
3715 .mpu_irqs
= omap44xx_usb_tll_hs_irqs
,
3716 .main_clk
= "usb_tll_hs_ick",
3719 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET
,
3720 .context_offs
= OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET
,
3721 .modulemode
= MODULEMODE_HWCTRL
,
3728 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3729 * overflow condition
3732 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc
= {
3734 .sysc_offs
= 0x0010,
3735 .syss_offs
= 0x0014,
3736 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
3737 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3738 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3740 .sysc_fields
= &omap_hwmod_sysc_type1
,
3743 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class
= {
3745 .sysc
= &omap44xx_wd_timer_sysc
,
3746 .pre_shutdown
= &omap2_wd_timer_disable
,
3747 .reset
= &omap2_wd_timer_reset
,
3751 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs
[] = {
3752 { .irq
= 80 + OMAP44XX_IRQ_GIC_START
},
3756 static struct omap_hwmod omap44xx_wd_timer2_hwmod
= {
3757 .name
= "wd_timer2",
3758 .class = &omap44xx_wd_timer_hwmod_class
,
3759 .clkdm_name
= "l4_wkup_clkdm",
3760 .mpu_irqs
= omap44xx_wd_timer2_irqs
,
3761 .main_clk
= "wd_timer2_fck",
3764 .clkctrl_offs
= OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET
,
3765 .context_offs
= OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET
,
3766 .modulemode
= MODULEMODE_SWCTRL
,
3772 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs
[] = {
3773 { .irq
= 36 + OMAP44XX_IRQ_GIC_START
},
3777 static struct omap_hwmod omap44xx_wd_timer3_hwmod
= {
3778 .name
= "wd_timer3",
3779 .class = &omap44xx_wd_timer_hwmod_class
,
3780 .clkdm_name
= "abe_clkdm",
3781 .mpu_irqs
= omap44xx_wd_timer3_irqs
,
3782 .main_clk
= "wd_timer3_fck",
3785 .clkctrl_offs
= OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET
,
3786 .context_offs
= OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET
,
3787 .modulemode
= MODULEMODE_SWCTRL
,
3797 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs
[] = {
3799 .pa_start
= 0x4a204000,
3800 .pa_end
= 0x4a2040ff,
3801 .flags
= ADDR_TYPE_RT
3806 /* c2c -> c2c_target_fw */
3807 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw
= {
3808 .master
= &omap44xx_c2c_hwmod
,
3809 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3810 .clk
= "div_core_ck",
3811 .addr
= omap44xx_c2c_target_fw_addrs
,
3812 .user
= OCP_USER_MPU
,
3815 /* l4_cfg -> c2c_target_fw */
3816 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw
= {
3817 .master
= &omap44xx_l4_cfg_hwmod
,
3818 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3820 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3823 /* l3_main_1 -> dmm */
3824 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm
= {
3825 .master
= &omap44xx_l3_main_1_hwmod
,
3826 .slave
= &omap44xx_dmm_hwmod
,
3828 .user
= OCP_USER_SDMA
,
3831 static struct omap_hwmod_addr_space omap44xx_dmm_addrs
[] = {
3833 .pa_start
= 0x4e000000,
3834 .pa_end
= 0x4e0007ff,
3835 .flags
= ADDR_TYPE_RT
3841 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm
= {
3842 .master
= &omap44xx_mpu_hwmod
,
3843 .slave
= &omap44xx_dmm_hwmod
,
3845 .addr
= omap44xx_dmm_addrs
,
3846 .user
= OCP_USER_MPU
,
3849 /* c2c -> emif_fw */
3850 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw
= {
3851 .master
= &omap44xx_c2c_hwmod
,
3852 .slave
= &omap44xx_emif_fw_hwmod
,
3853 .clk
= "div_core_ck",
3854 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3857 /* dmm -> emif_fw */
3858 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw
= {
3859 .master
= &omap44xx_dmm_hwmod
,
3860 .slave
= &omap44xx_emif_fw_hwmod
,
3862 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3865 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs
[] = {
3867 .pa_start
= 0x4a20c000,
3868 .pa_end
= 0x4a20c0ff,
3869 .flags
= ADDR_TYPE_RT
3874 /* l4_cfg -> emif_fw */
3875 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw
= {
3876 .master
= &omap44xx_l4_cfg_hwmod
,
3877 .slave
= &omap44xx_emif_fw_hwmod
,
3879 .addr
= omap44xx_emif_fw_addrs
,
3880 .user
= OCP_USER_MPU
,
3883 /* iva -> l3_instr */
3884 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr
= {
3885 .master
= &omap44xx_iva_hwmod
,
3886 .slave
= &omap44xx_l3_instr_hwmod
,
3888 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3891 /* l3_main_3 -> l3_instr */
3892 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr
= {
3893 .master
= &omap44xx_l3_main_3_hwmod
,
3894 .slave
= &omap44xx_l3_instr_hwmod
,
3896 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3899 /* ocp_wp_noc -> l3_instr */
3900 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr
= {
3901 .master
= &omap44xx_ocp_wp_noc_hwmod
,
3902 .slave
= &omap44xx_l3_instr_hwmod
,
3904 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3907 /* dsp -> l3_main_1 */
3908 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1
= {
3909 .master
= &omap44xx_dsp_hwmod
,
3910 .slave
= &omap44xx_l3_main_1_hwmod
,
3912 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3915 /* dss -> l3_main_1 */
3916 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1
= {
3917 .master
= &omap44xx_dss_hwmod
,
3918 .slave
= &omap44xx_l3_main_1_hwmod
,
3920 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3923 /* l3_main_2 -> l3_main_1 */
3924 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1
= {
3925 .master
= &omap44xx_l3_main_2_hwmod
,
3926 .slave
= &omap44xx_l3_main_1_hwmod
,
3928 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3931 /* l4_cfg -> l3_main_1 */
3932 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1
= {
3933 .master
= &omap44xx_l4_cfg_hwmod
,
3934 .slave
= &omap44xx_l3_main_1_hwmod
,
3936 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3939 /* mmc1 -> l3_main_1 */
3940 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1
= {
3941 .master
= &omap44xx_mmc1_hwmod
,
3942 .slave
= &omap44xx_l3_main_1_hwmod
,
3944 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3947 /* mmc2 -> l3_main_1 */
3948 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1
= {
3949 .master
= &omap44xx_mmc2_hwmod
,
3950 .slave
= &omap44xx_l3_main_1_hwmod
,
3952 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3955 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs
[] = {
3957 .pa_start
= 0x44000000,
3958 .pa_end
= 0x44000fff,
3959 .flags
= ADDR_TYPE_RT
3964 /* mpu -> l3_main_1 */
3965 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1
= {
3966 .master
= &omap44xx_mpu_hwmod
,
3967 .slave
= &omap44xx_l3_main_1_hwmod
,
3969 .addr
= omap44xx_l3_main_1_addrs
,
3970 .user
= OCP_USER_MPU
,
3973 /* c2c_target_fw -> l3_main_2 */
3974 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2
= {
3975 .master
= &omap44xx_c2c_target_fw_hwmod
,
3976 .slave
= &omap44xx_l3_main_2_hwmod
,
3978 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3981 /* debugss -> l3_main_2 */
3982 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2
= {
3983 .master
= &omap44xx_debugss_hwmod
,
3984 .slave
= &omap44xx_l3_main_2_hwmod
,
3985 .clk
= "dbgclk_mux_ck",
3986 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3989 /* dma_system -> l3_main_2 */
3990 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2
= {
3991 .master
= &omap44xx_dma_system_hwmod
,
3992 .slave
= &omap44xx_l3_main_2_hwmod
,
3994 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3997 /* fdif -> l3_main_2 */
3998 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2
= {
3999 .master
= &omap44xx_fdif_hwmod
,
4000 .slave
= &omap44xx_l3_main_2_hwmod
,
4002 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4005 /* gpu -> l3_main_2 */
4006 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2
= {
4007 .master
= &omap44xx_gpu_hwmod
,
4008 .slave
= &omap44xx_l3_main_2_hwmod
,
4010 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4013 /* hsi -> l3_main_2 */
4014 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2
= {
4015 .master
= &omap44xx_hsi_hwmod
,
4016 .slave
= &omap44xx_l3_main_2_hwmod
,
4018 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4021 /* ipu -> l3_main_2 */
4022 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2
= {
4023 .master
= &omap44xx_ipu_hwmod
,
4024 .slave
= &omap44xx_l3_main_2_hwmod
,
4026 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4029 /* iss -> l3_main_2 */
4030 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2
= {
4031 .master
= &omap44xx_iss_hwmod
,
4032 .slave
= &omap44xx_l3_main_2_hwmod
,
4034 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4037 /* iva -> l3_main_2 */
4038 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2
= {
4039 .master
= &omap44xx_iva_hwmod
,
4040 .slave
= &omap44xx_l3_main_2_hwmod
,
4042 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4045 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs
[] = {
4047 .pa_start
= 0x44800000,
4048 .pa_end
= 0x44801fff,
4049 .flags
= ADDR_TYPE_RT
4054 /* l3_main_1 -> l3_main_2 */
4055 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2
= {
4056 .master
= &omap44xx_l3_main_1_hwmod
,
4057 .slave
= &omap44xx_l3_main_2_hwmod
,
4059 .addr
= omap44xx_l3_main_2_addrs
,
4060 .user
= OCP_USER_MPU
,
4063 /* l4_cfg -> l3_main_2 */
4064 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2
= {
4065 .master
= &omap44xx_l4_cfg_hwmod
,
4066 .slave
= &omap44xx_l3_main_2_hwmod
,
4068 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4071 /* usb_host_fs -> l3_main_2 */
4072 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2
= {
4073 .master
= &omap44xx_usb_host_fs_hwmod
,
4074 .slave
= &omap44xx_l3_main_2_hwmod
,
4076 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4079 /* usb_host_hs -> l3_main_2 */
4080 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2
= {
4081 .master
= &omap44xx_usb_host_hs_hwmod
,
4082 .slave
= &omap44xx_l3_main_2_hwmod
,
4084 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4087 /* usb_otg_hs -> l3_main_2 */
4088 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2
= {
4089 .master
= &omap44xx_usb_otg_hs_hwmod
,
4090 .slave
= &omap44xx_l3_main_2_hwmod
,
4092 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4095 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs
[] = {
4097 .pa_start
= 0x45000000,
4098 .pa_end
= 0x45000fff,
4099 .flags
= ADDR_TYPE_RT
4104 /* l3_main_1 -> l3_main_3 */
4105 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3
= {
4106 .master
= &omap44xx_l3_main_1_hwmod
,
4107 .slave
= &omap44xx_l3_main_3_hwmod
,
4109 .addr
= omap44xx_l3_main_3_addrs
,
4110 .user
= OCP_USER_MPU
,
4113 /* l3_main_2 -> l3_main_3 */
4114 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3
= {
4115 .master
= &omap44xx_l3_main_2_hwmod
,
4116 .slave
= &omap44xx_l3_main_3_hwmod
,
4118 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4121 /* l4_cfg -> l3_main_3 */
4122 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3
= {
4123 .master
= &omap44xx_l4_cfg_hwmod
,
4124 .slave
= &omap44xx_l3_main_3_hwmod
,
4126 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4129 /* aess -> l4_abe */
4130 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe
= {
4131 .master
= &omap44xx_aess_hwmod
,
4132 .slave
= &omap44xx_l4_abe_hwmod
,
4133 .clk
= "ocp_abe_iclk",
4134 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4138 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe
= {
4139 .master
= &omap44xx_dsp_hwmod
,
4140 .slave
= &omap44xx_l4_abe_hwmod
,
4141 .clk
= "ocp_abe_iclk",
4142 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4145 /* l3_main_1 -> l4_abe */
4146 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe
= {
4147 .master
= &omap44xx_l3_main_1_hwmod
,
4148 .slave
= &omap44xx_l4_abe_hwmod
,
4150 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4154 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe
= {
4155 .master
= &omap44xx_mpu_hwmod
,
4156 .slave
= &omap44xx_l4_abe_hwmod
,
4157 .clk
= "ocp_abe_iclk",
4158 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4161 /* l3_main_1 -> l4_cfg */
4162 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg
= {
4163 .master
= &omap44xx_l3_main_1_hwmod
,
4164 .slave
= &omap44xx_l4_cfg_hwmod
,
4166 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4169 /* l3_main_2 -> l4_per */
4170 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per
= {
4171 .master
= &omap44xx_l3_main_2_hwmod
,
4172 .slave
= &omap44xx_l4_per_hwmod
,
4174 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4177 /* l4_cfg -> l4_wkup */
4178 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup
= {
4179 .master
= &omap44xx_l4_cfg_hwmod
,
4180 .slave
= &omap44xx_l4_wkup_hwmod
,
4182 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4185 /* mpu -> mpu_private */
4186 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private
= {
4187 .master
= &omap44xx_mpu_hwmod
,
4188 .slave
= &omap44xx_mpu_private_hwmod
,
4190 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4193 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs
[] = {
4195 .pa_start
= 0x4a102000,
4196 .pa_end
= 0x4a10207f,
4197 .flags
= ADDR_TYPE_RT
4202 /* l4_cfg -> ocp_wp_noc */
4203 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc
= {
4204 .master
= &omap44xx_l4_cfg_hwmod
,
4205 .slave
= &omap44xx_ocp_wp_noc_hwmod
,
4207 .addr
= omap44xx_ocp_wp_noc_addrs
,
4208 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4211 static struct omap_hwmod_addr_space omap44xx_aess_addrs
[] = {
4213 .pa_start
= 0x401f1000,
4214 .pa_end
= 0x401f13ff,
4215 .flags
= ADDR_TYPE_RT
4220 /* l4_abe -> aess */
4221 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess
= {
4222 .master
= &omap44xx_l4_abe_hwmod
,
4223 .slave
= &omap44xx_aess_hwmod
,
4224 .clk
= "ocp_abe_iclk",
4225 .addr
= omap44xx_aess_addrs
,
4226 .user
= OCP_USER_MPU
,
4229 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs
[] = {
4231 .pa_start
= 0x490f1000,
4232 .pa_end
= 0x490f13ff,
4233 .flags
= ADDR_TYPE_RT
4238 /* l4_abe -> aess (dma) */
4239 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma
= {
4240 .master
= &omap44xx_l4_abe_hwmod
,
4241 .slave
= &omap44xx_aess_hwmod
,
4242 .clk
= "ocp_abe_iclk",
4243 .addr
= omap44xx_aess_dma_addrs
,
4244 .user
= OCP_USER_SDMA
,
4247 /* l3_main_2 -> c2c */
4248 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c
= {
4249 .master
= &omap44xx_l3_main_2_hwmod
,
4250 .slave
= &omap44xx_c2c_hwmod
,
4252 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4255 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs
[] = {
4257 .pa_start
= 0x4a304000,
4258 .pa_end
= 0x4a30401f,
4259 .flags
= ADDR_TYPE_RT
4264 /* l4_wkup -> counter_32k */
4265 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k
= {
4266 .master
= &omap44xx_l4_wkup_hwmod
,
4267 .slave
= &omap44xx_counter_32k_hwmod
,
4268 .clk
= "l4_wkup_clk_mux_ck",
4269 .addr
= omap44xx_counter_32k_addrs
,
4270 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4273 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs
[] = {
4275 .pa_start
= 0x4a002000,
4276 .pa_end
= 0x4a0027ff,
4277 .flags
= ADDR_TYPE_RT
4282 /* l4_cfg -> ctrl_module_core */
4283 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core
= {
4284 .master
= &omap44xx_l4_cfg_hwmod
,
4285 .slave
= &omap44xx_ctrl_module_core_hwmod
,
4287 .addr
= omap44xx_ctrl_module_core_addrs
,
4288 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4291 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs
[] = {
4293 .pa_start
= 0x4a100000,
4294 .pa_end
= 0x4a1007ff,
4295 .flags
= ADDR_TYPE_RT
4300 /* l4_cfg -> ctrl_module_pad_core */
4301 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core
= {
4302 .master
= &omap44xx_l4_cfg_hwmod
,
4303 .slave
= &omap44xx_ctrl_module_pad_core_hwmod
,
4305 .addr
= omap44xx_ctrl_module_pad_core_addrs
,
4306 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4309 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs
[] = {
4311 .pa_start
= 0x4a30c000,
4312 .pa_end
= 0x4a30c7ff,
4313 .flags
= ADDR_TYPE_RT
4318 /* l4_wkup -> ctrl_module_wkup */
4319 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup
= {
4320 .master
= &omap44xx_l4_wkup_hwmod
,
4321 .slave
= &omap44xx_ctrl_module_wkup_hwmod
,
4322 .clk
= "l4_wkup_clk_mux_ck",
4323 .addr
= omap44xx_ctrl_module_wkup_addrs
,
4324 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4327 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs
[] = {
4329 .pa_start
= 0x4a31e000,
4330 .pa_end
= 0x4a31e7ff,
4331 .flags
= ADDR_TYPE_RT
4336 /* l4_wkup -> ctrl_module_pad_wkup */
4337 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup
= {
4338 .master
= &omap44xx_l4_wkup_hwmod
,
4339 .slave
= &omap44xx_ctrl_module_pad_wkup_hwmod
,
4340 .clk
= "l4_wkup_clk_mux_ck",
4341 .addr
= omap44xx_ctrl_module_pad_wkup_addrs
,
4342 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4345 static struct omap_hwmod_addr_space omap44xx_debugss_addrs
[] = {
4347 .pa_start
= 0x54160000,
4348 .pa_end
= 0x54167fff,
4349 .flags
= ADDR_TYPE_RT
4354 /* l3_instr -> debugss */
4355 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss
= {
4356 .master
= &omap44xx_l3_instr_hwmod
,
4357 .slave
= &omap44xx_debugss_hwmod
,
4359 .addr
= omap44xx_debugss_addrs
,
4360 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4363 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs
[] = {
4365 .pa_start
= 0x4a056000,
4366 .pa_end
= 0x4a056fff,
4367 .flags
= ADDR_TYPE_RT
4372 /* l4_cfg -> dma_system */
4373 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system
= {
4374 .master
= &omap44xx_l4_cfg_hwmod
,
4375 .slave
= &omap44xx_dma_system_hwmod
,
4377 .addr
= omap44xx_dma_system_addrs
,
4378 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4381 static struct omap_hwmod_addr_space omap44xx_dmic_addrs
[] = {
4384 .pa_start
= 0x4012e000,
4385 .pa_end
= 0x4012e07f,
4386 .flags
= ADDR_TYPE_RT
4391 /* l4_abe -> dmic */
4392 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic
= {
4393 .master
= &omap44xx_l4_abe_hwmod
,
4394 .slave
= &omap44xx_dmic_hwmod
,
4395 .clk
= "ocp_abe_iclk",
4396 .addr
= omap44xx_dmic_addrs
,
4397 .user
= OCP_USER_MPU
,
4400 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs
[] = {
4403 .pa_start
= 0x4902e000,
4404 .pa_end
= 0x4902e07f,
4405 .flags
= ADDR_TYPE_RT
4410 /* l4_abe -> dmic (dma) */
4411 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma
= {
4412 .master
= &omap44xx_l4_abe_hwmod
,
4413 .slave
= &omap44xx_dmic_hwmod
,
4414 .clk
= "ocp_abe_iclk",
4415 .addr
= omap44xx_dmic_dma_addrs
,
4416 .user
= OCP_USER_SDMA
,
4420 static struct omap_hwmod_ocp_if omap44xx_dsp__iva
= {
4421 .master
= &omap44xx_dsp_hwmod
,
4422 .slave
= &omap44xx_iva_hwmod
,
4423 .clk
= "dpll_iva_m5x2_ck",
4424 .user
= OCP_USER_DSP
,
4428 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if
= {
4429 .master
= &omap44xx_dsp_hwmod
,
4430 .slave
= &omap44xx_sl2if_hwmod
,
4431 .clk
= "dpll_iva_m5x2_ck",
4432 .user
= OCP_USER_DSP
,
4436 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp
= {
4437 .master
= &omap44xx_l4_cfg_hwmod
,
4438 .slave
= &omap44xx_dsp_hwmod
,
4440 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4443 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs
[] = {
4445 .pa_start
= 0x58000000,
4446 .pa_end
= 0x5800007f,
4447 .flags
= ADDR_TYPE_RT
4452 /* l3_main_2 -> dss */
4453 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss
= {
4454 .master
= &omap44xx_l3_main_2_hwmod
,
4455 .slave
= &omap44xx_dss_hwmod
,
4457 .addr
= omap44xx_dss_dma_addrs
,
4458 .user
= OCP_USER_SDMA
,
4461 static struct omap_hwmod_addr_space omap44xx_dss_addrs
[] = {
4463 .pa_start
= 0x48040000,
4464 .pa_end
= 0x4804007f,
4465 .flags
= ADDR_TYPE_RT
4471 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss
= {
4472 .master
= &omap44xx_l4_per_hwmod
,
4473 .slave
= &omap44xx_dss_hwmod
,
4475 .addr
= omap44xx_dss_addrs
,
4476 .user
= OCP_USER_MPU
,
4479 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs
[] = {
4481 .pa_start
= 0x58001000,
4482 .pa_end
= 0x58001fff,
4483 .flags
= ADDR_TYPE_RT
4488 /* l3_main_2 -> dss_dispc */
4489 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc
= {
4490 .master
= &omap44xx_l3_main_2_hwmod
,
4491 .slave
= &omap44xx_dss_dispc_hwmod
,
4493 .addr
= omap44xx_dss_dispc_dma_addrs
,
4494 .user
= OCP_USER_SDMA
,
4497 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs
[] = {
4499 .pa_start
= 0x48041000,
4500 .pa_end
= 0x48041fff,
4501 .flags
= ADDR_TYPE_RT
4506 /* l4_per -> dss_dispc */
4507 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc
= {
4508 .master
= &omap44xx_l4_per_hwmod
,
4509 .slave
= &omap44xx_dss_dispc_hwmod
,
4511 .addr
= omap44xx_dss_dispc_addrs
,
4512 .user
= OCP_USER_MPU
,
4515 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs
[] = {
4517 .pa_start
= 0x58004000,
4518 .pa_end
= 0x580041ff,
4519 .flags
= ADDR_TYPE_RT
4524 /* l3_main_2 -> dss_dsi1 */
4525 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1
= {
4526 .master
= &omap44xx_l3_main_2_hwmod
,
4527 .slave
= &omap44xx_dss_dsi1_hwmod
,
4529 .addr
= omap44xx_dss_dsi1_dma_addrs
,
4530 .user
= OCP_USER_SDMA
,
4533 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs
[] = {
4535 .pa_start
= 0x48044000,
4536 .pa_end
= 0x480441ff,
4537 .flags
= ADDR_TYPE_RT
4542 /* l4_per -> dss_dsi1 */
4543 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1
= {
4544 .master
= &omap44xx_l4_per_hwmod
,
4545 .slave
= &omap44xx_dss_dsi1_hwmod
,
4547 .addr
= omap44xx_dss_dsi1_addrs
,
4548 .user
= OCP_USER_MPU
,
4551 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs
[] = {
4553 .pa_start
= 0x58005000,
4554 .pa_end
= 0x580051ff,
4555 .flags
= ADDR_TYPE_RT
4560 /* l3_main_2 -> dss_dsi2 */
4561 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2
= {
4562 .master
= &omap44xx_l3_main_2_hwmod
,
4563 .slave
= &omap44xx_dss_dsi2_hwmod
,
4565 .addr
= omap44xx_dss_dsi2_dma_addrs
,
4566 .user
= OCP_USER_SDMA
,
4569 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs
[] = {
4571 .pa_start
= 0x48045000,
4572 .pa_end
= 0x480451ff,
4573 .flags
= ADDR_TYPE_RT
4578 /* l4_per -> dss_dsi2 */
4579 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2
= {
4580 .master
= &omap44xx_l4_per_hwmod
,
4581 .slave
= &omap44xx_dss_dsi2_hwmod
,
4583 .addr
= omap44xx_dss_dsi2_addrs
,
4584 .user
= OCP_USER_MPU
,
4587 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs
[] = {
4589 .pa_start
= 0x58006000,
4590 .pa_end
= 0x58006fff,
4591 .flags
= ADDR_TYPE_RT
4596 /* l3_main_2 -> dss_hdmi */
4597 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi
= {
4598 .master
= &omap44xx_l3_main_2_hwmod
,
4599 .slave
= &omap44xx_dss_hdmi_hwmod
,
4601 .addr
= omap44xx_dss_hdmi_dma_addrs
,
4602 .user
= OCP_USER_SDMA
,
4605 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs
[] = {
4607 .pa_start
= 0x48046000,
4608 .pa_end
= 0x48046fff,
4609 .flags
= ADDR_TYPE_RT
4614 /* l4_per -> dss_hdmi */
4615 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi
= {
4616 .master
= &omap44xx_l4_per_hwmod
,
4617 .slave
= &omap44xx_dss_hdmi_hwmod
,
4619 .addr
= omap44xx_dss_hdmi_addrs
,
4620 .user
= OCP_USER_MPU
,
4623 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs
[] = {
4625 .pa_start
= 0x58002000,
4626 .pa_end
= 0x580020ff,
4627 .flags
= ADDR_TYPE_RT
4632 /* l3_main_2 -> dss_rfbi */
4633 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi
= {
4634 .master
= &omap44xx_l3_main_2_hwmod
,
4635 .slave
= &omap44xx_dss_rfbi_hwmod
,
4637 .addr
= omap44xx_dss_rfbi_dma_addrs
,
4638 .user
= OCP_USER_SDMA
,
4641 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs
[] = {
4643 .pa_start
= 0x48042000,
4644 .pa_end
= 0x480420ff,
4645 .flags
= ADDR_TYPE_RT
4650 /* l4_per -> dss_rfbi */
4651 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi
= {
4652 .master
= &omap44xx_l4_per_hwmod
,
4653 .slave
= &omap44xx_dss_rfbi_hwmod
,
4655 .addr
= omap44xx_dss_rfbi_addrs
,
4656 .user
= OCP_USER_MPU
,
4659 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs
[] = {
4661 .pa_start
= 0x58003000,
4662 .pa_end
= 0x580030ff,
4663 .flags
= ADDR_TYPE_RT
4668 /* l3_main_2 -> dss_venc */
4669 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc
= {
4670 .master
= &omap44xx_l3_main_2_hwmod
,
4671 .slave
= &omap44xx_dss_venc_hwmod
,
4673 .addr
= omap44xx_dss_venc_dma_addrs
,
4674 .user
= OCP_USER_SDMA
,
4677 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs
[] = {
4679 .pa_start
= 0x48043000,
4680 .pa_end
= 0x480430ff,
4681 .flags
= ADDR_TYPE_RT
4686 /* l4_per -> dss_venc */
4687 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc
= {
4688 .master
= &omap44xx_l4_per_hwmod
,
4689 .slave
= &omap44xx_dss_venc_hwmod
,
4691 .addr
= omap44xx_dss_venc_addrs
,
4692 .user
= OCP_USER_MPU
,
4695 static struct omap_hwmod_addr_space omap44xx_elm_addrs
[] = {
4697 .pa_start
= 0x48078000,
4698 .pa_end
= 0x48078fff,
4699 .flags
= ADDR_TYPE_RT
4705 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm
= {
4706 .master
= &omap44xx_l4_per_hwmod
,
4707 .slave
= &omap44xx_elm_hwmod
,
4709 .addr
= omap44xx_elm_addrs
,
4710 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4713 static struct omap_hwmod_addr_space omap44xx_emif1_addrs
[] = {
4715 .pa_start
= 0x4c000000,
4716 .pa_end
= 0x4c0000ff,
4717 .flags
= ADDR_TYPE_RT
4722 /* emif_fw -> emif1 */
4723 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1
= {
4724 .master
= &omap44xx_emif_fw_hwmod
,
4725 .slave
= &omap44xx_emif1_hwmod
,
4727 .addr
= omap44xx_emif1_addrs
,
4728 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4731 static struct omap_hwmod_addr_space omap44xx_emif2_addrs
[] = {
4733 .pa_start
= 0x4d000000,
4734 .pa_end
= 0x4d0000ff,
4735 .flags
= ADDR_TYPE_RT
4740 /* emif_fw -> emif2 */
4741 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2
= {
4742 .master
= &omap44xx_emif_fw_hwmod
,
4743 .slave
= &omap44xx_emif2_hwmod
,
4745 .addr
= omap44xx_emif2_addrs
,
4746 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4749 static struct omap_hwmod_addr_space omap44xx_fdif_addrs
[] = {
4751 .pa_start
= 0x4a10a000,
4752 .pa_end
= 0x4a10a1ff,
4753 .flags
= ADDR_TYPE_RT
4758 /* l4_cfg -> fdif */
4759 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif
= {
4760 .master
= &omap44xx_l4_cfg_hwmod
,
4761 .slave
= &omap44xx_fdif_hwmod
,
4763 .addr
= omap44xx_fdif_addrs
,
4764 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4767 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs
[] = {
4769 .pa_start
= 0x4a310000,
4770 .pa_end
= 0x4a3101ff,
4771 .flags
= ADDR_TYPE_RT
4776 /* l4_wkup -> gpio1 */
4777 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1
= {
4778 .master
= &omap44xx_l4_wkup_hwmod
,
4779 .slave
= &omap44xx_gpio1_hwmod
,
4780 .clk
= "l4_wkup_clk_mux_ck",
4781 .addr
= omap44xx_gpio1_addrs
,
4782 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4785 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs
[] = {
4787 .pa_start
= 0x48055000,
4788 .pa_end
= 0x480551ff,
4789 .flags
= ADDR_TYPE_RT
4794 /* l4_per -> gpio2 */
4795 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2
= {
4796 .master
= &omap44xx_l4_per_hwmod
,
4797 .slave
= &omap44xx_gpio2_hwmod
,
4799 .addr
= omap44xx_gpio2_addrs
,
4800 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4803 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs
[] = {
4805 .pa_start
= 0x48057000,
4806 .pa_end
= 0x480571ff,
4807 .flags
= ADDR_TYPE_RT
4812 /* l4_per -> gpio3 */
4813 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3
= {
4814 .master
= &omap44xx_l4_per_hwmod
,
4815 .slave
= &omap44xx_gpio3_hwmod
,
4817 .addr
= omap44xx_gpio3_addrs
,
4818 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4821 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs
[] = {
4823 .pa_start
= 0x48059000,
4824 .pa_end
= 0x480591ff,
4825 .flags
= ADDR_TYPE_RT
4830 /* l4_per -> gpio4 */
4831 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4
= {
4832 .master
= &omap44xx_l4_per_hwmod
,
4833 .slave
= &omap44xx_gpio4_hwmod
,
4835 .addr
= omap44xx_gpio4_addrs
,
4836 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4839 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs
[] = {
4841 .pa_start
= 0x4805b000,
4842 .pa_end
= 0x4805b1ff,
4843 .flags
= ADDR_TYPE_RT
4848 /* l4_per -> gpio5 */
4849 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5
= {
4850 .master
= &omap44xx_l4_per_hwmod
,
4851 .slave
= &omap44xx_gpio5_hwmod
,
4853 .addr
= omap44xx_gpio5_addrs
,
4854 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4857 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs
[] = {
4859 .pa_start
= 0x4805d000,
4860 .pa_end
= 0x4805d1ff,
4861 .flags
= ADDR_TYPE_RT
4866 /* l4_per -> gpio6 */
4867 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6
= {
4868 .master
= &omap44xx_l4_per_hwmod
,
4869 .slave
= &omap44xx_gpio6_hwmod
,
4871 .addr
= omap44xx_gpio6_addrs
,
4872 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4875 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs
[] = {
4877 .pa_start
= 0x50000000,
4878 .pa_end
= 0x500003ff,
4879 .flags
= ADDR_TYPE_RT
4884 /* l3_main_2 -> gpmc */
4885 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc
= {
4886 .master
= &omap44xx_l3_main_2_hwmod
,
4887 .slave
= &omap44xx_gpmc_hwmod
,
4889 .addr
= omap44xx_gpmc_addrs
,
4890 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4893 static struct omap_hwmod_addr_space omap44xx_gpu_addrs
[] = {
4895 .pa_start
= 0x56000000,
4896 .pa_end
= 0x5600ffff,
4897 .flags
= ADDR_TYPE_RT
4902 /* l3_main_2 -> gpu */
4903 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu
= {
4904 .master
= &omap44xx_l3_main_2_hwmod
,
4905 .slave
= &omap44xx_gpu_hwmod
,
4907 .addr
= omap44xx_gpu_addrs
,
4908 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4911 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs
[] = {
4913 .pa_start
= 0x480b2000,
4914 .pa_end
= 0x480b201f,
4915 .flags
= ADDR_TYPE_RT
4920 /* l4_per -> hdq1w */
4921 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w
= {
4922 .master
= &omap44xx_l4_per_hwmod
,
4923 .slave
= &omap44xx_hdq1w_hwmod
,
4925 .addr
= omap44xx_hdq1w_addrs
,
4926 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4929 static struct omap_hwmod_addr_space omap44xx_hsi_addrs
[] = {
4931 .pa_start
= 0x4a058000,
4932 .pa_end
= 0x4a05bfff,
4933 .flags
= ADDR_TYPE_RT
4939 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi
= {
4940 .master
= &omap44xx_l4_cfg_hwmod
,
4941 .slave
= &omap44xx_hsi_hwmod
,
4943 .addr
= omap44xx_hsi_addrs
,
4944 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4947 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs
[] = {
4949 .pa_start
= 0x48070000,
4950 .pa_end
= 0x480700ff,
4951 .flags
= ADDR_TYPE_RT
4956 /* l4_per -> i2c1 */
4957 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1
= {
4958 .master
= &omap44xx_l4_per_hwmod
,
4959 .slave
= &omap44xx_i2c1_hwmod
,
4961 .addr
= omap44xx_i2c1_addrs
,
4962 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4965 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs
[] = {
4967 .pa_start
= 0x48072000,
4968 .pa_end
= 0x480720ff,
4969 .flags
= ADDR_TYPE_RT
4974 /* l4_per -> i2c2 */
4975 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2
= {
4976 .master
= &omap44xx_l4_per_hwmod
,
4977 .slave
= &omap44xx_i2c2_hwmod
,
4979 .addr
= omap44xx_i2c2_addrs
,
4980 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4983 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs
[] = {
4985 .pa_start
= 0x48060000,
4986 .pa_end
= 0x480600ff,
4987 .flags
= ADDR_TYPE_RT
4992 /* l4_per -> i2c3 */
4993 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3
= {
4994 .master
= &omap44xx_l4_per_hwmod
,
4995 .slave
= &omap44xx_i2c3_hwmod
,
4997 .addr
= omap44xx_i2c3_addrs
,
4998 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5001 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs
[] = {
5003 .pa_start
= 0x48350000,
5004 .pa_end
= 0x483500ff,
5005 .flags
= ADDR_TYPE_RT
5010 /* l4_per -> i2c4 */
5011 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4
= {
5012 .master
= &omap44xx_l4_per_hwmod
,
5013 .slave
= &omap44xx_i2c4_hwmod
,
5015 .addr
= omap44xx_i2c4_addrs
,
5016 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5019 /* l3_main_2 -> ipu */
5020 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu
= {
5021 .master
= &omap44xx_l3_main_2_hwmod
,
5022 .slave
= &omap44xx_ipu_hwmod
,
5024 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5027 static struct omap_hwmod_addr_space omap44xx_iss_addrs
[] = {
5029 .pa_start
= 0x52000000,
5030 .pa_end
= 0x520000ff,
5031 .flags
= ADDR_TYPE_RT
5036 /* l3_main_2 -> iss */
5037 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss
= {
5038 .master
= &omap44xx_l3_main_2_hwmod
,
5039 .slave
= &omap44xx_iss_hwmod
,
5041 .addr
= omap44xx_iss_addrs
,
5042 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5046 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if
= {
5047 .master
= &omap44xx_iva_hwmod
,
5048 .slave
= &omap44xx_sl2if_hwmod
,
5049 .clk
= "dpll_iva_m5x2_ck",
5050 .user
= OCP_USER_IVA
,
5053 static struct omap_hwmod_addr_space omap44xx_iva_addrs
[] = {
5055 .pa_start
= 0x5a000000,
5056 .pa_end
= 0x5a07ffff,
5057 .flags
= ADDR_TYPE_RT
5062 /* l3_main_2 -> iva */
5063 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva
= {
5064 .master
= &omap44xx_l3_main_2_hwmod
,
5065 .slave
= &omap44xx_iva_hwmod
,
5067 .addr
= omap44xx_iva_addrs
,
5068 .user
= OCP_USER_MPU
,
5071 static struct omap_hwmod_addr_space omap44xx_kbd_addrs
[] = {
5073 .pa_start
= 0x4a31c000,
5074 .pa_end
= 0x4a31c07f,
5075 .flags
= ADDR_TYPE_RT
5080 /* l4_wkup -> kbd */
5081 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd
= {
5082 .master
= &omap44xx_l4_wkup_hwmod
,
5083 .slave
= &omap44xx_kbd_hwmod
,
5084 .clk
= "l4_wkup_clk_mux_ck",
5085 .addr
= omap44xx_kbd_addrs
,
5086 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5089 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs
[] = {
5091 .pa_start
= 0x4a0f4000,
5092 .pa_end
= 0x4a0f41ff,
5093 .flags
= ADDR_TYPE_RT
5098 /* l4_cfg -> mailbox */
5099 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox
= {
5100 .master
= &omap44xx_l4_cfg_hwmod
,
5101 .slave
= &omap44xx_mailbox_hwmod
,
5103 .addr
= omap44xx_mailbox_addrs
,
5104 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5107 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs
[] = {
5109 .pa_start
= 0x40128000,
5110 .pa_end
= 0x401283ff,
5111 .flags
= ADDR_TYPE_RT
5116 /* l4_abe -> mcasp */
5117 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp
= {
5118 .master
= &omap44xx_l4_abe_hwmod
,
5119 .slave
= &omap44xx_mcasp_hwmod
,
5120 .clk
= "ocp_abe_iclk",
5121 .addr
= omap44xx_mcasp_addrs
,
5122 .user
= OCP_USER_MPU
,
5125 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs
[] = {
5127 .pa_start
= 0x49028000,
5128 .pa_end
= 0x490283ff,
5129 .flags
= ADDR_TYPE_RT
5134 /* l4_abe -> mcasp (dma) */
5135 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma
= {
5136 .master
= &omap44xx_l4_abe_hwmod
,
5137 .slave
= &omap44xx_mcasp_hwmod
,
5138 .clk
= "ocp_abe_iclk",
5139 .addr
= omap44xx_mcasp_dma_addrs
,
5140 .user
= OCP_USER_SDMA
,
5143 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs
[] = {
5146 .pa_start
= 0x40122000,
5147 .pa_end
= 0x401220ff,
5148 .flags
= ADDR_TYPE_RT
5153 /* l4_abe -> mcbsp1 */
5154 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1
= {
5155 .master
= &omap44xx_l4_abe_hwmod
,
5156 .slave
= &omap44xx_mcbsp1_hwmod
,
5157 .clk
= "ocp_abe_iclk",
5158 .addr
= omap44xx_mcbsp1_addrs
,
5159 .user
= OCP_USER_MPU
,
5162 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs
[] = {
5165 .pa_start
= 0x49022000,
5166 .pa_end
= 0x490220ff,
5167 .flags
= ADDR_TYPE_RT
5172 /* l4_abe -> mcbsp1 (dma) */
5173 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma
= {
5174 .master
= &omap44xx_l4_abe_hwmod
,
5175 .slave
= &omap44xx_mcbsp1_hwmod
,
5176 .clk
= "ocp_abe_iclk",
5177 .addr
= omap44xx_mcbsp1_dma_addrs
,
5178 .user
= OCP_USER_SDMA
,
5181 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs
[] = {
5184 .pa_start
= 0x40124000,
5185 .pa_end
= 0x401240ff,
5186 .flags
= ADDR_TYPE_RT
5191 /* l4_abe -> mcbsp2 */
5192 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2
= {
5193 .master
= &omap44xx_l4_abe_hwmod
,
5194 .slave
= &omap44xx_mcbsp2_hwmod
,
5195 .clk
= "ocp_abe_iclk",
5196 .addr
= omap44xx_mcbsp2_addrs
,
5197 .user
= OCP_USER_MPU
,
5200 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs
[] = {
5203 .pa_start
= 0x49024000,
5204 .pa_end
= 0x490240ff,
5205 .flags
= ADDR_TYPE_RT
5210 /* l4_abe -> mcbsp2 (dma) */
5211 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma
= {
5212 .master
= &omap44xx_l4_abe_hwmod
,
5213 .slave
= &omap44xx_mcbsp2_hwmod
,
5214 .clk
= "ocp_abe_iclk",
5215 .addr
= omap44xx_mcbsp2_dma_addrs
,
5216 .user
= OCP_USER_SDMA
,
5219 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs
[] = {
5222 .pa_start
= 0x40126000,
5223 .pa_end
= 0x401260ff,
5224 .flags
= ADDR_TYPE_RT
5229 /* l4_abe -> mcbsp3 */
5230 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3
= {
5231 .master
= &omap44xx_l4_abe_hwmod
,
5232 .slave
= &omap44xx_mcbsp3_hwmod
,
5233 .clk
= "ocp_abe_iclk",
5234 .addr
= omap44xx_mcbsp3_addrs
,
5235 .user
= OCP_USER_MPU
,
5238 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs
[] = {
5241 .pa_start
= 0x49026000,
5242 .pa_end
= 0x490260ff,
5243 .flags
= ADDR_TYPE_RT
5248 /* l4_abe -> mcbsp3 (dma) */
5249 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma
= {
5250 .master
= &omap44xx_l4_abe_hwmod
,
5251 .slave
= &omap44xx_mcbsp3_hwmod
,
5252 .clk
= "ocp_abe_iclk",
5253 .addr
= omap44xx_mcbsp3_dma_addrs
,
5254 .user
= OCP_USER_SDMA
,
5257 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs
[] = {
5259 .pa_start
= 0x48096000,
5260 .pa_end
= 0x480960ff,
5261 .flags
= ADDR_TYPE_RT
5266 /* l4_per -> mcbsp4 */
5267 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4
= {
5268 .master
= &omap44xx_l4_per_hwmod
,
5269 .slave
= &omap44xx_mcbsp4_hwmod
,
5271 .addr
= omap44xx_mcbsp4_addrs
,
5272 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5275 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs
[] = {
5278 .pa_start
= 0x40132000,
5279 .pa_end
= 0x4013207f,
5280 .flags
= ADDR_TYPE_RT
5285 /* l4_abe -> mcpdm */
5286 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm
= {
5287 .master
= &omap44xx_l4_abe_hwmod
,
5288 .slave
= &omap44xx_mcpdm_hwmod
,
5289 .clk
= "ocp_abe_iclk",
5290 .addr
= omap44xx_mcpdm_addrs
,
5291 .user
= OCP_USER_MPU
,
5294 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs
[] = {
5297 .pa_start
= 0x49032000,
5298 .pa_end
= 0x4903207f,
5299 .flags
= ADDR_TYPE_RT
5304 /* l4_abe -> mcpdm (dma) */
5305 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma
= {
5306 .master
= &omap44xx_l4_abe_hwmod
,
5307 .slave
= &omap44xx_mcpdm_hwmod
,
5308 .clk
= "ocp_abe_iclk",
5309 .addr
= omap44xx_mcpdm_dma_addrs
,
5310 .user
= OCP_USER_SDMA
,
5313 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs
[] = {
5315 .pa_start
= 0x48098000,
5316 .pa_end
= 0x480981ff,
5317 .flags
= ADDR_TYPE_RT
5322 /* l4_per -> mcspi1 */
5323 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1
= {
5324 .master
= &omap44xx_l4_per_hwmod
,
5325 .slave
= &omap44xx_mcspi1_hwmod
,
5327 .addr
= omap44xx_mcspi1_addrs
,
5328 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5331 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs
[] = {
5333 .pa_start
= 0x4809a000,
5334 .pa_end
= 0x4809a1ff,
5335 .flags
= ADDR_TYPE_RT
5340 /* l4_per -> mcspi2 */
5341 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2
= {
5342 .master
= &omap44xx_l4_per_hwmod
,
5343 .slave
= &omap44xx_mcspi2_hwmod
,
5345 .addr
= omap44xx_mcspi2_addrs
,
5346 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5349 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs
[] = {
5351 .pa_start
= 0x480b8000,
5352 .pa_end
= 0x480b81ff,
5353 .flags
= ADDR_TYPE_RT
5358 /* l4_per -> mcspi3 */
5359 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3
= {
5360 .master
= &omap44xx_l4_per_hwmod
,
5361 .slave
= &omap44xx_mcspi3_hwmod
,
5363 .addr
= omap44xx_mcspi3_addrs
,
5364 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5367 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs
[] = {
5369 .pa_start
= 0x480ba000,
5370 .pa_end
= 0x480ba1ff,
5371 .flags
= ADDR_TYPE_RT
5376 /* l4_per -> mcspi4 */
5377 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4
= {
5378 .master
= &omap44xx_l4_per_hwmod
,
5379 .slave
= &omap44xx_mcspi4_hwmod
,
5381 .addr
= omap44xx_mcspi4_addrs
,
5382 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5385 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs
[] = {
5387 .pa_start
= 0x4809c000,
5388 .pa_end
= 0x4809c3ff,
5389 .flags
= ADDR_TYPE_RT
5394 /* l4_per -> mmc1 */
5395 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1
= {
5396 .master
= &omap44xx_l4_per_hwmod
,
5397 .slave
= &omap44xx_mmc1_hwmod
,
5399 .addr
= omap44xx_mmc1_addrs
,
5400 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5403 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs
[] = {
5405 .pa_start
= 0x480b4000,
5406 .pa_end
= 0x480b43ff,
5407 .flags
= ADDR_TYPE_RT
5412 /* l4_per -> mmc2 */
5413 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2
= {
5414 .master
= &omap44xx_l4_per_hwmod
,
5415 .slave
= &omap44xx_mmc2_hwmod
,
5417 .addr
= omap44xx_mmc2_addrs
,
5418 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5421 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs
[] = {
5423 .pa_start
= 0x480ad000,
5424 .pa_end
= 0x480ad3ff,
5425 .flags
= ADDR_TYPE_RT
5430 /* l4_per -> mmc3 */
5431 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3
= {
5432 .master
= &omap44xx_l4_per_hwmod
,
5433 .slave
= &omap44xx_mmc3_hwmod
,
5435 .addr
= omap44xx_mmc3_addrs
,
5436 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5439 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs
[] = {
5441 .pa_start
= 0x480d1000,
5442 .pa_end
= 0x480d13ff,
5443 .flags
= ADDR_TYPE_RT
5448 /* l4_per -> mmc4 */
5449 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4
= {
5450 .master
= &omap44xx_l4_per_hwmod
,
5451 .slave
= &omap44xx_mmc4_hwmod
,
5453 .addr
= omap44xx_mmc4_addrs
,
5454 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5457 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs
[] = {
5459 .pa_start
= 0x480d5000,
5460 .pa_end
= 0x480d53ff,
5461 .flags
= ADDR_TYPE_RT
5466 /* l4_per -> mmc5 */
5467 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5
= {
5468 .master
= &omap44xx_l4_per_hwmod
,
5469 .slave
= &omap44xx_mmc5_hwmod
,
5471 .addr
= omap44xx_mmc5_addrs
,
5472 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5475 /* l3_main_2 -> ocmc_ram */
5476 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram
= {
5477 .master
= &omap44xx_l3_main_2_hwmod
,
5478 .slave
= &omap44xx_ocmc_ram_hwmod
,
5480 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5483 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs
[] = {
5485 .pa_start
= 0x4a0ad000,
5486 .pa_end
= 0x4a0ad01f,
5487 .flags
= ADDR_TYPE_RT
5492 /* l4_cfg -> ocp2scp_usb_phy */
5493 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy
= {
5494 .master
= &omap44xx_l4_cfg_hwmod
,
5495 .slave
= &omap44xx_ocp2scp_usb_phy_hwmod
,
5497 .addr
= omap44xx_ocp2scp_usb_phy_addrs
,
5498 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5501 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs
[] = {
5503 .pa_start
= 0x48243000,
5504 .pa_end
= 0x48243fff,
5505 .flags
= ADDR_TYPE_RT
5510 /* mpu_private -> prcm_mpu */
5511 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu
= {
5512 .master
= &omap44xx_mpu_private_hwmod
,
5513 .slave
= &omap44xx_prcm_mpu_hwmod
,
5515 .addr
= omap44xx_prcm_mpu_addrs
,
5516 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5519 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs
[] = {
5521 .pa_start
= 0x4a004000,
5522 .pa_end
= 0x4a004fff,
5523 .flags
= ADDR_TYPE_RT
5528 /* l4_wkup -> cm_core_aon */
5529 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon
= {
5530 .master
= &omap44xx_l4_wkup_hwmod
,
5531 .slave
= &omap44xx_cm_core_aon_hwmod
,
5532 .clk
= "l4_wkup_clk_mux_ck",
5533 .addr
= omap44xx_cm_core_aon_addrs
,
5534 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5537 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs
[] = {
5539 .pa_start
= 0x4a008000,
5540 .pa_end
= 0x4a009fff,
5541 .flags
= ADDR_TYPE_RT
5546 /* l4_cfg -> cm_core */
5547 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core
= {
5548 .master
= &omap44xx_l4_cfg_hwmod
,
5549 .slave
= &omap44xx_cm_core_hwmod
,
5551 .addr
= omap44xx_cm_core_addrs
,
5552 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5555 static struct omap_hwmod_addr_space omap44xx_prm_addrs
[] = {
5557 .pa_start
= 0x4a306000,
5558 .pa_end
= 0x4a307fff,
5559 .flags
= ADDR_TYPE_RT
5564 /* l4_wkup -> prm */
5565 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm
= {
5566 .master
= &omap44xx_l4_wkup_hwmod
,
5567 .slave
= &omap44xx_prm_hwmod
,
5568 .clk
= "l4_wkup_clk_mux_ck",
5569 .addr
= omap44xx_prm_addrs
,
5570 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5573 static struct omap_hwmod_addr_space omap44xx_scrm_addrs
[] = {
5575 .pa_start
= 0x4a30a000,
5576 .pa_end
= 0x4a30a7ff,
5577 .flags
= ADDR_TYPE_RT
5582 /* l4_wkup -> scrm */
5583 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm
= {
5584 .master
= &omap44xx_l4_wkup_hwmod
,
5585 .slave
= &omap44xx_scrm_hwmod
,
5586 .clk
= "l4_wkup_clk_mux_ck",
5587 .addr
= omap44xx_scrm_addrs
,
5588 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5591 /* l3_main_2 -> sl2if */
5592 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if
= {
5593 .master
= &omap44xx_l3_main_2_hwmod
,
5594 .slave
= &omap44xx_sl2if_hwmod
,
5596 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5599 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs
[] = {
5601 .pa_start
= 0x4012c000,
5602 .pa_end
= 0x4012c3ff,
5603 .flags
= ADDR_TYPE_RT
5608 /* l4_abe -> slimbus1 */
5609 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1
= {
5610 .master
= &omap44xx_l4_abe_hwmod
,
5611 .slave
= &omap44xx_slimbus1_hwmod
,
5612 .clk
= "ocp_abe_iclk",
5613 .addr
= omap44xx_slimbus1_addrs
,
5614 .user
= OCP_USER_MPU
,
5617 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs
[] = {
5619 .pa_start
= 0x4902c000,
5620 .pa_end
= 0x4902c3ff,
5621 .flags
= ADDR_TYPE_RT
5626 /* l4_abe -> slimbus1 (dma) */
5627 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma
= {
5628 .master
= &omap44xx_l4_abe_hwmod
,
5629 .slave
= &omap44xx_slimbus1_hwmod
,
5630 .clk
= "ocp_abe_iclk",
5631 .addr
= omap44xx_slimbus1_dma_addrs
,
5632 .user
= OCP_USER_SDMA
,
5635 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs
[] = {
5637 .pa_start
= 0x48076000,
5638 .pa_end
= 0x480763ff,
5639 .flags
= ADDR_TYPE_RT
5644 /* l4_per -> slimbus2 */
5645 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2
= {
5646 .master
= &omap44xx_l4_per_hwmod
,
5647 .slave
= &omap44xx_slimbus2_hwmod
,
5649 .addr
= omap44xx_slimbus2_addrs
,
5650 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5653 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs
[] = {
5655 .pa_start
= 0x4a0dd000,
5656 .pa_end
= 0x4a0dd03f,
5657 .flags
= ADDR_TYPE_RT
5662 /* l4_cfg -> smartreflex_core */
5663 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core
= {
5664 .master
= &omap44xx_l4_cfg_hwmod
,
5665 .slave
= &omap44xx_smartreflex_core_hwmod
,
5667 .addr
= omap44xx_smartreflex_core_addrs
,
5668 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5671 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs
[] = {
5673 .pa_start
= 0x4a0db000,
5674 .pa_end
= 0x4a0db03f,
5675 .flags
= ADDR_TYPE_RT
5680 /* l4_cfg -> smartreflex_iva */
5681 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva
= {
5682 .master
= &omap44xx_l4_cfg_hwmod
,
5683 .slave
= &omap44xx_smartreflex_iva_hwmod
,
5685 .addr
= omap44xx_smartreflex_iva_addrs
,
5686 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5689 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs
[] = {
5691 .pa_start
= 0x4a0d9000,
5692 .pa_end
= 0x4a0d903f,
5693 .flags
= ADDR_TYPE_RT
5698 /* l4_cfg -> smartreflex_mpu */
5699 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu
= {
5700 .master
= &omap44xx_l4_cfg_hwmod
,
5701 .slave
= &omap44xx_smartreflex_mpu_hwmod
,
5703 .addr
= omap44xx_smartreflex_mpu_addrs
,
5704 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5707 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs
[] = {
5709 .pa_start
= 0x4a0f6000,
5710 .pa_end
= 0x4a0f6fff,
5711 .flags
= ADDR_TYPE_RT
5716 /* l4_cfg -> spinlock */
5717 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock
= {
5718 .master
= &omap44xx_l4_cfg_hwmod
,
5719 .slave
= &omap44xx_spinlock_hwmod
,
5721 .addr
= omap44xx_spinlock_addrs
,
5722 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5725 static struct omap_hwmod_addr_space omap44xx_timer1_addrs
[] = {
5727 .pa_start
= 0x4a318000,
5728 .pa_end
= 0x4a31807f,
5729 .flags
= ADDR_TYPE_RT
5734 /* l4_wkup -> timer1 */
5735 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1
= {
5736 .master
= &omap44xx_l4_wkup_hwmod
,
5737 .slave
= &omap44xx_timer1_hwmod
,
5738 .clk
= "l4_wkup_clk_mux_ck",
5739 .addr
= omap44xx_timer1_addrs
,
5740 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5743 static struct omap_hwmod_addr_space omap44xx_timer2_addrs
[] = {
5745 .pa_start
= 0x48032000,
5746 .pa_end
= 0x4803207f,
5747 .flags
= ADDR_TYPE_RT
5752 /* l4_per -> timer2 */
5753 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2
= {
5754 .master
= &omap44xx_l4_per_hwmod
,
5755 .slave
= &omap44xx_timer2_hwmod
,
5757 .addr
= omap44xx_timer2_addrs
,
5758 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5761 static struct omap_hwmod_addr_space omap44xx_timer3_addrs
[] = {
5763 .pa_start
= 0x48034000,
5764 .pa_end
= 0x4803407f,
5765 .flags
= ADDR_TYPE_RT
5770 /* l4_per -> timer3 */
5771 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3
= {
5772 .master
= &omap44xx_l4_per_hwmod
,
5773 .slave
= &omap44xx_timer3_hwmod
,
5775 .addr
= omap44xx_timer3_addrs
,
5776 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5779 static struct omap_hwmod_addr_space omap44xx_timer4_addrs
[] = {
5781 .pa_start
= 0x48036000,
5782 .pa_end
= 0x4803607f,
5783 .flags
= ADDR_TYPE_RT
5788 /* l4_per -> timer4 */
5789 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4
= {
5790 .master
= &omap44xx_l4_per_hwmod
,
5791 .slave
= &omap44xx_timer4_hwmod
,
5793 .addr
= omap44xx_timer4_addrs
,
5794 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5797 static struct omap_hwmod_addr_space omap44xx_timer5_addrs
[] = {
5799 .pa_start
= 0x40138000,
5800 .pa_end
= 0x4013807f,
5801 .flags
= ADDR_TYPE_RT
5806 /* l4_abe -> timer5 */
5807 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5
= {
5808 .master
= &omap44xx_l4_abe_hwmod
,
5809 .slave
= &omap44xx_timer5_hwmod
,
5810 .clk
= "ocp_abe_iclk",
5811 .addr
= omap44xx_timer5_addrs
,
5812 .user
= OCP_USER_MPU
,
5815 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs
[] = {
5817 .pa_start
= 0x49038000,
5818 .pa_end
= 0x4903807f,
5819 .flags
= ADDR_TYPE_RT
5824 /* l4_abe -> timer5 (dma) */
5825 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma
= {
5826 .master
= &omap44xx_l4_abe_hwmod
,
5827 .slave
= &omap44xx_timer5_hwmod
,
5828 .clk
= "ocp_abe_iclk",
5829 .addr
= omap44xx_timer5_dma_addrs
,
5830 .user
= OCP_USER_SDMA
,
5833 static struct omap_hwmod_addr_space omap44xx_timer6_addrs
[] = {
5835 .pa_start
= 0x4013a000,
5836 .pa_end
= 0x4013a07f,
5837 .flags
= ADDR_TYPE_RT
5842 /* l4_abe -> timer6 */
5843 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6
= {
5844 .master
= &omap44xx_l4_abe_hwmod
,
5845 .slave
= &omap44xx_timer6_hwmod
,
5846 .clk
= "ocp_abe_iclk",
5847 .addr
= omap44xx_timer6_addrs
,
5848 .user
= OCP_USER_MPU
,
5851 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs
[] = {
5853 .pa_start
= 0x4903a000,
5854 .pa_end
= 0x4903a07f,
5855 .flags
= ADDR_TYPE_RT
5860 /* l4_abe -> timer6 (dma) */
5861 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma
= {
5862 .master
= &omap44xx_l4_abe_hwmod
,
5863 .slave
= &omap44xx_timer6_hwmod
,
5864 .clk
= "ocp_abe_iclk",
5865 .addr
= omap44xx_timer6_dma_addrs
,
5866 .user
= OCP_USER_SDMA
,
5869 static struct omap_hwmod_addr_space omap44xx_timer7_addrs
[] = {
5871 .pa_start
= 0x4013c000,
5872 .pa_end
= 0x4013c07f,
5873 .flags
= ADDR_TYPE_RT
5878 /* l4_abe -> timer7 */
5879 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7
= {
5880 .master
= &omap44xx_l4_abe_hwmod
,
5881 .slave
= &omap44xx_timer7_hwmod
,
5882 .clk
= "ocp_abe_iclk",
5883 .addr
= omap44xx_timer7_addrs
,
5884 .user
= OCP_USER_MPU
,
5887 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs
[] = {
5889 .pa_start
= 0x4903c000,
5890 .pa_end
= 0x4903c07f,
5891 .flags
= ADDR_TYPE_RT
5896 /* l4_abe -> timer7 (dma) */
5897 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma
= {
5898 .master
= &omap44xx_l4_abe_hwmod
,
5899 .slave
= &omap44xx_timer7_hwmod
,
5900 .clk
= "ocp_abe_iclk",
5901 .addr
= omap44xx_timer7_dma_addrs
,
5902 .user
= OCP_USER_SDMA
,
5905 static struct omap_hwmod_addr_space omap44xx_timer8_addrs
[] = {
5907 .pa_start
= 0x4013e000,
5908 .pa_end
= 0x4013e07f,
5909 .flags
= ADDR_TYPE_RT
5914 /* l4_abe -> timer8 */
5915 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8
= {
5916 .master
= &omap44xx_l4_abe_hwmod
,
5917 .slave
= &omap44xx_timer8_hwmod
,
5918 .clk
= "ocp_abe_iclk",
5919 .addr
= omap44xx_timer8_addrs
,
5920 .user
= OCP_USER_MPU
,
5923 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs
[] = {
5925 .pa_start
= 0x4903e000,
5926 .pa_end
= 0x4903e07f,
5927 .flags
= ADDR_TYPE_RT
5932 /* l4_abe -> timer8 (dma) */
5933 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma
= {
5934 .master
= &omap44xx_l4_abe_hwmod
,
5935 .slave
= &omap44xx_timer8_hwmod
,
5936 .clk
= "ocp_abe_iclk",
5937 .addr
= omap44xx_timer8_dma_addrs
,
5938 .user
= OCP_USER_SDMA
,
5941 static struct omap_hwmod_addr_space omap44xx_timer9_addrs
[] = {
5943 .pa_start
= 0x4803e000,
5944 .pa_end
= 0x4803e07f,
5945 .flags
= ADDR_TYPE_RT
5950 /* l4_per -> timer9 */
5951 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9
= {
5952 .master
= &omap44xx_l4_per_hwmod
,
5953 .slave
= &omap44xx_timer9_hwmod
,
5955 .addr
= omap44xx_timer9_addrs
,
5956 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5959 static struct omap_hwmod_addr_space omap44xx_timer10_addrs
[] = {
5961 .pa_start
= 0x48086000,
5962 .pa_end
= 0x4808607f,
5963 .flags
= ADDR_TYPE_RT
5968 /* l4_per -> timer10 */
5969 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10
= {
5970 .master
= &omap44xx_l4_per_hwmod
,
5971 .slave
= &omap44xx_timer10_hwmod
,
5973 .addr
= omap44xx_timer10_addrs
,
5974 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5977 static struct omap_hwmod_addr_space omap44xx_timer11_addrs
[] = {
5979 .pa_start
= 0x48088000,
5980 .pa_end
= 0x4808807f,
5981 .flags
= ADDR_TYPE_RT
5986 /* l4_per -> timer11 */
5987 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11
= {
5988 .master
= &omap44xx_l4_per_hwmod
,
5989 .slave
= &omap44xx_timer11_hwmod
,
5991 .addr
= omap44xx_timer11_addrs
,
5992 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5995 static struct omap_hwmod_addr_space omap44xx_uart1_addrs
[] = {
5997 .pa_start
= 0x4806a000,
5998 .pa_end
= 0x4806a0ff,
5999 .flags
= ADDR_TYPE_RT
6004 /* l4_per -> uart1 */
6005 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1
= {
6006 .master
= &omap44xx_l4_per_hwmod
,
6007 .slave
= &omap44xx_uart1_hwmod
,
6009 .addr
= omap44xx_uart1_addrs
,
6010 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6013 static struct omap_hwmod_addr_space omap44xx_uart2_addrs
[] = {
6015 .pa_start
= 0x4806c000,
6016 .pa_end
= 0x4806c0ff,
6017 .flags
= ADDR_TYPE_RT
6022 /* l4_per -> uart2 */
6023 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2
= {
6024 .master
= &omap44xx_l4_per_hwmod
,
6025 .slave
= &omap44xx_uart2_hwmod
,
6027 .addr
= omap44xx_uart2_addrs
,
6028 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6031 static struct omap_hwmod_addr_space omap44xx_uart3_addrs
[] = {
6033 .pa_start
= 0x48020000,
6034 .pa_end
= 0x480200ff,
6035 .flags
= ADDR_TYPE_RT
6040 /* l4_per -> uart3 */
6041 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3
= {
6042 .master
= &omap44xx_l4_per_hwmod
,
6043 .slave
= &omap44xx_uart3_hwmod
,
6045 .addr
= omap44xx_uart3_addrs
,
6046 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6049 static struct omap_hwmod_addr_space omap44xx_uart4_addrs
[] = {
6051 .pa_start
= 0x4806e000,
6052 .pa_end
= 0x4806e0ff,
6053 .flags
= ADDR_TYPE_RT
6058 /* l4_per -> uart4 */
6059 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4
= {
6060 .master
= &omap44xx_l4_per_hwmod
,
6061 .slave
= &omap44xx_uart4_hwmod
,
6063 .addr
= omap44xx_uart4_addrs
,
6064 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6067 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs
[] = {
6069 .pa_start
= 0x4a0a9000,
6070 .pa_end
= 0x4a0a93ff,
6071 .flags
= ADDR_TYPE_RT
6076 /* l4_cfg -> usb_host_fs */
6077 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs
= {
6078 .master
= &omap44xx_l4_cfg_hwmod
,
6079 .slave
= &omap44xx_usb_host_fs_hwmod
,
6081 .addr
= omap44xx_usb_host_fs_addrs
,
6082 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6085 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs
[] = {
6088 .pa_start
= 0x4a064000,
6089 .pa_end
= 0x4a0647ff,
6090 .flags
= ADDR_TYPE_RT
6094 .pa_start
= 0x4a064800,
6095 .pa_end
= 0x4a064bff,
6099 .pa_start
= 0x4a064c00,
6100 .pa_end
= 0x4a064fff,
6105 /* l4_cfg -> usb_host_hs */
6106 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs
= {
6107 .master
= &omap44xx_l4_cfg_hwmod
,
6108 .slave
= &omap44xx_usb_host_hs_hwmod
,
6110 .addr
= omap44xx_usb_host_hs_addrs
,
6111 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6114 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs
[] = {
6116 .pa_start
= 0x4a0ab000,
6117 .pa_end
= 0x4a0ab7ff,
6118 .flags
= ADDR_TYPE_RT
6121 /* XXX: Remove this once control module driver is in place */
6122 .pa_start
= 0x4a00233c,
6123 .pa_end
= 0x4a00233f,
6124 .flags
= ADDR_TYPE_RT
6129 /* l4_cfg -> usb_otg_hs */
6130 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs
= {
6131 .master
= &omap44xx_l4_cfg_hwmod
,
6132 .slave
= &omap44xx_usb_otg_hs_hwmod
,
6134 .addr
= omap44xx_usb_otg_hs_addrs
,
6135 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6138 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs
[] = {
6141 .pa_start
= 0x4a062000,
6142 .pa_end
= 0x4a063fff,
6143 .flags
= ADDR_TYPE_RT
6148 /* l4_cfg -> usb_tll_hs */
6149 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs
= {
6150 .master
= &omap44xx_l4_cfg_hwmod
,
6151 .slave
= &omap44xx_usb_tll_hs_hwmod
,
6153 .addr
= omap44xx_usb_tll_hs_addrs
,
6154 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6157 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs
[] = {
6159 .pa_start
= 0x4a314000,
6160 .pa_end
= 0x4a31407f,
6161 .flags
= ADDR_TYPE_RT
6166 /* l4_wkup -> wd_timer2 */
6167 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2
= {
6168 .master
= &omap44xx_l4_wkup_hwmod
,
6169 .slave
= &omap44xx_wd_timer2_hwmod
,
6170 .clk
= "l4_wkup_clk_mux_ck",
6171 .addr
= omap44xx_wd_timer2_addrs
,
6172 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6175 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs
[] = {
6177 .pa_start
= 0x40130000,
6178 .pa_end
= 0x4013007f,
6179 .flags
= ADDR_TYPE_RT
6184 /* l4_abe -> wd_timer3 */
6185 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3
= {
6186 .master
= &omap44xx_l4_abe_hwmod
,
6187 .slave
= &omap44xx_wd_timer3_hwmod
,
6188 .clk
= "ocp_abe_iclk",
6189 .addr
= omap44xx_wd_timer3_addrs
,
6190 .user
= OCP_USER_MPU
,
6193 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs
[] = {
6195 .pa_start
= 0x49030000,
6196 .pa_end
= 0x4903007f,
6197 .flags
= ADDR_TYPE_RT
6202 /* l4_abe -> wd_timer3 (dma) */
6203 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma
= {
6204 .master
= &omap44xx_l4_abe_hwmod
,
6205 .slave
= &omap44xx_wd_timer3_hwmod
,
6206 .clk
= "ocp_abe_iclk",
6207 .addr
= omap44xx_wd_timer3_dma_addrs
,
6208 .user
= OCP_USER_SDMA
,
6211 static struct omap_hwmod_ocp_if
*omap44xx_hwmod_ocp_ifs
[] __initdata
= {
6212 &omap44xx_c2c__c2c_target_fw
,
6213 &omap44xx_l4_cfg__c2c_target_fw
,
6214 &omap44xx_l3_main_1__dmm
,
6216 &omap44xx_c2c__emif_fw
,
6217 &omap44xx_dmm__emif_fw
,
6218 &omap44xx_l4_cfg__emif_fw
,
6219 &omap44xx_iva__l3_instr
,
6220 &omap44xx_l3_main_3__l3_instr
,
6221 &omap44xx_ocp_wp_noc__l3_instr
,
6222 &omap44xx_dsp__l3_main_1
,
6223 &omap44xx_dss__l3_main_1
,
6224 &omap44xx_l3_main_2__l3_main_1
,
6225 &omap44xx_l4_cfg__l3_main_1
,
6226 &omap44xx_mmc1__l3_main_1
,
6227 &omap44xx_mmc2__l3_main_1
,
6228 &omap44xx_mpu__l3_main_1
,
6229 &omap44xx_c2c_target_fw__l3_main_2
,
6230 &omap44xx_debugss__l3_main_2
,
6231 &omap44xx_dma_system__l3_main_2
,
6232 &omap44xx_fdif__l3_main_2
,
6233 &omap44xx_gpu__l3_main_2
,
6234 &omap44xx_hsi__l3_main_2
,
6235 &omap44xx_ipu__l3_main_2
,
6236 &omap44xx_iss__l3_main_2
,
6237 &omap44xx_iva__l3_main_2
,
6238 &omap44xx_l3_main_1__l3_main_2
,
6239 &omap44xx_l4_cfg__l3_main_2
,
6240 /* &omap44xx_usb_host_fs__l3_main_2, */
6241 &omap44xx_usb_host_hs__l3_main_2
,
6242 &omap44xx_usb_otg_hs__l3_main_2
,
6243 &omap44xx_l3_main_1__l3_main_3
,
6244 &omap44xx_l3_main_2__l3_main_3
,
6245 &omap44xx_l4_cfg__l3_main_3
,
6246 /* &omap44xx_aess__l4_abe, */
6247 &omap44xx_dsp__l4_abe
,
6248 &omap44xx_l3_main_1__l4_abe
,
6249 &omap44xx_mpu__l4_abe
,
6250 &omap44xx_l3_main_1__l4_cfg
,
6251 &omap44xx_l3_main_2__l4_per
,
6252 &omap44xx_l4_cfg__l4_wkup
,
6253 &omap44xx_mpu__mpu_private
,
6254 &omap44xx_l4_cfg__ocp_wp_noc
,
6255 /* &omap44xx_l4_abe__aess, */
6256 /* &omap44xx_l4_abe__aess_dma, */
6257 &omap44xx_l3_main_2__c2c
,
6258 &omap44xx_l4_wkup__counter_32k
,
6259 &omap44xx_l4_cfg__ctrl_module_core
,
6260 &omap44xx_l4_cfg__ctrl_module_pad_core
,
6261 &omap44xx_l4_wkup__ctrl_module_wkup
,
6262 &omap44xx_l4_wkup__ctrl_module_pad_wkup
,
6263 &omap44xx_l3_instr__debugss
,
6264 &omap44xx_l4_cfg__dma_system
,
6265 &omap44xx_l4_abe__dmic
,
6266 &omap44xx_l4_abe__dmic_dma
,
6268 /* &omap44xx_dsp__sl2if, */
6269 &omap44xx_l4_cfg__dsp
,
6270 &omap44xx_l3_main_2__dss
,
6271 &omap44xx_l4_per__dss
,
6272 &omap44xx_l3_main_2__dss_dispc
,
6273 &omap44xx_l4_per__dss_dispc
,
6274 &omap44xx_l3_main_2__dss_dsi1
,
6275 &omap44xx_l4_per__dss_dsi1
,
6276 &omap44xx_l3_main_2__dss_dsi2
,
6277 &omap44xx_l4_per__dss_dsi2
,
6278 &omap44xx_l3_main_2__dss_hdmi
,
6279 &omap44xx_l4_per__dss_hdmi
,
6280 &omap44xx_l3_main_2__dss_rfbi
,
6281 &omap44xx_l4_per__dss_rfbi
,
6282 &omap44xx_l3_main_2__dss_venc
,
6283 &omap44xx_l4_per__dss_venc
,
6284 &omap44xx_l4_per__elm
,
6285 &omap44xx_emif_fw__emif1
,
6286 &omap44xx_emif_fw__emif2
,
6287 &omap44xx_l4_cfg__fdif
,
6288 &omap44xx_l4_wkup__gpio1
,
6289 &omap44xx_l4_per__gpio2
,
6290 &omap44xx_l4_per__gpio3
,
6291 &omap44xx_l4_per__gpio4
,
6292 &omap44xx_l4_per__gpio5
,
6293 &omap44xx_l4_per__gpio6
,
6294 &omap44xx_l3_main_2__gpmc
,
6295 &omap44xx_l3_main_2__gpu
,
6296 &omap44xx_l4_per__hdq1w
,
6297 &omap44xx_l4_cfg__hsi
,
6298 &omap44xx_l4_per__i2c1
,
6299 &omap44xx_l4_per__i2c2
,
6300 &omap44xx_l4_per__i2c3
,
6301 &omap44xx_l4_per__i2c4
,
6302 &omap44xx_l3_main_2__ipu
,
6303 &omap44xx_l3_main_2__iss
,
6304 /* &omap44xx_iva__sl2if, */
6305 &omap44xx_l3_main_2__iva
,
6306 &omap44xx_l4_wkup__kbd
,
6307 &omap44xx_l4_cfg__mailbox
,
6308 &omap44xx_l4_abe__mcasp
,
6309 &omap44xx_l4_abe__mcasp_dma
,
6310 &omap44xx_l4_abe__mcbsp1
,
6311 &omap44xx_l4_abe__mcbsp1_dma
,
6312 &omap44xx_l4_abe__mcbsp2
,
6313 &omap44xx_l4_abe__mcbsp2_dma
,
6314 &omap44xx_l4_abe__mcbsp3
,
6315 &omap44xx_l4_abe__mcbsp3_dma
,
6316 &omap44xx_l4_per__mcbsp4
,
6317 &omap44xx_l4_abe__mcpdm
,
6318 &omap44xx_l4_abe__mcpdm_dma
,
6319 &omap44xx_l4_per__mcspi1
,
6320 &omap44xx_l4_per__mcspi2
,
6321 &omap44xx_l4_per__mcspi3
,
6322 &omap44xx_l4_per__mcspi4
,
6323 &omap44xx_l4_per__mmc1
,
6324 &omap44xx_l4_per__mmc2
,
6325 &omap44xx_l4_per__mmc3
,
6326 &omap44xx_l4_per__mmc4
,
6327 &omap44xx_l4_per__mmc5
,
6328 &omap44xx_l3_main_2__mmu_ipu
,
6329 &omap44xx_l4_cfg__mmu_dsp
,
6330 &omap44xx_l3_main_2__ocmc_ram
,
6331 &omap44xx_l4_cfg__ocp2scp_usb_phy
,
6332 &omap44xx_mpu_private__prcm_mpu
,
6333 &omap44xx_l4_wkup__cm_core_aon
,
6334 &omap44xx_l4_cfg__cm_core
,
6335 &omap44xx_l4_wkup__prm
,
6336 &omap44xx_l4_wkup__scrm
,
6337 /* &omap44xx_l3_main_2__sl2if, */
6338 &omap44xx_l4_abe__slimbus1
,
6339 &omap44xx_l4_abe__slimbus1_dma
,
6340 &omap44xx_l4_per__slimbus2
,
6341 &omap44xx_l4_cfg__smartreflex_core
,
6342 &omap44xx_l4_cfg__smartreflex_iva
,
6343 &omap44xx_l4_cfg__smartreflex_mpu
,
6344 &omap44xx_l4_cfg__spinlock
,
6345 &omap44xx_l4_wkup__timer1
,
6346 &omap44xx_l4_per__timer2
,
6347 &omap44xx_l4_per__timer3
,
6348 &omap44xx_l4_per__timer4
,
6349 &omap44xx_l4_abe__timer5
,
6350 &omap44xx_l4_abe__timer5_dma
,
6351 &omap44xx_l4_abe__timer6
,
6352 &omap44xx_l4_abe__timer6_dma
,
6353 &omap44xx_l4_abe__timer7
,
6354 &omap44xx_l4_abe__timer7_dma
,
6355 &omap44xx_l4_abe__timer8
,
6356 &omap44xx_l4_abe__timer8_dma
,
6357 &omap44xx_l4_per__timer9
,
6358 &omap44xx_l4_per__timer10
,
6359 &omap44xx_l4_per__timer11
,
6360 &omap44xx_l4_per__uart1
,
6361 &omap44xx_l4_per__uart2
,
6362 &omap44xx_l4_per__uart3
,
6363 &omap44xx_l4_per__uart4
,
6364 /* &omap44xx_l4_cfg__usb_host_fs, */
6365 &omap44xx_l4_cfg__usb_host_hs
,
6366 &omap44xx_l4_cfg__usb_otg_hs
,
6367 &omap44xx_l4_cfg__usb_tll_hs
,
6368 &omap44xx_l4_wkup__wd_timer2
,
6369 &omap44xx_l4_abe__wd_timer3
,
6370 &omap44xx_l4_abe__wd_timer3_dma
,
6374 int __init
omap44xx_hwmod_init(void)
6377 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs
);