include/asm-i386/mach-summit/mach_apic.h

   1 #ifndef __ASM_MACH_APIC_H
   2 #define __ASM_MACH_APIC_H
   3
   4 #include <asm/smp.h>
   5
   6 #define esr_disable (1)
   7 #define NO_BALANCE_IRQ (0)
   8
   9 /* In clustered mode, the high nibble of APIC ID is a cluster number.
  10  * The low nibble is a 4-bit bitmap. */
  11 #define XAPIC_DEST_CPUS_SHIFT   4
  12 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
  13 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
  14
  15 #define APIC_DFR_VALUE  (APIC_DFR_CLUSTER)
  16
  17 static inline cpumask_t target_cpus(void)
  18 {
  19         /* CPU_MASK_ALL (0xff) has undefined behaviour with
  20          * dest_LowestPrio mode logical clustered apic interrupt routing
  21          * Just start on cpu 0.  IRQ balancing will spread load
  22          */
  23         return cpumask_of_cpu(0);
  24 }
  25 #define TARGET_CPUS     (target_cpus())
  26
  27 #define INT_DELIVERY_MODE (dest_LowestPrio)
  28 #define INT_DEST_MODE 1     /* logical delivery broadcast to all procs */
  29
  30 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
  31 {
  32         return 0;
  33 }
  34
  35 /* we don't use the phys_cpu_present_map to indicate apicid presence */
  36 static inline unsigned long check_apicid_present(int bit)
  37 {
  38         return 1;
  39 }
  40
  41 #define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
  42
  43 extern u8 bios_cpu_apicid[];
  44 extern u8 cpu_2_logical_apicid[];
  45
  46 static inline void init_apic_ldr(void)
  47 {
  48         unsigned long val, id;
  49         int i, count;
  50         u8 lid;
  51         u8 my_id = (u8)hard_smp_processor_id();
  52         u8 my_cluster = (u8)apicid_cluster(my_id);
  53
  54         /* Create logical APIC IDs by counting CPUs already in cluster. */
  55         for (count = 0, i = NR_CPUS; --i >= 0; ) {
  56                 lid = cpu_2_logical_apicid[i];
  57                 if (lid != BAD_APICID && apicid_cluster(lid) == my_cluster)
  58                         ++count;
  59         }
  60         /* We only have a 4 wide bitmap in cluster mode.  If a deranged
  61          * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
  62         BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
  63         id = my_cluster | (1UL << count);
  64         apic_write_around(APIC_DFR, APIC_DFR_VALUE);
  65         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  66         val |= SET_APIC_LOGICAL_ID(id);
  67         apic_write_around(APIC_LDR, val);
  68 }
  69
  70 static inline int multi_timer_check(int apic, int irq)
  71 {
  72         return 0;
  73 }
  74
  75 static inline int apic_id_registered(void)
  76 {
  77         return 1;
  78 }
  79
  80 static inline void clustered_apic_check(void)
  81 {
  82         printk("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
  83                                                 nr_ioapics);
  84 }
  85
  86 static inline int apicid_to_node(int logical_apicid)
  87 {
  88         return logical_apicid >> 5;          /* 2 clusterids per CEC */
  89 }
  90
  91 /* Mapping from cpu number to logical apicid */
  92 static inline int cpu_to_logical_apicid(int cpu)
  93 {
  94        if (cpu >= NR_CPUS)
  95                return BAD_APICID;
  96         return (int)cpu_2_logical_apicid[cpu];
  97 }
  98
  99 static inline int cpu_present_to_apicid(int mps_cpu)
 100 {
 101         if (mps_cpu < NR_CPUS)
 102                 return (int)bios_cpu_apicid[mps_cpu];
 103         else
 104                 return BAD_APICID;
 105 }
 106
 107 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
 108 {
 109         /* For clustered we don't have a good way to do this yet - hack */
 110         return physids_promote(0x0F);
 111 }
 112
 113 static inline physid_mask_t apicid_to_cpu_present(int apicid)
 114 {
 115         return physid_mask_of_physid(0);
 116 }
 117
 118 static inline int mpc_apic_id(struct mpc_config_processor *m,
 119                         struct mpc_config_translation *translation_record)
 120 {
 121         printk("Processor #%d %ld:%ld APIC version %d\n",
 122                         m->mpc_apicid,
 123                         (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
 124                         (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
 125                         m->mpc_apicver);
 126         return (m->mpc_apicid);
 127 }
 128
 129 static inline void setup_portio_remap(void)
 130 {
 131 }
 132
 133 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
 134 {
 135         return 1;
 136 }
 137
 138 static inline void enable_apic_mode(void)
 139 {
 140 }
 141
 142 static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
 143 {
 144         int num_bits_set;
 145         int cpus_found = 0;
 146         int cpu;
 147         int apicid;
 148
 149         num_bits_set = cpus_weight(cpumask);
 150         /* Return id to all */
 151         if (num_bits_set == NR_CPUS)
 152                 return (int) 0xFF;
 153         /*
 154          * The cpus in the mask must all be on the apic cluster.  If are not
 155          * on the same apicid cluster return default value of TARGET_CPUS.
 156          */
 157         cpu = first_cpu(cpumask);
 158         apicid = cpu_to_logical_apicid(cpu);
 159         while (cpus_found < num_bits_set) {
 160                 if (cpu_isset(cpu, cpumask)) {
 161                         int new_apicid = cpu_to_logical_apicid(cpu);
 162                         if (apicid_cluster(apicid) !=
 163                                         apicid_cluster(new_apicid)){
 164                                 printk ("%s: Not a valid mask!\n",__FUNCTION__);
 165                                 return 0xFF;
 166                         }
 167                         apicid = apicid | new_apicid;
 168                         cpus_found++;
 169                 }
 170                 cpu++;
 171         }
 172         return apicid;
 173 }
 174
 175 /* cpuid returns the value latched in the HW at reset, not the APIC ID
 176  * register's value.  For any box whose BIOS changes APIC IDs, like
 177  * clustered APIC systems, we must use hard_smp_processor_id.
 178  *
 179  * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
 180  */
 181 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
 182 {
 183         return hard_smp_processor_id() >> index_msb;
 184 }
 185
 186 #endif /* __ASM_MACH_APIC_H */