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drm/exynos: fix types for compilation on 64bit architectures
[linux-2.6/btrfs-unstable.git] / include / linux / mlx4 / device.h
blob430a929f048b3d2f27d1e842f45e80f9e9e6347a
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
42
43 #include <linux/atomic.h>
44
45 #include <linux/timecounter.h>
46
47 #define MAX_MSIX_P_PORT 17
48 #define MAX_MSIX 64
49 #define MIN_MSIX_P_PORT 5
50 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
51 (dev_cap).num_ports * MIN_MSIX_P_PORT)
52
53 #define MLX4_MAX_100M_UNITS_VAL 255 /*
54 * work around: can't set values
55 * greater then this value when
56 * using 100 Mbps units.
57 */
58 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
59 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
60 #define MLX4_RATELIMIT_DEFAULT 0x00ff
61
62 #define MLX4_ROCE_MAX_GIDS 128
63 #define MLX4_ROCE_PF_GIDS 16
64
65 enum {
66 MLX4_FLAG_MSI_X = 1 << 0,
67 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
68 MLX4_FLAG_MASTER = 1 << 2,
69 MLX4_FLAG_SLAVE = 1 << 3,
70 MLX4_FLAG_SRIOV = 1 << 4,
71 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
72 MLX4_FLAG_BONDED = 1 << 7
73 };
74
75 enum {
76 MLX4_PORT_CAP_IS_SM = 1 << 1,
77 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
78 };
79
80 enum {
81 MLX4_MAX_PORTS = 2,
82 MLX4_MAX_PORT_PKEYS = 128,
83 MLX4_MAX_PORT_GIDS = 128
84 };
85
86 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
87 * These qkeys must not be allowed for general use. This is a 64k range,
88 * and to test for violation, we use the mask (protect against future chg).
89 */
90 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
91 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
92
93 enum {
94 MLX4_BOARD_ID_LEN = 64
95 };
96
97 enum {
98 MLX4_MAX_NUM_PF = 16,
99 MLX4_MAX_NUM_VF = 126,
100 MLX4_MAX_NUM_VF_P_PORT = 64,
101 MLX4_MFUNC_MAX = 128,
102 MLX4_MAX_EQ_NUM = 1024,
103 MLX4_MFUNC_EQ_NUM = 4,
104 MLX4_MFUNC_MAX_EQES = 8,
105 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
106 };
107
108 /* Driver supports 3 diffrent device methods to manage traffic steering:
109 * -device managed - High level API for ib and eth flow steering. FW is
110 * managing flow steering tables.
111 * - B0 steering mode - Common low level API for ib and (if supported) eth.
112 * - A0 steering mode - Limited low level API for eth. In case of IB,
113 * B0 mode is in use.
114 */
115 enum {
116 MLX4_STEERING_MODE_A0,
117 MLX4_STEERING_MODE_B0,
118 MLX4_STEERING_MODE_DEVICE_MANAGED
119 };
120
121 enum {
122 MLX4_STEERING_DMFS_A0_DEFAULT,
123 MLX4_STEERING_DMFS_A0_DYNAMIC,
124 MLX4_STEERING_DMFS_A0_STATIC,
125 MLX4_STEERING_DMFS_A0_DISABLE,
126 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
127 };
128
129 static inline const char *mlx4_steering_mode_str(int steering_mode)
130 {
131 switch (steering_mode) {
132 case MLX4_STEERING_MODE_A0:
133 return "A0 steering";
134
135 case MLX4_STEERING_MODE_B0:
136 return "B0 steering";
137
138 case MLX4_STEERING_MODE_DEVICE_MANAGED:
139 return "Device managed flow steering";
140
141 default:
142 return "Unrecognize steering mode";
143 }
144 }
145
146 enum {
147 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
148 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
149 };
150
151 enum {
152 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
153 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
154 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
155 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
156 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
157 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
158 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
159 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
160 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
161 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
162 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
163 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
164 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
165 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
166 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
167 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
168 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
169 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
170 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
171 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
172 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
173 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
174 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
175 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
176 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
177 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
178 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
179 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
180 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
181 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
182 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
183 };
184
185 enum {
186 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
187 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
188 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
189 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
190 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
191 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
192 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
193 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
194 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
195 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
196 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
197 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
198 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
199 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
200 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
201 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
202 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
203 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
204 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
205 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
206 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
207 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
208 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
209 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
210 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24,
211 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25,
212 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26,
213 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27,
214 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28,
215 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29,
216 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30,
217 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
218 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32,
219 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33,
220 };
221
222 enum {
223 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
224 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
225 };
226
227 enum {
228 MLX4_VF_CAP_FLAG_RESET = 1 << 0
229 };
230
231 /* bit enums for an 8-bit flags field indicating special use
232 * QPs which require special handling in qp_reserve_range.
233 * Currently, this only includes QPs used by the ETH interface,
234 * where we expect to use blueflame. These QPs must not have
235 * bits 6 and 7 set in their qp number.
236 *
237 * This enum may use only bits 0..7.
238 */
239 enum {
240 MLX4_RESERVE_A0_QP = 1 << 6,
241 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
242 };
243
244 enum {
245 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
246 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
247 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
248 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
249 };
250
251 enum {
252 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
253 };
254
255 enum {
256 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
257 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
258 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
259 };
260
261
262 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
263
264 enum {
265 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
266 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
267 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
268 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
269 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
270 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
271 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19,
272 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
273 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
274 };
275
276 enum {
277 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP,
278 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2
279 };
280
281 enum mlx4_event {
282 MLX4_EVENT_TYPE_COMP = 0x00,
283 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
284 MLX4_EVENT_TYPE_COMM_EST = 0x02,
285 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
286 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
287 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
288 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
289 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
290 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
291 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
292 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
293 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
294 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
295 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
296 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
297 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
298 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
299 MLX4_EVENT_TYPE_CMD = 0x0a,
300 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
301 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
302 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
303 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
304 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
305 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
306 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
307 MLX4_EVENT_TYPE_NONE = 0xff,
308 };
309
310 enum {
311 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
312 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
313 };
314
315 enum {
316 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
317 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
318 };
319
320 enum {
321 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
322 };
323
324 enum slave_port_state {
325 SLAVE_PORT_DOWN = 0,
326 SLAVE_PENDING_UP,
327 SLAVE_PORT_UP,
328 };
329
330 enum slave_port_gen_event {
331 SLAVE_PORT_GEN_EVENT_DOWN = 0,
332 SLAVE_PORT_GEN_EVENT_UP,
333 SLAVE_PORT_GEN_EVENT_NONE,
334 };
335
336 enum slave_port_state_event {
337 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
338 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
339 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
340 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
341 };
342
343 enum {
344 MLX4_PERM_LOCAL_READ = 1 << 10,
345 MLX4_PERM_LOCAL_WRITE = 1 << 11,
346 MLX4_PERM_REMOTE_READ = 1 << 12,
347 MLX4_PERM_REMOTE_WRITE = 1 << 13,
348 MLX4_PERM_ATOMIC = 1 << 14,
349 MLX4_PERM_BIND_MW = 1 << 15,
350 MLX4_PERM_MASK = 0xFC00
351 };
352
353 enum {
354 MLX4_OPCODE_NOP = 0x00,
355 MLX4_OPCODE_SEND_INVAL = 0x01,
356 MLX4_OPCODE_RDMA_WRITE = 0x08,
357 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
358 MLX4_OPCODE_SEND = 0x0a,
359 MLX4_OPCODE_SEND_IMM = 0x0b,
360 MLX4_OPCODE_LSO = 0x0e,
361 MLX4_OPCODE_RDMA_READ = 0x10,
362 MLX4_OPCODE_ATOMIC_CS = 0x11,
363 MLX4_OPCODE_ATOMIC_FA = 0x12,
364 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
365 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
366 MLX4_OPCODE_BIND_MW = 0x18,
367 MLX4_OPCODE_FMR = 0x19,
368 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
369 MLX4_OPCODE_CONFIG_CMD = 0x1f,
370
371 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
372 MLX4_RECV_OPCODE_SEND = 0x01,
373 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
374 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
375
376 MLX4_CQE_OPCODE_ERROR = 0x1e,
377 MLX4_CQE_OPCODE_RESIZE = 0x16,
378 };
379
380 enum {
381 MLX4_STAT_RATE_OFFSET = 5
382 };
383
384 enum mlx4_protocol {
385 MLX4_PROT_IB_IPV6 = 0,
386 MLX4_PROT_ETH,
387 MLX4_PROT_IB_IPV4,
388 MLX4_PROT_FCOE
389 };
390
391 enum {
392 MLX4_MTT_FLAG_PRESENT = 1
393 };
394
395 enum mlx4_qp_region {
396 MLX4_QP_REGION_FW = 0,
397 MLX4_QP_REGION_RSS_RAW_ETH,
398 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
399 MLX4_QP_REGION_ETH_ADDR,
400 MLX4_QP_REGION_FC_ADDR,
401 MLX4_QP_REGION_FC_EXCH,
402 MLX4_NUM_QP_REGION
403 };
404
405 enum mlx4_port_type {
406 MLX4_PORT_TYPE_NONE = 0,
407 MLX4_PORT_TYPE_IB = 1,
408 MLX4_PORT_TYPE_ETH = 2,
409 MLX4_PORT_TYPE_AUTO = 3
410 };
411
412 enum mlx4_special_vlan_idx {
413 MLX4_NO_VLAN_IDX = 0,
414 MLX4_VLAN_MISS_IDX,
415 MLX4_VLAN_REGULAR
416 };
417
418 enum mlx4_steer_type {
419 MLX4_MC_STEER = 0,
420 MLX4_UC_STEER,
421 MLX4_NUM_STEERS
422 };
423
424 enum {
425 MLX4_NUM_FEXCH = 64 * 1024,
426 };
427
428 enum {
429 MLX4_MAX_FAST_REG_PAGES = 511,
430 };
431
432 enum {
433 /*
434 * Max wqe size for rdma read is 512 bytes, so this
435 * limits our max_sge_rd as the wqe needs to fit:
436 * - ctrl segment (16 bytes)
437 * - rdma segment (16 bytes)
438 * - scatter elements (16 bytes each)
439 */
440 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16
441 };
442
443 enum {
444 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
445 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
446 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
447 };
448
449 /* Port mgmt change event handling */
450 enum {
451 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
452 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
453 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
454 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
455 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
456 };
457
458 enum {
459 MLX4_DEVICE_STATE_UP = 1 << 0,
460 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
461 };
462
463 enum {
464 MLX4_INTERFACE_STATE_UP = 1 << 0,
465 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
466 };
467
468 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
469 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
470
471 enum mlx4_module_id {
472 MLX4_MODULE_ID_SFP = 0x3,
473 MLX4_MODULE_ID_QSFP = 0xC,
474 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
475 MLX4_MODULE_ID_QSFP28 = 0x11,
476 };
477
478 enum { /* rl */
479 MLX4_QP_RATE_LIMIT_NONE = 0,
480 MLX4_QP_RATE_LIMIT_KBS = 1,
481 MLX4_QP_RATE_LIMIT_MBS = 2,
482 MLX4_QP_RATE_LIMIT_GBS = 3
483 };
484
485 struct mlx4_rate_limit_caps {
486 u16 num_rates; /* Number of different rates */
487 u8 min_unit;
488 u16 min_val;
489 u8 max_unit;
490 u16 max_val;
491 };
492
493 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
494 {
495 return (major << 32) | (minor << 16) | subminor;
496 }
497
498 struct mlx4_phys_caps {
499 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
500 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
501 u32 num_phys_eqs;
502 u32 base_sqpn;
503 u32 base_proxy_sqpn;
504 u32 base_tunnel_sqpn;
505 };
506
507 struct mlx4_caps {
508 u64 fw_ver;
509 u32 function;
510 int num_ports;
511 int vl_cap[MLX4_MAX_PORTS + 1];
512 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
513 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
514 u64 def_mac[MLX4_MAX_PORTS + 1];
515 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
516 int gid_table_len[MLX4_MAX_PORTS + 1];
517 int pkey_table_len[MLX4_MAX_PORTS + 1];
518 int trans_type[MLX4_MAX_PORTS + 1];
519 int vendor_oui[MLX4_MAX_PORTS + 1];
520 int wavelength[MLX4_MAX_PORTS + 1];
521 u64 trans_code[MLX4_MAX_PORTS + 1];
522 int local_ca_ack_delay;
523 int num_uars;
524 u32 uar_page_size;
525 int bf_reg_size;
526 int bf_regs_per_page;
527 int max_sq_sg;
528 int max_rq_sg;
529 int num_qps;
530 int max_wqes;
531 int max_sq_desc_sz;
532 int max_rq_desc_sz;
533 int max_qp_init_rdma;
534 int max_qp_dest_rdma;
535 u32 *qp0_qkey;
536 u32 *qp0_proxy;
537 u32 *qp1_proxy;
538 u32 *qp0_tunnel;
539 u32 *qp1_tunnel;
540 int num_srqs;
541 int max_srq_wqes;
542 int max_srq_sge;
543 int reserved_srqs;
544 int num_cqs;
545 int max_cqes;
546 int reserved_cqs;
547 int num_sys_eqs;
548 int num_eqs;
549 int reserved_eqs;
550 int num_comp_vectors;
551 int num_mpts;
552 int max_fmr_maps;
553 int num_mtts;
554 int fmr_reserved_mtts;
555 int reserved_mtts;
556 int reserved_mrws;
557 int reserved_uars;
558 int num_mgms;
559 int num_amgms;
560 int reserved_mcgs;
561 int num_qp_per_mgm;
562 int steering_mode;
563 int dmfs_high_steer_mode;
564 int fs_log_max_ucast_qp_range_size;
565 int num_pds;
566 int reserved_pds;
567 int max_xrcds;
568 int reserved_xrcds;
569 int mtt_entry_sz;
570 u32 max_msg_sz;
571 u32 page_size_cap;
572 u64 flags;
573 u64 flags2;
574 u32 bmme_flags;
575 u32 reserved_lkey;
576 u16 stat_rate_support;
577 u8 port_width_cap[MLX4_MAX_PORTS + 1];
578 int max_gso_sz;
579 int max_rss_tbl_sz;
580 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
581 int reserved_qps;
582 int reserved_qps_base[MLX4_NUM_QP_REGION];
583 int log_num_macs;
584 int log_num_vlans;
585 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
586 u8 supported_type[MLX4_MAX_PORTS + 1];
587 u8 suggested_type[MLX4_MAX_PORTS + 1];
588 u8 default_sense[MLX4_MAX_PORTS + 1];
589 u32 port_mask[MLX4_MAX_PORTS + 1];
590 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
591 u32 max_counters;
592 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
593 u16 sqp_demux;
594 u32 eqe_size;
595 u32 cqe_size;
596 u8 eqe_factor;
597 u32 userspace_caps; /* userspace must be aware of these */
598 u32 function_caps; /* VFs must be aware of these */
599 u16 hca_core_clock;
600 u64 phys_port_id[MLX4_MAX_PORTS + 1];
601 int tunnel_offload_mode;
602 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
603 u8 phv_bit[MLX4_MAX_PORTS + 1];
604 u8 alloc_res_qp_mask;
605 u32 dmfs_high_rate_qpn_base;
606 u32 dmfs_high_rate_qpn_range;
607 u32 vf_caps;
608 struct mlx4_rate_limit_caps rl_caps;
609 };
610
611 struct mlx4_buf_list {
612 void *buf;
613 dma_addr_t map;
614 };
615
616 struct mlx4_buf {
617 struct mlx4_buf_list direct;
618 struct mlx4_buf_list *page_list;
619 int nbufs;
620 int npages;
621 int page_shift;
622 };
623
624 struct mlx4_mtt {
625 u32 offset;
626 int order;
627 int page_shift;
628 };
629
630 enum {
631 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
632 };
633
634 struct mlx4_db_pgdir {
635 struct list_head list;
636 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
637 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
638 unsigned long *bits[2];
639 __be32 *db_page;
640 dma_addr_t db_dma;
641 };
642
643 struct mlx4_ib_user_db_page;
644
645 struct mlx4_db {
646 __be32 *db;
647 union {
648 struct mlx4_db_pgdir *pgdir;
649 struct mlx4_ib_user_db_page *user_page;
650 } u;
651 dma_addr_t dma;
652 int index;
653 int order;
654 };
655
656 struct mlx4_hwq_resources {
657 struct mlx4_db db;
658 struct mlx4_mtt mtt;
659 struct mlx4_buf buf;
660 };
661
662 struct mlx4_mr {
663 struct mlx4_mtt mtt;
664 u64 iova;
665 u64 size;
666 u32 key;
667 u32 pd;
668 u32 access;
669 int enabled;
670 };
671
672 enum mlx4_mw_type {
673 MLX4_MW_TYPE_1 = 1,
674 MLX4_MW_TYPE_2 = 2,
675 };
676
677 struct mlx4_mw {
678 u32 key;
679 u32 pd;
680 enum mlx4_mw_type type;
681 int enabled;
682 };
683
684 struct mlx4_fmr {
685 struct mlx4_mr mr;
686 struct mlx4_mpt_entry *mpt;
687 __be64 *mtts;
688 dma_addr_t dma_handle;
689 int max_pages;
690 int max_maps;
691 int maps;
692 u8 page_shift;
693 };
694
695 struct mlx4_uar {
696 unsigned long pfn;
697 int index;
698 struct list_head bf_list;
699 unsigned free_bf_bmap;
700 void __iomem *map;
701 void __iomem *bf_map;
702 };
703
704 struct mlx4_bf {
705 unsigned int offset;
706 int buf_size;
707 struct mlx4_uar *uar;
708 void __iomem *reg;
709 };
710
711 struct mlx4_cq {
712 void (*comp) (struct mlx4_cq *);
713 void (*event) (struct mlx4_cq *, enum mlx4_event);
714
715 struct mlx4_uar *uar;
716
717 u32 cons_index;
718
719 u16 irq;
720 __be32 *set_ci_db;
721 __be32 *arm_db;
722 int arm_sn;
723
724 int cqn;
725 unsigned vector;
726
727 atomic_t refcount;
728 struct completion free;
729 struct {
730 struct list_head list;
731 void (*comp)(struct mlx4_cq *);
732 void *priv;
733 } tasklet_ctx;
734 int reset_notify_added;
735 struct list_head reset_notify;
736 };
737
738 struct mlx4_qp {
739 void (*event) (struct mlx4_qp *, enum mlx4_event);
740
741 int qpn;
742
743 atomic_t refcount;
744 struct completion free;
745 };
746
747 struct mlx4_srq {
748 void (*event) (struct mlx4_srq *, enum mlx4_event);
749
750 int srqn;
751 int max;
752 int max_gs;
753 int wqe_shift;
754
755 atomic_t refcount;
756 struct completion free;
757 };
758
759 struct mlx4_av {
760 __be32 port_pd;
761 u8 reserved1;
762 u8 g_slid;
763 __be16 dlid;
764 u8 reserved2;
765 u8 gid_index;
766 u8 stat_rate;
767 u8 hop_limit;
768 __be32 sl_tclass_flowlabel;
769 u8 dgid[16];
770 };
771
772 struct mlx4_eth_av {
773 __be32 port_pd;
774 u8 reserved1;
775 u8 smac_idx;
776 u16 reserved2;
777 u8 reserved3;
778 u8 gid_index;
779 u8 stat_rate;
780 u8 hop_limit;
781 __be32 sl_tclass_flowlabel;
782 u8 dgid[16];
783 u8 s_mac[6];
784 u8 reserved4[2];
785 __be16 vlan;
786 u8 mac[ETH_ALEN];
787 };
788
789 union mlx4_ext_av {
790 struct mlx4_av ib;
791 struct mlx4_eth_av eth;
792 };
793
794 /* Counters should be saturate once they reach their maximum value */
795 #define ASSIGN_32BIT_COUNTER(counter, value) do { \
796 if ((value) > U32_MAX) \
797 counter = cpu_to_be32(U32_MAX); \
798 else \
799 counter = cpu_to_be32(value); \
800 } while (0)
801
802 struct mlx4_counter {
803 u8 reserved1[3];
804 u8 counter_mode;
805 __be32 num_ifc;
806 u32 reserved2[2];
807 __be64 rx_frames;
808 __be64 rx_bytes;
809 __be64 tx_frames;
810 __be64 tx_bytes;
811 };
812
813 struct mlx4_quotas {
814 int qp;
815 int cq;
816 int srq;
817 int mpt;
818 int mtt;
819 int counter;
820 int xrcd;
821 };
822
823 struct mlx4_vf_dev {
824 u8 min_port;
825 u8 n_ports;
826 };
827
828 struct mlx4_dev_persistent {
829 struct pci_dev *pdev;
830 struct mlx4_dev *dev;
831 int nvfs[MLX4_MAX_PORTS + 1];
832 int num_vfs;
833 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
834 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
835 struct work_struct catas_work;
836 struct workqueue_struct *catas_wq;
837 struct mutex device_state_mutex; /* protect HW state */
838 u8 state;
839 struct mutex interface_state_mutex; /* protect SW state */
840 u8 interface_state;
841 };
842
843 struct mlx4_dev {
844 struct mlx4_dev_persistent *persist;
845 unsigned long flags;
846 unsigned long num_slaves;
847 struct mlx4_caps caps;
848 struct mlx4_phys_caps phys_caps;
849 struct mlx4_quotas quotas;
850 struct radix_tree_root qp_table_tree;
851 u8 rev_id;
852 u8 port_random_macs;
853 char board_id[MLX4_BOARD_ID_LEN];
854 int numa_node;
855 int oper_log_mgm_entry_size;
856 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
857 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
858 struct mlx4_vf_dev *dev_vfs;
859 };
860
861 struct mlx4_clock_params {
862 u64 offset;
863 u8 bar;
864 u8 size;
865 };
866
867 struct mlx4_eqe {
868 u8 reserved1;
869 u8 type;
870 u8 reserved2;
871 u8 subtype;
872 union {
873 u32 raw[6];
874 struct {
875 __be32 cqn;
876 } __packed comp;
877 struct {
878 u16 reserved1;
879 __be16 token;
880 u32 reserved2;
881 u8 reserved3[3];
882 u8 status;
883 __be64 out_param;
884 } __packed cmd;
885 struct {
886 __be32 qpn;
887 } __packed qp;
888 struct {
889 __be32 srqn;
890 } __packed srq;
891 struct {
892 __be32 cqn;
893 u32 reserved1;
894 u8 reserved2[3];
895 u8 syndrome;
896 } __packed cq_err;
897 struct {
898 u32 reserved1[2];
899 __be32 port;
900 } __packed port_change;
901 struct {
902 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
903 u32 reserved;
904 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
905 } __packed comm_channel_arm;
906 struct {
907 u8 port;
908 u8 reserved[3];
909 __be64 mac;
910 } __packed mac_update;
911 struct {
912 __be32 slave_id;
913 } __packed flr_event;
914 struct {
915 __be16 current_temperature;
916 __be16 warning_threshold;
917 } __packed warming;
918 struct {
919 u8 reserved[3];
920 u8 port;
921 union {
922 struct {
923 __be16 mstr_sm_lid;
924 __be16 port_lid;
925 __be32 changed_attr;
926 u8 reserved[3];
927 u8 mstr_sm_sl;
928 __be64 gid_prefix;
929 } __packed port_info;
930 struct {
931 __be32 block_ptr;
932 __be32 tbl_entries_mask;
933 } __packed tbl_change_info;
934 } params;
935 } __packed port_mgmt_change;
936 struct {
937 u8 reserved[3];
938 u8 port;
939 u32 reserved1[5];
940 } __packed bad_cable;
941 } event;
942 u8 slave_id;
943 u8 reserved3[2];
944 u8 owner;
945 } __packed;
946
947 struct mlx4_init_port_param {
948 int set_guid0;
949 int set_node_guid;
950 int set_si_guid;
951 u16 mtu;
952 int port_width_cap;
953 u16 vl_cap;
954 u16 max_gid;
955 u16 max_pkey;
956 u64 guid0;
957 u64 node_guid;
958 u64 si_guid;
959 };
960
961 #define MAD_IFC_DATA_SZ 192
962 /* MAD IFC Mailbox */
963 struct mlx4_mad_ifc {
964 u8 base_version;
965 u8 mgmt_class;
966 u8 class_version;
967 u8 method;
968 __be16 status;
969 __be16 class_specific;
970 __be64 tid;
971 __be16 attr_id;
972 __be16 resv;
973 __be32 attr_mod;
974 __be64 mkey;
975 __be16 dr_slid;
976 __be16 dr_dlid;
977 u8 reserved[28];
978 u8 data[MAD_IFC_DATA_SZ];
979 } __packed;
980
981 #define mlx4_foreach_port(port, dev, type) \
982 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
983 if ((type) == (dev)->caps.port_mask[(port)])
984
985 #define mlx4_foreach_ib_transport_port(port, dev) \
986 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
987 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
988 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) || \
989 ((dev)->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2))
990
991 #define MLX4_INVALID_SLAVE_ID 0xFF
992 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1)
993
994 void handle_port_mgmt_change_event(struct work_struct *work);
995
996 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
997 {
998 return dev->caps.function;
999 }
1000
1001 static inline int mlx4_is_master(struct mlx4_dev *dev)
1002 {
1003 return dev->flags & MLX4_FLAG_MASTER;
1004 }
1005
1006 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
1007 {
1008 return dev->phys_caps.base_sqpn + 8 +
1009 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
1010 }
1011
1012 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
1013 {
1014 return (qpn < dev->phys_caps.base_sqpn + 8 +
1015 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
1016 qpn >= dev->phys_caps.base_sqpn) ||
1017 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
1018 }
1019
1020 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
1021 {
1022 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
1023
1024 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
1025 return 1;
1026
1027 return 0;
1028 }
1029
1030 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
1031 {
1032 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
1033 }
1034
1035 static inline int mlx4_is_slave(struct mlx4_dev *dev)
1036 {
1037 return dev->flags & MLX4_FLAG_SLAVE;
1038 }
1039
1040 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1041 {
1042 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1043 }
1044
1045 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1046 struct mlx4_buf *buf, gfp_t gfp);
1047 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1048 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1049 {
1050 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
1051 return buf->direct.buf + offset;
1052 else
1053 return buf->page_list[offset >> PAGE_SHIFT].buf +
1054 (offset & (PAGE_SIZE - 1));
1055 }
1056
1057 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1058 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1059 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1060 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1061
1062 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1063 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1064 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1065 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1066
1067 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1068 struct mlx4_mtt *mtt);
1069 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1070 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1071
1072 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1073 int npages, int page_shift, struct mlx4_mr *mr);
1074 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1075 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1076 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1077 struct mlx4_mw *mw);
1078 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1079 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1080 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1081 int start_index, int npages, u64 *page_list);
1082 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1083 struct mlx4_buf *buf, gfp_t gfp);
1084
1085 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
1086 gfp_t gfp);
1087 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1088
1089 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1090 int size, int max_direct);
1091 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1092 int size);
1093
1094 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1095 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1096 unsigned vector, int collapsed, int timestamp_en);
1097 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1098 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1099 int *base, u8 flags);
1100 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1101
1102 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1103 gfp_t gfp);
1104 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1105
1106 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1107 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1108 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1109 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1110 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1111
1112 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1113 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1114
1115 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1116 int block_mcast_loopback, enum mlx4_protocol prot);
1117 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1118 enum mlx4_protocol prot);
1119 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1120 u8 port, int block_mcast_loopback,
1121 enum mlx4_protocol protocol, u64 *reg_id);
1122 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1123 enum mlx4_protocol protocol, u64 reg_id);
1124
1125 enum {
1126 MLX4_DOMAIN_UVERBS = 0x1000,
1127 MLX4_DOMAIN_ETHTOOL = 0x2000,
1128 MLX4_DOMAIN_RFS = 0x3000,
1129 MLX4_DOMAIN_NIC = 0x5000,
1130 };
1131
1132 enum mlx4_net_trans_rule_id {
1133 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1134 MLX4_NET_TRANS_RULE_ID_IB,
1135 MLX4_NET_TRANS_RULE_ID_IPV6,
1136 MLX4_NET_TRANS_RULE_ID_IPV4,
1137 MLX4_NET_TRANS_RULE_ID_TCP,
1138 MLX4_NET_TRANS_RULE_ID_UDP,
1139 MLX4_NET_TRANS_RULE_ID_VXLAN,
1140 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1141 };
1142
1143 extern const u16 __sw_id_hw[];
1144
1145 static inline int map_hw_to_sw_id(u16 header_id)
1146 {
1147
1148 int i;
1149 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1150 if (header_id == __sw_id_hw[i])
1151 return i;
1152 }
1153 return -EINVAL;
1154 }
1155
1156 enum mlx4_net_trans_promisc_mode {
1157 MLX4_FS_REGULAR = 1,
1158 MLX4_FS_ALL_DEFAULT,
1159 MLX4_FS_MC_DEFAULT,
1160 MLX4_FS_UC_SNIFFER,
1161 MLX4_FS_MC_SNIFFER,
1162 MLX4_FS_MODE_NUM, /* should be last */
1163 };
1164
1165 struct mlx4_spec_eth {
1166 u8 dst_mac[ETH_ALEN];
1167 u8 dst_mac_msk[ETH_ALEN];
1168 u8 src_mac[ETH_ALEN];
1169 u8 src_mac_msk[ETH_ALEN];
1170 u8 ether_type_enable;
1171 __be16 ether_type;
1172 __be16 vlan_id_msk;
1173 __be16 vlan_id;
1174 };
1175
1176 struct mlx4_spec_tcp_udp {
1177 __be16 dst_port;
1178 __be16 dst_port_msk;
1179 __be16 src_port;
1180 __be16 src_port_msk;
1181 };
1182
1183 struct mlx4_spec_ipv4 {
1184 __be32 dst_ip;
1185 __be32 dst_ip_msk;
1186 __be32 src_ip;
1187 __be32 src_ip_msk;
1188 };
1189
1190 struct mlx4_spec_ib {
1191 __be32 l3_qpn;
1192 __be32 qpn_msk;
1193 u8 dst_gid[16];
1194 u8 dst_gid_msk[16];
1195 };
1196
1197 struct mlx4_spec_vxlan {
1198 __be32 vni;
1199 __be32 vni_mask;
1200
1201 };
1202
1203 struct mlx4_spec_list {
1204 struct list_head list;
1205 enum mlx4_net_trans_rule_id id;
1206 union {
1207 struct mlx4_spec_eth eth;
1208 struct mlx4_spec_ib ib;
1209 struct mlx4_spec_ipv4 ipv4;
1210 struct mlx4_spec_tcp_udp tcp_udp;
1211 struct mlx4_spec_vxlan vxlan;
1212 };
1213 };
1214
1215 enum mlx4_net_trans_hw_rule_queue {
1216 MLX4_NET_TRANS_Q_FIFO,
1217 MLX4_NET_TRANS_Q_LIFO,
1218 };
1219
1220 struct mlx4_net_trans_rule {
1221 struct list_head list;
1222 enum mlx4_net_trans_hw_rule_queue queue_mode;
1223 bool exclusive;
1224 bool allow_loopback;
1225 enum mlx4_net_trans_promisc_mode promisc_mode;
1226 u8 port;
1227 u16 priority;
1228 u32 qpn;
1229 };
1230
1231 struct mlx4_net_trans_rule_hw_ctrl {
1232 __be16 prio;
1233 u8 type;
1234 u8 flags;
1235 u8 rsvd1;
1236 u8 funcid;
1237 u8 vep;
1238 u8 port;
1239 __be32 qpn;
1240 __be32 rsvd2;
1241 };
1242
1243 struct mlx4_net_trans_rule_hw_ib {
1244 u8 size;
1245 u8 rsvd1;
1246 __be16 id;
1247 u32 rsvd2;
1248 __be32 l3_qpn;
1249 __be32 qpn_mask;
1250 u8 dst_gid[16];
1251 u8 dst_gid_msk[16];
1252 } __packed;
1253
1254 struct mlx4_net_trans_rule_hw_eth {
1255 u8 size;
1256 u8 rsvd;
1257 __be16 id;
1258 u8 rsvd1[6];
1259 u8 dst_mac[6];
1260 u16 rsvd2;
1261 u8 dst_mac_msk[6];
1262 u16 rsvd3;
1263 u8 src_mac[6];
1264 u16 rsvd4;
1265 u8 src_mac_msk[6];
1266 u8 rsvd5;
1267 u8 ether_type_enable;
1268 __be16 ether_type;
1269 __be16 vlan_tag_msk;
1270 __be16 vlan_tag;
1271 } __packed;
1272
1273 struct mlx4_net_trans_rule_hw_tcp_udp {
1274 u8 size;
1275 u8 rsvd;
1276 __be16 id;
1277 __be16 rsvd1[3];
1278 __be16 dst_port;
1279 __be16 rsvd2;
1280 __be16 dst_port_msk;
1281 __be16 rsvd3;
1282 __be16 src_port;
1283 __be16 rsvd4;
1284 __be16 src_port_msk;
1285 } __packed;
1286
1287 struct mlx4_net_trans_rule_hw_ipv4 {
1288 u8 size;
1289 u8 rsvd;
1290 __be16 id;
1291 __be32 rsvd1;
1292 __be32 dst_ip;
1293 __be32 dst_ip_msk;
1294 __be32 src_ip;
1295 __be32 src_ip_msk;
1296 } __packed;
1297
1298 struct mlx4_net_trans_rule_hw_vxlan {
1299 u8 size;
1300 u8 rsvd;
1301 __be16 id;
1302 __be32 rsvd1;
1303 __be32 vni;
1304 __be32 vni_mask;
1305 } __packed;
1306
1307 struct _rule_hw {
1308 union {
1309 struct {
1310 u8 size;
1311 u8 rsvd;
1312 __be16 id;
1313 };
1314 struct mlx4_net_trans_rule_hw_eth eth;
1315 struct mlx4_net_trans_rule_hw_ib ib;
1316 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1317 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1318 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1319 };
1320 };
1321
1322 enum {
1323 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1324 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1325 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1326 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1327 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1328 };
1329
1330
1331 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1332 enum mlx4_net_trans_promisc_mode mode);
1333 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1334 enum mlx4_net_trans_promisc_mode mode);
1335 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1336 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1337 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1338 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1339 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1340
1341 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1342 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1343 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1344 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1345 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1346 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1347 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1348 u8 promisc);
1349 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
1350 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
1351 u8 ignore_fcs_value);
1352 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1353 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
1354 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
1355 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1356 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1357 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1358 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1359
1360 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1361 int npages, u64 iova, u32 *lkey, u32 *rkey);
1362 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1363 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1364 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1365 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1366 u32 *lkey, u32 *rkey);
1367 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1368 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1369 int mlx4_test_interrupts(struct mlx4_dev *dev);
1370 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
1371 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
1372 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
1373 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
1374 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1375
1376 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
1377 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1378
1379 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1380 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1381 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1382
1383 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1384 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1385 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
1386
1387 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
1388 int port);
1389 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
1390 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
1391 int mlx4_flow_attach(struct mlx4_dev *dev,
1392 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1393 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1394 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1395 enum mlx4_net_trans_promisc_mode flow_type);
1396 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1397 enum mlx4_net_trans_rule_id id);
1398 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1399
1400 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1401 int port, int qpn, u16 prio, u64 *reg_id);
1402
1403 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1404 int i, int val);
1405
1406 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1407
1408 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1409 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1410 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1411 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1412 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1413 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1414 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1415
1416 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1417 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1418
1419 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1420 int *slave_id);
1421 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1422 u8 *gid);
1423
1424 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1425 u32 max_range_qpn);
1426
1427 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1428
1429 struct mlx4_active_ports {
1430 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1431 };
1432 /* Returns a bitmap of the physical ports which are assigned to slave */
1433 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1434
1435 /* Returns the physical port that represents the virtual port of the slave, */
1436 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1437 /* mapping is returned. */
1438 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1439
1440 struct mlx4_slaves_pport {
1441 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1442 };
1443 /* Returns a bitmap of all slaves that are assigned to port. */
1444 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1445 int port);
1446
1447 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1448 /* the ports that are set in crit_ports. */
1449 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1450 struct mlx4_dev *dev,
1451 const struct mlx4_active_ports *crit_ports);
1452
1453 /* Returns the slave's virtual port that represents the physical port. */
1454 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1455
1456 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1457
1458 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1459 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1460 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port);
1461 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1462 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1463 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1464 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1465 int enable);
1466 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1467 struct mlx4_mpt_entry ***mpt_entry);
1468 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1469 struct mlx4_mpt_entry **mpt_entry);
1470 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1471 u32 pdn);
1472 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1473 struct mlx4_mpt_entry *mpt_entry,
1474 u32 access);
1475 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1476 struct mlx4_mpt_entry **mpt_entry);
1477 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1478 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1479 u64 iova, u64 size, int npages,
1480 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1481
1482 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1483 u16 offset, u16 size, u8 *data);
1484
1485 /* Returns true if running in low memory profile (kdump kernel) */
1486 static inline bool mlx4_low_memory_profile(void)
1487 {
1488 return is_kdump_kernel();
1489 }
1490
1491 /* ACCESS REG commands */
1492 enum mlx4_access_reg_method {
1493 MLX4_ACCESS_REG_QUERY = 0x1,
1494 MLX4_ACCESS_REG_WRITE = 0x2,
1495 };
1496
1497 /* ACCESS PTYS Reg command */
1498 enum mlx4_ptys_proto {
1499 MLX4_PTYS_IB = 1<<0,
1500 MLX4_PTYS_EN = 1<<2,
1501 };
1502
1503 struct mlx4_ptys_reg {
1504 u8 resrvd1;
1505 u8 local_port;
1506 u8 resrvd2;
1507 u8 proto_mask;
1508 __be32 resrvd3[2];
1509 __be32 eth_proto_cap;
1510 __be16 ib_width_cap;
1511 __be16 ib_speed_cap;
1512 __be32 resrvd4;
1513 __be32 eth_proto_admin;
1514 __be16 ib_width_admin;
1515 __be16 ib_speed_admin;
1516 __be32 resrvd5;
1517 __be32 eth_proto_oper;
1518 __be16 ib_width_oper;
1519 __be16 ib_speed_oper;
1520 __be32 resrvd6;
1521 __be32 eth_proto_lp_adv;
1522 } __packed;
1523
1524 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1525 enum mlx4_access_reg_method method,
1526 struct mlx4_ptys_reg *ptys_reg);
1527
1528 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1529 struct mlx4_clock_params *params);
1530
1531 #endif /* MLX4_DEVICE_H */
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