drivers/net/s2io.h

   1 /************************************************************************
   2  * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2007 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  ************************************************************************/
  13 #ifndef _S2IO_H
  14 #define _S2IO_H
  15
  16 #define TBD 0
  17 #define BIT(loc)                (0x8000000000000000ULL >> (loc))
  18 #define vBIT(val, loc, sz)      (((u64)val) << (64-loc-sz))
  19 #define INV(d)  ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
  20
  21 #ifndef BOOL
  22 #define BOOL    int
  23 #endif
  24
  25 #ifndef TRUE
  26 #define TRUE    1
  27 #define FALSE   0
  28 #endif
  29
  30 #undef SUCCESS
  31 #define SUCCESS 0
  32 #define FAILURE -1
  33 #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
  34 #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
  35 #define S2IO_BIT_RESET 1
  36 #define S2IO_BIT_SET 2
  37 #define CHECKBIT(value, nbit) (value & (1 << nbit))
  38
  39 /* Maximum time to flicker LED when asked to identify NIC using ethtool */
  40 #define MAX_FLICKER_TIME        60000 /* 60 Secs */
  41
  42 /* Maximum outstanding splits to be configured into xena. */
  43 enum {
  44         XENA_ONE_SPLIT_TRANSACTION = 0,
  45         XENA_TWO_SPLIT_TRANSACTION = 1,
  46         XENA_THREE_SPLIT_TRANSACTION = 2,
  47         XENA_FOUR_SPLIT_TRANSACTION = 3,
  48         XENA_EIGHT_SPLIT_TRANSACTION = 4,
  49         XENA_TWELVE_SPLIT_TRANSACTION = 5,
  50         XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
  51         XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
  52 };
  53 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
  54
  55 /*  OS concerned variables and constants */
  56 #define WATCH_DOG_TIMEOUT               15*HZ
  57 #define EFILL                           0x1234
  58 #define ALIGN_SIZE                      127
  59 #define PCIX_COMMAND_REGISTER           0x62
  60
  61 /*
  62  * Debug related variables.
  63  */
  64 /* different debug levels. */
  65 #define ERR_DBG         0
  66 #define INIT_DBG        1
  67 #define INFO_DBG        2
  68 #define TX_DBG          3
  69 #define INTR_DBG        4
  70
  71 /* Global variable that defines the present debug level of the driver. */
  72 static int debug_level = ERR_DBG;
  73
  74 /* DEBUG message print. */
  75 #define DBG_PRINT(dbg_level, args...)  if(!(debug_level<dbg_level)) printk(args)
  76
  77 /* Protocol assist features of the NIC */
  78 #define L3_CKSUM_OK 0xFFFF
  79 #define L4_CKSUM_OK 0xFFFF
  80 #define S2IO_JUMBO_SIZE 9600
  81
  82 /* Driver statistics maintained by driver */
  83 struct swStat {
  84         unsigned long long single_ecc_errs;
  85         unsigned long long double_ecc_errs;
  86         unsigned long long parity_err_cnt;
  87         unsigned long long serious_err_cnt;
  88         unsigned long long soft_reset_cnt;
  89         unsigned long long fifo_full_cnt;
  90         unsigned long long ring_full_cnt;
  91         /* LRO statistics */
  92         unsigned long long clubbed_frms_cnt;
  93         unsigned long long sending_both;
  94         unsigned long long outof_sequence_pkts;
  95         unsigned long long flush_max_pkts;
  96         unsigned long long sum_avg_pkts_aggregated;
  97         unsigned long long num_aggregations;
  98 };
  99
 100 /* Xpak releated alarm and warnings */
 101 struct xpakStat {
 102         u64 alarm_transceiver_temp_high;
 103         u64 alarm_transceiver_temp_low;
 104         u64 alarm_laser_bias_current_high;
 105         u64 alarm_laser_bias_current_low;
 106         u64 alarm_laser_output_power_high;
 107         u64 alarm_laser_output_power_low;
 108         u64 warn_transceiver_temp_high;
 109         u64 warn_transceiver_temp_low;
 110         u64 warn_laser_bias_current_high;
 111         u64 warn_laser_bias_current_low;
 112         u64 warn_laser_output_power_high;
 113         u64 warn_laser_output_power_low;
 114         u64 xpak_regs_stat;
 115         u32 xpak_timer_count;
 116 };
 117
 118
 119 /* The statistics block of Xena */
 120 struct stat_block {
 121 /* Tx MAC statistics counters. */
 122         __le32 tmac_data_octets;
 123         __le32 tmac_frms;
 124         __le64 tmac_drop_frms;
 125         __le32 tmac_bcst_frms;
 126         __le32 tmac_mcst_frms;
 127         __le64 tmac_pause_ctrl_frms;
 128         __le32 tmac_ucst_frms;
 129         __le32 tmac_ttl_octets;
 130         __le32 tmac_any_err_frms;
 131         __le32 tmac_nucst_frms;
 132         __le64 tmac_ttl_less_fb_octets;
 133         __le64 tmac_vld_ip_octets;
 134         __le32 tmac_drop_ip;
 135         __le32 tmac_vld_ip;
 136         __le32 tmac_rst_tcp;
 137         __le32 tmac_icmp;
 138         __le64 tmac_tcp;
 139         __le32 reserved_0;
 140         __le32 tmac_udp;
 141
 142 /* Rx MAC Statistics counters. */
 143         __le32 rmac_data_octets;
 144         __le32 rmac_vld_frms;
 145         __le64 rmac_fcs_err_frms;
 146         __le64 rmac_drop_frms;
 147         __le32 rmac_vld_bcst_frms;
 148         __le32 rmac_vld_mcst_frms;
 149         __le32 rmac_out_rng_len_err_frms;
 150         __le32 rmac_in_rng_len_err_frms;
 151         __le64 rmac_long_frms;
 152         __le64 rmac_pause_ctrl_frms;
 153         __le64 rmac_unsup_ctrl_frms;
 154         __le32 rmac_accepted_ucst_frms;
 155         __le32 rmac_ttl_octets;
 156         __le32 rmac_discarded_frms;
 157         __le32 rmac_accepted_nucst_frms;
 158         __le32 reserved_1;
 159         __le32 rmac_drop_events;
 160         __le64 rmac_ttl_less_fb_octets;
 161         __le64 rmac_ttl_frms;
 162         __le64 reserved_2;
 163         __le32 rmac_usized_frms;
 164         __le32 reserved_3;
 165         __le32 rmac_frag_frms;
 166         __le32 rmac_osized_frms;
 167         __le32 reserved_4;
 168         __le32 rmac_jabber_frms;
 169         __le64 rmac_ttl_64_frms;
 170         __le64 rmac_ttl_65_127_frms;
 171         __le64 reserved_5;
 172         __le64 rmac_ttl_128_255_frms;
 173         __le64 rmac_ttl_256_511_frms;
 174         __le64 reserved_6;
 175         __le64 rmac_ttl_512_1023_frms;
 176         __le64 rmac_ttl_1024_1518_frms;
 177         __le32 rmac_ip;
 178         __le32 reserved_7;
 179         __le64 rmac_ip_octets;
 180         __le32 rmac_drop_ip;
 181         __le32 rmac_hdr_err_ip;
 182         __le32 reserved_8;
 183         __le32 rmac_icmp;
 184         __le64 rmac_tcp;
 185         __le32 rmac_err_drp_udp;
 186         __le32 rmac_udp;
 187         __le64 rmac_xgmii_err_sym;
 188         __le64 rmac_frms_q0;
 189         __le64 rmac_frms_q1;
 190         __le64 rmac_frms_q2;
 191         __le64 rmac_frms_q3;
 192         __le64 rmac_frms_q4;
 193         __le64 rmac_frms_q5;
 194         __le64 rmac_frms_q6;
 195         __le64 rmac_frms_q7;
 196         __le16 rmac_full_q3;
 197         __le16 rmac_full_q2;
 198         __le16 rmac_full_q1;
 199         __le16 rmac_full_q0;
 200         __le16 rmac_full_q7;
 201         __le16 rmac_full_q6;
 202         __le16 rmac_full_q5;
 203         __le16 rmac_full_q4;
 204         __le32 reserved_9;
 205         __le32 rmac_pause_cnt;
 206         __le64 rmac_xgmii_data_err_cnt;
 207         __le64 rmac_xgmii_ctrl_err_cnt;
 208         __le32 rmac_err_tcp;
 209         __le32 rmac_accepted_ip;
 210
 211 /* PCI/PCI-X Read transaction statistics. */
 212         __le32 new_rd_req_cnt;
 213         __le32 rd_req_cnt;
 214         __le32 rd_rtry_cnt;
 215         __le32 new_rd_req_rtry_cnt;
 216
 217 /* PCI/PCI-X Write/Read transaction statistics. */
 218         __le32 wr_req_cnt;
 219         __le32 wr_rtry_rd_ack_cnt;
 220         __le32 new_wr_req_rtry_cnt;
 221         __le32 new_wr_req_cnt;
 222         __le32 wr_disc_cnt;
 223         __le32 wr_rtry_cnt;
 224
 225 /*      PCI/PCI-X Write / DMA Transaction statistics. */
 226         __le32 txp_wr_cnt;
 227         __le32 rd_rtry_wr_ack_cnt;
 228         __le32 txd_wr_cnt;
 229         __le32 txd_rd_cnt;
 230         __le32 rxd_wr_cnt;
 231         __le32 rxd_rd_cnt;
 232         __le32 rxf_wr_cnt;
 233         __le32 txf_rd_cnt;
 234
 235 /* Tx MAC statistics overflow counters. */
 236         __le32 tmac_data_octets_oflow;
 237         __le32 tmac_frms_oflow;
 238         __le32 tmac_bcst_frms_oflow;
 239         __le32 tmac_mcst_frms_oflow;
 240         __le32 tmac_ucst_frms_oflow;
 241         __le32 tmac_ttl_octets_oflow;
 242         __le32 tmac_any_err_frms_oflow;
 243         __le32 tmac_nucst_frms_oflow;
 244         __le64 tmac_vlan_frms;
 245         __le32 tmac_drop_ip_oflow;
 246         __le32 tmac_vld_ip_oflow;
 247         __le32 tmac_rst_tcp_oflow;
 248         __le32 tmac_icmp_oflow;
 249         __le32 tpa_unknown_protocol;
 250         __le32 tmac_udp_oflow;
 251         __le32 reserved_10;
 252         __le32 tpa_parse_failure;
 253
 254 /* Rx MAC Statistics overflow counters. */
 255         __le32 rmac_data_octets_oflow;
 256         __le32 rmac_vld_frms_oflow;
 257         __le32 rmac_vld_bcst_frms_oflow;
 258         __le32 rmac_vld_mcst_frms_oflow;
 259         __le32 rmac_accepted_ucst_frms_oflow;
 260         __le32 rmac_ttl_octets_oflow;
 261         __le32 rmac_discarded_frms_oflow;
 262         __le32 rmac_accepted_nucst_frms_oflow;
 263         __le32 rmac_usized_frms_oflow;
 264         __le32 rmac_drop_events_oflow;
 265         __le32 rmac_frag_frms_oflow;
 266         __le32 rmac_osized_frms_oflow;
 267         __le32 rmac_ip_oflow;
 268         __le32 rmac_jabber_frms_oflow;
 269         __le32 rmac_icmp_oflow;
 270         __le32 rmac_drop_ip_oflow;
 271         __le32 rmac_err_drp_udp_oflow;
 272         __le32 rmac_udp_oflow;
 273         __le32 reserved_11;
 274         __le32 rmac_pause_cnt_oflow;
 275         __le64 rmac_ttl_1519_4095_frms;
 276         __le64 rmac_ttl_4096_8191_frms;
 277         __le64 rmac_ttl_8192_max_frms;
 278         __le64 rmac_ttl_gt_max_frms;
 279         __le64 rmac_osized_alt_frms;
 280         __le64 rmac_jabber_alt_frms;
 281         __le64 rmac_gt_max_alt_frms;
 282         __le64 rmac_vlan_frms;
 283         __le32 rmac_len_discard;
 284         __le32 rmac_fcs_discard;
 285         __le32 rmac_pf_discard;
 286         __le32 rmac_da_discard;
 287         __le32 rmac_red_discard;
 288         __le32 rmac_rts_discard;
 289         __le32 reserved_12;
 290         __le32 rmac_ingm_full_discard;
 291         __le32 reserved_13;
 292         __le32 rmac_accepted_ip_oflow;
 293         __le32 reserved_14;
 294         __le32 link_fault_cnt;
 295         u8  buffer[20];
 296         struct swStat sw_stat;
 297         struct xpakStat xpak_stat;
 298 };
 299
 300 /* Default value for 'vlan_strip_tag' configuration parameter */
 301 #define NO_STRIP_IN_PROMISC 2
 302
 303 /*
 304  * Structures representing different init time configuration
 305  * parameters of the NIC.
 306  */
 307
 308 #define MAX_TX_FIFOS 8
 309 #define MAX_RX_RINGS 8
 310
 311 #define MAX_RX_DESC_1  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
 312 #define MAX_RX_DESC_2  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
 313 #define MAX_RX_DESC_3  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
 314 #define MAX_TX_DESC    (MAX_AVAILABLE_TXDS)
 315
 316 /* FIFO mappings for all possible number of fifos configured */
 317 static int fifo_map[][MAX_TX_FIFOS] = {
 318         {0, 0, 0, 0, 0, 0, 0, 0},
 319         {0, 0, 0, 0, 1, 1, 1, 1},
 320         {0, 0, 0, 1, 1, 1, 2, 2},
 321         {0, 0, 1, 1, 2, 2, 3, 3},
 322         {0, 0, 1, 1, 2, 2, 3, 4},
 323         {0, 0, 1, 1, 2, 3, 4, 5},
 324         {0, 0, 1, 2, 3, 4, 5, 6},
 325         {0, 1, 2, 3, 4, 5, 6, 7},
 326 };
 327
 328 /* Maintains Per FIFO related information. */
 329 struct tx_fifo_config {
 330 #define MAX_AVAILABLE_TXDS      8192
 331         u32 fifo_len;           /* specifies len of FIFO upto 8192, ie no of TxDLs */
 332 /* Priority definition */
 333 #define TX_FIFO_PRI_0               0   /*Highest */
 334 #define TX_FIFO_PRI_1               1
 335 #define TX_FIFO_PRI_2               2
 336 #define TX_FIFO_PRI_3               3
 337 #define TX_FIFO_PRI_4               4
 338 #define TX_FIFO_PRI_5               5
 339 #define TX_FIFO_PRI_6               6
 340 #define TX_FIFO_PRI_7               7   /*lowest */
 341         u8 fifo_priority;       /* specifies pointer level for FIFO */
 342         /* user should not set twos fifos with same pri */
 343         u8 f_no_snoop;
 344 #define NO_SNOOP_TXD                0x01
 345 #define NO_SNOOP_TXD_BUFFER          0x02
 346 };
 347
 348
 349 /* Maintains per Ring related information */
 350 struct rx_ring_config {
 351         u32 num_rxd;            /*No of RxDs per Rx Ring */
 352 #define RX_RING_PRI_0               0   /* highest */
 353 #define RX_RING_PRI_1               1
 354 #define RX_RING_PRI_2               2
 355 #define RX_RING_PRI_3               3
 356 #define RX_RING_PRI_4               4
 357 #define RX_RING_PRI_5               5
 358 #define RX_RING_PRI_6               6
 359 #define RX_RING_PRI_7               7   /* lowest */
 360
 361         u8 ring_priority;       /*Specifies service priority of ring */
 362         /* OSM should not set any two rings with same priority */
 363         u8 ring_org;            /*Organization of ring */
 364 #define RING_ORG_BUFF1          0x01
 365 #define RX_RING_ORG_BUFF3       0x03
 366 #define RX_RING_ORG_BUFF5       0x05
 367
 368         u8 f_no_snoop;
 369 #define NO_SNOOP_RXD                0x01
 370 #define NO_SNOOP_RXD_BUFFER         0x02
 371 };
 372
 373 /* This structure provides contains values of the tunable parameters
 374  * of the H/W
 375  */
 376 struct config_param {
 377 /* Tx Side */
 378         u32 tx_fifo_num;        /*Number of Tx FIFOs */
 379
 380         u8 fifo_mapping[MAX_TX_FIFOS];
 381         struct tx_fifo_config tx_cfg[MAX_TX_FIFOS];     /*Per-Tx FIFO config */
 382         u32 max_txds;           /*Max no. of Tx buffer descriptor per TxDL */
 383         u64 tx_intr_type;
 384         /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
 385
 386 /* Rx Side */
 387         u32 rx_ring_num;        /*Number of receive rings */
 388 #define MAX_RX_BLOCKS_PER_RING  150
 389
 390         struct rx_ring_config rx_cfg[MAX_RX_RINGS];     /*Per-Rx Ring config */
 391         u8 bimodal;             /*Flag for setting bimodal interrupts*/
 392
 393 #define HEADER_ETHERNET_II_802_3_SIZE 14
 394 #define HEADER_802_2_SIZE              3
 395 #define HEADER_SNAP_SIZE               5
 396 #define HEADER_VLAN_SIZE               4
 397
 398 #define MIN_MTU                       46
 399 #define MAX_PYLD                    1500
 400 #define MAX_MTU                     (MAX_PYLD+18)
 401 #define MAX_MTU_VLAN                (MAX_PYLD+22)
 402 #define MAX_PYLD_JUMBO              9600
 403 #define MAX_MTU_JUMBO               (MAX_PYLD_JUMBO+18)
 404 #define MAX_MTU_JUMBO_VLAN          (MAX_PYLD_JUMBO+22)
 405         u16 bus_speed;
 406 };
 407
 408 /* Structure representing MAC Addrs */
 409 struct mac_addr {
 410         u8 mac_addr[ETH_ALEN];
 411 };
 412
 413 /* Structure that represent every FIFO element in the BAR1
 414  * Address location.
 415  */
 416 struct TxFIFO_element {
 417         u64 TxDL_Pointer;
 418
 419         u64 List_Control;
 420 #define TX_FIFO_LAST_TXD_NUM( val)     vBIT(val,0,8)
 421 #define TX_FIFO_FIRST_LIST             BIT(14)
 422 #define TX_FIFO_LAST_LIST              BIT(15)
 423 #define TX_FIFO_FIRSTNLAST_LIST        vBIT(3,14,2)
 424 #define TX_FIFO_SPECIAL_FUNC           BIT(23)
 425 #define TX_FIFO_DS_NO_SNOOP            BIT(31)
 426 #define TX_FIFO_BUFF_NO_SNOOP          BIT(30)
 427 };
 428
 429 /* Tx descriptor structure */
 430 struct TxD {
 431         u64 Control_1;
 432 /* bit mask */
 433 #define TXD_LIST_OWN_XENA       BIT(7)
 434 #define TXD_T_CODE              (BIT(12)|BIT(13)|BIT(14)|BIT(15))
 435 #define TXD_T_CODE_OK(val)      (|(val & TXD_T_CODE))
 436 #define GET_TXD_T_CODE(val)     ((val & TXD_T_CODE)<<12)
 437 #define TXD_GATHER_CODE         (BIT(22) | BIT(23))
 438 #define TXD_GATHER_CODE_FIRST   BIT(22)
 439 #define TXD_GATHER_CODE_LAST    BIT(23)
 440 #define TXD_TCP_LSO_EN          BIT(30)
 441 #define TXD_UDP_COF_EN          BIT(31)
 442 #define TXD_UFO_EN              BIT(31) | BIT(30)
 443 #define TXD_TCP_LSO_MSS(val)    vBIT(val,34,14)
 444 #define TXD_UFO_MSS(val)        vBIT(val,34,14)
 445 #define TXD_BUFFER0_SIZE(val)   vBIT(val,48,16)
 446
 447         u64 Control_2;
 448 #define TXD_TX_CKO_CONTROL      (BIT(5)|BIT(6)|BIT(7))
 449 #define TXD_TX_CKO_IPV4_EN      BIT(5)
 450 #define TXD_TX_CKO_TCP_EN       BIT(6)
 451 #define TXD_TX_CKO_UDP_EN       BIT(7)
 452 #define TXD_VLAN_ENABLE         BIT(15)
 453 #define TXD_VLAN_TAG(val)       vBIT(val,16,16)
 454 #define TXD_INT_NUMBER(val)     vBIT(val,34,6)
 455 #define TXD_INT_TYPE_PER_LIST   BIT(47)
 456 #define TXD_INT_TYPE_UTILZ      BIT(46)
 457 #define TXD_SET_MARKER         vBIT(0x6,0,4)
 458
 459         u64 Buffer_Pointer;
 460         u64 Host_Control;       /* reserved for host */
 461 };
 462
 463 /* Structure to hold the phy and virt addr of every TxDL. */
 464 struct list_info_hold {
 465         dma_addr_t list_phy_addr;
 466         void *list_virt_addr;
 467 };
 468
 469 /* Rx descriptor structure for 1 buffer mode */
 470 struct RxD_t {
 471         u64 Host_Control;       /* reserved for host */
 472         u64 Control_1;
 473 #define RXD_OWN_XENA            BIT(7)
 474 #define RXD_T_CODE              (BIT(12)|BIT(13)|BIT(14)|BIT(15))
 475 #define RXD_FRAME_PROTO         vBIT(0xFFFF,24,8)
 476 #define RXD_FRAME_PROTO_IPV4    BIT(27)
 477 #define RXD_FRAME_PROTO_IPV6    BIT(28)
 478 #define RXD_FRAME_IP_FRAG       BIT(29)
 479 #define RXD_FRAME_PROTO_TCP     BIT(30)
 480 #define RXD_FRAME_PROTO_UDP     BIT(31)
 481 #define TCP_OR_UDP_FRAME        (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
 482 #define RXD_GET_L3_CKSUM(val)   ((u16)(val>> 16) & 0xFFFF)
 483 #define RXD_GET_L4_CKSUM(val)   ((u16)(val) & 0xFFFF)
 484
 485         u64 Control_2;
 486 #define THE_RXD_MARK            0x3
 487 #define SET_RXD_MARKER          vBIT(THE_RXD_MARK, 0, 2)
 488 #define GET_RXD_MARKER(ctrl)    ((ctrl & SET_RXD_MARKER) >> 62)
 489
 490 #define MASK_VLAN_TAG           vBIT(0xFFFF,48,16)
 491 #define SET_VLAN_TAG(val)       vBIT(val,48,16)
 492 #define SET_NUM_TAG(val)       vBIT(val,16,32)
 493
 494
 495 };
 496 /* Rx descriptor structure for 1 buffer mode */
 497 struct RxD1 {
 498         struct RxD_t h;
 499
 500 #define MASK_BUFFER0_SIZE_1       vBIT(0x3FFF,2,14)
 501 #define SET_BUFFER0_SIZE_1(val)   vBIT(val,2,14)
 502 #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
 503         (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
 504         u64 Buffer0_ptr;
 505 };
 506 /* Rx descriptor structure for 3 or 2 buffer mode */
 507
 508 struct RxD3 {
 509         struct RxD_t h;
 510
 511 #define MASK_BUFFER0_SIZE_3       vBIT(0xFF,2,14)
 512 #define MASK_BUFFER1_SIZE_3       vBIT(0xFFFF,16,16)
 513 #define MASK_BUFFER2_SIZE_3       vBIT(0xFFFF,32,16)
 514 #define SET_BUFFER0_SIZE_3(val)   vBIT(val,8,8)
 515 #define SET_BUFFER1_SIZE_3(val)   vBIT(val,16,16)
 516 #define SET_BUFFER2_SIZE_3(val)   vBIT(val,32,16)
 517 #define RXD_GET_BUFFER0_SIZE_3(Control_2) \
 518         (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
 519 #define RXD_GET_BUFFER1_SIZE_3(Control_2) \
 520         (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
 521 #define RXD_GET_BUFFER2_SIZE_3(Control_2) \
 522         (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
 523 #define BUF0_LEN        40
 524 #define BUF1_LEN        1
 525
 526         u64 Buffer0_ptr;
 527         u64 Buffer1_ptr;
 528         u64 Buffer2_ptr;
 529 };
 530
 531
 532 /* Structure that represents the Rx descriptor block which contains
 533  * 128 Rx descriptors.
 534  */
 535 struct RxD_block {
 536 #define MAX_RXDS_PER_BLOCK_1            127
 537         struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
 538
 539         u64 reserved_0;
 540 #define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL
 541         u64 reserved_1;         /* 0xFEFFFFFFFFFFFFFF to mark last
 542                                  * Rxd in this blk */
 543         u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
 544         u64 pNext_RxD_Blk_physical;     /* Buff0_ptr.In a 32 bit arch
 545                                          * the upper 32 bits should
 546                                          * be 0 */
 547 };
 548
 549 #define SIZE_OF_BLOCK   4096
 550
 551 #define RXD_MODE_1      0 /* One Buffer mode */
 552 #define RXD_MODE_3A     1 /* Three Buffer mode */
 553 #define RXD_MODE_3B     2 /* Two Buffer mode */
 554
 555 /* Structure to hold virtual addresses of Buf0 and Buf1 in
 556  * 2buf mode. */
 557 struct buffAdd {
 558         void *ba_0_org;
 559         void *ba_1_org;
 560         void *ba_0;
 561         void *ba_1;
 562 };
 563
 564 /* Structure which stores all the MAC control parameters */
 565
 566 /* This structure stores the offset of the RxD in the ring
 567  * from which the Rx Interrupt processor can start picking
 568  * up the RxDs for processing.
 569  */
 570 struct rx_curr_get_info {
 571         u32 block_index;
 572         u32 offset;
 573         u32 ring_len;
 574 };
 575
 576 struct rx_curr_put_info {
 577         u32 block_index;
 578         u32 offset;
 579         u32 ring_len;
 580 };
 581
 582 /* This structure stores the offset of the TxDl in the FIFO
 583  * from which the Tx Interrupt processor can start picking
 584  * up the TxDLs for send complete interrupt processing.
 585  */
 586 struct tx_curr_get_info {
 587         u32 offset;
 588         u32 fifo_len;
 589 };
 590
 591 struct tx_curr_put_info {
 592         u32 offset;
 593         u32 fifo_len;
 594 };
 595
 596 struct rxd_info {
 597         void *virt_addr;
 598         dma_addr_t dma_addr;
 599 };
 600
 601 /* Structure that holds the Phy and virt addresses of the Blocks */
 602 struct rx_block_info {
 603         void *block_virt_addr;
 604         dma_addr_t block_dma_addr;
 605         struct rxd_info *rxds;
 606 };
 607
 608 /* Ring specific structure */
 609 struct ring_info {
 610         /* The ring number */
 611         int ring_no;
 612
 613         /*
 614          *  Place holders for the virtual and physical addresses of
 615          *  all the Rx Blocks
 616          */
 617         struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
 618         int block_count;
 619         int pkt_cnt;
 620
 621         /*
 622          * Put pointer info which indictes which RxD has to be replenished
 623          * with a new buffer.
 624          */
 625         struct rx_curr_put_info rx_curr_put_info;
 626
 627         /*
 628          * Get pointer info which indictes which is the last RxD that was
 629          * processed by the driver.
 630          */
 631         struct rx_curr_get_info rx_curr_get_info;
 632
 633         /* Index to the absolute position of the put pointer of Rx ring */
 634         int put_pos;
 635
 636         /* Buffer Address store. */
 637         struct buffAdd **ba;
 638         struct s2io_nic *nic;
 639 };
 640
 641 /* Fifo specific structure */
 642 struct fifo_info {
 643         /* FIFO number */
 644         int fifo_no;
 645
 646         /* Maximum TxDs per TxDL */
 647         int max_txds;
 648
 649         /* Place holder of all the TX List's Phy and Virt addresses. */
 650         struct list_info_hold *list_info;
 651
 652         /*
 653          * Current offset within the tx FIFO where driver would write
 654          * new Tx frame
 655          */
 656         struct tx_curr_put_info tx_curr_put_info;
 657
 658         /*
 659          * Current offset within tx FIFO from where the driver would start freeing
 660          * the buffers
 661          */
 662         struct tx_curr_get_info tx_curr_get_info;
 663
 664         struct s2io_nic *nic;
 665 };
 666
 667 /* Information related to the Tx and Rx FIFOs and Rings of Xena
 668  * is maintained in this structure.
 669  */
 670 struct mac_info {
 671 /* tx side stuff */
 672         /* logical pointer of start of each Tx FIFO */
 673         struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
 674
 675         /* Fifo specific structure */
 676         struct fifo_info fifos[MAX_TX_FIFOS];
 677
 678         /* Save virtual address of TxD page with zero DMA addr(if any) */
 679         void *zerodma_virt_addr;
 680
 681 /* rx side stuff */
 682         /* Ring specific structure */
 683         struct ring_info rings[MAX_RX_RINGS];
 684
 685         u16 rmac_pause_time;
 686         u16 mc_pause_threshold_q0q3;
 687         u16 mc_pause_threshold_q4q7;
 688
 689         void *stats_mem;        /* orignal pointer to allocated mem */
 690         dma_addr_t stats_mem_phy;       /* Physical address of the stat block */
 691         u32 stats_mem_sz;
 692         struct stat_block *stats_info;  /* Logical address of the stat block */
 693 };
 694
 695 /* structure representing the user defined MAC addresses */
 696 struct usr_addr {
 697         char addr[ETH_ALEN];
 698         int usage_cnt;
 699 };
 700
 701 /* Default Tunable parameters of the NIC. */
 702 #define DEFAULT_FIFO_0_LEN 4096
 703 #define DEFAULT_FIFO_1_7_LEN 512
 704 #define SMALL_BLK_CNT   30
 705 #define LARGE_BLK_CNT   100
 706
 707 /*
 708  * Structure to keep track of the MSI-X vectors and the corresponding
 709  * argument registered against each vector
 710  */
 711 #define MAX_REQUESTED_MSI_X     17
 712 struct s2io_msix_entry
 713 {
 714         u16 vector;
 715         u16 entry;
 716         void *arg;
 717
 718         u8 type;
 719 #define MSIX_FIFO_TYPE  1
 720 #define MSIX_RING_TYPE  2
 721
 722         u8 in_use;
 723 #define MSIX_REGISTERED_SUCCESS 0xAA
 724 };
 725
 726 struct msix_info_st {
 727         u64 addr;
 728         u64 data;
 729 };
 730
 731 /* Data structure to represent a LRO session */
 732 struct lro {
 733         struct sk_buff  *parent;
 734         struct sk_buff  *last_frag;
 735         u8              *l2h;
 736         struct iphdr    *iph;
 737         struct tcphdr   *tcph;
 738         u32             tcp_next_seq;
 739         __be32          tcp_ack;
 740         int             total_len;
 741         int             frags_len;
 742         int             sg_num;
 743         int             in_use;
 744         __be16          window;
 745         u32             cur_tsval;
 746         u32             cur_tsecr;
 747         u8              saw_ts;
 748 };
 749
 750 /* Structure representing one instance of the NIC */
 751 struct s2io_nic {
 752         int rxd_mode;
 753         /*
 754          * Count of packets to be processed in a given iteration, it will be indicated
 755          * by the quota field of the device structure when NAPI is enabled.
 756          */
 757         int pkts_to_process;
 758         struct net_device *dev;
 759         struct mac_info mac_control;
 760         struct config_param config;
 761         struct pci_dev *pdev;
 762         void __iomem *bar0;
 763         void __iomem *bar1;
 764 #define MAX_MAC_SUPPORTED   16
 765 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
 766
 767         struct mac_addr def_mac_addr[MAX_MAC_SUPPORTED];
 768
 769         struct net_device_stats stats;
 770         int high_dma_flag;
 771         int device_close_flag;
 772         int device_enabled_once;
 773
 774         char name[60];
 775         struct tasklet_struct task;
 776         volatile unsigned long tasklet_status;
 777
 778         /* Timer that handles I/O errors/exceptions */
 779         struct timer_list alarm_timer;
 780
 781         /* Space to back up the PCI config space */
 782         u32 config_space[256 / sizeof(u32)];
 783
 784         atomic_t rx_bufs_left[MAX_RX_RINGS];
 785
 786         spinlock_t tx_lock;
 787         spinlock_t put_lock;
 788
 789 #define PROMISC     1
 790 #define ALL_MULTI   2
 791
 792 #define MAX_ADDRS_SUPPORTED 64
 793         u16 usr_addr_count;
 794         u16 mc_addr_count;
 795         struct usr_addr usr_addrs[MAX_ADDRS_SUPPORTED];
 796
 797         u16 m_cast_flg;
 798         u16 all_multi_pos;
 799         u16 promisc_flg;
 800
 801         /*  Id timer, used to blink NIC to physically identify NIC. */
 802         struct timer_list id_timer;
 803
 804         /*  Restart timer, used to restart NIC if the device is stuck and
 805          *  a schedule task that will set the correct Link state once the
 806          *  NIC's PHY has stabilized after a state change.
 807          */
 808         struct work_struct rst_timer_task;
 809         struct work_struct set_link_task;
 810
 811         /* Flag that can be used to turn on or turn off the Rx checksum
 812          * offload feature.
 813          */
 814         int rx_csum;
 815
 816         /*  after blink, the adapter must be restored with original
 817          *  values.
 818          */
 819         u64 adapt_ctrl_org;
 820
 821         /* Last known link state. */
 822         u16 last_link_state;
 823 #define LINK_DOWN       1
 824 #define LINK_UP         2
 825
 826         int task_flag;
 827 #define CARD_DOWN 1
 828 #define CARD_UP 2
 829         atomic_t card_state;
 830         volatile unsigned long link_state;
 831         struct vlan_group *vlgrp;
 832 #define MSIX_FLG                0xA5
 833         struct msix_entry *entries;
 834         struct s2io_msix_entry *s2io_entries;
 835         char desc[MAX_REQUESTED_MSI_X][25];
 836
 837         int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
 838
 839         struct msix_info_st msix_info[0x3f];
 840
 841 #define XFRAME_I_DEVICE         1
 842 #define XFRAME_II_DEVICE        2
 843         u8 device_type;
 844
 845 #define MAX_LRO_SESSIONS        32
 846         struct lro lro0_n[MAX_LRO_SESSIONS];
 847         unsigned long   clubbed_frms_cnt;
 848         unsigned long   sending_both;
 849         u8              lro;
 850         u16             lro_max_aggr_per_sess;
 851
 852 #define INTA    0
 853 #define MSI     1
 854 #define MSI_X   2
 855         u8 intr_type;
 856
 857         spinlock_t      rx_lock;
 858         atomic_t        isr_cnt;
 859         u64 *ufo_in_band_v;
 860 #define VPD_STRING_LEN 80
 861         u8  product_name[VPD_STRING_LEN];
 862         u8  serial_num[VPD_STRING_LEN];
 863 };
 864
 865 #define RESET_ERROR 1;
 866 #define CMD_ERROR   2;
 867
 868 /*  OS related system calls */
 869 #ifndef readq
 870 static inline u64 readq(void __iomem *addr)
 871 {
 872         u64 ret = 0;
 873         ret = readl(addr + 4);
 874         ret <<= 32;
 875         ret |= readl(addr);
 876
 877         return ret;
 878 }
 879 #endif
 880
 881 #ifndef writeq
 882 static inline void writeq(u64 val, void __iomem *addr)
 883 {
 884         writel((u32) (val), addr);
 885         writel((u32) (val >> 32), (addr + 4));
 886 }
 887 #endif
 888
 889 /*
 890  * Some registers have to be written in a particular order to
 891  * expect correct hardware operation. The macro SPECIAL_REG_WRITE
 892  * is used to perform such ordered writes. Defines UF (Upper First)
 893  * and LF (Lower First) will be used to specify the required write order.
 894  */
 895 #define UF      1
 896 #define LF      2
 897 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
 898 {
 899         u32 ret;
 900
 901         if (order == LF) {
 902                 writel((u32) (val), addr);
 903                 ret = readl(addr);
 904                 writel((u32) (val >> 32), (addr + 4));
 905                 ret = readl(addr + 4);
 906         } else {
 907                 writel((u32) (val >> 32), (addr + 4));
 908                 ret = readl(addr + 4);
 909                 writel((u32) (val), addr);
 910                 ret = readl(addr);
 911         }
 912 }
 913
 914 /*  Interrupt related values of Xena */
 915
 916 #define ENABLE_INTRS    1
 917 #define DISABLE_INTRS   2
 918
 919 /*  Highest level interrupt blocks */
 920 #define TX_PIC_INTR     (0x0001<<0)
 921 #define TX_DMA_INTR     (0x0001<<1)
 922 #define TX_MAC_INTR     (0x0001<<2)
 923 #define TX_XGXS_INTR    (0x0001<<3)
 924 #define TX_TRAFFIC_INTR (0x0001<<4)
 925 #define RX_PIC_INTR     (0x0001<<5)
 926 #define RX_DMA_INTR     (0x0001<<6)
 927 #define RX_MAC_INTR     (0x0001<<7)
 928 #define RX_XGXS_INTR    (0x0001<<8)
 929 #define RX_TRAFFIC_INTR (0x0001<<9)
 930 #define MC_INTR         (0x0001<<10)
 931 #define ENA_ALL_INTRS    (   TX_PIC_INTR     | \
 932                             TX_DMA_INTR     | \
 933                             TX_MAC_INTR     | \
 934                             TX_XGXS_INTR    | \
 935                             TX_TRAFFIC_INTR | \
 936                             RX_PIC_INTR     | \
 937                             RX_DMA_INTR     | \
 938                             RX_MAC_INTR     | \
 939                             RX_XGXS_INTR    | \
 940                             RX_TRAFFIC_INTR | \
 941                             MC_INTR )
 942
 943 /*  Interrupt masks for the general interrupt mask register */
 944 #define DISABLE_ALL_INTRS   0xFFFFFFFFFFFFFFFFULL
 945
 946 #define TXPIC_INT_M         BIT(0)
 947 #define TXDMA_INT_M         BIT(1)
 948 #define TXMAC_INT_M         BIT(2)
 949 #define TXXGXS_INT_M        BIT(3)
 950 #define TXTRAFFIC_INT_M     BIT(8)
 951 #define PIC_RX_INT_M        BIT(32)
 952 #define RXDMA_INT_M         BIT(33)
 953 #define RXMAC_INT_M         BIT(34)
 954 #define MC_INT_M            BIT(35)
 955 #define RXXGXS_INT_M        BIT(36)
 956 #define RXTRAFFIC_INT_M     BIT(40)
 957
 958 /*  PIC level Interrupts TODO*/
 959
 960 /*  DMA level Inressupts */
 961 #define TXDMA_PFC_INT_M     BIT(0)
 962 #define TXDMA_PCC_INT_M     BIT(2)
 963
 964 /*  PFC block interrupts */
 965 #define PFC_MISC_ERR_1      BIT(0)      /* Interrupt to indicate FIFO full */
 966
 967 /* PCC block interrupts. */
 968 #define PCC_FB_ECC_ERR     vBIT(0xff, 16, 8)    /* Interrupt to indicate
 969                                                    PCC_FB_ECC Error. */
 970
 971 #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
 972 /*
 973  * Prototype declaration.
 974  */
 975 static int __devinit s2io_init_nic(struct pci_dev *pdev,
 976                                    const struct pci_device_id *pre);
 977 static void __devexit s2io_rem_nic(struct pci_dev *pdev);
 978 static int init_shared_mem(struct s2io_nic *sp);
 979 static void free_shared_mem(struct s2io_nic *sp);
 980 static int init_nic(struct s2io_nic *nic);
 981 static void rx_intr_handler(struct ring_info *ring_data);
 982 static void tx_intr_handler(struct fifo_info *fifo_data);
 983 static void alarm_intr_handler(struct s2io_nic *sp);
 984
 985 static int s2io_starter(void);
 986 static void s2io_closer(void);
 987 static void s2io_tx_watchdog(struct net_device *dev);
 988 static void s2io_tasklet(unsigned long dev_addr);
 989 static void s2io_set_multicast(struct net_device *dev);
 990 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
 991 static void s2io_link(struct s2io_nic * sp, int link);
 992 static void s2io_reset(struct s2io_nic * sp);
 993 static int s2io_poll(struct net_device *dev, int *budget);
 994 static void s2io_init_pci(struct s2io_nic * sp);
 995 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
 996 static void s2io_alarm_handle(unsigned long data);
 997 static int s2io_enable_msi(struct s2io_nic *nic);
 998 static irqreturn_t s2io_msi_handle(int irq, void *dev_id);
 999 static irqreturn_t
1000 s2io_msix_ring_handle(int irq, void *dev_id);
1001 static irqreturn_t
1002 s2io_msix_fifo_handle(int irq, void *dev_id);
1003 static irqreturn_t s2io_isr(int irq, void *dev_id);
1004 static int verify_xena_quiescence(struct s2io_nic *sp);
1005 static const struct ethtool_ops netdev_ethtool_ops;
1006 static void s2io_set_link(struct work_struct *work);
1007 static int s2io_set_swapper(struct s2io_nic * sp);
1008 static void s2io_card_down(struct s2io_nic *nic);
1009 static int s2io_card_up(struct s2io_nic *nic);
1010 static int get_xena_rev_id(struct pci_dev *pdev);
1011 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1012                                         int bit_state);
1013 static int s2io_add_isr(struct s2io_nic * sp);
1014 static void s2io_rem_isr(struct s2io_nic * sp);
1015
1016 static void restore_xmsi_data(struct s2io_nic *nic);
1017
1018 static int
1019 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
1020                       struct RxD_t *rxdp, struct s2io_nic *sp);
1021 static void clear_lro_session(struct lro *lro);
1022 static void queue_rx_frame(struct sk_buff *skb);
1023 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1024 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1025                            struct sk_buff *skb, u32 tcp_len);
1026 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
1027
1028 #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1029 #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1030 #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1031
1032 #define S2IO_PARM_INT(X, def_val) \
1033         static unsigned int X = def_val;\
1034                 module_param(X , uint, 0);
1035
1036 #endif                          /* _S2IO_H */