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rt2x00: Align RT3572 channel switch RFCSR 1 programming with Ralink driver.
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
blob135e8a40edd3a49445edb35187771abc1c0142e6
1 /*
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 /*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89 {
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
114 {
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
146 {
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
170 {
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
201 {
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227 {
228 u32 reg;
229
230 /*
231 * SOC devices don't support MCU requests.
232 */
233 if (rt2x00_is_soc(rt2x00dev))
234 return;
235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255 }
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
257
258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259 {
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272 }
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276 {
277 unsigned int i;
278 u32 reg;
279
280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
290 msleep(10);
291 }
292
293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294 return -EACCES;
295 }
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299 {
300 u16 fw_crc;
301 u16 crc;
302
303 /*
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
306 * algorithm.
307 */
308 fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310 /*
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
316 */
317 crc = crc_ccitt(~0, data, len - 2);
318
319 /*
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
323 * value.
324 */
325 crc = swab16(crc);
326
327 return fw_crc == crc;
328 }
329
330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331 const u8 *data, const size_t len)
332 {
333 size_t offset = 0;
334 size_t fw_len;
335 bool multiple;
336
337 /*
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
344 */
345 if (rt2x00_is_usb(rt2x00dev)) {
346 fw_len = 4096;
347 multiple = true;
348 } else {
349 fw_len = 8192;
350 multiple = true;
351 }
352
353 /*
354 * Validate the firmware length
355 */
356 if (len != fw_len && (!multiple || (len % fw_len) != 0))
357 return FW_BAD_LENGTH;
358
359 /*
360 * Check if the chipset requires one of the upper parts
361 * of the firmware.
362 */
363 if (rt2x00_is_usb(rt2x00dev) &&
364 !rt2x00_rt(rt2x00dev, RT2860) &&
365 !rt2x00_rt(rt2x00dev, RT2872) &&
366 !rt2x00_rt(rt2x00dev, RT3070) &&
367 ((len / fw_len) == 1))
368 return FW_BAD_VERSION;
369
370 /*
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
373 */
374 while (offset < len) {
375 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376 return FW_BAD_CRC;
377
378 offset += fw_len;
379 }
380
381 return FW_OK;
382 }
383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386 const u8 *data, const size_t len)
387 {
388 unsigned int i;
389 u32 reg;
390
391 /*
392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
394 */
395 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
396
397 /*
398 * Wait for stable hardware.
399 */
400 if (rt2800_wait_csr_ready(rt2x00dev))
401 return -EBUSY;
402
403 if (rt2x00_is_pci(rt2x00dev)) {
404 if (rt2x00_rt(rt2x00dev, RT3572) ||
405 rt2x00_rt(rt2x00dev, RT5390)) {
406 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
407 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
408 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
409 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
410 }
411 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
412 }
413
414 /*
415 * Write firmware to the device.
416 */
417 rt2800_drv_write_firmware(rt2x00dev, data, len);
418
419 /*
420 * Wait for device to stabilize.
421 */
422 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
423 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
424 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
425 break;
426 msleep(1);
427 }
428
429 if (i == REGISTER_BUSY_COUNT) {
430 ERROR(rt2x00dev, "PBF system register not ready.\n");
431 return -EBUSY;
432 }
433
434 /*
435 * Disable DMA, will be reenabled later when enabling
436 * the radio.
437 */
438 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
439 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
440 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
441 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
442
443 /*
444 * Initialize firmware.
445 */
446 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
447 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
448 if (rt2x00_is_usb(rt2x00dev))
449 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
450 msleep(1);
451
452 return 0;
453 }
454 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
455
456 void rt2800_write_tx_data(struct queue_entry *entry,
457 struct txentry_desc *txdesc)
458 {
459 __le32 *txwi = rt2800_drv_get_txwi(entry);
460 u32 word;
461
462 /*
463 * Initialize TX Info descriptor
464 */
465 rt2x00_desc_read(txwi, 0, &word);
466 rt2x00_set_field32(&word, TXWI_W0_FRAG,
467 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
468 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
469 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
470 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
471 rt2x00_set_field32(&word, TXWI_W0_TS,
472 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
473 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
474 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
475 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
476 txdesc->u.ht.mpdu_density);
477 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
478 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
479 rt2x00_set_field32(&word, TXWI_W0_BW,
480 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
481 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
482 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
483 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
484 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
485 rt2x00_desc_write(txwi, 0, word);
486
487 rt2x00_desc_read(txwi, 1, &word);
488 rt2x00_set_field32(&word, TXWI_W1_ACK,
489 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
490 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
491 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
492 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
493 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
494 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
495 txdesc->key_idx : txdesc->u.ht.wcid);
496 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
497 txdesc->length);
498 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
499 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
500 rt2x00_desc_write(txwi, 1, word);
501
502 /*
503 * Always write 0 to IV/EIV fields, hardware will insert the IV
504 * from the IVEIV register when TXD_W3_WIV is set to 0.
505 * When TXD_W3_WIV is set to 1 it will use the IV data
506 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
507 * crypto entry in the registers should be used to encrypt the frame.
508 */
509 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
510 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
511 }
512 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
513
514 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
515 {
516 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
517 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
518 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
519 u16 eeprom;
520 u8 offset0;
521 u8 offset1;
522 u8 offset2;
523
524 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
525 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
526 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
527 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
528 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
529 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
530 } else {
531 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
532 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
533 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
534 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
535 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
536 }
537
538 /*
539 * Convert the value from the descriptor into the RSSI value
540 * If the value in the descriptor is 0, it is considered invalid
541 * and the default (extremely low) rssi value is assumed
542 */
543 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
544 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
545 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
546
547 /*
548 * mac80211 only accepts a single RSSI value. Calculating the
549 * average doesn't deliver a fair answer either since -60:-60 would
550 * be considered equally good as -50:-70 while the second is the one
551 * which gives less energy...
552 */
553 rssi0 = max(rssi0, rssi1);
554 return max(rssi0, rssi2);
555 }
556
557 void rt2800_process_rxwi(struct queue_entry *entry,
558 struct rxdone_entry_desc *rxdesc)
559 {
560 __le32 *rxwi = (__le32 *) entry->skb->data;
561 u32 word;
562
563 rt2x00_desc_read(rxwi, 0, &word);
564
565 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
566 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
567
568 rt2x00_desc_read(rxwi, 1, &word);
569
570 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
571 rxdesc->flags |= RX_FLAG_SHORT_GI;
572
573 if (rt2x00_get_field32(word, RXWI_W1_BW))
574 rxdesc->flags |= RX_FLAG_40MHZ;
575
576 /*
577 * Detect RX rate, always use MCS as signal type.
578 */
579 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
580 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
581 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
582
583 /*
584 * Mask of 0x8 bit to remove the short preamble flag.
585 */
586 if (rxdesc->rate_mode == RATE_MODE_CCK)
587 rxdesc->signal &= ~0x8;
588
589 rt2x00_desc_read(rxwi, 2, &word);
590
591 /*
592 * Convert descriptor AGC value to RSSI value.
593 */
594 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
595
596 /*
597 * Remove RXWI descriptor from start of buffer.
598 */
599 skb_pull(entry->skb, RXWI_DESC_SIZE);
600 }
601 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
602
603 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
604 {
605 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
606 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
607 struct txdone_entry_desc txdesc;
608 u32 word;
609 u16 mcs, real_mcs;
610 int aggr, ampdu;
611
612 /*
613 * Obtain the status about this packet.
614 */
615 txdesc.flags = 0;
616 rt2x00_desc_read(txwi, 0, &word);
617
618 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
619 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
620
621 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
622 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
623
624 /*
625 * If a frame was meant to be sent as a single non-aggregated MPDU
626 * but ended up in an aggregate the used tx rate doesn't correlate
627 * with the one specified in the TXWI as the whole aggregate is sent
628 * with the same rate.
629 *
630 * For example: two frames are sent to rt2x00, the first one sets
631 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
632 * and requests MCS15. If the hw aggregates both frames into one
633 * AMDPU the tx status for both frames will contain MCS7 although
634 * the frame was sent successfully.
635 *
636 * Hence, replace the requested rate with the real tx rate to not
637 * confuse the rate control algortihm by providing clearly wrong
638 * data.
639 */
640 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
641 skbdesc->tx_rate_idx = real_mcs;
642 mcs = real_mcs;
643 }
644
645 if (aggr == 1 || ampdu == 1)
646 __set_bit(TXDONE_AMPDU, &txdesc.flags);
647
648 /*
649 * Ralink has a retry mechanism using a global fallback
650 * table. We setup this fallback table to try the immediate
651 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
652 * always contains the MCS used for the last transmission, be
653 * it successful or not.
654 */
655 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
656 /*
657 * Transmission succeeded. The number of retries is
658 * mcs - real_mcs
659 */
660 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
661 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
662 } else {
663 /*
664 * Transmission failed. The number of retries is
665 * always 7 in this case (for a total number of 8
666 * frames sent).
667 */
668 __set_bit(TXDONE_FAILURE, &txdesc.flags);
669 txdesc.retry = rt2x00dev->long_retry;
670 }
671
672 /*
673 * the frame was retried at least once
674 * -> hw used fallback rates
675 */
676 if (txdesc.retry)
677 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
678
679 rt2x00lib_txdone(entry, &txdesc);
680 }
681 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
682
683 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
684 {
685 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
686 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
687 unsigned int beacon_base;
688 unsigned int padding_len;
689 u32 orig_reg, reg;
690
691 /*
692 * Disable beaconing while we are reloading the beacon data,
693 * otherwise we might be sending out invalid data.
694 */
695 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
696 orig_reg = reg;
697 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
698 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
699
700 /*
701 * Add space for the TXWI in front of the skb.
702 */
703 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
704
705 /*
706 * Register descriptor details in skb frame descriptor.
707 */
708 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
709 skbdesc->desc = entry->skb->data;
710 skbdesc->desc_len = TXWI_DESC_SIZE;
711
712 /*
713 * Add the TXWI for the beacon to the skb.
714 */
715 rt2800_write_tx_data(entry, txdesc);
716
717 /*
718 * Dump beacon to userspace through debugfs.
719 */
720 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
721
722 /*
723 * Write entire beacon with TXWI and padding to register.
724 */
725 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
726 if (padding_len && skb_pad(entry->skb, padding_len)) {
727 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
728 /* skb freed by skb_pad() on failure */
729 entry->skb = NULL;
730 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
731 return;
732 }
733
734 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
735 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
736 entry->skb->len + padding_len);
737
738 /*
739 * Enable beaconing again.
740 */
741 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
742 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
743
744 /*
745 * Clean up beacon skb.
746 */
747 dev_kfree_skb_any(entry->skb);
748 entry->skb = NULL;
749 }
750 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
751
752 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
753 unsigned int beacon_base)
754 {
755 int i;
756
757 /*
758 * For the Beacon base registers we only need to clear
759 * the whole TXWI which (when set to 0) will invalidate
760 * the entire beacon.
761 */
762 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
763 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
764 }
765
766 void rt2800_clear_beacon(struct queue_entry *entry)
767 {
768 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
769 u32 reg;
770
771 /*
772 * Disable beaconing while we are reloading the beacon data,
773 * otherwise we might be sending out invalid data.
774 */
775 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
776 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
777 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
778
779 /*
780 * Clear beacon.
781 */
782 rt2800_clear_beacon_register(rt2x00dev,
783 HW_BEACON_OFFSET(entry->entry_idx));
784
785 /*
786 * Enabled beaconing again.
787 */
788 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
789 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
790 }
791 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
792
793 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
794 const struct rt2x00debug rt2800_rt2x00debug = {
795 .owner = THIS_MODULE,
796 .csr = {
797 .read = rt2800_register_read,
798 .write = rt2800_register_write,
799 .flags = RT2X00DEBUGFS_OFFSET,
800 .word_base = CSR_REG_BASE,
801 .word_size = sizeof(u32),
802 .word_count = CSR_REG_SIZE / sizeof(u32),
803 },
804 .eeprom = {
805 .read = rt2x00_eeprom_read,
806 .write = rt2x00_eeprom_write,
807 .word_base = EEPROM_BASE,
808 .word_size = sizeof(u16),
809 .word_count = EEPROM_SIZE / sizeof(u16),
810 },
811 .bbp = {
812 .read = rt2800_bbp_read,
813 .write = rt2800_bbp_write,
814 .word_base = BBP_BASE,
815 .word_size = sizeof(u8),
816 .word_count = BBP_SIZE / sizeof(u8),
817 },
818 .rf = {
819 .read = rt2x00_rf_read,
820 .write = rt2800_rf_write,
821 .word_base = RF_BASE,
822 .word_size = sizeof(u32),
823 .word_count = RF_SIZE / sizeof(u32),
824 },
825 };
826 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
827 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
828
829 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
830 {
831 u32 reg;
832
833 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
834 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
835 }
836 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
837
838 #ifdef CONFIG_RT2X00_LIB_LEDS
839 static void rt2800_brightness_set(struct led_classdev *led_cdev,
840 enum led_brightness brightness)
841 {
842 struct rt2x00_led *led =
843 container_of(led_cdev, struct rt2x00_led, led_dev);
844 unsigned int enabled = brightness != LED_OFF;
845 unsigned int bg_mode =
846 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
847 unsigned int polarity =
848 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
849 EEPROM_FREQ_LED_POLARITY);
850 unsigned int ledmode =
851 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
852 EEPROM_FREQ_LED_MODE);
853 u32 reg;
854
855 /* Check for SoC (SOC devices don't support MCU requests) */
856 if (rt2x00_is_soc(led->rt2x00dev)) {
857 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
858
859 /* Set LED Polarity */
860 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
861
862 /* Set LED Mode */
863 if (led->type == LED_TYPE_RADIO) {
864 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
865 enabled ? 3 : 0);
866 } else if (led->type == LED_TYPE_ASSOC) {
867 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
868 enabled ? 3 : 0);
869 } else if (led->type == LED_TYPE_QUALITY) {
870 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
871 enabled ? 3 : 0);
872 }
873
874 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
875
876 } else {
877 if (led->type == LED_TYPE_RADIO) {
878 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
879 enabled ? 0x20 : 0);
880 } else if (led->type == LED_TYPE_ASSOC) {
881 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
882 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
883 } else if (led->type == LED_TYPE_QUALITY) {
884 /*
885 * The brightness is divided into 6 levels (0 - 5),
886 * The specs tell us the following levels:
887 * 0, 1 ,3, 7, 15, 31
888 * to determine the level in a simple way we can simply
889 * work with bitshifting:
890 * (1 << level) - 1
891 */
892 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
893 (1 << brightness / (LED_FULL / 6)) - 1,
894 polarity);
895 }
896 }
897 }
898
899 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
900 struct rt2x00_led *led, enum led_type type)
901 {
902 led->rt2x00dev = rt2x00dev;
903 led->type = type;
904 led->led_dev.brightness_set = rt2800_brightness_set;
905 led->flags = LED_INITIALIZED;
906 }
907 #endif /* CONFIG_RT2X00_LIB_LEDS */
908
909 /*
910 * Configuration handlers.
911 */
912 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
913 const u8 *address,
914 int wcid)
915 {
916 struct mac_wcid_entry wcid_entry;
917 u32 offset;
918
919 offset = MAC_WCID_ENTRY(wcid);
920
921 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
922 if (address)
923 memcpy(wcid_entry.mac, address, ETH_ALEN);
924
925 rt2800_register_multiwrite(rt2x00dev, offset,
926 &wcid_entry, sizeof(wcid_entry));
927 }
928
929 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
930 {
931 u32 offset;
932 offset = MAC_WCID_ATTR_ENTRY(wcid);
933 rt2800_register_write(rt2x00dev, offset, 0);
934 }
935
936 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
937 int wcid, u32 bssidx)
938 {
939 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
940 u32 reg;
941
942 /*
943 * The BSS Idx numbers is split in a main value of 3 bits,
944 * and a extended field for adding one additional bit to the value.
945 */
946 rt2800_register_read(rt2x00dev, offset, &reg);
947 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
948 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
949 (bssidx & 0x8) >> 3);
950 rt2800_register_write(rt2x00dev, offset, reg);
951 }
952
953 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
954 struct rt2x00lib_crypto *crypto,
955 struct ieee80211_key_conf *key)
956 {
957 struct mac_iveiv_entry iveiv_entry;
958 u32 offset;
959 u32 reg;
960
961 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
962
963 if (crypto->cmd == SET_KEY) {
964 rt2800_register_read(rt2x00dev, offset, &reg);
965 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
966 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
967 /*
968 * Both the cipher as the BSS Idx numbers are split in a main
969 * value of 3 bits, and a extended field for adding one additional
970 * bit to the value.
971 */
972 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
973 (crypto->cipher & 0x7));
974 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
975 (crypto->cipher & 0x8) >> 3);
976 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
977 rt2800_register_write(rt2x00dev, offset, reg);
978 } else {
979 /* Delete the cipher without touching the bssidx */
980 rt2800_register_read(rt2x00dev, offset, &reg);
981 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
982 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
983 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
984 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
985 rt2800_register_write(rt2x00dev, offset, reg);
986 }
987
988 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
989
990 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
991 if ((crypto->cipher == CIPHER_TKIP) ||
992 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
993 (crypto->cipher == CIPHER_AES))
994 iveiv_entry.iv[3] |= 0x20;
995 iveiv_entry.iv[3] |= key->keyidx << 6;
996 rt2800_register_multiwrite(rt2x00dev, offset,
997 &iveiv_entry, sizeof(iveiv_entry));
998 }
999
1000 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1001 struct rt2x00lib_crypto *crypto,
1002 struct ieee80211_key_conf *key)
1003 {
1004 struct hw_key_entry key_entry;
1005 struct rt2x00_field32 field;
1006 u32 offset;
1007 u32 reg;
1008
1009 if (crypto->cmd == SET_KEY) {
1010 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1011
1012 memcpy(key_entry.key, crypto->key,
1013 sizeof(key_entry.key));
1014 memcpy(key_entry.tx_mic, crypto->tx_mic,
1015 sizeof(key_entry.tx_mic));
1016 memcpy(key_entry.rx_mic, crypto->rx_mic,
1017 sizeof(key_entry.rx_mic));
1018
1019 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1020 rt2800_register_multiwrite(rt2x00dev, offset,
1021 &key_entry, sizeof(key_entry));
1022 }
1023
1024 /*
1025 * The cipher types are stored over multiple registers
1026 * starting with SHARED_KEY_MODE_BASE each word will have
1027 * 32 bits and contains the cipher types for 2 bssidx each.
1028 * Using the correct defines correctly will cause overhead,
1029 * so just calculate the correct offset.
1030 */
1031 field.bit_offset = 4 * (key->hw_key_idx % 8);
1032 field.bit_mask = 0x7 << field.bit_offset;
1033
1034 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1035
1036 rt2800_register_read(rt2x00dev, offset, &reg);
1037 rt2x00_set_field32(&reg, field,
1038 (crypto->cmd == SET_KEY) * crypto->cipher);
1039 rt2800_register_write(rt2x00dev, offset, reg);
1040
1041 /*
1042 * Update WCID information
1043 */
1044 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1045 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1046 crypto->bssidx);
1047 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1048
1049 return 0;
1050 }
1051 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1052
1053 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1054 {
1055 struct mac_wcid_entry wcid_entry;
1056 int idx;
1057 u32 offset;
1058
1059 /*
1060 * Search for the first free WCID entry and return the corresponding
1061 * index.
1062 *
1063 * Make sure the WCID starts _after_ the last possible shared key
1064 * entry (>32).
1065 *
1066 * Since parts of the pairwise key table might be shared with
1067 * the beacon frame buffers 6 & 7 we should only write into the
1068 * first 222 entries.
1069 */
1070 for (idx = 33; idx <= 222; idx++) {
1071 offset = MAC_WCID_ENTRY(idx);
1072 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1073 sizeof(wcid_entry));
1074 if (is_broadcast_ether_addr(wcid_entry.mac))
1075 return idx;
1076 }
1077
1078 /*
1079 * Use -1 to indicate that we don't have any more space in the WCID
1080 * table.
1081 */
1082 return -1;
1083 }
1084
1085 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1086 struct rt2x00lib_crypto *crypto,
1087 struct ieee80211_key_conf *key)
1088 {
1089 struct hw_key_entry key_entry;
1090 u32 offset;
1091
1092 if (crypto->cmd == SET_KEY) {
1093 /*
1094 * Allow key configuration only for STAs that are
1095 * known by the hw.
1096 */
1097 if (crypto->wcid < 0)
1098 return -ENOSPC;
1099 key->hw_key_idx = crypto->wcid;
1100
1101 memcpy(key_entry.key, crypto->key,
1102 sizeof(key_entry.key));
1103 memcpy(key_entry.tx_mic, crypto->tx_mic,
1104 sizeof(key_entry.tx_mic));
1105 memcpy(key_entry.rx_mic, crypto->rx_mic,
1106 sizeof(key_entry.rx_mic));
1107
1108 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1109 rt2800_register_multiwrite(rt2x00dev, offset,
1110 &key_entry, sizeof(key_entry));
1111 }
1112
1113 /*
1114 * Update WCID information
1115 */
1116 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1117
1118 return 0;
1119 }
1120 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1121
1122 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1123 struct ieee80211_sta *sta)
1124 {
1125 int wcid;
1126 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1127
1128 /*
1129 * Find next free WCID.
1130 */
1131 wcid = rt2800_find_wcid(rt2x00dev);
1132
1133 /*
1134 * Store selected wcid even if it is invalid so that we can
1135 * later decide if the STA is uploaded into the hw.
1136 */
1137 sta_priv->wcid = wcid;
1138
1139 /*
1140 * No space left in the device, however, we can still communicate
1141 * with the STA -> No error.
1142 */
1143 if (wcid < 0)
1144 return 0;
1145
1146 /*
1147 * Clean up WCID attributes and write STA address to the device.
1148 */
1149 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1150 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1151 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1152 rt2x00lib_get_bssidx(rt2x00dev, vif));
1153 return 0;
1154 }
1155 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1156
1157 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1158 {
1159 /*
1160 * Remove WCID entry, no need to clean the attributes as they will
1161 * get renewed when the WCID is reused.
1162 */
1163 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1164
1165 return 0;
1166 }
1167 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1168
1169 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1170 const unsigned int filter_flags)
1171 {
1172 u32 reg;
1173
1174 /*
1175 * Start configuration steps.
1176 * Note that the version error will always be dropped
1177 * and broadcast frames will always be accepted since
1178 * there is no filter for it at this time.
1179 */
1180 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1181 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1182 !(filter_flags & FIF_FCSFAIL));
1183 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1184 !(filter_flags & FIF_PLCPFAIL));
1185 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1186 !(filter_flags & FIF_PROMISC_IN_BSS));
1187 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1188 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1189 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1190 !(filter_flags & FIF_ALLMULTI));
1191 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1192 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1193 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1194 !(filter_flags & FIF_CONTROL));
1195 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1196 !(filter_flags & FIF_CONTROL));
1197 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1198 !(filter_flags & FIF_CONTROL));
1199 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1200 !(filter_flags & FIF_CONTROL));
1201 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1202 !(filter_flags & FIF_CONTROL));
1203 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1204 !(filter_flags & FIF_PSPOLL));
1205 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1206 !(filter_flags & FIF_CONTROL));
1207 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1208 !(filter_flags & FIF_CONTROL));
1209 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1210 !(filter_flags & FIF_CONTROL));
1211 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1212 }
1213 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1214
1215 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1216 struct rt2x00intf_conf *conf, const unsigned int flags)
1217 {
1218 u32 reg;
1219 bool update_bssid = false;
1220
1221 if (flags & CONFIG_UPDATE_TYPE) {
1222 /*
1223 * Enable synchronisation.
1224 */
1225 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1226 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1227 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1228
1229 if (conf->sync == TSF_SYNC_AP_NONE) {
1230 /*
1231 * Tune beacon queue transmit parameters for AP mode
1232 */
1233 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1234 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1235 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1236 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1237 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1238 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1239 } else {
1240 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1241 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1242 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1243 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1244 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1245 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1246 }
1247 }
1248
1249 if (flags & CONFIG_UPDATE_MAC) {
1250 if (flags & CONFIG_UPDATE_TYPE &&
1251 conf->sync == TSF_SYNC_AP_NONE) {
1252 /*
1253 * The BSSID register has to be set to our own mac
1254 * address in AP mode.
1255 */
1256 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1257 update_bssid = true;
1258 }
1259
1260 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1261 reg = le32_to_cpu(conf->mac[1]);
1262 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1263 conf->mac[1] = cpu_to_le32(reg);
1264 }
1265
1266 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1267 conf->mac, sizeof(conf->mac));
1268 }
1269
1270 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1271 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1272 reg = le32_to_cpu(conf->bssid[1]);
1273 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1274 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1275 conf->bssid[1] = cpu_to_le32(reg);
1276 }
1277
1278 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1279 conf->bssid, sizeof(conf->bssid));
1280 }
1281 }
1282 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1283
1284 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1285 struct rt2x00lib_erp *erp)
1286 {
1287 bool any_sta_nongf = !!(erp->ht_opmode &
1288 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1289 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1290 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1291 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1292 u32 reg;
1293
1294 /* default protection rate for HT20: OFDM 24M */
1295 mm20_rate = gf20_rate = 0x4004;
1296
1297 /* default protection rate for HT40: duplicate OFDM 24M */
1298 mm40_rate = gf40_rate = 0x4084;
1299
1300 switch (protection) {
1301 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1302 /*
1303 * All STAs in this BSS are HT20/40 but there might be
1304 * STAs not supporting greenfield mode.
1305 * => Disable protection for HT transmissions.
1306 */
1307 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1308
1309 break;
1310 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1311 /*
1312 * All STAs in this BSS are HT20 or HT20/40 but there
1313 * might be STAs not supporting greenfield mode.
1314 * => Protect all HT40 transmissions.
1315 */
1316 mm20_mode = gf20_mode = 0;
1317 mm40_mode = gf40_mode = 2;
1318
1319 break;
1320 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1321 /*
1322 * Nonmember protection:
1323 * According to 802.11n we _should_ protect all
1324 * HT transmissions (but we don't have to).
1325 *
1326 * But if cts_protection is enabled we _shall_ protect
1327 * all HT transmissions using a CCK rate.
1328 *
1329 * And if any station is non GF we _shall_ protect
1330 * GF transmissions.
1331 *
1332 * We decide to protect everything
1333 * -> fall through to mixed mode.
1334 */
1335 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1336 /*
1337 * Legacy STAs are present
1338 * => Protect all HT transmissions.
1339 */
1340 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1341
1342 /*
1343 * If erp protection is needed we have to protect HT
1344 * transmissions with CCK 11M long preamble.
1345 */
1346 if (erp->cts_protection) {
1347 /* don't duplicate RTS/CTS in CCK mode */
1348 mm20_rate = mm40_rate = 0x0003;
1349 gf20_rate = gf40_rate = 0x0003;
1350 }
1351 break;
1352 }
1353
1354 /* check for STAs not supporting greenfield mode */
1355 if (any_sta_nongf)
1356 gf20_mode = gf40_mode = 2;
1357
1358 /* Update HT protection config */
1359 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1360 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1361 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1362 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1363
1364 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1365 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1366 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1367 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1368
1369 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1370 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1371 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1372 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1373
1374 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1375 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1376 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1377 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1378 }
1379
1380 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1381 u32 changed)
1382 {
1383 u32 reg;
1384
1385 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1386 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1387 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1388 !!erp->short_preamble);
1389 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1390 !!erp->short_preamble);
1391 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1392 }
1393
1394 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1395 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1396 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1397 erp->cts_protection ? 2 : 0);
1398 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1399 }
1400
1401 if (changed & BSS_CHANGED_BASIC_RATES) {
1402 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1403 erp->basic_rates);
1404 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1405 }
1406
1407 if (changed & BSS_CHANGED_ERP_SLOT) {
1408 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1409 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1410 erp->slot_time);
1411 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1412
1413 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1414 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1415 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1416 }
1417
1418 if (changed & BSS_CHANGED_BEACON_INT) {
1419 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1420 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1421 erp->beacon_int * 16);
1422 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1423 }
1424
1425 if (changed & BSS_CHANGED_HT)
1426 rt2800_config_ht_opmode(rt2x00dev, erp);
1427 }
1428 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1429
1430 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1431 {
1432 u32 reg;
1433 u16 eeprom;
1434 u8 led_ctrl, led_g_mode, led_r_mode;
1435
1436 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1437 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1438 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1439 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1440 } else {
1441 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1442 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1443 }
1444 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1445
1446 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1447 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1448 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1449 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1450 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1451 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1452 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1453 if (led_ctrl == 0 || led_ctrl > 0x40) {
1454 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1455 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1456 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1457 } else {
1458 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1459 (led_g_mode << 2) | led_r_mode, 1);
1460 }
1461 }
1462 }
1463
1464 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1465 enum antenna ant)
1466 {
1467 u32 reg;
1468 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1469 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1470
1471 if (rt2x00_is_pci(rt2x00dev)) {
1472 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1473 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1474 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1475 } else if (rt2x00_is_usb(rt2x00dev))
1476 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1477 eesk_pin, 0);
1478
1479 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1480 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1481 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1482 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1483 }
1484
1485 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1486 {
1487 u8 r1;
1488 u8 r3;
1489 u16 eeprom;
1490
1491 rt2800_bbp_read(rt2x00dev, 1, &r1);
1492 rt2800_bbp_read(rt2x00dev, 3, &r3);
1493
1494 if (rt2x00_rt(rt2x00dev, RT3572) &&
1495 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1496 rt2800_config_3572bt_ant(rt2x00dev);
1497
1498 /*
1499 * Configure the TX antenna.
1500 */
1501 switch (ant->tx_chain_num) {
1502 case 1:
1503 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1504 break;
1505 case 2:
1506 if (rt2x00_rt(rt2x00dev, RT3572) &&
1507 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1508 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1509 else
1510 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1511 break;
1512 case 3:
1513 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1514 break;
1515 }
1516
1517 /*
1518 * Configure the RX antenna.
1519 */
1520 switch (ant->rx_chain_num) {
1521 case 1:
1522 if (rt2x00_rt(rt2x00dev, RT3070) ||
1523 rt2x00_rt(rt2x00dev, RT3090) ||
1524 rt2x00_rt(rt2x00dev, RT3390)) {
1525 rt2x00_eeprom_read(rt2x00dev,
1526 EEPROM_NIC_CONF1, &eeprom);
1527 if (rt2x00_get_field16(eeprom,
1528 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1529 rt2800_set_ant_diversity(rt2x00dev,
1530 rt2x00dev->default_ant.rx);
1531 }
1532 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1533 break;
1534 case 2:
1535 if (rt2x00_rt(rt2x00dev, RT3572) &&
1536 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1537 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1538 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1539 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1540 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1541 } else {
1542 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1543 }
1544 break;
1545 case 3:
1546 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1547 break;
1548 }
1549
1550 rt2800_bbp_write(rt2x00dev, 3, r3);
1551 rt2800_bbp_write(rt2x00dev, 1, r1);
1552 }
1553 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1554
1555 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1556 struct rt2x00lib_conf *libconf)
1557 {
1558 u16 eeprom;
1559 short lna_gain;
1560
1561 if (libconf->rf.channel <= 14) {
1562 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1563 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1564 } else if (libconf->rf.channel <= 64) {
1565 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1566 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1567 } else if (libconf->rf.channel <= 128) {
1568 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1569 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1570 } else {
1571 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1572 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1573 }
1574
1575 rt2x00dev->lna_gain = lna_gain;
1576 }
1577
1578 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1579 struct ieee80211_conf *conf,
1580 struct rf_channel *rf,
1581 struct channel_info *info)
1582 {
1583 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1584
1585 if (rt2x00dev->default_ant.tx_chain_num == 1)
1586 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1587
1588 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1589 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1590 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1591 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1592 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1593
1594 if (rf->channel > 14) {
1595 /*
1596 * When TX power is below 0, we should increase it by 7 to
1597 * make it a positive value (Minimum value is -7).
1598 * However this means that values between 0 and 7 have
1599 * double meaning, and we should set a 7DBm boost flag.
1600 */
1601 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1602 (info->default_power1 >= 0));
1603
1604 if (info->default_power1 < 0)
1605 info->default_power1 += 7;
1606
1607 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1608
1609 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1610 (info->default_power2 >= 0));
1611
1612 if (info->default_power2 < 0)
1613 info->default_power2 += 7;
1614
1615 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1616 } else {
1617 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1618 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1619 }
1620
1621 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1622
1623 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1624 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1625 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1626 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1627
1628 udelay(200);
1629
1630 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1631 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1632 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1633 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1634
1635 udelay(200);
1636
1637 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1638 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1639 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1640 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1641 }
1642
1643 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1644 struct ieee80211_conf *conf,
1645 struct rf_channel *rf,
1646 struct channel_info *info)
1647 {
1648 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1649 u8 rfcsr, calib_tx, calib_rx;
1650
1651 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1652
1653 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1654 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1655 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1656
1657 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1658 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1659 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1660
1661 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1662 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1663 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1664
1665 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1666 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1667 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1668
1669 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1670 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1671 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1672 if (rt2x00_rt(rt2x00dev, RT3390)) {
1673 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1674 rt2x00dev->default_ant.rx_chain_num == 1);
1675 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1676 rt2x00dev->default_ant.tx_chain_num == 1);
1677 } else {
1678 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1679 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1680 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1681 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1682
1683 switch (rt2x00dev->default_ant.tx_chain_num) {
1684 case 1:
1685 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1686 /* fall through */
1687 case 2:
1688 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1689 break;
1690 }
1691
1692 switch (rt2x00dev->default_ant.rx_chain_num) {
1693 case 1:
1694 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1695 /* fall through */
1696 case 2:
1697 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1698 break;
1699 }
1700 }
1701 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1702
1703 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1704 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1705 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1706 msleep(1);
1707 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1708 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1709
1710 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1711 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1712 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1713
1714 if (rt2x00_rt(rt2x00dev, RT3390)) {
1715 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1716 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1717 } else {
1718 if (conf_is_ht40(conf)) {
1719 calib_tx = drv_data->calibration_bw40;
1720 calib_rx = drv_data->calibration_bw40;
1721 } else {
1722 calib_tx = drv_data->calibration_bw20;
1723 calib_rx = drv_data->calibration_bw20;
1724 }
1725 }
1726
1727 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1728 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1729 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1730
1731 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1732 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1733 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1734
1735 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1736 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1737 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1738
1739 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1740 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1741 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1742 msleep(1);
1743 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1744 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1745 }
1746
1747 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1748 struct ieee80211_conf *conf,
1749 struct rf_channel *rf,
1750 struct channel_info *info)
1751 {
1752 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1753 u8 rfcsr;
1754 u32 reg;
1755
1756 if (rf->channel <= 14) {
1757 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1758 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1759 } else {
1760 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1761 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1762 }
1763
1764 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1765 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1766
1767 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1768 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1769 if (rf->channel <= 14)
1770 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1771 else
1772 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1773 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1774
1775 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1776 if (rf->channel <= 14)
1777 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1778 else
1779 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1780 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1781
1782 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1783 if (rf->channel <= 14) {
1784 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1785 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1786 info->default_power1);
1787 } else {
1788 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1789 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1790 (info->default_power1 & 0x3) |
1791 ((info->default_power1 & 0xC) << 1));
1792 }
1793 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1794
1795 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1796 if (rf->channel <= 14) {
1797 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1798 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1799 info->default_power2);
1800 } else {
1801 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1802 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1803 (info->default_power2 & 0x3) |
1804 ((info->default_power2 & 0xC) << 1));
1805 }
1806 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1807
1808 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1809 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1810 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1811 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1812 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1813 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1814 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1815 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1816 if (rf->channel <= 14) {
1817 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1818 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1819 }
1820 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1821 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1822 } else {
1823 switch (rt2x00dev->default_ant.tx_chain_num) {
1824 case 1:
1825 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1826 case 2:
1827 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1828 break;
1829 }
1830
1831 switch (rt2x00dev->default_ant.rx_chain_num) {
1832 case 1:
1833 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1834 case 2:
1835 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1836 break;
1837 }
1838 }
1839 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1840
1841 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1842 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1843 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1844
1845 if (conf_is_ht40(conf)) {
1846 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1847 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1848 } else {
1849 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1850 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1851 }
1852
1853 if (rf->channel <= 14) {
1854 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1855 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1856 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1857 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1858 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1859 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
1860 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1861 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1862 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1863 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1864 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1865 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1866 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1867 } else {
1868 rt2800_rfcsr_write(rt2x00dev, 7, 0x14);
1869 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1870 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1871 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1872 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1873 rt2800_rfcsr_write(rt2x00dev, 16, 0x7a);
1874 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1875 if (rf->channel <= 64) {
1876 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1877 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1878 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1879 } else if (rf->channel <= 128) {
1880 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1881 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1882 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1883 } else {
1884 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1885 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1886 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1887 }
1888 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1889 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1890 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1891 }
1892
1893 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1894 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1895 if (rf->channel <= 14)
1896 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1897 else
1898 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1899 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1900
1901 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1902 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1903 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1904 }
1905
1906 #define RT5390_POWER_BOUND 0x27
1907 #define RT5390_FREQ_OFFSET_BOUND 0x5f
1908
1909 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1910 struct ieee80211_conf *conf,
1911 struct rf_channel *rf,
1912 struct channel_info *info)
1913 {
1914 u8 rfcsr;
1915
1916 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1917 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1918 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1919 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1920 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1921
1922 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1923 if (info->default_power1 > RT5390_POWER_BOUND)
1924 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1925 else
1926 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1927 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1928
1929 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1930 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1931 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1932 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1933 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1934 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1935
1936 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1937 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1938 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1939 RT5390_FREQ_OFFSET_BOUND);
1940 else
1941 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1942 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1943
1944 if (rf->channel <= 14) {
1945 int idx = rf->channel-1;
1946
1947 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1948 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1949 /* r55/r59 value array of channel 1~14 */
1950 static const char r55_bt_rev[] = {0x83, 0x83,
1951 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1952 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1953 static const char r59_bt_rev[] = {0x0e, 0x0e,
1954 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1955 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1956
1957 rt2800_rfcsr_write(rt2x00dev, 55,
1958 r55_bt_rev[idx]);
1959 rt2800_rfcsr_write(rt2x00dev, 59,
1960 r59_bt_rev[idx]);
1961 } else {
1962 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1963 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1964 0x88, 0x88, 0x86, 0x85, 0x84};
1965
1966 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1967 }
1968 } else {
1969 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1970 static const char r55_nonbt_rev[] = {0x23, 0x23,
1971 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1972 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1973 static const char r59_nonbt_rev[] = {0x07, 0x07,
1974 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1975 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1976
1977 rt2800_rfcsr_write(rt2x00dev, 55,
1978 r55_nonbt_rev[idx]);
1979 rt2800_rfcsr_write(rt2x00dev, 59,
1980 r59_nonbt_rev[idx]);
1981 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1982 static const char r59_non_bt[] = {0x8f, 0x8f,
1983 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1984 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1985
1986 rt2800_rfcsr_write(rt2x00dev, 59,
1987 r59_non_bt[idx]);
1988 }
1989 }
1990 }
1991
1992 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1993 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1994 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1995 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1996
1997 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1998 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1999 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2000 }
2001
2002 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2003 struct ieee80211_conf *conf,
2004 struct rf_channel *rf,
2005 struct channel_info *info)
2006 {
2007 u32 reg;
2008 unsigned int tx_pin;
2009 u8 bbp;
2010
2011 if (rf->channel <= 14) {
2012 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2013 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2014 } else {
2015 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2016 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2017 }
2018
2019 switch (rt2x00dev->chip.rf) {
2020 case RF2020:
2021 case RF3020:
2022 case RF3021:
2023 case RF3022:
2024 case RF3320:
2025 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2026 break;
2027 case RF3052:
2028 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2029 break;
2030 case RF5370:
2031 case RF5390:
2032 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2033 break;
2034 default:
2035 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2036 }
2037
2038 /*
2039 * Change BBP settings
2040 */
2041 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2042 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2043 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2044 rt2800_bbp_write(rt2x00dev, 86, 0);
2045
2046 if (rf->channel <= 14) {
2047 if (!rt2x00_rt(rt2x00dev, RT5390)) {
2048 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2049 &rt2x00dev->cap_flags)) {
2050 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2051 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2052 } else {
2053 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2054 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2055 }
2056 }
2057 } else {
2058 if (rt2x00_rt(rt2x00dev, RT3572))
2059 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2060 else
2061 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2062
2063 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2064 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2065 else
2066 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2067 }
2068
2069 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2070 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2071 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2072 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2073 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2074
2075 if (rt2x00_rt(rt2x00dev, RT3572))
2076 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2077
2078 tx_pin = 0;
2079
2080 /* Turn on unused PA or LNA when not using 1T or 1R */
2081 if (rt2x00dev->default_ant.tx_chain_num == 2) {
2082 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2083 rf->channel > 14);
2084 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2085 rf->channel <= 14);
2086 }
2087
2088 /* Turn on unused PA or LNA when not using 1T or 1R */
2089 if (rt2x00dev->default_ant.rx_chain_num == 2) {
2090 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2091 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2092 }
2093
2094 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2095 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2096 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2097 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2098 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2099 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2100 else
2101 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2102 rf->channel <= 14);
2103 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2104
2105 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2106
2107 if (rt2x00_rt(rt2x00dev, RT3572))
2108 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2109
2110 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2111 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2112 rt2800_bbp_write(rt2x00dev, 4, bbp);
2113
2114 rt2800_bbp_read(rt2x00dev, 3, &bbp);
2115 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2116 rt2800_bbp_write(rt2x00dev, 3, bbp);
2117
2118 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2119 if (conf_is_ht40(conf)) {
2120 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2121 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2122 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2123 } else {
2124 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2125 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2126 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2127 }
2128 }
2129
2130 msleep(1);
2131
2132 /*
2133 * Clear channel statistic counters
2134 */
2135 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2136 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2137 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2138 }
2139
2140 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2141 {
2142 u8 tssi_bounds[9];
2143 u8 current_tssi;
2144 u16 eeprom;
2145 u8 step;
2146 int i;
2147
2148 /*
2149 * Read TSSI boundaries for temperature compensation from
2150 * the EEPROM.
2151 *
2152 * Array idx 0 1 2 3 4 5 6 7 8
2153 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2154 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2155 */
2156 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2157 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2158 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2159 EEPROM_TSSI_BOUND_BG1_MINUS4);
2160 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2161 EEPROM_TSSI_BOUND_BG1_MINUS3);
2162
2163 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2164 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2165 EEPROM_TSSI_BOUND_BG2_MINUS2);
2166 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2167 EEPROM_TSSI_BOUND_BG2_MINUS1);
2168
2169 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2170 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2171 EEPROM_TSSI_BOUND_BG3_REF);
2172 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2173 EEPROM_TSSI_BOUND_BG3_PLUS1);
2174
2175 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2176 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2177 EEPROM_TSSI_BOUND_BG4_PLUS2);
2178 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2179 EEPROM_TSSI_BOUND_BG4_PLUS3);
2180
2181 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2182 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2183 EEPROM_TSSI_BOUND_BG5_PLUS4);
2184
2185 step = rt2x00_get_field16(eeprom,
2186 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2187 } else {
2188 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2189 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2190 EEPROM_TSSI_BOUND_A1_MINUS4);
2191 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2192 EEPROM_TSSI_BOUND_A1_MINUS3);
2193
2194 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2195 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2196 EEPROM_TSSI_BOUND_A2_MINUS2);
2197 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2198 EEPROM_TSSI_BOUND_A2_MINUS1);
2199
2200 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2201 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2202 EEPROM_TSSI_BOUND_A3_REF);
2203 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2204 EEPROM_TSSI_BOUND_A3_PLUS1);
2205
2206 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2207 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2208 EEPROM_TSSI_BOUND_A4_PLUS2);
2209 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2210 EEPROM_TSSI_BOUND_A4_PLUS3);
2211
2212 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2213 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2214 EEPROM_TSSI_BOUND_A5_PLUS4);
2215
2216 step = rt2x00_get_field16(eeprom,
2217 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2218 }
2219
2220 /*
2221 * Check if temperature compensation is supported.
2222 */
2223 if (tssi_bounds[4] == 0xff)
2224 return 0;
2225
2226 /*
2227 * Read current TSSI (BBP 49).
2228 */
2229 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2230
2231 /*
2232 * Compare TSSI value (BBP49) with the compensation boundaries
2233 * from the EEPROM and increase or decrease tx power.
2234 */
2235 for (i = 0; i <= 3; i++) {
2236 if (current_tssi > tssi_bounds[i])
2237 break;
2238 }
2239
2240 if (i == 4) {
2241 for (i = 8; i >= 5; i--) {
2242 if (current_tssi < tssi_bounds[i])
2243 break;
2244 }
2245 }
2246
2247 return (i - 4) * step;
2248 }
2249
2250 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2251 enum ieee80211_band band)
2252 {
2253 u16 eeprom;
2254 u8 comp_en;
2255 u8 comp_type;
2256 int comp_value = 0;
2257
2258 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2259
2260 /*
2261 * HT40 compensation not required.
2262 */
2263 if (eeprom == 0xffff ||
2264 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2265 return 0;
2266
2267 if (band == IEEE80211_BAND_2GHZ) {
2268 comp_en = rt2x00_get_field16(eeprom,
2269 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2270 if (comp_en) {
2271 comp_type = rt2x00_get_field16(eeprom,
2272 EEPROM_TXPOWER_DELTA_TYPE_2G);
2273 comp_value = rt2x00_get_field16(eeprom,
2274 EEPROM_TXPOWER_DELTA_VALUE_2G);
2275 if (!comp_type)
2276 comp_value = -comp_value;
2277 }
2278 } else {
2279 comp_en = rt2x00_get_field16(eeprom,
2280 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2281 if (comp_en) {
2282 comp_type = rt2x00_get_field16(eeprom,
2283 EEPROM_TXPOWER_DELTA_TYPE_5G);
2284 comp_value = rt2x00_get_field16(eeprom,
2285 EEPROM_TXPOWER_DELTA_VALUE_5G);
2286 if (!comp_type)
2287 comp_value = -comp_value;
2288 }
2289 }
2290
2291 return comp_value;
2292 }
2293
2294 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2295 enum ieee80211_band band, int power_level,
2296 u8 txpower, int delta)
2297 {
2298 u32 reg;
2299 u16 eeprom;
2300 u8 criterion;
2301 u8 eirp_txpower;
2302 u8 eirp_txpower_criterion;
2303 u8 reg_limit;
2304
2305 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2306 return txpower;
2307
2308 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2309 /*
2310 * Check if eirp txpower exceed txpower_limit.
2311 * We use OFDM 6M as criterion and its eirp txpower
2312 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2313 * .11b data rate need add additional 4dbm
2314 * when calculating eirp txpower.
2315 */
2316 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2317 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2318
2319 rt2x00_eeprom_read(rt2x00dev,
2320 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2321
2322 if (band == IEEE80211_BAND_2GHZ)
2323 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2324 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2325 else
2326 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2327 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2328
2329 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2330 (is_rate_b ? 4 : 0) + delta;
2331
2332 reg_limit = (eirp_txpower > power_level) ?
2333 (eirp_txpower - power_level) : 0;
2334 } else
2335 reg_limit = 0;
2336
2337 return txpower + delta - reg_limit;
2338 }
2339
2340 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2341 enum ieee80211_band band,
2342 int power_level)
2343 {
2344 u8 txpower;
2345 u16 eeprom;
2346 int i, is_rate_b;
2347 u32 reg;
2348 u8 r1;
2349 u32 offset;
2350 int delta;
2351
2352 /*
2353 * Calculate HT40 compensation delta
2354 */
2355 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2356
2357 /*
2358 * calculate temperature compensation delta
2359 */
2360 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2361
2362 /*
2363 * set to normal bbp tx power control mode: +/- 0dBm
2364 */
2365 rt2800_bbp_read(rt2x00dev, 1, &r1);
2366 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2367 rt2800_bbp_write(rt2x00dev, 1, r1);
2368 offset = TX_PWR_CFG_0;
2369
2370 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2371 /* just to be safe */
2372 if (offset > TX_PWR_CFG_4)
2373 break;
2374
2375 rt2800_register_read(rt2x00dev, offset, &reg);
2376
2377 /* read the next four txpower values */
2378 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2379 &eeprom);
2380
2381 is_rate_b = i ? 0 : 1;
2382 /*
2383 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2384 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2385 * TX_PWR_CFG_4: unknown
2386 */
2387 txpower = rt2x00_get_field16(eeprom,
2388 EEPROM_TXPOWER_BYRATE_RATE0);
2389 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2390 power_level, txpower, delta);
2391 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2392
2393 /*
2394 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2395 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2396 * TX_PWR_CFG_4: unknown
2397 */
2398 txpower = rt2x00_get_field16(eeprom,
2399 EEPROM_TXPOWER_BYRATE_RATE1);
2400 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2401 power_level, txpower, delta);
2402 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2403
2404 /*
2405 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2406 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
2407 * TX_PWR_CFG_4: unknown
2408 */
2409 txpower = rt2x00_get_field16(eeprom,
2410 EEPROM_TXPOWER_BYRATE_RATE2);
2411 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2412 power_level, txpower, delta);
2413 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2414
2415 /*
2416 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2417 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
2418 * TX_PWR_CFG_4: unknown
2419 */
2420 txpower = rt2x00_get_field16(eeprom,
2421 EEPROM_TXPOWER_BYRATE_RATE3);
2422 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2423 power_level, txpower, delta);
2424 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2425
2426 /* read the next four txpower values */
2427 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2428 &eeprom);
2429
2430 is_rate_b = 0;
2431 /*
2432 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2433 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2434 * TX_PWR_CFG_4: unknown
2435 */
2436 txpower = rt2x00_get_field16(eeprom,
2437 EEPROM_TXPOWER_BYRATE_RATE0);
2438 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2439 power_level, txpower, delta);
2440 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2441
2442 /*
2443 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2444 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2445 * TX_PWR_CFG_4: unknown
2446 */
2447 txpower = rt2x00_get_field16(eeprom,
2448 EEPROM_TXPOWER_BYRATE_RATE1);
2449 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2450 power_level, txpower, delta);
2451 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2452
2453 /*
2454 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2455 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2456 * TX_PWR_CFG_4: unknown
2457 */
2458 txpower = rt2x00_get_field16(eeprom,
2459 EEPROM_TXPOWER_BYRATE_RATE2);
2460 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2461 power_level, txpower, delta);
2462 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2463
2464 /*
2465 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2466 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2467 * TX_PWR_CFG_4: unknown
2468 */
2469 txpower = rt2x00_get_field16(eeprom,
2470 EEPROM_TXPOWER_BYRATE_RATE3);
2471 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2472 power_level, txpower, delta);
2473 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2474
2475 rt2800_register_write(rt2x00dev, offset, reg);
2476
2477 /* next TX_PWR_CFG register */
2478 offset += 4;
2479 }
2480 }
2481
2482 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2483 {
2484 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2485 rt2x00dev->tx_power);
2486 }
2487 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2488
2489 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2490 struct rt2x00lib_conf *libconf)
2491 {
2492 u32 reg;
2493
2494 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2495 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2496 libconf->conf->short_frame_max_tx_count);
2497 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2498 libconf->conf->long_frame_max_tx_count);
2499 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2500 }
2501
2502 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2503 struct rt2x00lib_conf *libconf)
2504 {
2505 enum dev_state state =
2506 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2507 STATE_SLEEP : STATE_AWAKE;
2508 u32 reg;
2509
2510 if (state == STATE_SLEEP) {
2511 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2512
2513 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2514 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2515 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2516 libconf->conf->listen_interval - 1);
2517 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2518 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2519
2520 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2521 } else {
2522 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2523 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2524 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2525 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2526 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2527
2528 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2529 }
2530 }
2531
2532 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2533 struct rt2x00lib_conf *libconf,
2534 const unsigned int flags)
2535 {
2536 /* Always recalculate LNA gain before changing configuration */
2537 rt2800_config_lna_gain(rt2x00dev, libconf);
2538
2539 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2540 rt2800_config_channel(rt2x00dev, libconf->conf,
2541 &libconf->rf, &libconf->channel);
2542 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2543 libconf->conf->power_level);
2544 }
2545 if (flags & IEEE80211_CONF_CHANGE_POWER)
2546 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2547 libconf->conf->power_level);
2548 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2549 rt2800_config_retry_limit(rt2x00dev, libconf);
2550 if (flags & IEEE80211_CONF_CHANGE_PS)
2551 rt2800_config_ps(rt2x00dev, libconf);
2552 }
2553 EXPORT_SYMBOL_GPL(rt2800_config);
2554
2555 /*
2556 * Link tuning
2557 */
2558 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2559 {
2560 u32 reg;
2561
2562 /*
2563 * Update FCS error count from register.
2564 */
2565 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2566 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2567 }
2568 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2569
2570 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2571 {
2572 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2573 if (rt2x00_rt(rt2x00dev, RT3070) ||
2574 rt2x00_rt(rt2x00dev, RT3071) ||
2575 rt2x00_rt(rt2x00dev, RT3090) ||
2576 rt2x00_rt(rt2x00dev, RT3390) ||
2577 rt2x00_rt(rt2x00dev, RT5390))
2578 return 0x1c + (2 * rt2x00dev->lna_gain);
2579 else
2580 return 0x2e + rt2x00dev->lna_gain;
2581 }
2582
2583 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2584 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2585 else
2586 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2587 }
2588
2589 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2590 struct link_qual *qual, u8 vgc_level)
2591 {
2592 if (qual->vgc_level != vgc_level) {
2593 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2594 qual->vgc_level = vgc_level;
2595 qual->vgc_level_reg = vgc_level;
2596 }
2597 }
2598
2599 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2600 {
2601 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2602 }
2603 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2604
2605 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2606 const u32 count)
2607 {
2608 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2609 return;
2610
2611 /*
2612 * When RSSI is better then -80 increase VGC level with 0x10
2613 */
2614 rt2800_set_vgc(rt2x00dev, qual,
2615 rt2800_get_default_vgc(rt2x00dev) +
2616 ((qual->rssi > -80) * 0x10));
2617 }
2618 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2619
2620 /*
2621 * Initialization functions.
2622 */
2623 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2624 {
2625 u32 reg;
2626 u16 eeprom;
2627 unsigned int i;
2628 int ret;
2629
2630 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2631 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2632 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2633 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2634 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2635 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2636 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2637
2638 ret = rt2800_drv_init_registers(rt2x00dev);
2639 if (ret)
2640 return ret;
2641
2642 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2643 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2644 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2645 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2646 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2647 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2648
2649 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2650 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2651 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2652 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2653 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2654 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2655
2656 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2657 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2658
2659 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2660
2661 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2662 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2663 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2664 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2665 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2666 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2667 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2668 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2669
2670 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2671
2672 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2673 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2674 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2675 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2676
2677 if (rt2x00_rt(rt2x00dev, RT3071) ||
2678 rt2x00_rt(rt2x00dev, RT3090) ||
2679 rt2x00_rt(rt2x00dev, RT3390)) {
2680 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2681 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2682 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2683 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2684 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2685 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2686 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2687 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2688 0x0000002c);
2689 else
2690 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2691 0x0000000f);
2692 } else {
2693 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2694 }
2695 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2696 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2697
2698 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2699 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2700 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2701 } else {
2702 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2703 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2704 }
2705 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2706 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2707 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2708 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2709 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2710 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2711 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2712 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2713 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2714 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2715 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2716 } else {
2717 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2718 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2719 }
2720
2721 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2722 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2723 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2724 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2725 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2726 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2727 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2728 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2729 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2730 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2731
2732 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2733 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2734 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2735 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2736 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2737
2738 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2739 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2740 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2741 rt2x00_rt(rt2x00dev, RT2883) ||
2742 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2743 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2744 else
2745 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2746 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2747 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2748 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2749
2750 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2751 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2752 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2753 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2754 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2755 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2756 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2757 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2758 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2759
2760 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2761
2762 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2763 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2764 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2765 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2766 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2767 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2768 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2769 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2770
2771 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2772 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2773 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2774 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2775 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2776 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2777 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2778 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2779 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2780
2781 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2782 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2783 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2784 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2785 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2786 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2787 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2788 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2789 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2790 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2791 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2792 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2793
2794 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2795 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2796 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2797 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2798 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2799 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2800 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2801 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2802 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2803 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2804 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2805 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2806
2807 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2808 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2809 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2810 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2811 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2812 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2813 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2814 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2815 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2816 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2817 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2818 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2819
2820 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2821 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2822 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2823 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2824 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2825 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2826 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2827 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2828 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2829 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2830 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2831 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2832
2833 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2834 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2835 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2836 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2837 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2838 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2839 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2840 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2841 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2842 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2843 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2844 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2845
2846 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2847 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2848 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2849 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2850 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2851 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2852 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2853 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2854 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2855 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2856 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2857 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2858
2859 if (rt2x00_is_usb(rt2x00dev)) {
2860 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2861
2862 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2863 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2864 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2865 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2866 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2867 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2868 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2869 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2870 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2871 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2872 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2873 }
2874
2875 /*
2876 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2877 * although it is reserved.
2878 */
2879 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2880 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2881 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2882 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2883 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2884 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2885 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2886 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2887 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2888 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2889 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2890 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2891
2892 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2893
2894 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2895 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2896 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2897 IEEE80211_MAX_RTS_THRESHOLD);
2898 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2899 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2900
2901 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2902
2903 /*
2904 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2905 * time should be set to 16. However, the original Ralink driver uses
2906 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2907 * connection problems with 11g + CTS protection. Hence, use the same
2908 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2909 */
2910 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2911 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2912 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2913 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2914 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2915 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2916 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2917
2918 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2919
2920 /*
2921 * ASIC will keep garbage value after boot, clear encryption keys.
2922 */
2923 for (i = 0; i < 4; i++)
2924 rt2800_register_write(rt2x00dev,
2925 SHARED_KEY_MODE_ENTRY(i), 0);
2926
2927 for (i = 0; i < 256; i++) {
2928 rt2800_config_wcid(rt2x00dev, NULL, i);
2929 rt2800_delete_wcid_attr(rt2x00dev, i);
2930 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2931 }
2932
2933 /*
2934 * Clear all beacons
2935 */
2936 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2937 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2938 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2939 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2940 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2941 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2942 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2943 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2944
2945 if (rt2x00_is_usb(rt2x00dev)) {
2946 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2947 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2948 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2949 } else if (rt2x00_is_pcie(rt2x00dev)) {
2950 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2951 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2952 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2953 }
2954
2955 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2956 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2957 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2958 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2959 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2960 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2961 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2962 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2963 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2964 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2965
2966 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2967 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2968 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2969 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2970 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2971 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2972 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2973 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2974 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2975 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2976
2977 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2978 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2979 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2980 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2981 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2982 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2983 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2984 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2985 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2986 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2987
2988 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2989 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2990 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2991 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2992 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2993 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2994
2995 /*
2996 * Do not force the BA window size, we use the TXWI to set it
2997 */
2998 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2999 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3000 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3001 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3002
3003 /*
3004 * We must clear the error counters.
3005 * These registers are cleared on read,
3006 * so we may pass a useless variable to store the value.
3007 */
3008 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3009 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3010 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3011 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3012 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3013 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3014
3015 /*
3016 * Setup leadtime for pre tbtt interrupt to 6ms
3017 */
3018 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3019 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3020 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3021
3022 /*
3023 * Set up channel statistics timer
3024 */
3025 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3026 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3027 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3028 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3029 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3030 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3031 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3032
3033 return 0;
3034 }
3035
3036 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3037 {
3038 unsigned int i;
3039 u32 reg;
3040
3041 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3042 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3043 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3044 return 0;
3045
3046 udelay(REGISTER_BUSY_DELAY);
3047 }
3048
3049 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3050 return -EACCES;
3051 }
3052
3053 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3054 {
3055 unsigned int i;
3056 u8 value;
3057
3058 /*
3059 * BBP was enabled after firmware was loaded,
3060 * but we need to reactivate it now.
3061 */
3062 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3063 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3064 msleep(1);
3065
3066 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3067 rt2800_bbp_read(rt2x00dev, 0, &value);
3068 if ((value != 0xff) && (value != 0x00))
3069 return 0;
3070 udelay(REGISTER_BUSY_DELAY);
3071 }
3072
3073 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3074 return -EACCES;
3075 }
3076
3077 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3078 {
3079 unsigned int i;
3080 u16 eeprom;
3081 u8 reg_id;
3082 u8 value;
3083
3084 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3085 rt2800_wait_bbp_ready(rt2x00dev)))
3086 return -EACCES;
3087
3088 if (rt2x00_rt(rt2x00dev, RT5390)) {
3089 rt2800_bbp_read(rt2x00dev, 4, &value);
3090 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3091 rt2800_bbp_write(rt2x00dev, 4, value);
3092 }
3093
3094 if (rt2800_is_305x_soc(rt2x00dev) ||
3095 rt2x00_rt(rt2x00dev, RT3572) ||
3096 rt2x00_rt(rt2x00dev, RT5390))
3097 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3098
3099 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3100 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3101
3102 if (rt2x00_rt(rt2x00dev, RT5390))
3103 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3104
3105 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3106 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3107 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3108 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3109 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3110 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3111 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3112 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3113 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3114 } else {
3115 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3116 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3117 }
3118
3119 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3120
3121 if (rt2x00_rt(rt2x00dev, RT3070) ||
3122 rt2x00_rt(rt2x00dev, RT3071) ||
3123 rt2x00_rt(rt2x00dev, RT3090) ||
3124 rt2x00_rt(rt2x00dev, RT3390) ||
3125 rt2x00_rt(rt2x00dev, RT3572) ||
3126 rt2x00_rt(rt2x00dev, RT5390)) {
3127 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3128 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3129 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3130 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3131 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3132 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3133 } else {
3134 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3135 }
3136
3137 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3138 if (rt2x00_rt(rt2x00dev, RT5390))
3139 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3140 else
3141 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3142
3143 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3144 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3145 else if (rt2x00_rt(rt2x00dev, RT5390))
3146 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3147 else
3148 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3149
3150 if (rt2x00_rt(rt2x00dev, RT5390))
3151 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3152 else
3153 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3154
3155 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3156
3157 if (rt2x00_rt(rt2x00dev, RT5390))
3158 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3159 else
3160 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3161
3162 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3163 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3164 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3165 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3166 rt2x00_rt(rt2x00dev, RT3572) ||
3167 rt2x00_rt(rt2x00dev, RT5390) ||
3168 rt2800_is_305x_soc(rt2x00dev))
3169 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3170 else
3171 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3172
3173 if (rt2x00_rt(rt2x00dev, RT5390))
3174 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3175
3176 if (rt2800_is_305x_soc(rt2x00dev))
3177 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3178 else if (rt2x00_rt(rt2x00dev, RT5390))
3179 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3180 else
3181 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3182
3183 if (rt2x00_rt(rt2x00dev, RT5390))
3184 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3185 else
3186 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3187
3188 if (rt2x00_rt(rt2x00dev, RT5390))
3189 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3190
3191 if (rt2x00_rt(rt2x00dev, RT3071) ||
3192 rt2x00_rt(rt2x00dev, RT3090) ||
3193 rt2x00_rt(rt2x00dev, RT3390) ||
3194 rt2x00_rt(rt2x00dev, RT3572) ||
3195 rt2x00_rt(rt2x00dev, RT5390)) {
3196 rt2800_bbp_read(rt2x00dev, 138, &value);
3197
3198 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3199 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3200 value |= 0x20;
3201 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3202 value &= ~0x02;
3203
3204 rt2800_bbp_write(rt2x00dev, 138, value);
3205 }
3206
3207 if (rt2x00_rt(rt2x00dev, RT5390)) {
3208 int ant, div_mode;
3209
3210 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3211 div_mode = rt2x00_get_field16(eeprom,
3212 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3213 ant = (div_mode == 3) ? 1 : 0;
3214
3215 /* check if this is a Bluetooth combo card */
3216 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3217 u32 reg;
3218
3219 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3220 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3221 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3222 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3223 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3224 if (ant == 0)
3225 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3226 else if (ant == 1)
3227 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3228 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3229 }
3230
3231 rt2800_bbp_read(rt2x00dev, 152, &value);
3232 if (ant == 0)
3233 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3234 else
3235 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3236 rt2800_bbp_write(rt2x00dev, 152, value);
3237
3238 /* Init frequency calibration */
3239 rt2800_bbp_write(rt2x00dev, 142, 1);
3240 rt2800_bbp_write(rt2x00dev, 143, 57);
3241 }
3242
3243 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3244 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3245
3246 if (eeprom != 0xffff && eeprom != 0x0000) {
3247 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3248 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3249 rt2800_bbp_write(rt2x00dev, reg_id, value);
3250 }
3251 }
3252
3253 return 0;
3254 }
3255
3256 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3257 bool bw40, u8 rfcsr24, u8 filter_target)
3258 {
3259 unsigned int i;
3260 u8 bbp;
3261 u8 rfcsr;
3262 u8 passband;
3263 u8 stopband;
3264 u8 overtuned = 0;
3265
3266 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3267
3268 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3269 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3270 rt2800_bbp_write(rt2x00dev, 4, bbp);
3271
3272 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3273 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3274 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3275
3276 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3277 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3278 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3279
3280 /*
3281 * Set power & frequency of passband test tone
3282 */
3283 rt2800_bbp_write(rt2x00dev, 24, 0);
3284
3285 for (i = 0; i < 100; i++) {
3286 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3287 msleep(1);
3288
3289 rt2800_bbp_read(rt2x00dev, 55, &passband);
3290 if (passband)
3291 break;
3292 }
3293
3294 /*
3295 * Set power & frequency of stopband test tone
3296 */
3297 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3298
3299 for (i = 0; i < 100; i++) {
3300 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3301 msleep(1);
3302
3303 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3304
3305 if ((passband - stopband) <= filter_target) {
3306 rfcsr24++;
3307 overtuned += ((passband - stopband) == filter_target);
3308 } else
3309 break;
3310
3311 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3312 }
3313
3314 rfcsr24 -= !!overtuned;
3315
3316 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3317 return rfcsr24;
3318 }
3319
3320 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3321 {
3322 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3323 u8 rfcsr;
3324 u8 bbp;
3325 u32 reg;
3326 u16 eeprom;
3327
3328 if (!rt2x00_rt(rt2x00dev, RT3070) &&
3329 !rt2x00_rt(rt2x00dev, RT3071) &&
3330 !rt2x00_rt(rt2x00dev, RT3090) &&
3331 !rt2x00_rt(rt2x00dev, RT3390) &&
3332 !rt2x00_rt(rt2x00dev, RT3572) &&
3333 !rt2x00_rt(rt2x00dev, RT5390) &&
3334 !rt2800_is_305x_soc(rt2x00dev))
3335 return 0;
3336
3337 /*
3338 * Init RF calibration.
3339 */
3340 if (rt2x00_rt(rt2x00dev, RT5390)) {
3341 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3342 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3343 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3344 msleep(1);
3345 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3346 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3347 } else {
3348 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3349 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3350 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3351 msleep(1);
3352 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3353 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3354 }
3355
3356 if (rt2x00_rt(rt2x00dev, RT3070) ||
3357 rt2x00_rt(rt2x00dev, RT3071) ||
3358 rt2x00_rt(rt2x00dev, RT3090)) {
3359 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3360 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3361 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3362 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3363 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3364 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3365 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3366 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3367 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3368 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3369 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3370 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3371 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3372 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3373 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3374 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3375 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3376 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3377 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3378 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3379 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3380 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3381 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3382 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3383 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3384 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3385 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3386 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3387 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3388 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3389 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3390 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3391 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3392 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3393 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3394 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3395 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3396 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3397 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3398 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3399 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3400 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3401 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3402 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3403 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3404 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3405 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3406 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3407 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3408 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3409 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3410 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3411 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3412 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3413 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3414 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3415 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3416 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3417 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3418 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3419 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3420 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3421 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3422 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3423 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3424 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3425 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3426 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3427 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3428 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3429 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3430 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3431 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3432 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3433 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3434 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3435 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3436 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3437 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3438 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3439 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3440 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3441 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3442 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3443 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3444 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3445 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3446 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3447 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3448 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3449 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3450 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3451 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3452 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3453 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3454 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3455 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3456 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3457 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3458 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3459 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3460 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3461 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3462 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3463 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3464 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3465 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3466 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3467 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3468 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3469 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3470 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3471 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3472 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3473 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3474 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3475 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3476 return 0;
3477 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3478 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3479 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3480 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3481 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3482 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3483 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3484 else
3485 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3486 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3487 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3488 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3489 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3490 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3491 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3492 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3493 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3494 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3495 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3496
3497 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3498 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3499 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3500 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3501 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3502 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3503 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3504 else
3505 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3506 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3507 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3508 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3509 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3510
3511 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3512 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3513 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3514 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3515 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3516 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3517 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3518 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3519 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3520 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3521
3522 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3523 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3524 else
3525 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3526 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3527 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3528 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3529 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3530 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3531 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3532 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3533 else
3534 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3535 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3536 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3537 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3538
3539 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3540 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3541 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3542 else
3543 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3544 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3545 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3546 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3547 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3548 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3549 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3550
3551 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3552 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3553 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3554 else
3555 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3556 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3557 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3558 }
3559
3560 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3561 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3562 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3563 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3564 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3565 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3566 rt2x00_rt(rt2x00dev, RT3090)) {
3567 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3568
3569 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3570 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3571 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3572
3573 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3574 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3575 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3576 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3577 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3578 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3579 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3580 else
3581 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3582 }
3583 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3584
3585 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3586 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3587 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3588 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3589 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3590 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3591 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3592 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3593 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3594 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3595 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3596
3597 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3598 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3599 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3600 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3601 msleep(1);
3602 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3603 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3604 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3605 }
3606
3607 /*
3608 * Set RX Filter calibration for 20MHz and 40MHz
3609 */
3610 if (rt2x00_rt(rt2x00dev, RT3070)) {
3611 drv_data->calibration_bw20 =
3612 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3613 drv_data->calibration_bw40 =
3614 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3615 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3616 rt2x00_rt(rt2x00dev, RT3090) ||
3617 rt2x00_rt(rt2x00dev, RT3390) ||
3618 rt2x00_rt(rt2x00dev, RT3572)) {
3619 drv_data->calibration_bw20 =
3620 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3621 drv_data->calibration_bw40 =
3622 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3623 }
3624
3625 /*
3626 * Save BBP 25 & 26 values for later use in channel switching
3627 */
3628 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
3629 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
3630
3631 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3632 /*
3633 * Set back to initial state
3634 */
3635 rt2800_bbp_write(rt2x00dev, 24, 0);
3636
3637 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3638 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3639 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3640
3641 /*
3642 * Set BBP back to BW20
3643 */
3644 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3645 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3646 rt2800_bbp_write(rt2x00dev, 4, bbp);
3647 }
3648
3649 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3650 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3651 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3652 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3653 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3654
3655 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3656 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3657 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3658
3659 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3660 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3661 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3662 if (rt2x00_rt(rt2x00dev, RT3070) ||
3663 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3664 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3665 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3666 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3667 &rt2x00dev->cap_flags))
3668 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3669 }
3670 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3671 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3672 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3673 rt2x00_get_field16(eeprom,
3674 EEPROM_TXMIXER_GAIN_BG_VAL));
3675 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3676 }
3677
3678 if (rt2x00_rt(rt2x00dev, RT3090)) {
3679 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3680
3681 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
3682 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3683 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3684 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3685 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3686 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3687
3688 rt2800_bbp_write(rt2x00dev, 138, bbp);
3689 }
3690
3691 if (rt2x00_rt(rt2x00dev, RT3071) ||
3692 rt2x00_rt(rt2x00dev, RT3090) ||
3693 rt2x00_rt(rt2x00dev, RT3390)) {
3694 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3695 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3696 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3697 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3698 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3699 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3700 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3701
3702 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3703 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3704 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3705
3706 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3707 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3708 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3709
3710 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3711 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3712 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3713 }
3714
3715 if (rt2x00_rt(rt2x00dev, RT3070)) {
3716 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3717 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3718 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3719 else
3720 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3721 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3722 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3723 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3724 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3725 }
3726
3727 if (rt2x00_rt(rt2x00dev, RT5390)) {
3728 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3729 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3730 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3731
3732 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3733 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3734 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3735
3736 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3737 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3738 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3739 }
3740
3741 return 0;
3742 }
3743
3744 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3745 {
3746 u32 reg;
3747 u16 word;
3748
3749 /*
3750 * Initialize all registers.
3751 */
3752 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3753 rt2800_init_registers(rt2x00dev) ||
3754 rt2800_init_bbp(rt2x00dev) ||
3755 rt2800_init_rfcsr(rt2x00dev)))
3756 return -EIO;
3757
3758 /*
3759 * Send signal to firmware during boot time.
3760 */
3761 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3762
3763 if (rt2x00_is_usb(rt2x00dev) &&
3764 (rt2x00_rt(rt2x00dev, RT3070) ||
3765 rt2x00_rt(rt2x00dev, RT3071) ||
3766 rt2x00_rt(rt2x00dev, RT3572))) {
3767 udelay(200);
3768 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3769 udelay(10);
3770 }
3771
3772 /*
3773 * Enable RX.
3774 */
3775 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3776 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3777 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3778 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3779
3780 udelay(50);
3781
3782 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3783 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3784 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3785 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3786 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3787 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3788
3789 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3790 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3791 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3792 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3793
3794 /*
3795 * Initialize LED control
3796 */
3797 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3798 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3799 word & 0xff, (word >> 8) & 0xff);
3800
3801 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3802 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3803 word & 0xff, (word >> 8) & 0xff);
3804
3805 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3806 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3807 word & 0xff, (word >> 8) & 0xff);
3808
3809 return 0;
3810 }
3811 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3812
3813 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3814 {
3815 u32 reg;
3816
3817 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3818 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3819 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3820 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3821
3822 /* Wait for DMA, ignore error */
3823 rt2800_wait_wpdma_ready(rt2x00dev);
3824
3825 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3826 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3827 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3828 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3829 }
3830 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
3831
3832 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3833 {
3834 u32 reg;
3835
3836 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3837
3838 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3839 }
3840 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3841
3842 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3843 {
3844 u32 reg;
3845
3846 mutex_lock(&rt2x00dev->csr_mutex);
3847
3848 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
3849 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3850 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3851 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
3852 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
3853
3854 /* Wait until the EEPROM has been loaded */
3855 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3856
3857 /* Apparently the data is read from end to start */
3858 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg);
3859 /* The returned value is in CPU order, but eeprom is le */
3860 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
3861 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg);
3862 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
3863 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg);
3864 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
3865 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg);
3866 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
3867
3868 mutex_unlock(&rt2x00dev->csr_mutex);
3869 }
3870
3871 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3872 {
3873 unsigned int i;
3874
3875 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3876 rt2800_efuse_read(rt2x00dev, i);
3877 }
3878 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3879
3880 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3881 {
3882 u16 word;
3883 u8 *mac;
3884 u8 default_lna_gain;
3885
3886 /*
3887 * Start validation of the data that has been read.
3888 */
3889 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3890 if (!is_valid_ether_addr(mac)) {
3891 random_ether_addr(mac);
3892 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3893 }
3894
3895 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
3896 if (word == 0xffff) {
3897 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3898 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3899 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3900 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3901 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
3902 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
3903 rt2x00_rt(rt2x00dev, RT2872)) {
3904 /*
3905 * There is a max of 2 RX streams for RT28x0 series
3906 */
3907 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3908 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3909 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3910 }
3911
3912 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
3913 if (word == 0xffff) {
3914 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3915 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3916 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3917 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3918 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3919 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3920 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3921 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3922 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3923 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3924 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3925 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3926 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3927 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3928 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3929 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
3930 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3931 }
3932
3933 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3934 if ((word & 0x00ff) == 0x00ff) {
3935 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3936 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3937 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3938 }
3939 if ((word & 0xff00) == 0xff00) {
3940 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3941 LED_MODE_TXRX_ACTIVITY);
3942 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3943 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3944 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3945 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3946 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
3947 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
3948 }
3949
3950 /*
3951 * During the LNA validation we are going to use
3952 * lna0 as correct value. Note that EEPROM_LNA
3953 * is never validated.
3954 */
3955 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3956 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3957
3958 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3959 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3960 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3961 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3962 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3963 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3964
3965 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3966 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3967 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3968 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3969 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3970 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3971 default_lna_gain);
3972 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3973
3974 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3975 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3976 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3977 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3978 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3979 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3980
3981 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3982 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3983 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3984 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3985 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3986 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3987 default_lna_gain);
3988 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3989
3990 return 0;
3991 }
3992 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3993
3994 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3995 {
3996 u32 reg;
3997 u16 value;
3998 u16 eeprom;
3999
4000 /*
4001 * Read EEPROM word for configuration.
4002 */
4003 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4004
4005 /*
4006 * Identify RF chipset by EEPROM value
4007 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4008 * RT53xx: defined in "EEPROM_CHIP_ID" field
4009 */
4010 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
4011 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
4012 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4013 else
4014 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
4015
4016 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4017 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4018
4019 switch (rt2x00dev->chip.rt) {
4020 case RT2860:
4021 case RT2872:
4022 case RT2883:
4023 case RT3070:
4024 case RT3071:
4025 case RT3090:
4026 case RT3390:
4027 case RT3572:
4028 case RT5390:
4029 break;
4030 default:
4031 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
4032 return -ENODEV;
4033 }
4034
4035 switch (rt2x00dev->chip.rf) {
4036 case RF2820:
4037 case RF2850:
4038 case RF2720:
4039 case RF2750:
4040 case RF3020:
4041 case RF2020:
4042 case RF3021:
4043 case RF3022:
4044 case RF3052:
4045 case RF3320:
4046 case RF5370:
4047 case RF5390:
4048 break;
4049 default:
4050 ERROR(rt2x00dev, "Invalid RF chipset 0x%x detected.\n",
4051 rt2x00dev->chip.rf);
4052 return -ENODEV;
4053 }
4054
4055 /*
4056 * Identify default antenna configuration.
4057 */
4058 rt2x00dev->default_ant.tx_chain_num =
4059 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
4060 rt2x00dev->default_ant.rx_chain_num =
4061 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
4062
4063 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4064
4065 if (rt2x00_rt(rt2x00dev, RT3070) ||
4066 rt2x00_rt(rt2x00dev, RT3090) ||
4067 rt2x00_rt(rt2x00dev, RT3390)) {
4068 value = rt2x00_get_field16(eeprom,
4069 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4070 switch (value) {
4071 case 0:
4072 case 1:
4073 case 2:
4074 rt2x00dev->default_ant.tx = ANTENNA_A;
4075 rt2x00dev->default_ant.rx = ANTENNA_A;
4076 break;
4077 case 3:
4078 rt2x00dev->default_ant.tx = ANTENNA_A;
4079 rt2x00dev->default_ant.rx = ANTENNA_B;
4080 break;
4081 }
4082 } else {
4083 rt2x00dev->default_ant.tx = ANTENNA_A;
4084 rt2x00dev->default_ant.rx = ANTENNA_A;
4085 }
4086
4087 /*
4088 * Determine external LNA informations.
4089 */
4090 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
4091 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
4092 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
4093 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
4094
4095 /*
4096 * Detect if this device has an hardware controlled radio.
4097 */
4098 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
4099 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
4100
4101 /*
4102 * Detect if this device has Bluetooth co-existence.
4103 */
4104 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4105 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4106
4107 /*
4108 * Read frequency offset and RF programming sequence.
4109 */
4110 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4111 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4112
4113 /*
4114 * Store led settings, for correct led behaviour.
4115 */
4116 #ifdef CONFIG_RT2X00_LIB_LEDS
4117 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4118 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4119 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4120
4121 rt2x00dev->led_mcu_reg = eeprom;
4122 #endif /* CONFIG_RT2X00_LIB_LEDS */
4123
4124 /*
4125 * Check if support EIRP tx power limit feature.
4126 */
4127 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4128
4129 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4130 EIRP_MAX_TX_POWER_LIMIT)
4131 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
4132
4133 return 0;
4134 }
4135 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4136
4137 /*
4138 * RF value list for rt28xx
4139 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4140 */
4141 static const struct rf_channel rf_vals[] = {
4142 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4143 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4144 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4145 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4146 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4147 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4148 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4149 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4150 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4151 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4152 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4153 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4154 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4155 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4156
4157 /* 802.11 UNI / HyperLan 2 */
4158 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4159 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4160 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4161 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4162 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4163 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4164 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4165 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4166 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4167 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4168 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4169 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4170
4171 /* 802.11 HyperLan 2 */
4172 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4173 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4174 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4175 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4176 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4177 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4178 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4179 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4180 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4181 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4182 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4183 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4184 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4185 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4186 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4187 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4188
4189 /* 802.11 UNII */
4190 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4191 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4192 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4193 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4194 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4195 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4196 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4197 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4198 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4199 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4200 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4201
4202 /* 802.11 Japan */
4203 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4204 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4205 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4206 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4207 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4208 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4209 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4210 };
4211
4212 /*
4213 * RF value list for rt3xxx
4214 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4215 */
4216 static const struct rf_channel rf_vals_3x[] = {
4217 {1, 241, 2, 2 },
4218 {2, 241, 2, 7 },
4219 {3, 242, 2, 2 },
4220 {4, 242, 2, 7 },
4221 {5, 243, 2, 2 },
4222 {6, 243, 2, 7 },
4223 {7, 244, 2, 2 },
4224 {8, 244, 2, 7 },
4225 {9, 245, 2, 2 },
4226 {10, 245, 2, 7 },
4227 {11, 246, 2, 2 },
4228 {12, 246, 2, 7 },
4229 {13, 247, 2, 2 },
4230 {14, 248, 2, 4 },
4231
4232 /* 802.11 UNI / HyperLan 2 */
4233 {36, 0x56, 0, 4},
4234 {38, 0x56, 0, 6},
4235 {40, 0x56, 0, 8},
4236 {44, 0x57, 0, 0},
4237 {46, 0x57, 0, 2},
4238 {48, 0x57, 0, 4},
4239 {52, 0x57, 0, 8},
4240 {54, 0x57, 0, 10},
4241 {56, 0x58, 0, 0},
4242 {60, 0x58, 0, 4},
4243 {62, 0x58, 0, 6},
4244 {64, 0x58, 0, 8},
4245
4246 /* 802.11 HyperLan 2 */
4247 {100, 0x5b, 0, 8},
4248 {102, 0x5b, 0, 10},
4249 {104, 0x5c, 0, 0},
4250 {108, 0x5c, 0, 4},
4251 {110, 0x5c, 0, 6},
4252 {112, 0x5c, 0, 8},
4253 {116, 0x5d, 0, 0},
4254 {118, 0x5d, 0, 2},
4255 {120, 0x5d, 0, 4},
4256 {124, 0x5d, 0, 8},
4257 {126, 0x5d, 0, 10},
4258 {128, 0x5e, 0, 0},
4259 {132, 0x5e, 0, 4},
4260 {134, 0x5e, 0, 6},
4261 {136, 0x5e, 0, 8},
4262 {140, 0x5f, 0, 0},
4263
4264 /* 802.11 UNII */
4265 {149, 0x5f, 0, 9},
4266 {151, 0x5f, 0, 11},
4267 {153, 0x60, 0, 1},
4268 {157, 0x60, 0, 5},
4269 {159, 0x60, 0, 7},
4270 {161, 0x60, 0, 9},
4271 {165, 0x61, 0, 1},
4272 {167, 0x61, 0, 3},
4273 {169, 0x61, 0, 5},
4274 {171, 0x61, 0, 7},
4275 {173, 0x61, 0, 9},
4276 };
4277
4278 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4279 {
4280 struct hw_mode_spec *spec = &rt2x00dev->spec;
4281 struct channel_info *info;
4282 char *default_power1;
4283 char *default_power2;
4284 unsigned int i;
4285 u16 eeprom;
4286
4287 /*
4288 * Disable powersaving as default on PCI devices.
4289 */
4290 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
4291 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4292
4293 /*
4294 * Initialize all hw fields.
4295 */
4296 rt2x00dev->hw->flags =
4297 IEEE80211_HW_SIGNAL_DBM |
4298 IEEE80211_HW_SUPPORTS_PS |
4299 IEEE80211_HW_PS_NULLFUNC_STACK |
4300 IEEE80211_HW_AMPDU_AGGREGATION;
4301 /*
4302 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4303 * unless we are capable of sending the buffered frames out after the
4304 * DTIM transmission using rt2x00lib_beacondone. This will send out
4305 * multicast and broadcast traffic immediately instead of buffering it
4306 * infinitly and thus dropping it after some time.
4307 */
4308 if (!rt2x00_is_usb(rt2x00dev))
4309 rt2x00dev->hw->flags |=
4310 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4311
4312 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4313 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4314 rt2x00_eeprom_addr(rt2x00dev,
4315 EEPROM_MAC_ADDR_0));
4316
4317 /*
4318 * As rt2800 has a global fallback table we cannot specify
4319 * more then one tx rate per frame but since the hw will
4320 * try several rates (based on the fallback table) we should
4321 * initialize max_report_rates to the maximum number of rates
4322 * we are going to try. Otherwise mac80211 will truncate our
4323 * reported tx rates and the rc algortihm will end up with
4324 * incorrect data.
4325 */
4326 rt2x00dev->hw->max_rates = 1;
4327 rt2x00dev->hw->max_report_rates = 7;
4328 rt2x00dev->hw->max_rate_tries = 1;
4329
4330 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4331
4332 /*
4333 * Initialize hw_mode information.
4334 */
4335 spec->supported_bands = SUPPORT_BAND_2GHZ;
4336 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4337
4338 if (rt2x00_rf(rt2x00dev, RF2820) ||
4339 rt2x00_rf(rt2x00dev, RF2720)) {
4340 spec->num_channels = 14;
4341 spec->channels = rf_vals;
4342 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4343 rt2x00_rf(rt2x00dev, RF2750)) {
4344 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4345 spec->num_channels = ARRAY_SIZE(rf_vals);
4346 spec->channels = rf_vals;
4347 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4348 rt2x00_rf(rt2x00dev, RF2020) ||
4349 rt2x00_rf(rt2x00dev, RF3021) ||
4350 rt2x00_rf(rt2x00dev, RF3022) ||
4351 rt2x00_rf(rt2x00dev, RF3320) ||
4352 rt2x00_rf(rt2x00dev, RF5370) ||
4353 rt2x00_rf(rt2x00dev, RF5390)) {
4354 spec->num_channels = 14;
4355 spec->channels = rf_vals_3x;
4356 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4357 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4358 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4359 spec->channels = rf_vals_3x;
4360 }
4361
4362 /*
4363 * Initialize HT information.
4364 */
4365 if (!rt2x00_rf(rt2x00dev, RF2020))
4366 spec->ht.ht_supported = true;
4367 else
4368 spec->ht.ht_supported = false;
4369
4370 spec->ht.cap =
4371 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4372 IEEE80211_HT_CAP_GRN_FLD |
4373 IEEE80211_HT_CAP_SGI_20 |
4374 IEEE80211_HT_CAP_SGI_40;
4375
4376 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4377 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4378
4379 spec->ht.cap |=
4380 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4381 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4382
4383 spec->ht.ampdu_factor = 3;
4384 spec->ht.ampdu_density = 4;
4385 spec->ht.mcs.tx_params =
4386 IEEE80211_HT_MCS_TX_DEFINED |
4387 IEEE80211_HT_MCS_TX_RX_DIFF |
4388 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4389 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4390
4391 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4392 case 3:
4393 spec->ht.mcs.rx_mask[2] = 0xff;
4394 case 2:
4395 spec->ht.mcs.rx_mask[1] = 0xff;
4396 case 1:
4397 spec->ht.mcs.rx_mask[0] = 0xff;
4398 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4399 break;
4400 }
4401
4402 /*
4403 * Create channel information array
4404 */
4405 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4406 if (!info)
4407 return -ENOMEM;
4408
4409 spec->channels_info = info;
4410
4411 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4412 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4413
4414 for (i = 0; i < 14; i++) {
4415 info[i].default_power1 = default_power1[i];
4416 info[i].default_power2 = default_power2[i];
4417 }
4418
4419 if (spec->num_channels > 14) {
4420 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4421 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4422
4423 for (i = 14; i < spec->num_channels; i++) {
4424 info[i].default_power1 = default_power1[i];
4425 info[i].default_power2 = default_power2[i];
4426 }
4427 }
4428
4429 return 0;
4430 }
4431 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4432
4433 /*
4434 * IEEE80211 stack callback functions.
4435 */
4436 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4437 u16 *iv16)
4438 {
4439 struct rt2x00_dev *rt2x00dev = hw->priv;
4440 struct mac_iveiv_entry iveiv_entry;
4441 u32 offset;
4442
4443 offset = MAC_IVEIV_ENTRY(hw_key_idx);
4444 rt2800_register_multiread(rt2x00dev, offset,
4445 &iveiv_entry, sizeof(iveiv_entry));
4446
4447 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4448 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4449 }
4450 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4451
4452 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4453 {
4454 struct rt2x00_dev *rt2x00dev = hw->priv;
4455 u32 reg;
4456 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4457
4458 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4459 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4460 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4461
4462 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4463 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4464 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4465
4466 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4467 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4468 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4469
4470 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4471 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4472 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4473
4474 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4475 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4476 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4477
4478 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4479 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4480 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4481
4482 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4483 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4484 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4485
4486 return 0;
4487 }
4488 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4489
4490 int rt2800_conf_tx(struct ieee80211_hw *hw,
4491 struct ieee80211_vif *vif, u16 queue_idx,
4492 const struct ieee80211_tx_queue_params *params)
4493 {
4494 struct rt2x00_dev *rt2x00dev = hw->priv;
4495 struct data_queue *queue;
4496 struct rt2x00_field32 field;
4497 int retval;
4498 u32 reg;
4499 u32 offset;
4500
4501 /*
4502 * First pass the configuration through rt2x00lib, that will
4503 * update the queue settings and validate the input. After that
4504 * we are free to update the registers based on the value
4505 * in the queue parameter.
4506 */
4507 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
4508 if (retval)
4509 return retval;
4510
4511 /*
4512 * We only need to perform additional register initialization
4513 * for WMM queues/
4514 */
4515 if (queue_idx >= 4)
4516 return 0;
4517
4518 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
4519
4520 /* Update WMM TXOP register */
4521 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4522 field.bit_offset = (queue_idx & 1) * 16;
4523 field.bit_mask = 0xffff << field.bit_offset;
4524
4525 rt2800_register_read(rt2x00dev, offset, &reg);
4526 rt2x00_set_field32(&reg, field, queue->txop);
4527 rt2800_register_write(rt2x00dev, offset, reg);
4528
4529 /* Update WMM registers */
4530 field.bit_offset = queue_idx * 4;
4531 field.bit_mask = 0xf << field.bit_offset;
4532
4533 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4534 rt2x00_set_field32(&reg, field, queue->aifs);
4535 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4536
4537 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4538 rt2x00_set_field32(&reg, field, queue->cw_min);
4539 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4540
4541 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4542 rt2x00_set_field32(&reg, field, queue->cw_max);
4543 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4544
4545 /* Update EDCA registers */
4546 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4547
4548 rt2800_register_read(rt2x00dev, offset, &reg);
4549 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4550 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4551 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4552 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4553 rt2800_register_write(rt2x00dev, offset, reg);
4554
4555 return 0;
4556 }
4557 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4558
4559 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
4560 {
4561 struct rt2x00_dev *rt2x00dev = hw->priv;
4562 u64 tsf;
4563 u32 reg;
4564
4565 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4566 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4567 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4568 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4569
4570 return tsf;
4571 }
4572 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4573
4574 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4575 enum ieee80211_ampdu_mlme_action action,
4576 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4577 u8 buf_size)
4578 {
4579 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
4580 int ret = 0;
4581
4582 /*
4583 * Don't allow aggregation for stations the hardware isn't aware
4584 * of because tx status reports for frames to an unknown station
4585 * always contain wcid=255 and thus we can't distinguish between
4586 * multiple stations which leads to unwanted situations when the
4587 * hw reorders frames due to aggregation.
4588 */
4589 if (sta_priv->wcid < 0)
4590 return 1;
4591
4592 switch (action) {
4593 case IEEE80211_AMPDU_RX_START:
4594 case IEEE80211_AMPDU_RX_STOP:
4595 /*
4596 * The hw itself takes care of setting up BlockAck mechanisms.
4597 * So, we only have to allow mac80211 to nagotiate a BlockAck
4598 * agreement. Once that is done, the hw will BlockAck incoming
4599 * AMPDUs without further setup.
4600 */
4601 break;
4602 case IEEE80211_AMPDU_TX_START:
4603 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4604 break;
4605 case IEEE80211_AMPDU_TX_STOP:
4606 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4607 break;
4608 case IEEE80211_AMPDU_TX_OPERATIONAL:
4609 break;
4610 default:
4611 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4612 }
4613
4614 return ret;
4615 }
4616 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4617
4618 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4619 struct survey_info *survey)
4620 {
4621 struct rt2x00_dev *rt2x00dev = hw->priv;
4622 struct ieee80211_conf *conf = &hw->conf;
4623 u32 idle, busy, busy_ext;
4624
4625 if (idx != 0)
4626 return -ENOENT;
4627
4628 survey->channel = conf->channel;
4629
4630 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4631 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4632 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4633
4634 if (idle || busy) {
4635 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4636 SURVEY_INFO_CHANNEL_TIME_BUSY |
4637 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4638
4639 survey->channel_time = (idle + busy) / 1000;
4640 survey->channel_time_busy = busy / 1000;
4641 survey->channel_time_ext_busy = busy_ext / 1000;
4642 }
4643
4644 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
4645 survey->filled |= SURVEY_INFO_IN_USE;
4646
4647 return 0;
4648
4649 }
4650 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4651
4652 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4653 MODULE_VERSION(DRV_VERSION);
4654 MODULE_DESCRIPTION("Ralink RT2800 library");
4655 MODULE_LICENSE("GPL");
(deprecated) Btrfs devel tree