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gpu: ipu-v3: add support for 15-bit RGB with 1-bit alpha formats
[linux-2.6/btrfs-unstable.git] / drivers / gpu / ipu-v3 / ipu-common.c
blobc0b19160a94671dc68bb551e81a2577e37483386
1 /*
2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15 #include <linux/module.h>
16 #include <linux/export.h>
17 #include <linux/types.h>
18 #include <linux/reset.h>
19 #include <linux/platform_device.h>
20 #include <linux/err.h>
21 #include <linux/spinlock.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/list.h>
27 #include <linux/irq.h>
28 #include <linux/irqchip/chained_irq.h>
29 #include <linux/irqdomain.h>
30 #include <linux/of_device.h>
31
32 #include <drm/drm_fourcc.h>
33
34 #include <video/imx-ipu-v3.h>
35 #include "ipu-prv.h"
36
37 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
38 {
39 return readl(ipu->cm_reg + offset);
40 }
41
42 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
43 {
44 writel(value, ipu->cm_reg + offset);
45 }
46
47 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
48 {
49 u32 val;
50
51 val = ipu_cm_read(ipu, IPU_SRM_PRI2);
52 val |= 0x8;
53 ipu_cm_write(ipu, val, IPU_SRM_PRI2);
54 }
55 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
56
57 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
58 {
59 switch (drm_fourcc) {
60 case DRM_FORMAT_ARGB1555:
61 case DRM_FORMAT_ABGR1555:
62 case DRM_FORMAT_RGBA5551:
63 case DRM_FORMAT_BGRA5551:
64 case DRM_FORMAT_RGB565:
65 case DRM_FORMAT_BGR565:
66 case DRM_FORMAT_RGB888:
67 case DRM_FORMAT_BGR888:
68 case DRM_FORMAT_XRGB8888:
69 case DRM_FORMAT_XBGR8888:
70 case DRM_FORMAT_RGBX8888:
71 case DRM_FORMAT_BGRX8888:
72 case DRM_FORMAT_ARGB8888:
73 case DRM_FORMAT_ABGR8888:
74 case DRM_FORMAT_RGBA8888:
75 case DRM_FORMAT_BGRA8888:
76 return IPUV3_COLORSPACE_RGB;
77 case DRM_FORMAT_YUYV:
78 case DRM_FORMAT_UYVY:
79 case DRM_FORMAT_YUV420:
80 case DRM_FORMAT_YVU420:
81 case DRM_FORMAT_YUV422:
82 case DRM_FORMAT_YVU422:
83 case DRM_FORMAT_NV12:
84 case DRM_FORMAT_NV21:
85 case DRM_FORMAT_NV16:
86 case DRM_FORMAT_NV61:
87 return IPUV3_COLORSPACE_YUV;
88 default:
89 return IPUV3_COLORSPACE_UNKNOWN;
90 }
91 }
92 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
93
94 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
95 {
96 switch (pixelformat) {
97 case V4L2_PIX_FMT_YUV420:
98 case V4L2_PIX_FMT_YVU420:
99 case V4L2_PIX_FMT_YUV422P:
100 case V4L2_PIX_FMT_UYVY:
101 case V4L2_PIX_FMT_YUYV:
102 case V4L2_PIX_FMT_NV12:
103 case V4L2_PIX_FMT_NV21:
104 case V4L2_PIX_FMT_NV16:
105 case V4L2_PIX_FMT_NV61:
106 return IPUV3_COLORSPACE_YUV;
107 case V4L2_PIX_FMT_RGB32:
108 case V4L2_PIX_FMT_BGR32:
109 case V4L2_PIX_FMT_RGB24:
110 case V4L2_PIX_FMT_BGR24:
111 case V4L2_PIX_FMT_RGB565:
112 return IPUV3_COLORSPACE_RGB;
113 default:
114 return IPUV3_COLORSPACE_UNKNOWN;
115 }
116 }
117 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
118
119 bool ipu_pixelformat_is_planar(u32 pixelformat)
120 {
121 switch (pixelformat) {
122 case V4L2_PIX_FMT_YUV420:
123 case V4L2_PIX_FMT_YVU420:
124 case V4L2_PIX_FMT_YUV422P:
125 case V4L2_PIX_FMT_NV12:
126 case V4L2_PIX_FMT_NV21:
127 case V4L2_PIX_FMT_NV16:
128 case V4L2_PIX_FMT_NV61:
129 return true;
130 }
131
132 return false;
133 }
134 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
135
136 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
137 {
138 switch (mbus_code & 0xf000) {
139 case 0x1000:
140 return IPUV3_COLORSPACE_RGB;
141 case 0x2000:
142 return IPUV3_COLORSPACE_YUV;
143 default:
144 return IPUV3_COLORSPACE_UNKNOWN;
145 }
146 }
147 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
148
149 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
150 {
151 switch (pixelformat) {
152 case V4L2_PIX_FMT_YUV420:
153 case V4L2_PIX_FMT_YVU420:
154 case V4L2_PIX_FMT_YUV422P:
155 case V4L2_PIX_FMT_NV12:
156 case V4L2_PIX_FMT_NV21:
157 case V4L2_PIX_FMT_NV16:
158 case V4L2_PIX_FMT_NV61:
159 /*
160 * for the planar YUV formats, the stride passed to
161 * cpmem must be the stride in bytes of the Y plane.
162 * And all the planar YUV formats have an 8-bit
163 * Y component.
164 */
165 return (8 * pixel_stride) >> 3;
166 case V4L2_PIX_FMT_RGB565:
167 case V4L2_PIX_FMT_YUYV:
168 case V4L2_PIX_FMT_UYVY:
169 return (16 * pixel_stride) >> 3;
170 case V4L2_PIX_FMT_BGR24:
171 case V4L2_PIX_FMT_RGB24:
172 return (24 * pixel_stride) >> 3;
173 case V4L2_PIX_FMT_BGR32:
174 case V4L2_PIX_FMT_RGB32:
175 return (32 * pixel_stride) >> 3;
176 default:
177 break;
178 }
179
180 return -EINVAL;
181 }
182 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
183
184 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
185 bool hflip, bool vflip)
186 {
187 u32 r90, vf, hf;
188
189 switch (degrees) {
190 case 0:
191 vf = hf = r90 = 0;
192 break;
193 case 90:
194 vf = hf = 0;
195 r90 = 1;
196 break;
197 case 180:
198 vf = hf = 1;
199 r90 = 0;
200 break;
201 case 270:
202 vf = hf = r90 = 1;
203 break;
204 default:
205 return -EINVAL;
206 }
207
208 hf ^= (u32)hflip;
209 vf ^= (u32)vflip;
210
211 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
212 return 0;
213 }
214 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
215
216 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
217 bool hflip, bool vflip)
218 {
219 u32 r90, vf, hf;
220
221 r90 = ((u32)mode >> 2) & 0x1;
222 hf = ((u32)mode >> 1) & 0x1;
223 vf = ((u32)mode >> 0) & 0x1;
224 hf ^= (u32)hflip;
225 vf ^= (u32)vflip;
226
227 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
228 case IPU_ROTATE_NONE:
229 *degrees = 0;
230 break;
231 case IPU_ROTATE_90_RIGHT:
232 *degrees = 90;
233 break;
234 case IPU_ROTATE_180:
235 *degrees = 180;
236 break;
237 case IPU_ROTATE_90_LEFT:
238 *degrees = 270;
239 break;
240 default:
241 return -EINVAL;
242 }
243
244 return 0;
245 }
246 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
247
248 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
249 {
250 struct ipuv3_channel *channel;
251
252 dev_dbg(ipu->dev, "%s %d\n", __func__, num);
253
254 if (num > 63)
255 return ERR_PTR(-ENODEV);
256
257 mutex_lock(&ipu->channel_lock);
258
259 channel = &ipu->channel[num];
260
261 if (channel->busy) {
262 channel = ERR_PTR(-EBUSY);
263 goto out;
264 }
265
266 channel->busy = true;
267 channel->num = num;
268
269 out:
270 mutex_unlock(&ipu->channel_lock);
271
272 return channel;
273 }
274 EXPORT_SYMBOL_GPL(ipu_idmac_get);
275
276 void ipu_idmac_put(struct ipuv3_channel *channel)
277 {
278 struct ipu_soc *ipu = channel->ipu;
279
280 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
281
282 mutex_lock(&ipu->channel_lock);
283
284 channel->busy = false;
285
286 mutex_unlock(&ipu->channel_lock);
287 }
288 EXPORT_SYMBOL_GPL(ipu_idmac_put);
289
290 #define idma_mask(ch) (1 << ((ch) & 0x1f))
291
292 /*
293 * This is an undocumented feature, a write one to a channel bit in
294 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
295 * internal current buffer pointer so that transfers start from buffer
296 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
297 * only says these are read-only registers). This operation is required
298 * for channel linking to work correctly, for instance video capture
299 * pipelines that carry out image rotations will fail after the first
300 * streaming unless this function is called for each channel before
301 * re-enabling the channels.
302 */
303 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
304 {
305 struct ipu_soc *ipu = channel->ipu;
306 unsigned int chno = channel->num;
307
308 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
309 }
310
311 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
312 bool doublebuffer)
313 {
314 struct ipu_soc *ipu = channel->ipu;
315 unsigned long flags;
316 u32 reg;
317
318 spin_lock_irqsave(&ipu->lock, flags);
319
320 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
321 if (doublebuffer)
322 reg |= idma_mask(channel->num);
323 else
324 reg &= ~idma_mask(channel->num);
325 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
326
327 __ipu_idmac_reset_current_buffer(channel);
328
329 spin_unlock_irqrestore(&ipu->lock, flags);
330 }
331 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
332
333 static const struct {
334 int chnum;
335 u32 reg;
336 int shift;
337 } idmac_lock_en_info[] = {
338 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, },
339 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, },
340 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, },
341 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, },
342 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, },
343 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
344 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
345 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
346 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
347 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
348 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
349 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, },
350 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, },
351 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, },
352 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, },
353 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, },
354 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
355 };
356
357 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
358 {
359 struct ipu_soc *ipu = channel->ipu;
360 unsigned long flags;
361 u32 bursts, regval;
362 int i;
363
364 switch (num_bursts) {
365 case 0:
366 case 1:
367 bursts = 0x00; /* locking disabled */
368 break;
369 case 2:
370 bursts = 0x01;
371 break;
372 case 4:
373 bursts = 0x02;
374 break;
375 case 8:
376 bursts = 0x03;
377 break;
378 default:
379 return -EINVAL;
380 }
381
382 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
383 if (channel->num == idmac_lock_en_info[i].chnum)
384 break;
385 }
386 if (i >= ARRAY_SIZE(idmac_lock_en_info))
387 return -EINVAL;
388
389 spin_lock_irqsave(&ipu->lock, flags);
390
391 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
392 regval &= ~(0x03 << idmac_lock_en_info[i].shift);
393 regval |= (bursts << idmac_lock_en_info[i].shift);
394 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
395
396 spin_unlock_irqrestore(&ipu->lock, flags);
397
398 return 0;
399 }
400 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
401
402 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
403 {
404 unsigned long lock_flags;
405 u32 val;
406
407 spin_lock_irqsave(&ipu->lock, lock_flags);
408
409 val = ipu_cm_read(ipu, IPU_DISP_GEN);
410
411 if (mask & IPU_CONF_DI0_EN)
412 val |= IPU_DI0_COUNTER_RELEASE;
413 if (mask & IPU_CONF_DI1_EN)
414 val |= IPU_DI1_COUNTER_RELEASE;
415
416 ipu_cm_write(ipu, val, IPU_DISP_GEN);
417
418 val = ipu_cm_read(ipu, IPU_CONF);
419 val |= mask;
420 ipu_cm_write(ipu, val, IPU_CONF);
421
422 spin_unlock_irqrestore(&ipu->lock, lock_flags);
423
424 return 0;
425 }
426 EXPORT_SYMBOL_GPL(ipu_module_enable);
427
428 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
429 {
430 unsigned long lock_flags;
431 u32 val;
432
433 spin_lock_irqsave(&ipu->lock, lock_flags);
434
435 val = ipu_cm_read(ipu, IPU_CONF);
436 val &= ~mask;
437 ipu_cm_write(ipu, val, IPU_CONF);
438
439 val = ipu_cm_read(ipu, IPU_DISP_GEN);
440
441 if (mask & IPU_CONF_DI0_EN)
442 val &= ~IPU_DI0_COUNTER_RELEASE;
443 if (mask & IPU_CONF_DI1_EN)
444 val &= ~IPU_DI1_COUNTER_RELEASE;
445
446 ipu_cm_write(ipu, val, IPU_DISP_GEN);
447
448 spin_unlock_irqrestore(&ipu->lock, lock_flags);
449
450 return 0;
451 }
452 EXPORT_SYMBOL_GPL(ipu_module_disable);
453
454 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
455 {
456 struct ipu_soc *ipu = channel->ipu;
457 unsigned int chno = channel->num;
458
459 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
460 }
461 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
462
463 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
464 {
465 struct ipu_soc *ipu = channel->ipu;
466 unsigned long flags;
467 u32 reg = 0;
468
469 spin_lock_irqsave(&ipu->lock, flags);
470 switch (buf_num) {
471 case 0:
472 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
473 break;
474 case 1:
475 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
476 break;
477 case 2:
478 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
479 break;
480 }
481 spin_unlock_irqrestore(&ipu->lock, flags);
482
483 return ((reg & idma_mask(channel->num)) != 0);
484 }
485 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
486
487 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
488 {
489 struct ipu_soc *ipu = channel->ipu;
490 unsigned int chno = channel->num;
491 unsigned long flags;
492
493 spin_lock_irqsave(&ipu->lock, flags);
494
495 /* Mark buffer as ready. */
496 if (buf_num == 0)
497 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
498 else
499 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
500
501 spin_unlock_irqrestore(&ipu->lock, flags);
502 }
503 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
504
505 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
506 {
507 struct ipu_soc *ipu = channel->ipu;
508 unsigned int chno = channel->num;
509 unsigned long flags;
510
511 spin_lock_irqsave(&ipu->lock, flags);
512
513 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
514 switch (buf_num) {
515 case 0:
516 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
517 break;
518 case 1:
519 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
520 break;
521 case 2:
522 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
523 break;
524 default:
525 break;
526 }
527 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
528
529 spin_unlock_irqrestore(&ipu->lock, flags);
530 }
531 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
532
533 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
534 {
535 struct ipu_soc *ipu = channel->ipu;
536 u32 val;
537 unsigned long flags;
538
539 spin_lock_irqsave(&ipu->lock, flags);
540
541 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
542 val |= idma_mask(channel->num);
543 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
544
545 spin_unlock_irqrestore(&ipu->lock, flags);
546
547 return 0;
548 }
549 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
550
551 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
552 {
553 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
554 }
555 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
556
557 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
558 {
559 struct ipu_soc *ipu = channel->ipu;
560 unsigned long timeout;
561
562 timeout = jiffies + msecs_to_jiffies(ms);
563 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
564 idma_mask(channel->num)) {
565 if (time_after(jiffies, timeout))
566 return -ETIMEDOUT;
567 cpu_relax();
568 }
569
570 return 0;
571 }
572 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
573
574 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
575 {
576 unsigned long timeout;
577
578 timeout = jiffies + msecs_to_jiffies(ms);
579 ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
580 while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
581 if (time_after(jiffies, timeout))
582 return -ETIMEDOUT;
583 cpu_relax();
584 }
585
586 return 0;
587 }
588 EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
589
590 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
591 {
592 struct ipu_soc *ipu = channel->ipu;
593 u32 val;
594 unsigned long flags;
595
596 spin_lock_irqsave(&ipu->lock, flags);
597
598 /* Disable DMA channel(s) */
599 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
600 val &= ~idma_mask(channel->num);
601 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
602
603 __ipu_idmac_reset_current_buffer(channel);
604
605 /* Set channel buffers NOT to be ready */
606 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
607
608 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
609 idma_mask(channel->num)) {
610 ipu_cm_write(ipu, idma_mask(channel->num),
611 IPU_CHA_BUF0_RDY(channel->num));
612 }
613
614 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
615 idma_mask(channel->num)) {
616 ipu_cm_write(ipu, idma_mask(channel->num),
617 IPU_CHA_BUF1_RDY(channel->num));
618 }
619
620 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
621
622 /* Reset the double buffer */
623 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
624 val &= ~idma_mask(channel->num);
625 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
626
627 spin_unlock_irqrestore(&ipu->lock, flags);
628
629 return 0;
630 }
631 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
632
633 /*
634 * The imx6 rev. D TRM says that enabling the WM feature will increase
635 * a channel's priority. Refer to Table 36-8 Calculated priority value.
636 * The sub-module that is the sink or source for the channel must enable
637 * watermark signal for this to take effect (SMFC_WM for instance).
638 */
639 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
640 {
641 struct ipu_soc *ipu = channel->ipu;
642 unsigned long flags;
643 u32 val;
644
645 spin_lock_irqsave(&ipu->lock, flags);
646
647 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
648 if (enable)
649 val |= 1 << (channel->num % 32);
650 else
651 val &= ~(1 << (channel->num % 32));
652 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
653
654 spin_unlock_irqrestore(&ipu->lock, flags);
655 }
656 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
657
658 static int ipu_memory_reset(struct ipu_soc *ipu)
659 {
660 unsigned long timeout;
661
662 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
663
664 timeout = jiffies + msecs_to_jiffies(1000);
665 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
666 if (time_after(jiffies, timeout))
667 return -ETIME;
668 cpu_relax();
669 }
670
671 return 0;
672 }
673
674 /*
675 * Set the source mux for the given CSI. Selects either parallel or
676 * MIPI CSI2 sources.
677 */
678 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
679 {
680 unsigned long flags;
681 u32 val, mask;
682
683 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
684 IPU_CONF_CSI0_DATA_SOURCE;
685
686 spin_lock_irqsave(&ipu->lock, flags);
687
688 val = ipu_cm_read(ipu, IPU_CONF);
689 if (mipi_csi2)
690 val |= mask;
691 else
692 val &= ~mask;
693 ipu_cm_write(ipu, val, IPU_CONF);
694
695 spin_unlock_irqrestore(&ipu->lock, flags);
696 }
697 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
698
699 /*
700 * Set the source mux for the IC. Selects either CSI[01] or the VDI.
701 */
702 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
703 {
704 unsigned long flags;
705 u32 val;
706
707 spin_lock_irqsave(&ipu->lock, flags);
708
709 val = ipu_cm_read(ipu, IPU_CONF);
710 if (vdi) {
711 val |= IPU_CONF_IC_INPUT;
712 } else {
713 val &= ~IPU_CONF_IC_INPUT;
714 if (csi_id == 1)
715 val |= IPU_CONF_CSI_SEL;
716 else
717 val &= ~IPU_CONF_CSI_SEL;
718 }
719 ipu_cm_write(ipu, val, IPU_CONF);
720
721 spin_unlock_irqrestore(&ipu->lock, flags);
722 }
723 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
724
725 struct ipu_devtype {
726 const char *name;
727 unsigned long cm_ofs;
728 unsigned long cpmem_ofs;
729 unsigned long srm_ofs;
730 unsigned long tpm_ofs;
731 unsigned long csi0_ofs;
732 unsigned long csi1_ofs;
733 unsigned long ic_ofs;
734 unsigned long disp0_ofs;
735 unsigned long disp1_ofs;
736 unsigned long dc_tmpl_ofs;
737 unsigned long vdi_ofs;
738 enum ipuv3_type type;
739 };
740
741 static struct ipu_devtype ipu_type_imx51 = {
742 .name = "IPUv3EX",
743 .cm_ofs = 0x1e000000,
744 .cpmem_ofs = 0x1f000000,
745 .srm_ofs = 0x1f040000,
746 .tpm_ofs = 0x1f060000,
747 .csi0_ofs = 0x1f030000,
748 .csi1_ofs = 0x1f038000,
749 .ic_ofs = 0x1e020000,
750 .disp0_ofs = 0x1e040000,
751 .disp1_ofs = 0x1e048000,
752 .dc_tmpl_ofs = 0x1f080000,
753 .vdi_ofs = 0x1e068000,
754 .type = IPUV3EX,
755 };
756
757 static struct ipu_devtype ipu_type_imx53 = {
758 .name = "IPUv3M",
759 .cm_ofs = 0x06000000,
760 .cpmem_ofs = 0x07000000,
761 .srm_ofs = 0x07040000,
762 .tpm_ofs = 0x07060000,
763 .csi0_ofs = 0x07030000,
764 .csi1_ofs = 0x07038000,
765 .ic_ofs = 0x06020000,
766 .disp0_ofs = 0x06040000,
767 .disp1_ofs = 0x06048000,
768 .dc_tmpl_ofs = 0x07080000,
769 .vdi_ofs = 0x06068000,
770 .type = IPUV3M,
771 };
772
773 static struct ipu_devtype ipu_type_imx6q = {
774 .name = "IPUv3H",
775 .cm_ofs = 0x00200000,
776 .cpmem_ofs = 0x00300000,
777 .srm_ofs = 0x00340000,
778 .tpm_ofs = 0x00360000,
779 .csi0_ofs = 0x00230000,
780 .csi1_ofs = 0x00238000,
781 .ic_ofs = 0x00220000,
782 .disp0_ofs = 0x00240000,
783 .disp1_ofs = 0x00248000,
784 .dc_tmpl_ofs = 0x00380000,
785 .vdi_ofs = 0x00268000,
786 .type = IPUV3H,
787 };
788
789 static const struct of_device_id imx_ipu_dt_ids[] = {
790 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
791 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
792 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
793 { /* sentinel */ }
794 };
795 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
796
797 static int ipu_submodules_init(struct ipu_soc *ipu,
798 struct platform_device *pdev, unsigned long ipu_base,
799 struct clk *ipu_clk)
800 {
801 char *unit;
802 int ret;
803 struct device *dev = &pdev->dev;
804 const struct ipu_devtype *devtype = ipu->devtype;
805
806 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
807 if (ret) {
808 unit = "cpmem";
809 goto err_cpmem;
810 }
811
812 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
813 IPU_CONF_CSI0_EN, ipu_clk);
814 if (ret) {
815 unit = "csi0";
816 goto err_csi_0;
817 }
818
819 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
820 IPU_CONF_CSI1_EN, ipu_clk);
821 if (ret) {
822 unit = "csi1";
823 goto err_csi_1;
824 }
825
826 ret = ipu_ic_init(ipu, dev,
827 ipu_base + devtype->ic_ofs,
828 ipu_base + devtype->tpm_ofs);
829 if (ret) {
830 unit = "ic";
831 goto err_ic;
832 }
833
834 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
835 IPU_CONF_DI0_EN, ipu_clk);
836 if (ret) {
837 unit = "di0";
838 goto err_di_0;
839 }
840
841 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
842 IPU_CONF_DI1_EN, ipu_clk);
843 if (ret) {
844 unit = "di1";
845 goto err_di_1;
846 }
847
848 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
849 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
850 if (ret) {
851 unit = "dc_template";
852 goto err_dc;
853 }
854
855 ret = ipu_dmfc_init(ipu, dev, ipu_base +
856 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
857 if (ret) {
858 unit = "dmfc";
859 goto err_dmfc;
860 }
861
862 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
863 if (ret) {
864 unit = "dp";
865 goto err_dp;
866 }
867
868 ret = ipu_smfc_init(ipu, dev, ipu_base +
869 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
870 if (ret) {
871 unit = "smfc";
872 goto err_smfc;
873 }
874
875 return 0;
876
877 err_smfc:
878 ipu_dp_exit(ipu);
879 err_dp:
880 ipu_dmfc_exit(ipu);
881 err_dmfc:
882 ipu_dc_exit(ipu);
883 err_dc:
884 ipu_di_exit(ipu, 1);
885 err_di_1:
886 ipu_di_exit(ipu, 0);
887 err_di_0:
888 ipu_ic_exit(ipu);
889 err_ic:
890 ipu_csi_exit(ipu, 1);
891 err_csi_1:
892 ipu_csi_exit(ipu, 0);
893 err_csi_0:
894 ipu_cpmem_exit(ipu);
895 err_cpmem:
896 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
897 return ret;
898 }
899
900 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
901 {
902 unsigned long status;
903 int i, bit, irq;
904
905 for (i = 0; i < num_regs; i++) {
906
907 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
908 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
909
910 for_each_set_bit(bit, &status, 32) {
911 irq = irq_linear_revmap(ipu->domain,
912 regs[i] * 32 + bit);
913 if (irq)
914 generic_handle_irq(irq);
915 }
916 }
917 }
918
919 static void ipu_irq_handler(struct irq_desc *desc)
920 {
921 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
922 struct irq_chip *chip = irq_desc_get_chip(desc);
923 const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
924
925 chained_irq_enter(chip, desc);
926
927 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
928
929 chained_irq_exit(chip, desc);
930 }
931
932 static void ipu_err_irq_handler(struct irq_desc *desc)
933 {
934 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
935 struct irq_chip *chip = irq_desc_get_chip(desc);
936 const int int_reg[] = { 4, 5, 8, 9};
937
938 chained_irq_enter(chip, desc);
939
940 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
941
942 chained_irq_exit(chip, desc);
943 }
944
945 int ipu_map_irq(struct ipu_soc *ipu, int irq)
946 {
947 int virq;
948
949 virq = irq_linear_revmap(ipu->domain, irq);
950 if (!virq)
951 virq = irq_create_mapping(ipu->domain, irq);
952
953 return virq;
954 }
955 EXPORT_SYMBOL_GPL(ipu_map_irq);
956
957 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
958 enum ipu_channel_irq irq_type)
959 {
960 return ipu_map_irq(ipu, irq_type + channel->num);
961 }
962 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
963
964 static void ipu_submodules_exit(struct ipu_soc *ipu)
965 {
966 ipu_smfc_exit(ipu);
967 ipu_dp_exit(ipu);
968 ipu_dmfc_exit(ipu);
969 ipu_dc_exit(ipu);
970 ipu_di_exit(ipu, 1);
971 ipu_di_exit(ipu, 0);
972 ipu_ic_exit(ipu);
973 ipu_csi_exit(ipu, 1);
974 ipu_csi_exit(ipu, 0);
975 ipu_cpmem_exit(ipu);
976 }
977
978 static int platform_remove_devices_fn(struct device *dev, void *unused)
979 {
980 struct platform_device *pdev = to_platform_device(dev);
981
982 platform_device_unregister(pdev);
983
984 return 0;
985 }
986
987 static void platform_device_unregister_children(struct platform_device *pdev)
988 {
989 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
990 }
991
992 struct ipu_platform_reg {
993 struct ipu_client_platformdata pdata;
994 const char *name;
995 int reg_offset;
996 };
997
998 static const struct ipu_platform_reg client_reg[] = {
999 {
1000 .pdata = {
1001 .di = 0,
1002 .dc = 5,
1003 .dp = IPU_DP_FLOW_SYNC_BG,
1004 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
1005 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
1006 },
1007 .name = "imx-ipuv3-crtc",
1008 }, {
1009 .pdata = {
1010 .di = 1,
1011 .dc = 1,
1012 .dp = -EINVAL,
1013 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1014 .dma[1] = -EINVAL,
1015 },
1016 .name = "imx-ipuv3-crtc",
1017 }, {
1018 .pdata = {
1019 .csi = 0,
1020 .dma[0] = IPUV3_CHANNEL_CSI0,
1021 .dma[1] = -EINVAL,
1022 },
1023 .reg_offset = IPU_CM_CSI0_REG_OFS,
1024 .name = "imx-ipuv3-camera",
1025 }, {
1026 .pdata = {
1027 .csi = 1,
1028 .dma[0] = IPUV3_CHANNEL_CSI1,
1029 .dma[1] = -EINVAL,
1030 },
1031 .reg_offset = IPU_CM_CSI1_REG_OFS,
1032 .name = "imx-ipuv3-camera",
1033 },
1034 };
1035
1036 static DEFINE_MUTEX(ipu_client_id_mutex);
1037 static int ipu_client_id;
1038
1039 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
1040 {
1041 struct device *dev = ipu->dev;
1042 unsigned i;
1043 int id, ret;
1044
1045 mutex_lock(&ipu_client_id_mutex);
1046 id = ipu_client_id;
1047 ipu_client_id += ARRAY_SIZE(client_reg);
1048 mutex_unlock(&ipu_client_id_mutex);
1049
1050 for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1051 const struct ipu_platform_reg *reg = &client_reg[i];
1052 struct platform_device *pdev;
1053 struct resource res;
1054
1055 if (reg->reg_offset) {
1056 memset(&res, 0, sizeof(res));
1057 res.flags = IORESOURCE_MEM;
1058 res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset;
1059 res.end = res.start + PAGE_SIZE - 1;
1060 pdev = platform_device_register_resndata(dev, reg->name,
1061 id++, &res, 1, &reg->pdata, sizeof(reg->pdata));
1062 } else {
1063 pdev = platform_device_register_data(dev, reg->name,
1064 id++, &reg->pdata, sizeof(reg->pdata));
1065 }
1066
1067 if (IS_ERR(pdev)) {
1068 ret = PTR_ERR(pdev);
1069 goto err_register;
1070 }
1071 }
1072
1073 return 0;
1074
1075 err_register:
1076 platform_device_unregister_children(to_platform_device(dev));
1077
1078 return ret;
1079 }
1080
1081
1082 static int ipu_irq_init(struct ipu_soc *ipu)
1083 {
1084 struct irq_chip_generic *gc;
1085 struct irq_chip_type *ct;
1086 unsigned long unused[IPU_NUM_IRQS / 32] = {
1087 0x400100d0, 0xffe000fd,
1088 0x400100d0, 0xffe000fd,
1089 0x400100d0, 0xffe000fd,
1090 0x4077ffff, 0xffe7e1fd,
1091 0x23fffffe, 0x8880fff0,
1092 0xf98fe7d0, 0xfff81fff,
1093 0x400100d0, 0xffe000fd,
1094 0x00000000,
1095 };
1096 int ret, i;
1097
1098 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1099 &irq_generic_chip_ops, ipu);
1100 if (!ipu->domain) {
1101 dev_err(ipu->dev, "failed to add irq domain\n");
1102 return -ENODEV;
1103 }
1104
1105 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1106 handle_level_irq, 0, 0, 0);
1107 if (ret < 0) {
1108 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1109 irq_domain_remove(ipu->domain);
1110 return ret;
1111 }
1112
1113 for (i = 0; i < IPU_NUM_IRQS; i += 32)
1114 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1115
1116 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1117 gc = irq_get_domain_generic_chip(ipu->domain, i);
1118 gc->reg_base = ipu->cm_reg;
1119 gc->unused = unused[i / 32];
1120 ct = gc->chip_types;
1121 ct->chip.irq_ack = irq_gc_ack_set_bit;
1122 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1123 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1124 ct->regs.ack = IPU_INT_STAT(i / 32);
1125 ct->regs.mask = IPU_INT_CTRL(i / 32);
1126 }
1127
1128 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1129 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1130 ipu);
1131
1132 return 0;
1133 }
1134
1135 static void ipu_irq_exit(struct ipu_soc *ipu)
1136 {
1137 int i, irq;
1138
1139 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1140 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
1141
1142 /* TODO: remove irq_domain_generic_chips */
1143
1144 for (i = 0; i < IPU_NUM_IRQS; i++) {
1145 irq = irq_linear_revmap(ipu->domain, i);
1146 if (irq)
1147 irq_dispose_mapping(irq);
1148 }
1149
1150 irq_domain_remove(ipu->domain);
1151 }
1152
1153 void ipu_dump(struct ipu_soc *ipu)
1154 {
1155 int i;
1156
1157 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1158 ipu_cm_read(ipu, IPU_CONF));
1159 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1160 ipu_idmac_read(ipu, IDMAC_CONF));
1161 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1162 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1163 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1164 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1165 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1166 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1167 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1168 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1169 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1170 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1171 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1172 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1173 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1174 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1175 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1176 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1177 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1178 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1179 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1180 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1181 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1182 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1183 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1184 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1185 for (i = 0; i < 15; i++)
1186 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1187 ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1188 }
1189 EXPORT_SYMBOL_GPL(ipu_dump);
1190
1191 static int ipu_probe(struct platform_device *pdev)
1192 {
1193 const struct of_device_id *of_id =
1194 of_match_device(imx_ipu_dt_ids, &pdev->dev);
1195 struct ipu_soc *ipu;
1196 struct resource *res;
1197 unsigned long ipu_base;
1198 int i, ret, irq_sync, irq_err;
1199 const struct ipu_devtype *devtype;
1200
1201 devtype = of_id->data;
1202
1203 irq_sync = platform_get_irq(pdev, 0);
1204 irq_err = platform_get_irq(pdev, 1);
1205 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1206
1207 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1208 irq_sync, irq_err);
1209
1210 if (!res || irq_sync < 0 || irq_err < 0)
1211 return -ENODEV;
1212
1213 ipu_base = res->start;
1214
1215 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1216 if (!ipu)
1217 return -ENODEV;
1218
1219 for (i = 0; i < 64; i++)
1220 ipu->channel[i].ipu = ipu;
1221 ipu->devtype = devtype;
1222 ipu->ipu_type = devtype->type;
1223
1224 spin_lock_init(&ipu->lock);
1225 mutex_init(&ipu->channel_lock);
1226
1227 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
1228 ipu_base + devtype->cm_ofs);
1229 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
1230 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1231 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
1232 ipu_base + devtype->cpmem_ofs);
1233 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
1234 ipu_base + devtype->csi0_ofs);
1235 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
1236 ipu_base + devtype->csi1_ofs);
1237 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1238 ipu_base + devtype->ic_ofs);
1239 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
1240 ipu_base + devtype->disp0_ofs);
1241 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
1242 ipu_base + devtype->disp1_ofs);
1243 dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
1244 ipu_base + devtype->srm_ofs);
1245 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
1246 ipu_base + devtype->tpm_ofs);
1247 dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
1248 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1249 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1250 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1251 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
1252 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1253 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
1254 ipu_base + devtype->vdi_ofs);
1255
1256 ipu->cm_reg = devm_ioremap(&pdev->dev,
1257 ipu_base + devtype->cm_ofs, PAGE_SIZE);
1258 ipu->idmac_reg = devm_ioremap(&pdev->dev,
1259 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1260 PAGE_SIZE);
1261
1262 if (!ipu->cm_reg || !ipu->idmac_reg)
1263 return -ENOMEM;
1264
1265 ipu->clk = devm_clk_get(&pdev->dev, "bus");
1266 if (IS_ERR(ipu->clk)) {
1267 ret = PTR_ERR(ipu->clk);
1268 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1269 return ret;
1270 }
1271
1272 platform_set_drvdata(pdev, ipu);
1273
1274 ret = clk_prepare_enable(ipu->clk);
1275 if (ret) {
1276 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1277 return ret;
1278 }
1279
1280 ipu->dev = &pdev->dev;
1281 ipu->irq_sync = irq_sync;
1282 ipu->irq_err = irq_err;
1283
1284 ret = ipu_irq_init(ipu);
1285 if (ret)
1286 goto out_failed_irq;
1287
1288 ret = device_reset(&pdev->dev);
1289 if (ret) {
1290 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1291 goto out_failed_reset;
1292 }
1293 ret = ipu_memory_reset(ipu);
1294 if (ret)
1295 goto out_failed_reset;
1296
1297 /* Set MCU_T to divide MCU access window into 2 */
1298 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1299 IPU_DISP_GEN);
1300
1301 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1302 if (ret)
1303 goto failed_submodules_init;
1304
1305 ret = ipu_add_client_devices(ipu, ipu_base);
1306 if (ret) {
1307 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1308 ret);
1309 goto failed_add_clients;
1310 }
1311
1312 dev_info(&pdev->dev, "%s probed\n", devtype->name);
1313
1314 return 0;
1315
1316 failed_add_clients:
1317 ipu_submodules_exit(ipu);
1318 failed_submodules_init:
1319 out_failed_reset:
1320 ipu_irq_exit(ipu);
1321 out_failed_irq:
1322 clk_disable_unprepare(ipu->clk);
1323 return ret;
1324 }
1325
1326 static int ipu_remove(struct platform_device *pdev)
1327 {
1328 struct ipu_soc *ipu = platform_get_drvdata(pdev);
1329
1330 platform_device_unregister_children(pdev);
1331 ipu_submodules_exit(ipu);
1332 ipu_irq_exit(ipu);
1333
1334 clk_disable_unprepare(ipu->clk);
1335
1336 return 0;
1337 }
1338
1339 static struct platform_driver imx_ipu_driver = {
1340 .driver = {
1341 .name = "imx-ipuv3",
1342 .of_match_table = imx_ipu_dt_ids,
1343 },
1344 .probe = ipu_probe,
1345 .remove = ipu_remove,
1346 };
1347
1348 module_platform_driver(imx_ipu_driver);
1349
1350 MODULE_ALIAS("platform:imx-ipuv3");
1351 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1352 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1353 MODULE_LICENSE("GPL");
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