include/linux/mmc/dw_mmc.h

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #ifndef LINUX_MMC_DW_MMC_H
  15 #define LINUX_MMC_DW_MMC_H
  16
  17 #include <linux/scatterlist.h>
  18 #include <linux/mmc/core.h>
  19
  20 #define MAX_MCI_SLOTS   2
  21
  22 enum dw_mci_state {
  23         STATE_IDLE = 0,
  24         STATE_SENDING_CMD,
  25         STATE_SENDING_DATA,
  26         STATE_DATA_BUSY,
  27         STATE_SENDING_STOP,
  28         STATE_DATA_ERROR,
  29 };
  30
  31 enum {
  32         EVENT_CMD_COMPLETE = 0,
  33         EVENT_XFER_COMPLETE,
  34         EVENT_DATA_COMPLETE,
  35         EVENT_DATA_ERROR,
  36         EVENT_XFER_ERROR
  37 };
  38
  39 struct mmc_data;
  40
  41 /**
  42  * struct dw_mci - MMC controller state shared between all slots
  43  * @lock: Spinlock protecting the queue and associated data.
  44  * @regs: Pointer to MMIO registers.
  45  * @sg: Scatterlist entry currently being processed by PIO code, if any.
  46  * @sg_miter: PIO mapping scatterlist iterator.
  47  * @cur_slot: The slot which is currently using the controller.
  48  * @mrq: The request currently being processed on @cur_slot,
  49  *      or NULL if the controller is idle.
  50  * @cmd: The command currently being sent to the card, or NULL.
  51  * @data: The data currently being transferred, or NULL if no data
  52  *      transfer is in progress.
  53  * @use_dma: Whether DMA channel is initialized or not.
  54  * @using_dma: Whether DMA is in use for the current transfer.
  55  * @sg_dma: Bus address of DMA buffer.
  56  * @sg_cpu: Virtual address of DMA buffer.
  57  * @dma_ops: Pointer to platform-specific DMA callbacks.
  58  * @cmd_status: Snapshot of SR taken upon completion of the current
  59  *      command. Only valid when EVENT_CMD_COMPLETE is pending.
  60  * @data_status: Snapshot of SR taken upon completion of the current
  61  *      data transfer. Only valid when EVENT_DATA_COMPLETE or
  62  *      EVENT_DATA_ERROR is pending.
  63  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
  64  *      to be sent.
  65  * @dir_status: Direction of current transfer.
  66  * @tasklet: Tasklet running the request state machine.
  67  * @card_tasklet: Tasklet handling card detect.
  68  * @pending_events: Bitmask of events flagged by the interrupt handler
  69  *      to be processed by the tasklet.
  70  * @completed_events: Bitmask of events which the state machine has
  71  *      processed.
  72  * @state: Tasklet state.
  73  * @queue: List of slots waiting for access to the controller.
  74  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
  75  *      rate and timeout calculations.
  76  * @current_speed: Configured rate of the controller.
  77  * @num_slots: Number of slots available.
  78  * @verid: Denote Version ID.
  79  * @data_offset: Set the offset of DATA register according to VERID.
  80  * @dev: Device associated with the MMC controller.
  81  * @pdata: Platform data associated with the MMC controller.
  82  * @drv_data: Driver specific data for identified variant of the controller
  83  * @priv: Implementation defined private data.
  84  * @biu_clk: Pointer to bus interface unit clock instance.
  85  * @ciu_clk: Pointer to card interface unit clock instance.
  86  * @slot: Slots sharing this MMC controller.
  87  * @fifo_depth: depth of FIFO.
  88  * @data_shift: log2 of FIFO item size.
  89  * @part_buf_start: Start index in part_buf.
  90  * @part_buf_count: Bytes of partial data in part_buf.
  91  * @part_buf: Simple buffer for partial fifo reads/writes.
  92  * @push_data: Pointer to FIFO push function.
  93  * @pull_data: Pointer to FIFO pull function.
  94  * @quirks: Set of quirks that apply to specific versions of the IP.
  95  * @irq_flags: The flags to be passed to request_irq.
  96  * @irq: The irq value to be passed to request_irq.
  97  *
  98  * Locking
  99  * =======
 100  *
 101  * @lock is a softirq-safe spinlock protecting @queue as well as
 102  * @cur_slot, @mrq and @state. These must always be updated
 103  * at the same time while holding @lock.
 104  *
 105  * The @mrq field of struct dw_mci_slot is also protected by @lock,
 106  * and must always be written at the same time as the slot is added to
 107  * @queue.
 108  *
 109  * @pending_events and @completed_events are accessed using atomic bit
 110  * operations, so they don't need any locking.
 111  *
 112  * None of the fields touched by the interrupt handler need any
 113  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
 114  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
 115  * interrupts must be disabled and @data_status updated with a
 116  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
 117  * CMDRDY interrupt must be disabled and @cmd_status updated with a
 118  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
 119  * bytes_xfered field of @data must be written. This is ensured by
 120  * using barriers.
 121  */
 122 struct dw_mci {
 123         spinlock_t              lock;
 124         void __iomem            *regs;
 125
 126         struct scatterlist      *sg;
 127         struct sg_mapping_iter  sg_miter;
 128
 129         struct dw_mci_slot      *cur_slot;
 130         struct mmc_request      *mrq;
 131         struct mmc_command      *cmd;
 132         struct mmc_data         *data;
 133         struct mmc_command      stop_abort;
 134         unsigned int            prev_blksz;
 135         unsigned char           timing;
 136         struct workqueue_struct *card_workqueue;
 137
 138         /* DMA interface members*/
 139         int                     use_dma;
 140         int                     using_dma;
 141
 142         dma_addr_t              sg_dma;
 143         void                    *sg_cpu;
 144         const struct dw_mci_dma_ops     *dma_ops;
 145 #ifdef CONFIG_MMC_DW_IDMAC
 146         unsigned int            ring_size;
 147 #else
 148         struct dw_mci_dma_data  *dma_data;
 149 #endif
 150         u32                     cmd_status;
 151         u32                     data_status;
 152         u32                     stop_cmdr;
 153         u32                     dir_status;
 154         struct tasklet_struct   tasklet;
 155         struct work_struct      card_work;
 156         unsigned long           pending_events;
 157         unsigned long           completed_events;
 158         enum dw_mci_state       state;
 159         struct list_head        queue;
 160
 161         u32                     bus_hz;
 162         u32                     current_speed;
 163         u32                     num_slots;
 164         u32                     fifoth_val;
 165         u16                     verid;
 166         u16                     data_offset;
 167         struct device           *dev;
 168         struct dw_mci_board     *pdata;
 169         const struct dw_mci_drv_data    *drv_data;
 170         void                    *priv;
 171         struct clk              *biu_clk;
 172         struct clk              *ciu_clk;
 173         struct dw_mci_slot      *slot[MAX_MCI_SLOTS];
 174
 175         /* FIFO push and pull */
 176         int                     fifo_depth;
 177         int                     data_shift;
 178         u8                      part_buf_start;
 179         u8                      part_buf_count;
 180         union {
 181                 u16             part_buf16;
 182                 u32             part_buf32;
 183                 u64             part_buf;
 184         };
 185         void (*push_data)(struct dw_mci *host, void *buf, int cnt);
 186         void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
 187
 188         /* Workaround flags */
 189         u32                     quirks;
 190
 191         struct regulator        *vmmc;  /* Power regulator */
 192         unsigned long           irq_flags; /* IRQ flags */
 193         int                     irq;
 194 };
 195
 196 /* DMA ops for Internal/External DMAC interface */
 197 struct dw_mci_dma_ops {
 198         /* DMA Ops */
 199         int (*init)(struct dw_mci *host);
 200         void (*start)(struct dw_mci *host, unsigned int sg_len);
 201         void (*complete)(struct dw_mci *host);
 202         void (*stop)(struct dw_mci *host);
 203         void (*cleanup)(struct dw_mci *host);
 204         void (*exit)(struct dw_mci *host);
 205 };
 206
 207 /* IP Quirks/flags. */
 208 /* DTO fix for command transmission with IDMAC configured */
 209 #define DW_MCI_QUIRK_IDMAC_DTO                  BIT(0)
 210 /* delay needed between retries on some 2.11a implementations */
 211 #define DW_MCI_QUIRK_RETRY_DELAY                BIT(1)
 212 /* High Speed Capable - Supports HS cards (up to 50MHz) */
 213 #define DW_MCI_QUIRK_HIGHSPEED                  BIT(2)
 214 /* Unreliable card detection */
 215 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION      BIT(3)
 216
 217 /* Slot level quirks */
 218 /* This slot has no write protect */
 219 #define DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT      BIT(0)
 220
 221 struct dma_pdata;
 222
 223 struct block_settings {
 224         unsigned short  max_segs;       /* see blk_queue_max_segments */
 225         unsigned int    max_blk_size;   /* maximum size of one mmc block */
 226         unsigned int    max_blk_count;  /* maximum number of blocks in one req*/
 227         unsigned int    max_req_size;   /* maximum number of bytes in one req*/
 228         unsigned int    max_seg_size;   /* see blk_queue_max_segment_size */
 229 };
 230
 231 /* Board platform data */
 232 struct dw_mci_board {
 233         u32 num_slots;
 234
 235         u32 quirks; /* Workaround / Quirk flags */
 236         unsigned int bus_hz; /* Clock speed at the cclk_in pad */
 237
 238         u32 caps;       /* Capabilities */
 239         u32 caps2;      /* More capabilities */
 240         u32 pm_caps;    /* PM capabilities */
 241         /*
 242          * Override fifo depth. If 0, autodetect it from the FIFOTH register,
 243          * but note that this may not be reliable after a bootloader has used
 244          * it.
 245          */
 246         unsigned int fifo_depth;
 247
 248         /* delay in mS before detecting cards after interrupt */
 249         u32 detect_delay_ms;
 250
 251         int (*init)(u32 slot_id, irq_handler_t , void *);
 252         int (*get_ro)(u32 slot_id);
 253         int (*get_cd)(u32 slot_id);
 254         int (*get_ocr)(u32 slot_id);
 255         int (*get_bus_wd)(u32 slot_id);
 256         /*
 257          * Enable power to selected slot and set voltage to desired level.
 258          * Voltage levels are specified using MMC_VDD_xxx defines defined
 259          * in linux/mmc/host.h file.
 260          */
 261         void (*setpower)(u32 slot_id, u32 volt);
 262         void (*exit)(u32 slot_id);
 263         void (*select_slot)(u32 slot_id);
 264
 265         struct dw_mci_dma_ops *dma_ops;
 266         struct dma_pdata *data;
 267         struct block_settings *blk_settings;
 268 };
 269
 270 #endif /* LINUX_MMC_DW_MMC_H */