2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <linux/bitops.h>
27 #include <plat/clock.h>
28 #include <plat/clockdomain.h>
30 #include <plat/prcm.h>
34 #include "prm-regbits-24xx.h"
36 #include "cm-regbits-24xx.h"
37 #include "cm-regbits-34xx.h"
41 /*-------------------------------------------------------------------------
42 * OMAP2/3/4 specific clock functions
43 *-------------------------------------------------------------------------*/
46 * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
49 * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
50 * don't take effect until the VALID_CONFIG bit is written, write the
51 * VALID_CONFIG bit and wait for the write to complete. No return value.
53 static void _omap2xxx_clk_commit(struct clk
*clk
)
55 if (!cpu_is_omap24xx())
58 if (!(clk
->flags
& DELAYED_APP
))
61 prm_write_mod_reg(OMAP24XX_VALID_CONFIG
, OMAP24XX_GR_MOD
,
62 OMAP2_PRCM_CLKCFG_CTRL_OFFSET
);
64 prm_read_mod_reg(OMAP24XX_GR_MOD
, OMAP2_PRCM_CLKCFG_CTRL_OFFSET
);
68 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
69 * @clk: OMAP clock struct ptr to use
71 * Convert a clockdomain name stored in a struct clk 'clk' into a
72 * clockdomain pointer, and save it into the struct clk. Intended to be
73 * called during clk_register(). No return value.
75 void omap2_init_clk_clkdm(struct clk
*clk
)
77 struct clockdomain
*clkdm
;
82 clkdm
= clkdm_lookup(clk
->clkdm_name
);
84 pr_debug("clock: associated clk %s to clkdm %s\n",
85 clk
->name
, clk
->clkdm_name
);
88 pr_debug("clock: could not associate clk %s to "
89 "clkdm %s\n", clk
->name
, clk
->clkdm_name
);
94 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
95 * @clk: OMAP clock struct ptr to use
97 * Given a pointer to a source-selectable struct clk, read the hardware
98 * register and determine what its parent is currently set to. Update the
99 * clk->parent field with the appropriate clk ptr.
101 void omap2_init_clksel_parent(struct clk
*clk
)
103 const struct clksel
*clks
;
104 const struct clksel_rate
*clkr
;
110 r
= __raw_readl(clk
->clksel_reg
) & clk
->clksel_mask
;
111 r
>>= __ffs(clk
->clksel_mask
);
113 for (clks
= clk
->clksel
; clks
->parent
&& !found
; clks
++) {
114 for (clkr
= clks
->rates
; clkr
->div
&& !found
; clkr
++) {
115 if ((clkr
->flags
& cpu_mask
) && (clkr
->val
== r
)) {
116 if (clk
->parent
!= clks
->parent
) {
117 pr_debug("clock: inited %s parent "
119 clk
->name
, clks
->parent
->name
,
121 clk
->parent
->name
: "NULL"));
122 clk_reparent(clk
, clks
->parent
);
130 printk(KERN_ERR
"clock: init parent: could not find "
131 "regval %0x for clock %s\n", r
, clk
->name
);
137 * omap2_clk_dflt_find_companion - find companion clock to @clk
138 * @clk: struct clk * to find the companion clock of
139 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
140 * @other_bit: u8 ** to return the companion clock bit shift in
142 * Note: We don't need special code here for INVERT_ENABLE for the
143 * time being since INVERT_ENABLE only applies to clocks enabled by
146 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
147 * just a matter of XORing the bits.
149 * Some clocks don't have companion clocks. For example, modules with
150 * only an interface clock (such as MAILBOXES) don't have a companion
151 * clock. Right now, this code relies on the hardware exporting a bit
152 * in the correct companion register that indicates that the
153 * nonexistent 'companion clock' is active. Future patches will
154 * associate this type of code with per-module data structures to
155 * avoid this issue, and remove the casts. No return value.
157 void omap2_clk_dflt_find_companion(struct clk
*clk
, void __iomem
**other_reg
,
163 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
164 * it's just a matter of XORing the bits.
166 r
= ((__force u32
)clk
->enable_reg
^ (CM_FCLKEN
^ CM_ICLKEN
));
168 *other_reg
= (__force
void __iomem
*)r
;
169 *other_bit
= clk
->enable_bit
;
173 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
174 * @clk: struct clk * to find IDLEST info for
175 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
176 * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in
178 * Return the CM_IDLEST register address and bit shift corresponding
179 * to the module that "owns" this clock. This default code assumes
180 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
181 * the IDLEST register address ID corresponds to the CM_*CLKEN
182 * register address ID (e.g., that CM_FCLKEN2 corresponds to
183 * CM_IDLEST2). This is not true for all modules. No return value.
185 void omap2_clk_dflt_find_idlest(struct clk
*clk
, void __iomem
**idlest_reg
,
190 r
= (((__force u32
)clk
->enable_reg
& ~0xf0) | 0x20);
191 *idlest_reg
= (__force
void __iomem
*)r
;
192 *idlest_bit
= clk
->enable_bit
;
196 * omap2_module_wait_ready - wait for an OMAP module to leave IDLE
197 * @clk: struct clk * belonging to the module
199 * If the necessary clocks for the OMAP hardware IP block that
200 * corresponds to clock @clk are enabled, then wait for the module to
201 * indicate readiness (i.e., to leave IDLE). This code does not
202 * belong in the clock code and will be moved in the medium term to
203 * module-dependent code. No return value.
205 static void omap2_module_wait_ready(struct clk
*clk
)
207 void __iomem
*companion_reg
, *idlest_reg
;
208 u8 other_bit
, idlest_bit
;
210 /* Not all modules have multiple clocks that their IDLEST depends on */
211 if (clk
->ops
->find_companion
) {
212 clk
->ops
->find_companion(clk
, &companion_reg
, &other_bit
);
213 if (!(__raw_readl(companion_reg
) & (1 << other_bit
)))
217 clk
->ops
->find_idlest(clk
, &idlest_reg
, &idlest_bit
);
219 omap2_cm_wait_idlest(idlest_reg
, (1 << idlest_bit
), clk
->name
);
222 int omap2_dflt_clk_enable(struct clk
*clk
)
226 if (unlikely(clk
->enable_reg
== NULL
)) {
227 pr_err("clock.c: Enable for %s without enable code\n",
229 return 0; /* REVISIT: -EINVAL */
232 v
= __raw_readl(clk
->enable_reg
);
233 if (clk
->flags
& INVERT_ENABLE
)
234 v
&= ~(1 << clk
->enable_bit
);
236 v
|= (1 << clk
->enable_bit
);
237 __raw_writel(v
, clk
->enable_reg
);
238 v
= __raw_readl(clk
->enable_reg
); /* OCP barrier */
240 if (clk
->ops
->find_idlest
)
241 omap2_module_wait_ready(clk
);
246 void omap2_dflt_clk_disable(struct clk
*clk
)
250 if (!clk
->enable_reg
) {
252 * 'Independent' here refers to a clock which is not
253 * controlled by its parent.
255 printk(KERN_ERR
"clock: clk_disable called on independent "
256 "clock %s which has no enable_reg\n", clk
->name
);
260 v
= __raw_readl(clk
->enable_reg
);
261 if (clk
->flags
& INVERT_ENABLE
)
262 v
|= (1 << clk
->enable_bit
);
264 v
&= ~(1 << clk
->enable_bit
);
265 __raw_writel(v
, clk
->enable_reg
);
266 /* No OCP barrier needed here since it is a disable operation */
269 const struct clkops clkops_omap2_dflt_wait
= {
270 .enable
= omap2_dflt_clk_enable
,
271 .disable
= omap2_dflt_clk_disable
,
272 .find_companion
= omap2_clk_dflt_find_companion
,
273 .find_idlest
= omap2_clk_dflt_find_idlest
,
276 const struct clkops clkops_omap2_dflt
= {
277 .enable
= omap2_dflt_clk_enable
,
278 .disable
= omap2_dflt_clk_disable
,
281 /* Enables clock without considering parent dependencies or use count
282 * REVISIT: Maybe change this to use clk->enable like on omap1?
284 static int _omap2_clk_enable(struct clk
*clk
)
286 return clk
->ops
->enable(clk
);
289 /* Disables clock without considering parent dependencies or use count */
290 static void _omap2_clk_disable(struct clk
*clk
)
292 clk
->ops
->disable(clk
);
295 void omap2_clk_disable(struct clk
*clk
)
297 if (clk
->usecount
> 0 && !(--clk
->usecount
)) {
298 _omap2_clk_disable(clk
);
300 omap2_clk_disable(clk
->parent
);
302 omap2_clkdm_clk_disable(clk
->clkdm
, clk
);
307 int omap2_clk_enable(struct clk
*clk
)
311 if (clk
->usecount
++ == 0) {
313 omap2_clkdm_clk_enable(clk
->clkdm
, clk
);
316 ret
= omap2_clk_enable(clk
->parent
);
321 ret
= _omap2_clk_enable(clk
);
324 omap2_clk_disable(clk
->parent
);
333 omap2_clkdm_clk_disable(clk
->clkdm
, clk
);
339 * Used for clocks that are part of CLKSEL_xyz governed clocks.
340 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
342 unsigned long omap2_clksel_recalc(struct clk
*clk
)
347 pr_debug("clock: recalc'ing clksel clk %s\n", clk
->name
);
349 div
= omap2_clksel_get_divisor(clk
);
353 rate
= clk
->parent
->rate
/ div
;
355 pr_debug("clock: new clock rate is %ld (div %d)\n", rate
, div
);
361 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
362 * @clk: OMAP struct clk ptr to inspect
363 * @src_clk: OMAP struct clk ptr of the parent clk to search for
365 * Scan the struct clksel array associated with the clock to find
366 * the element associated with the supplied parent clock address.
367 * Returns a pointer to the struct clksel on success or NULL on error.
369 static const struct clksel
*omap2_get_clksel_by_parent(struct clk
*clk
,
372 const struct clksel
*clks
;
377 for (clks
= clk
->clksel
; clks
->parent
; clks
++) {
378 if (clks
->parent
== src_clk
)
379 break; /* Found the requested parent */
383 printk(KERN_ERR
"clock: Could not find parent clock %s in "
384 "clksel array of clock %s\n", src_clk
->name
,
393 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
394 * @clk: OMAP struct clk to use
395 * @target_rate: desired clock rate
396 * @new_div: ptr to where we should store the divisor
398 * Finds 'best' divider value in an array based on the source and target
399 * rates. The divider array must be sorted with smallest divider first.
400 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
401 * they are only settable as part of virtual_prcm set.
403 * Returns the rounded clock rate or returns 0xffffffff on error.
405 u32
omap2_clksel_round_rate_div(struct clk
*clk
, unsigned long target_rate
,
408 unsigned long test_rate
;
409 const struct clksel
*clks
;
410 const struct clksel_rate
*clkr
;
413 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
414 clk
->name
, target_rate
);
418 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
422 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
423 if (!(clkr
->flags
& cpu_mask
))
427 if (clkr
->div
<= last_div
)
428 pr_err("clock: clksel_rate table not sorted "
429 "for clock %s", clk
->name
);
431 last_div
= clkr
->div
;
433 test_rate
= clk
->parent
->rate
/ clkr
->div
;
435 if (test_rate
<= target_rate
)
436 break; /* found it */
440 pr_err("clock: Could not find divisor for target "
441 "rate %ld for clock %s parent %s\n", target_rate
,
442 clk
->name
, clk
->parent
->name
);
446 *new_div
= clkr
->div
;
448 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div
,
449 (clk
->parent
->rate
/ clkr
->div
));
451 return (clk
->parent
->rate
/ clkr
->div
);
455 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
456 * @clk: OMAP struct clk to use
457 * @target_rate: desired clock rate
459 * Compatibility wrapper for OMAP clock framework
460 * Finds best target rate based on the source clock and possible dividers.
461 * rates. The divider array must be sorted with smallest divider first.
462 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
463 * they are only settable as part of virtual_prcm set.
465 * Returns the rounded clock rate or returns 0xffffffff on error.
467 long omap2_clksel_round_rate(struct clk
*clk
, unsigned long target_rate
)
471 return omap2_clksel_round_rate_div(clk
, target_rate
, &new_div
);
475 /* Given a clock and a rate apply a clock specific rounding function */
476 long omap2_clk_round_rate(struct clk
*clk
, unsigned long rate
)
479 return clk
->round_rate(clk
, rate
);
481 if (clk
->flags
& RATE_FIXED
)
482 printk(KERN_ERR
"clock: generic omap2_clk_round_rate called "
483 "on fixed-rate clock %s\n", clk
->name
);
489 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
490 * @clk: OMAP struct clk to use
491 * @field_val: register field value to find
493 * Given a struct clk of a rate-selectable clksel clock, and a register field
494 * value to search for, find the corresponding clock divisor. The register
495 * field value should be pre-masked and shifted down so the LSB is at bit 0
496 * before calling. Returns 0 on error
498 u32
omap2_clksel_to_divisor(struct clk
*clk
, u32 field_val
)
500 const struct clksel
*clks
;
501 const struct clksel_rate
*clkr
;
503 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
507 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
508 if ((clkr
->flags
& cpu_mask
) && (clkr
->val
== field_val
))
513 printk(KERN_ERR
"clock: Could not find fieldval %d for "
514 "clock %s parent %s\n", field_val
, clk
->name
,
523 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
524 * @clk: OMAP struct clk to use
525 * @div: integer divisor to search for
527 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
528 * find the corresponding register field value. The return register value is
529 * the value before left-shifting. Returns ~0 on error
531 u32
omap2_divisor_to_clksel(struct clk
*clk
, u32 div
)
533 const struct clksel
*clks
;
534 const struct clksel_rate
*clkr
;
536 /* should never happen */
539 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
543 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
544 if ((clkr
->flags
& cpu_mask
) && (clkr
->div
== div
))
549 printk(KERN_ERR
"clock: Could not find divisor %d for "
550 "clock %s parent %s\n", div
, clk
->name
,
559 * omap2_clksel_get_divisor - get current divider applied to parent clock.
560 * @clk: OMAP struct clk to use.
562 * Returns the integer divisor upon success or 0 on error.
564 u32
omap2_clksel_get_divisor(struct clk
*clk
)
568 if (!clk
->clksel_mask
)
571 v
= __raw_readl(clk
->clksel_reg
) & clk
->clksel_mask
;
572 v
>>= __ffs(clk
->clksel_mask
);
574 return omap2_clksel_to_divisor(clk
, v
);
577 int omap2_clksel_set_rate(struct clk
*clk
, unsigned long rate
)
579 u32 v
, field_val
, validrate
, new_div
= 0;
581 if (!clk
->clksel_mask
)
584 validrate
= omap2_clksel_round_rate_div(clk
, rate
, &new_div
);
585 if (validrate
!= rate
)
588 field_val
= omap2_divisor_to_clksel(clk
, new_div
);
592 v
= __raw_readl(clk
->clksel_reg
);
593 v
&= ~clk
->clksel_mask
;
594 v
|= field_val
<< __ffs(clk
->clksel_mask
);
595 __raw_writel(v
, clk
->clksel_reg
);
596 v
= __raw_readl(clk
->clksel_reg
); /* OCP barrier */
598 clk
->rate
= clk
->parent
->rate
/ new_div
;
600 _omap2xxx_clk_commit(clk
);
606 /* Set the clock rate for a clock source */
607 int omap2_clk_set_rate(struct clk
*clk
, unsigned long rate
)
611 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk
->name
, rate
);
613 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
614 rate table mechanism, driven by mpu_speed */
615 if (clk
->flags
& CONFIG_PARTICIPANT
)
618 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
620 ret
= clk
->set_rate(clk
, rate
);
626 * Converts encoded control register address into a full address
627 * On error, the return value (parent_div) will be 0.
629 static u32
_omap2_clksel_get_src_field(struct clk
*src_clk
, struct clk
*clk
,
632 const struct clksel
*clks
;
633 const struct clksel_rate
*clkr
;
635 clks
= omap2_get_clksel_by_parent(clk
, src_clk
);
639 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
640 if (clkr
->flags
& cpu_mask
&& clkr
->flags
& DEFAULT_RATE
)
641 break; /* Found the default rate for this platform */
645 printk(KERN_ERR
"clock: Could not find default rate for "
646 "clock %s parent %s\n", clk
->name
,
647 src_clk
->parent
->name
);
651 /* Should never happen. Add a clksel mask to the struct clk. */
652 WARN_ON(clk
->clksel_mask
== 0);
654 *field_val
= clkr
->val
;
659 int omap2_clk_set_parent(struct clk
*clk
, struct clk
*new_parent
)
661 u32 field_val
, v
, parent_div
;
663 if (clk
->flags
& CONFIG_PARTICIPANT
)
669 parent_div
= _omap2_clksel_get_src_field(new_parent
, clk
, &field_val
);
673 /* Set new source value (previous dividers if any in effect) */
674 v
= __raw_readl(clk
->clksel_reg
);
675 v
&= ~clk
->clksel_mask
;
676 v
|= field_val
<< __ffs(clk
->clksel_mask
);
677 __raw_writel(v
, clk
->clksel_reg
);
678 v
= __raw_readl(clk
->clksel_reg
); /* OCP barrier */
680 _omap2xxx_clk_commit(clk
);
682 clk_reparent(clk
, new_parent
);
684 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
685 clk
->rate
= new_parent
->rate
;
688 clk
->rate
/= parent_div
;
690 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
691 clk
->name
, clk
->parent
->name
, clk
->rate
);
696 /*-------------------------------------------------------------------------
697 * Omap2 clock reset and init functions
698 *-------------------------------------------------------------------------*/
700 #ifdef CONFIG_OMAP_RESET_CLOCKS
701 void omap2_clk_disable_unused(struct clk
*clk
)
705 v
= (clk
->flags
& INVERT_ENABLE
) ? (1 << clk
->enable_bit
) : 0;
707 regval32
= __raw_readl(clk
->enable_reg
);
708 if ((regval32
& (1 << clk
->enable_bit
)) == v
)
711 printk(KERN_DEBUG
"Disabling unused clock \"%s\"\n", clk
->name
);
712 if (cpu_is_omap34xx()) {
713 omap2_clk_enable(clk
);
714 omap2_clk_disable(clk
);
716 _omap2_clk_disable(clk
);
717 if (clk
->clkdm
!= NULL
)
718 pwrdm_clkdm_state_switch(clk
->clkdm
);