drivers/scsi/cxlflash/common.h

   1 /*
   2  * CXL Flash Device Driver
   3  *
   4  * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
   5  *             Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
   6  *
   7  * Copyright (C) 2015 IBM Corporation
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14
  15 #ifndef _CXLFLASH_COMMON_H
  16 #define _CXLFLASH_COMMON_H
  17
  18 #include <linux/async.h>
  19 #include <linux/irq_poll.h>
  20 #include <linux/list.h>
  21 #include <linux/rwsem.h>
  22 #include <linux/types.h>
  23 #include <scsi/scsi.h>
  24 #include <scsi/scsi_cmnd.h>
  25 #include <scsi/scsi_device.h>
  26
  27 extern const struct file_operations cxlflash_cxl_fops;
  28
  29 #define MAX_CONTEXT     CXLFLASH_MAX_CONTEXT    /* num contexts per afu */
  30 #define MAX_FC_PORTS    CXLFLASH_MAX_FC_PORTS   /* max ports per AFU */
  31 #define LEGACY_FC_PORTS 2                       /* legacy ports per AFU */
  32
  33 #define CHAN2PORTBANK(_x)       ((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
  34 #define CHAN2BANKPORT(_x)       ((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))
  35
  36 #define CHAN2PORTMASK(_x)       (1 << (_x))     /* channel to port mask */
  37 #define PORTMASK2CHAN(_x)       (ilog2((_x)))   /* port mask to channel */
  38 #define PORTNUM2CHAN(_x)        ((_x) - 1)      /* port number to channel */
  39
  40 #define CXLFLASH_BLOCK_SIZE     4096            /* 4K blocks */
  41 #define CXLFLASH_MAX_XFER_SIZE  16777216        /* 16MB transfer */
  42 #define CXLFLASH_MAX_SECTORS    (CXLFLASH_MAX_XFER_SIZE/512)    /* SCSI wants
  43                                                                  * max_sectors
  44                                                                  * in units of
  45                                                                  * 512 byte
  46                                                                  * sectors
  47                                                                  */
  48
  49 #define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))
  50
  51 /* AFU command retry limit */
  52 #define MC_RETRY_CNT    5       /* Sufficient for SCSI and certain AFU errors */
  53
  54 /* Command management definitions */
  55 #define CXLFLASH_MAX_CMDS               256
  56 #define CXLFLASH_MAX_CMDS_PER_LUN       CXLFLASH_MAX_CMDS
  57
  58 /* RRQ for master issued cmds */
  59 #define NUM_RRQ_ENTRY                   CXLFLASH_MAX_CMDS
  60
  61 /* SQ for master issued cmds */
  62 #define NUM_SQ_ENTRY                    CXLFLASH_MAX_CMDS
  63
  64 /* Hardware queue definitions */
  65 #define CXLFLASH_DEF_HWQS               1
  66 #define CXLFLASH_MAX_HWQS               8
  67 #define PRIMARY_HWQ                     0
  68
  69
  70 static inline void check_sizes(void)
  71 {
  72         BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK);
  73         BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS);
  74 }
  75
  76 /* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
  77 #define CMD_BUFSIZE     SIZE_4K
  78
  79 enum cxlflash_lr_state {
  80         LINK_RESET_INVALID,
  81         LINK_RESET_REQUIRED,
  82         LINK_RESET_COMPLETE
  83 };
  84
  85 enum cxlflash_init_state {
  86         INIT_STATE_NONE,
  87         INIT_STATE_PCI,
  88         INIT_STATE_AFU,
  89         INIT_STATE_SCSI
  90 };
  91
  92 enum cxlflash_state {
  93         STATE_PROBING,  /* Initial state during probe */
  94         STATE_PROBED,   /* Temporary state, probe completed but EEH occurred */
  95         STATE_NORMAL,   /* Normal running state, everything good */
  96         STATE_RESET,    /* Reset state, trying to reset/recover */
  97         STATE_FAILTERM  /* Failed/terminating state, error out users/threads */
  98 };
  99
 100 enum cxlflash_hwq_mode {
 101         HWQ_MODE_RR,    /* Roundrobin (default) */
 102         HWQ_MODE_TAG,   /* Distribute based on block MQ tag */
 103         HWQ_MODE_CPU,   /* CPU affinity */
 104         MAX_HWQ_MODE
 105 };
 106
 107 /*
 108  * Each context has its own set of resource handles that is visible
 109  * only from that context.
 110  */
 111
 112 struct cxlflash_cfg {
 113         struct afu *afu;
 114
 115         struct pci_dev *dev;
 116         struct pci_device_id *dev_id;
 117         struct Scsi_Host *host;
 118         int num_fc_ports;
 119
 120         ulong cxlflash_regs_pci;
 121
 122         struct work_struct work_q;
 123         enum cxlflash_init_state init_state;
 124         enum cxlflash_lr_state lr_state;
 125         int lr_port;
 126         atomic_t scan_host_needed;
 127
 128         struct cxl_afu *cxl_afu;
 129
 130         atomic_t recovery_threads;
 131         struct mutex ctx_recovery_mutex;
 132         struct mutex ctx_tbl_list_mutex;
 133         struct rw_semaphore ioctl_rwsem;
 134         struct ctx_info *ctx_tbl[MAX_CONTEXT];
 135         struct list_head ctx_err_recovery; /* contexts w/ recovery pending */
 136         struct file_operations cxl_fops;
 137
 138         /* Parameters that are LUN table related */
 139         int last_lun_index[MAX_FC_PORTS];
 140         int promote_lun_index;
 141         struct list_head lluns; /* list of llun_info structs */
 142
 143         wait_queue_head_t tmf_waitq;
 144         spinlock_t tmf_slock;
 145         bool tmf_active;
 146         wait_queue_head_t reset_waitq;
 147         enum cxlflash_state state;
 148         async_cookie_t async_reset_cookie;
 149 };
 150
 151 struct afu_cmd {
 152         struct sisl_ioarcb rcb; /* IOARCB (cache line aligned) */
 153         struct sisl_ioasa sa;   /* IOASA must follow IOARCB */
 154         struct afu *parent;
 155         struct scsi_cmnd *scp;
 156         struct completion cevent;
 157         struct list_head queue;
 158         u32 hwq_index;
 159
 160         u8 cmd_tmf:1;
 161
 162         /* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
 163          * However for performance reasons the IOARCB/IOASA should be
 164          * cache line aligned.
 165          */
 166 } __aligned(cache_line_size());
 167
 168 static inline struct afu_cmd *sc_to_afuc(struct scsi_cmnd *sc)
 169 {
 170         return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd));
 171 }
 172
 173 static inline struct afu_cmd *sc_to_afucz(struct scsi_cmnd *sc)
 174 {
 175         struct afu_cmd *afuc = sc_to_afuc(sc);
 176
 177         memset(afuc, 0, sizeof(*afuc));
 178         return afuc;
 179 }
 180
 181 struct hwq {
 182         /* Stuff requiring alignment go first. */
 183         struct sisl_ioarcb sq[NUM_SQ_ENTRY];            /* 16K SQ */
 184         u64 rrq_entry[NUM_RRQ_ENTRY];                   /* 2K RRQ */
 185
 186         /* Beware of alignment till here. Preferably introduce new
 187          * fields after this point
 188          */
 189         struct afu *afu;
 190         struct cxl_context *ctx;
 191         struct cxl_ioctl_start_work work;
 192         struct sisl_host_map __iomem *host_map;         /* MC host map */
 193         struct sisl_ctrl_map __iomem *ctrl_map;         /* MC control map */
 194         ctx_hndl_t ctx_hndl;    /* master's context handle */
 195         u32 index;              /* Index of this hwq */
 196
 197         atomic_t hsq_credits;
 198         spinlock_t hsq_slock;   /* Hardware send queue lock */
 199         struct sisl_ioarcb *hsq_start;
 200         struct sisl_ioarcb *hsq_end;
 201         struct sisl_ioarcb *hsq_curr;
 202         spinlock_t hrrq_slock;
 203         u64 *hrrq_start;
 204         u64 *hrrq_end;
 205         u64 *hrrq_curr;
 206         bool toggle;
 207
 208         s64 room;
 209
 210         struct irq_poll irqpoll;
 211 } __aligned(cache_line_size());
 212
 213 struct afu {
 214         struct hwq hwqs[CXLFLASH_MAX_HWQS];
 215         int (*send_cmd)(struct afu *, struct afu_cmd *);
 216         int (*context_reset)(struct hwq *);
 217
 218         /* AFU HW */
 219         struct cxlflash_afu_map __iomem *afu_map;       /* entire MMIO map */
 220
 221         atomic_t cmds_active;   /* Number of currently active AFU commands */
 222         u64 hb;
 223         u32 internal_lun;       /* User-desired LUN mode for this AFU */
 224
 225         u32 num_hwqs;           /* Number of hardware queues */
 226         u32 desired_hwqs;       /* Desired h/w queues, effective on AFU reset */
 227         enum cxlflash_hwq_mode hwq_mode; /* Steering mode for h/w queues */
 228         u32 hwq_rr_count;       /* Count to distribute traffic for roundrobin */
 229
 230         char version[16];
 231         u64 interface_version;
 232
 233         u32 irqpoll_weight;
 234         struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */
 235 };
 236
 237 static inline struct hwq *get_hwq(struct afu *afu, u32 index)
 238 {
 239         WARN_ON(index >= CXLFLASH_MAX_HWQS);
 240
 241         return &afu->hwqs[index];
 242 }
 243
 244 static inline bool afu_is_irqpoll_enabled(struct afu *afu)
 245 {
 246         return !!afu->irqpoll_weight;
 247 }
 248
 249 static inline bool afu_is_cmd_mode(struct afu *afu, u64 cmd_mode)
 250 {
 251         u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT;
 252
 253         return afu_cap & cmd_mode;
 254 }
 255
 256 static inline bool afu_is_sq_cmd_mode(struct afu *afu)
 257 {
 258         return afu_is_cmd_mode(afu, SISL_INTVER_CAP_SQ_CMD_MODE);
 259 }
 260
 261 static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu)
 262 {
 263         return afu_is_cmd_mode(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE);
 264 }
 265
 266 static inline u64 lun_to_lunid(u64 lun)
 267 {
 268         __be64 lun_id;
 269
 270         int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
 271         return be64_to_cpu(lun_id);
 272 }
 273
 274 static inline struct fc_port_bank __iomem *get_fc_port_bank(
 275                                             struct cxlflash_cfg *cfg, int i)
 276 {
 277         struct afu *afu = cfg->afu;
 278
 279         return &afu->afu_map->global.bank[CHAN2PORTBANK(i)];
 280 }
 281
 282 static inline __be64 __iomem *get_fc_port_regs(struct cxlflash_cfg *cfg, int i)
 283 {
 284         struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
 285
 286         return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0];
 287 }
 288
 289 static inline __be64 __iomem *get_fc_port_luns(struct cxlflash_cfg *cfg, int i)
 290 {
 291         struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
 292
 293         return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0];
 294 }
 295
 296 int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode);
 297 void cxlflash_list_init(void);
 298 void cxlflash_term_global_luns(void);
 299 void cxlflash_free_errpage(void);
 300 int cxlflash_ioctl(struct scsi_device *sdev, int cmd, void __user *arg);
 301 void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg);
 302 int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg);
 303 void cxlflash_term_local_luns(struct cxlflash_cfg *cfg);
 304 void cxlflash_restore_luntable(struct cxlflash_cfg *cfg);
 305
 306 #endif /* ifndef _CXLFLASH_COMMON_H */