2 * phy-ti-pipe3 - PIPE3 PHY driver.
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * Author: Kishon Vijay Abraham I <kishon@ti.com>
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <linux/phy/phy.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/delay.h>
29 #include <linux/phy/omap_control_phy.h>
30 #include <linux/of_platform.h>
31 #include <linux/spinlock.h>
33 #define PLL_STATUS 0x00000004
34 #define PLL_GO 0x00000008
35 #define PLL_CONFIGURATION1 0x0000000C
36 #define PLL_CONFIGURATION2 0x00000010
37 #define PLL_CONFIGURATION3 0x00000014
38 #define PLL_CONFIGURATION4 0x00000020
40 #define PLL_REGM_MASK 0x001FFE00
41 #define PLL_REGM_SHIFT 0x9
42 #define PLL_REGM_F_MASK 0x0003FFFF
43 #define PLL_REGM_F_SHIFT 0x0
44 #define PLL_REGN_MASK 0x000001FE
45 #define PLL_REGN_SHIFT 0x1
46 #define PLL_SELFREQDCO_MASK 0x0000000E
47 #define PLL_SELFREQDCO_SHIFT 0x1
48 #define PLL_SD_MASK 0x0003FC00
49 #define PLL_SD_SHIFT 10
50 #define SET_PLL_GO 0x1
51 #define PLL_LDOPWDN BIT(15)
52 #define PLL_TICOPWDN BIT(16)
57 * This is an Empirical value that works, need to confirm the actual
58 * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
59 * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
61 #define PLL_IDLE_TIME 100 /* in milliseconds */
62 #define PLL_LOCK_TIME 100 /* in milliseconds */
64 struct pipe3_dpll_params
{
72 struct pipe3_dpll_map
{
74 struct pipe3_dpll_params params
;
78 void __iomem
*pll_ctrl_base
;
80 struct device
*control_dev
;
85 struct pipe3_dpll_map
*dpll_map
;
87 spinlock_t lock
; /* serialize clock enable/disable */
88 /* the below flag is needed specifically for SATA */
92 static struct pipe3_dpll_map dpll_map_usb
[] = {
93 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
94 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
95 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
96 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
97 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
98 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
102 static struct pipe3_dpll_map dpll_map_sata
[] = {
103 {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
104 {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
105 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
106 {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
107 {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
108 {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
109 { }, /* Terminator */
112 static inline u32
ti_pipe3_readl(void __iomem
*addr
, unsigned offset
)
114 return __raw_readl(addr
+ offset
);
117 static inline void ti_pipe3_writel(void __iomem
*addr
, unsigned offset
,
120 __raw_writel(data
, addr
+ offset
);
123 static struct pipe3_dpll_params
*ti_pipe3_get_dpll_params(struct ti_pipe3
*phy
)
126 struct pipe3_dpll_map
*dpll_map
= phy
->dpll_map
;
128 rate
= clk_get_rate(phy
->sys_clk
);
130 for (; dpll_map
->rate
; dpll_map
++) {
131 if (rate
== dpll_map
->rate
)
132 return &dpll_map
->params
;
135 dev_err(phy
->dev
, "No DPLL configuration for %lu Hz SYS CLK\n", rate
);
140 static int ti_pipe3_power_off(struct phy
*x
)
142 struct ti_pipe3
*phy
= phy_get_drvdata(x
);
144 omap_control_phy_power(phy
->control_dev
, 0);
149 static int ti_pipe3_power_on(struct phy
*x
)
151 struct ti_pipe3
*phy
= phy_get_drvdata(x
);
153 omap_control_phy_power(phy
->control_dev
, 1);
158 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3
*phy
)
161 unsigned long timeout
;
163 timeout
= jiffies
+ msecs_to_jiffies(PLL_LOCK_TIME
);
166 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_STATUS
);
169 } while (!time_after(jiffies
, timeout
));
171 dev_err(phy
->dev
, "DPLL failed to lock\n");
175 static int ti_pipe3_dpll_program(struct ti_pipe3
*phy
)
178 struct pipe3_dpll_params
*dpll_params
;
180 dpll_params
= ti_pipe3_get_dpll_params(phy
);
184 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION1
);
185 val
&= ~PLL_REGN_MASK
;
186 val
|= dpll_params
->n
<< PLL_REGN_SHIFT
;
187 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION1
, val
);
189 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
);
190 val
&= ~PLL_SELFREQDCO_MASK
;
191 val
|= dpll_params
->freq
<< PLL_SELFREQDCO_SHIFT
;
192 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
, val
);
194 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION1
);
195 val
&= ~PLL_REGM_MASK
;
196 val
|= dpll_params
->m
<< PLL_REGM_SHIFT
;
197 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION1
, val
);
199 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION4
);
200 val
&= ~PLL_REGM_F_MASK
;
201 val
|= dpll_params
->mf
<< PLL_REGM_F_SHIFT
;
202 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION4
, val
);
204 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION3
);
206 val
|= dpll_params
->sd
<< PLL_SD_SHIFT
;
207 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION3
, val
);
209 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_GO
, SET_PLL_GO
);
211 return ti_pipe3_dpll_wait_lock(phy
);
214 static int ti_pipe3_init(struct phy
*x
)
216 struct ti_pipe3
*phy
= phy_get_drvdata(x
);
221 * Set pcie_pcs register to 0x96 for proper functioning of phy
222 * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
225 if (of_device_is_compatible(phy
->dev
->of_node
, "ti,phy-pipe3-pcie")) {
226 omap_control_pcie_pcs(phy
->control_dev
, 0x96);
230 /* Bring it out of IDLE if it is IDLE */
231 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
);
232 if (val
& PLL_IDLE
) {
234 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
, val
);
235 ret
= ti_pipe3_dpll_wait_lock(phy
);
238 /* Program the DPLL only if not locked */
239 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_STATUS
);
240 if (!(val
& PLL_LOCK
))
241 if (ti_pipe3_dpll_program(phy
))
247 static int ti_pipe3_exit(struct phy
*x
)
249 struct ti_pipe3
*phy
= phy_get_drvdata(x
);
251 unsigned long timeout
;
253 /* SATA DPLL can't be powered down due to Errata i783 and PCIe
254 * does not have internal DPLL
256 if (of_device_is_compatible(phy
->dev
->of_node
, "ti,phy-pipe3-sata") ||
257 of_device_is_compatible(phy
->dev
->of_node
, "ti,phy-pipe3-pcie"))
260 /* Put DPLL in IDLE mode */
261 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
);
263 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
, val
);
265 /* wait for LDO and Oscillator to power down */
266 timeout
= jiffies
+ msecs_to_jiffies(PLL_IDLE_TIME
);
269 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_STATUS
);
270 if ((val
& PLL_TICOPWDN
) && (val
& PLL_LDOPWDN
))
272 } while (!time_after(jiffies
, timeout
));
274 if (!(val
& PLL_TICOPWDN
) || !(val
& PLL_LDOPWDN
)) {
275 dev_err(phy
->dev
, "Failed to power down: PLL_STATUS 0x%x\n",
282 static struct phy_ops ops
= {
283 .init
= ti_pipe3_init
,
284 .exit
= ti_pipe3_exit
,
285 .power_on
= ti_pipe3_power_on
,
286 .power_off
= ti_pipe3_power_off
,
287 .owner
= THIS_MODULE
,
291 static const struct of_device_id ti_pipe3_id_table
[];
294 static int ti_pipe3_probe(struct platform_device
*pdev
)
296 struct ti_pipe3
*phy
;
297 struct phy
*generic_phy
;
298 struct phy_provider
*phy_provider
;
299 struct resource
*res
;
300 struct device_node
*node
= pdev
->dev
.of_node
;
301 struct device_node
*control_node
;
302 struct platform_device
*control_pdev
;
303 const struct of_device_id
*match
;
306 phy
= devm_kzalloc(&pdev
->dev
, sizeof(*phy
), GFP_KERNEL
);
310 phy
->dev
= &pdev
->dev
;
311 spin_lock_init(&phy
->lock
);
313 if (!of_device_is_compatible(node
, "ti,phy-pipe3-pcie")) {
314 match
= of_match_device(of_match_ptr(ti_pipe3_id_table
),
319 phy
->dpll_map
= (struct pipe3_dpll_map
*)match
->data
;
320 if (!phy
->dpll_map
) {
321 dev_err(&pdev
->dev
, "no DPLL data\n");
325 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
327 phy
->pll_ctrl_base
= devm_ioremap_resource(&pdev
->dev
, res
);
328 if (IS_ERR(phy
->pll_ctrl_base
))
329 return PTR_ERR(phy
->pll_ctrl_base
);
331 phy
->sys_clk
= devm_clk_get(phy
->dev
, "sysclk");
332 if (IS_ERR(phy
->sys_clk
)) {
333 dev_err(&pdev
->dev
, "unable to get sysclk\n");
338 phy
->refclk
= devm_clk_get(phy
->dev
, "refclk");
339 if (IS_ERR(phy
->refclk
)) {
340 dev_err(&pdev
->dev
, "unable to get refclk\n");
341 /* older DTBs have missing refclk in SATA PHY
342 * so don't bail out in case of SATA PHY.
344 if (!of_device_is_compatible(node
, "ti,phy-pipe3-sata"))
345 return PTR_ERR(phy
->refclk
);
348 if (!of_device_is_compatible(node
, "ti,phy-pipe3-sata")) {
349 phy
->wkupclk
= devm_clk_get(phy
->dev
, "wkupclk");
350 if (IS_ERR(phy
->wkupclk
)) {
351 dev_err(&pdev
->dev
, "unable to get wkupclk\n");
352 return PTR_ERR(phy
->wkupclk
);
355 phy
->wkupclk
= ERR_PTR(-ENODEV
);
358 if (of_device_is_compatible(node
, "ti,phy-pipe3-pcie")) {
360 clk
= devm_clk_get(phy
->dev
, "dpll_ref");
362 dev_err(&pdev
->dev
, "unable to get dpll ref clk\n");
365 clk_set_rate(clk
, 1500000000);
367 clk
= devm_clk_get(phy
->dev
, "dpll_ref_m2");
369 dev_err(&pdev
->dev
, "unable to get dpll ref m2 clk\n");
372 clk_set_rate(clk
, 100000000);
374 clk
= devm_clk_get(phy
->dev
, "phy-div");
376 dev_err(&pdev
->dev
, "unable to get phy-div clk\n");
379 clk_set_rate(clk
, 100000000);
381 phy
->div_clk
= devm_clk_get(phy
->dev
, "div-clk");
382 if (IS_ERR(phy
->div_clk
)) {
383 dev_err(&pdev
->dev
, "unable to get div-clk\n");
384 return PTR_ERR(phy
->div_clk
);
387 phy
->div_clk
= ERR_PTR(-ENODEV
);
390 control_node
= of_parse_phandle(node
, "ctrl-module", 0);
392 dev_err(&pdev
->dev
, "Failed to get control device phandle\n");
396 control_pdev
= of_find_device_by_node(control_node
);
398 dev_err(&pdev
->dev
, "Failed to get control device\n");
402 phy
->control_dev
= &control_pdev
->dev
;
404 omap_control_phy_power(phy
->control_dev
, 0);
406 platform_set_drvdata(pdev
, phy
);
407 pm_runtime_enable(phy
->dev
);
409 generic_phy
= devm_phy_create(phy
->dev
, NULL
, &ops
);
410 if (IS_ERR(generic_phy
))
411 return PTR_ERR(generic_phy
);
413 phy_set_drvdata(generic_phy
, phy
);
414 phy_provider
= devm_of_phy_provider_register(phy
->dev
,
415 of_phy_simple_xlate
);
416 if (IS_ERR(phy_provider
))
417 return PTR_ERR(phy_provider
);
419 pm_runtime_get(&pdev
->dev
);
424 static int ti_pipe3_remove(struct platform_device
*pdev
)
426 if (!pm_runtime_suspended(&pdev
->dev
))
427 pm_runtime_put(&pdev
->dev
);
428 pm_runtime_disable(&pdev
->dev
);
434 static int ti_pipe3_enable_refclk(struct ti_pipe3
*phy
)
436 if (!IS_ERR(phy
->refclk
) && !phy
->refclk_enabled
) {
439 ret
= clk_prepare_enable(phy
->refclk
);
441 dev_err(phy
->dev
, "Failed to enable refclk %d\n", ret
);
444 phy
->refclk_enabled
= true;
450 static void ti_pipe3_disable_refclk(struct ti_pipe3
*phy
)
452 if (!IS_ERR(phy
->refclk
))
453 clk_disable_unprepare(phy
->refclk
);
455 phy
->refclk_enabled
= false;
458 static int ti_pipe3_enable_clocks(struct ti_pipe3
*phy
)
463 spin_lock_irqsave(&phy
->lock
, flags
);
467 ret
= ti_pipe3_enable_refclk(phy
);
471 if (!IS_ERR(phy
->wkupclk
)) {
472 ret
= clk_prepare_enable(phy
->wkupclk
);
474 dev_err(phy
->dev
, "Failed to enable wkupclk %d\n", ret
);
479 if (!IS_ERR(phy
->div_clk
)) {
480 ret
= clk_prepare_enable(phy
->div_clk
);
482 dev_err(phy
->dev
, "Failed to enable div_clk %d\n", ret
);
488 spin_unlock_irqrestore(&phy
->lock
, flags
);
492 if (!IS_ERR(phy
->wkupclk
))
493 clk_disable_unprepare(phy
->wkupclk
);
496 if (!IS_ERR(phy
->refclk
))
497 clk_disable_unprepare(phy
->refclk
);
499 ti_pipe3_disable_refclk(phy
);
501 spin_unlock_irqrestore(&phy
->lock
, flags
);
505 static void ti_pipe3_disable_clocks(struct ti_pipe3
*phy
)
509 spin_lock_irqsave(&phy
->lock
, flags
);
511 spin_unlock_irqrestore(&phy
->lock
, flags
);
515 if (!IS_ERR(phy
->wkupclk
))
516 clk_disable_unprepare(phy
->wkupclk
);
517 /* Don't disable refclk for SATA PHY due to Errata i783 */
518 if (!of_device_is_compatible(phy
->dev
->of_node
, "ti,phy-pipe3-sata"))
519 ti_pipe3_disable_refclk(phy
);
520 if (!IS_ERR(phy
->div_clk
))
521 clk_disable_unprepare(phy
->div_clk
);
522 phy
->enabled
= false;
523 spin_unlock_irqrestore(&phy
->lock
, flags
);
526 static int ti_pipe3_runtime_suspend(struct device
*dev
)
528 struct ti_pipe3
*phy
= dev_get_drvdata(dev
);
530 ti_pipe3_disable_clocks(phy
);
534 static int ti_pipe3_runtime_resume(struct device
*dev
)
536 struct ti_pipe3
*phy
= dev_get_drvdata(dev
);
539 ret
= ti_pipe3_enable_clocks(phy
);
543 static int ti_pipe3_suspend(struct device
*dev
)
545 struct ti_pipe3
*phy
= dev_get_drvdata(dev
);
547 ti_pipe3_disable_clocks(phy
);
551 static int ti_pipe3_resume(struct device
*dev
)
553 struct ti_pipe3
*phy
= dev_get_drvdata(dev
);
556 ret
= ti_pipe3_enable_clocks(phy
);
560 pm_runtime_disable(dev
);
561 pm_runtime_set_active(dev
);
562 pm_runtime_enable(dev
);
567 static const struct dev_pm_ops ti_pipe3_pm_ops
= {
568 SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend
,
569 ti_pipe3_runtime_resume
, NULL
)
570 SET_SYSTEM_SLEEP_PM_OPS(ti_pipe3_suspend
, ti_pipe3_resume
)
574 static const struct of_device_id ti_pipe3_id_table
[] = {
576 .compatible
= "ti,phy-usb3",
577 .data
= dpll_map_usb
,
580 .compatible
= "ti,omap-usb3",
581 .data
= dpll_map_usb
,
584 .compatible
= "ti,phy-pipe3-sata",
585 .data
= dpll_map_sata
,
588 .compatible
= "ti,phy-pipe3-pcie",
592 MODULE_DEVICE_TABLE(of
, ti_pipe3_id_table
);
595 static struct platform_driver ti_pipe3_driver
= {
596 .probe
= ti_pipe3_probe
,
597 .remove
= ti_pipe3_remove
,
600 .pm
= &ti_pipe3_pm_ops
,
601 .of_match_table
= of_match_ptr(ti_pipe3_id_table
),
605 module_platform_driver(ti_pipe3_driver
);
607 MODULE_ALIAS("platform:ti_pipe3");
608 MODULE_AUTHOR("Texas Instruments Inc.");
609 MODULE_DESCRIPTION("TI PIPE3 phy driver");
610 MODULE_LICENSE("GPL v2");