arch/arm/mach-exynos/pm.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power Management support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/io.h>
  20 #include <linux/irqchip/arm-gic.h>
  21 #include <linux/err.h>
  22 #include <linux/clk.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/hardware/cache-l2x0.h>
  26 #include <asm/smp_scu.h>
  27 #include <asm/suspend.h>
  28
  29 #include <plat/cpu.h>
  30 #include <plat/pm-common.h>
  31 #include <plat/pll.h>
  32 #include <plat/regs-srom.h>
  33
  34 #include <mach/map.h>
  35
  36 #include "common.h"
  37 #include "regs-pmu.h"
  38
  39 /**
  40  * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
  41  * @hwirq: Hardware IRQ signal of the GIC
  42  * @mask: Mask in PMU wake-up mask register
  43  */
  44 struct exynos_wkup_irq {
  45         unsigned int hwirq;
  46         u32 mask;
  47 };
  48
  49 static struct sleep_save exynos5_sys_save[] = {
  50         SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
  51 };
  52
  53 static struct sleep_save exynos_core_save[] = {
  54         /* SROM side */
  55         SAVE_ITEM(S5P_SROM_BW),
  56         SAVE_ITEM(S5P_SROM_BC0),
  57         SAVE_ITEM(S5P_SROM_BC1),
  58         SAVE_ITEM(S5P_SROM_BC2),
  59         SAVE_ITEM(S5P_SROM_BC3),
  60 };
  61
  62 /*
  63  * GIC wake-up support
  64  */
  65
  66 static u32 exynos_irqwake_intmask = 0xffffffff;
  67
  68 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
  69         { 76, BIT(1) }, /* RTC alarm */
  70         { 77, BIT(2) }, /* RTC tick */
  71         { /* sentinel */ },
  72 };
  73
  74 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
  75         { 75, BIT(1) }, /* RTC alarm */
  76         { 76, BIT(2) }, /* RTC tick */
  77         { /* sentinel */ },
  78 };
  79
  80 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
  81 {
  82         const struct exynos_wkup_irq *wkup_irq;
  83
  84         if (soc_is_exynos5250())
  85                 wkup_irq = exynos5250_wkup_irq;
  86         else
  87                 wkup_irq = exynos4_wkup_irq;
  88
  89         while (wkup_irq->mask) {
  90                 if (wkup_irq->hwirq == data->hwirq) {
  91                         if (!state)
  92                                 exynos_irqwake_intmask |= wkup_irq->mask;
  93                         else
  94                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
  95                         return 0;
  96                 }
  97                 ++wkup_irq;
  98         }
  99
 100         return -ENOENT;
 101 }
 102
 103 /**
 104  * exynos_core_power_down : power down the specified cpu
 105  * @cpu : the cpu to power down
 106  *
 107  * Power down the specified cpu. The sequence must be finished by a
 108  * call to cpu_do_idle()
 109  *
 110  */
 111 void exynos_cpu_power_down(int cpu)
 112 {
 113         __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 114 }
 115
 116 /**
 117  * exynos_cpu_power_up : power up the specified cpu
 118  * @cpu : the cpu to power up
 119  *
 120  * Power up the specified cpu
 121  */
 122 void exynos_cpu_power_up(int cpu)
 123 {
 124         __raw_writel(S5P_CORE_LOCAL_PWR_EN,
 125                      EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 126 }
 127
 128 /**
 129  * exynos_cpu_power_state : returns the power state of the cpu
 130  * @cpu : the cpu to retrieve the power state from
 131  *
 132  */
 133 int exynos_cpu_power_state(int cpu)
 134 {
 135         return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
 136                         S5P_CORE_LOCAL_PWR_EN);
 137 }
 138
 139 /**
 140  * exynos_cluster_power_down : power down the specified cluster
 141  * @cluster : the cluster to power down
 142  */
 143 void exynos_cluster_power_down(int cluster)
 144 {
 145         __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
 146 }
 147
 148 /**
 149  * exynos_cluster_power_up : power up the specified cluster
 150  * @cluster : the cluster to power up
 151  */
 152 void exynos_cluster_power_up(int cluster)
 153 {
 154         __raw_writel(S5P_CORE_LOCAL_PWR_EN,
 155                      EXYNOS_COMMON_CONFIGURATION(cluster));
 156 }
 157
 158 /**
 159  * exynos_cluster_power_state : returns the power state of the cluster
 160  * @cluster : the cluster to retrieve the power state from
 161  *
 162  */
 163 int exynos_cluster_power_state(int cluster)
 164 {
 165         return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
 166                         S5P_CORE_LOCAL_PWR_EN);
 167 }
 168
 169 /* For Cortex-A9 Diagnostic and Power control register */
 170 static unsigned int save_arm_register[2];
 171
 172 static int exynos_cpu_suspend(unsigned long arg)
 173 {
 174 #ifdef CONFIG_CACHE_L2X0
 175         outer_flush_all();
 176 #endif
 177
 178         if (soc_is_exynos5250())
 179                 flush_cache_all();
 180
 181         /* issue the standby signal into the pm unit. */
 182         cpu_do_idle();
 183
 184         pr_info("Failed to suspend the system\n");
 185         return 1; /* Aborting suspend */
 186 }
 187
 188 static void exynos_pm_prepare(void)
 189 {
 190         unsigned int tmp;
 191
 192         /* Set wake-up mask registers */
 193         __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
 194         __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 195
 196         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 197
 198         if (soc_is_exynos5250()) {
 199                 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
 200                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
 201                 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
 202                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 203                 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
 204         }
 205
 206         /* Set value of power down register for sleep mode */
 207
 208         exynos_sys_powerdown_conf(SYS_SLEEP);
 209         __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 210
 211         /* ensure at least INFORM0 has the resume address */
 212
 213         __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 214 }
 215
 216 static int exynos_pm_suspend(void)
 217 {
 218         unsigned long tmp;
 219
 220         /* Setting Central Sequence Register for power down mode */
 221
 222         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 223         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 224         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 225
 226         /* Setting SEQ_OPTION register */
 227
 228         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 229         __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 230
 231         if (!soc_is_exynos5250()) {
 232                 /* Save Power control register */
 233                 asm ("mrc p15, 0, %0, c15, c0, 0"
 234                      : "=r" (tmp) : : "cc");
 235                 save_arm_register[0] = tmp;
 236
 237                 /* Save Diagnostic register */
 238                 asm ("mrc p15, 0, %0, c15, c0, 1"
 239                      : "=r" (tmp) : : "cc");
 240                 save_arm_register[1] = tmp;
 241         }
 242
 243         return 0;
 244 }
 245
 246 static void exynos_pm_resume(void)
 247 {
 248         unsigned long tmp;
 249
 250         /*
 251          * If PMU failed while entering sleep mode, WFI will be
 252          * ignored by PMU and then exiting cpu_do_idle().
 253          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 254          * in this situation.
 255          */
 256         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 257         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 258                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 259                 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 260                 /* clear the wakeup state register */
 261                 __raw_writel(0x0, S5P_WAKEUP_STAT);
 262                 /* No need to perform below restore code */
 263                 goto early_wakeup;
 264         }
 265         if (!soc_is_exynos5250()) {
 266                 /* Restore Power control register */
 267                 tmp = save_arm_register[0];
 268                 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
 269                               : : "r" (tmp)
 270                               : "cc");
 271
 272                 /* Restore Diagnostic register */
 273                 tmp = save_arm_register[1];
 274                 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
 275                               : : "r" (tmp)
 276                               : "cc");
 277         }
 278
 279         /* For release retention */
 280
 281         __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
 282         __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
 283         __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
 284         __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
 285         __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
 286         __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
 287         __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 288
 289         if (soc_is_exynos5250())
 290                 s3c_pm_do_restore(exynos5_sys_save,
 291                         ARRAY_SIZE(exynos5_sys_save));
 292
 293         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 294
 295         if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250())
 296                 scu_enable(S5P_VA_SCU);
 297
 298 early_wakeup:
 299
 300         /* Clear SLEEP mode set in INFORM1 */
 301         __raw_writel(0x0, S5P_INFORM1);
 302
 303         return;
 304 }
 305
 306 static struct syscore_ops exynos_pm_syscore_ops = {
 307         .suspend        = exynos_pm_suspend,
 308         .resume         = exynos_pm_resume,
 309 };
 310
 311 /*
 312  * Suspend Ops
 313  */
 314
 315 static int exynos_suspend_enter(suspend_state_t state)
 316 {
 317         int ret;
 318
 319         s3c_pm_debug_init();
 320
 321         S3C_PMDBG("%s: suspending the system...\n", __func__);
 322
 323         S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
 324                         exynos_irqwake_intmask, exynos_get_eint_wake_mask());
 325
 326         if (exynos_irqwake_intmask == -1U
 327             && exynos_get_eint_wake_mask() == -1U) {
 328                 pr_err("%s: No wake-up sources!\n", __func__);
 329                 pr_err("%s: Aborting sleep\n", __func__);
 330                 return -EINVAL;
 331         }
 332
 333         s3c_pm_save_uarts();
 334         exynos_pm_prepare();
 335         flush_cache_all();
 336         s3c_pm_check_store();
 337
 338         ret = cpu_suspend(0, exynos_cpu_suspend);
 339         if (ret)
 340                 return ret;
 341
 342         s3c_pm_restore_uarts();
 343
 344         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
 345                         __raw_readl(S5P_WAKEUP_STAT));
 346
 347         s3c_pm_check_restore();
 348
 349         S3C_PMDBG("%s: resuming the system...\n", __func__);
 350
 351         return 0;
 352 }
 353
 354 static int exynos_suspend_prepare(void)
 355 {
 356         s3c_pm_check_prepare();
 357
 358         return 0;
 359 }
 360
 361 static void exynos_suspend_finish(void)
 362 {
 363         s3c_pm_check_cleanup();
 364 }
 365
 366 static const struct platform_suspend_ops exynos_suspend_ops = {
 367         .enter          = exynos_suspend_enter,
 368         .prepare        = exynos_suspend_prepare,
 369         .finish         = exynos_suspend_finish,
 370         .valid          = suspend_valid_only_mem,
 371 };
 372
 373 void __init exynos_pm_init(void)
 374 {
 375         u32 tmp;
 376
 377         /* Platform-specific GIC callback */
 378         gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 379
 380         /* All wakeup disable */
 381         tmp = __raw_readl(S5P_WAKEUP_MASK);
 382         tmp |= ((0xFF << 8) | (0x1F << 1));
 383         __raw_writel(tmp, S5P_WAKEUP_MASK);
 384
 385         register_syscore_ops(&exynos_pm_syscore_ops);
 386         suspend_set_ops(&exynos_suspend_ops);
 387 }