4 * Copyright 1993, Drew Eckhardt
6 * (Unix consulting and custom programming)
10 * DISTRIBUTION RELEASE 7
12 * For more information, please consult
15 * SCSI Protocol Controller
17 * NCR Microelectronics
18 * 1635 Aeroplaza Drive
19 * Colorado Springs, CO 80916
27 #include <linux/interrupt.h>
30 #include <scsi/scsi_eh.h>
33 #define NCR5380_PUBLIC_RELEASE 7
34 #define NCR53C400_PUBLIC_RELEASE 2
36 #define NDEBUG_ARBITRATION 0x1
37 #define NDEBUG_AUTOSENSE 0x2
38 #define NDEBUG_DMA 0x4
39 #define NDEBUG_HANDSHAKE 0x8
40 #define NDEBUG_INFORMATION 0x10
41 #define NDEBUG_INIT 0x20
42 #define NDEBUG_INTR 0x40
43 #define NDEBUG_LINKED 0x80
44 #define NDEBUG_MAIN 0x100
45 #define NDEBUG_NO_DATAOUT 0x200
46 #define NDEBUG_NO_WRITE 0x400
47 #define NDEBUG_PIO 0x800
48 #define NDEBUG_PSEUDO_DMA 0x1000
49 #define NDEBUG_QUEUES 0x2000
50 #define NDEBUG_RESELECTION 0x4000
51 #define NDEBUG_SELECTION 0x8000
52 #define NDEBUG_USLEEP 0x10000
53 #define NDEBUG_LAST_BYTE_SENT 0x20000
54 #define NDEBUG_RESTART_SELECT 0x40000
55 #define NDEBUG_EXTENDED 0x80000
56 #define NDEBUG_C400_PREAD 0x100000
57 #define NDEBUG_C400_PWRITE 0x200000
58 #define NDEBUG_LISTS 0x400000
59 #define NDEBUG_ABORT 0x800000
60 #define NDEBUG_TAGS 0x1000000
61 #define NDEBUG_MERGING 0x2000000
63 #define NDEBUG_ANY 0xFFFFFFFFUL
66 * The contents of the OUTPUT DATA register are asserted on the bus when
67 * either arbitration is occurring or the phase-indicating signals (
68 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
69 * bit in the INITIATOR COMMAND register is set.
72 #define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
73 #define CURRENT_SCSI_DATA_REG 0 /* ro same */
75 #define INITIATOR_COMMAND_REG 1 /* rw */
76 #define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
77 #define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
78 #define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
79 #define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
80 #define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
81 #define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
82 #define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
83 #define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
84 #define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
85 #define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
88 #define ICR_BASE ICR_DIFF_ENABLE
95 * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
96 * transfer, causing the chip to hog the bus. You probably don't want
99 #define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
100 #define MR_TARGET 0x40 /* rw target mode */
101 #define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
102 #define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
103 #define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
104 #define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
105 #define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
106 #define MR_ARBITRATE 0x01 /* rw start arbitration */
109 #define MR_BASE MR_ENABLE_PAR_CHECK
114 #define TARGET_COMMAND_REG 3
115 #define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
116 #define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
117 #define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
118 #define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
119 #define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
121 #define STATUS_REG 4 /* ro */
123 * Note : a set bit indicates an active signal, driven by us or another
136 * Setting a bit in this register will cause an interrupt to be generated when
137 * BSY is false and SEL true and this bit is asserted on the bus.
139 #define SELECT_ENABLE_REG 4 /* wo */
141 #define BUS_AND_STATUS_REG 5 /* ro */
142 #define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
143 #define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
144 #define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
145 #define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
146 #define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
147 #define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
148 #define BASR_ATN 0x02 /* ro BUS status */
149 #define BASR_ACK 0x01 /* ro BUS status */
151 /* Write any value to this register to start a DMA send */
152 #define START_DMA_SEND_REG 5 /* wo */
155 * Used in DMA transfer mode, data is latched from the SCSI bus on
156 * the falling edge of REQ (ini) or ACK (tgt)
158 #define INPUT_DATA_REG 6 /* ro */
160 /* Write any value to this register to start a DMA receive */
161 #define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
163 /* Read this register to clear interrupt conditions */
164 #define RESET_PARITY_INTERRUPT_REG 7 /* ro */
166 /* Write any value to this register to start an ini mode DMA receive */
167 #define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
169 #define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */
171 #define CSR_RESET 0x80 /* wo Resets 53c400 */
172 #define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
173 #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
174 #define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
175 #define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
176 #define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
177 #define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
178 #define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
179 #define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
182 #define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
184 #define CSR_BASE CSR_53C80_INTR
187 /* Number of 128-byte blocks to be transferred */
188 #define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */
190 /* Resume transfer after disconnect */
191 #define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */
193 /* Access to host buffer stack */
194 #define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */
197 /* Note : PHASE_* macros are based on the values of the STATUS register */
198 #define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
200 #define PHASE_DATAOUT 0
201 #define PHASE_DATAIN SR_IO
202 #define PHASE_CMDOUT SR_CD
203 #define PHASE_STATIN (SR_CD | SR_IO)
204 #define PHASE_MSGOUT (SR_MSG | SR_CD)
205 #define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
206 #define PHASE_UNKNOWN 0xff
209 * Convert status register phase to something we can use to set phase in
210 * the target register so we can get phase mismatch interrupts on DMA
214 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
217 * The internal should_disconnect() function returns these based on the
218 * expected length of a disconnect if a device supports disconnect/
222 #define DISCONNECT_NONE 0
223 #define DISCONNECT_TIME_TO_DATA 1
224 #define DISCONNECT_LONG 2
227 * These are "special" values for the tag parameter passed to NCR5380_select.
230 #define TAG_NEXT -1 /* Use next free tag */
231 #define TAG_NONE -2 /*
232 * Establish I_T_L nexus instead of I_T_L_Q
233 * even on SCSI-II devices.
237 * These are "special" values for the irq and dma_channel fields of the
238 * Scsi_Host structure
241 #define SCSI_IRQ_NONE 255
245 #define PORT_AUTO 0xffff /* autoprobe io port for 53c400a */
247 #define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */
248 #define FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */
249 #define FLAG_NCR53C400 4 /* NCR53c400 */
250 #define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
251 #define FLAG_DTC3181E 16 /* DTC3181E */
254 struct NCR5380_hostdata
{
255 NCR5380_implementation_fields
; /* implementation specific */
256 struct Scsi_Host
*host
; /* Host backpointer */
257 unsigned char id_mask
, id_higher_mask
; /* 1 << id, all bits greater */
258 unsigned char targets_present
; /* targets we have connected
259 to, so we can call a select
260 failure a retryable condition */
261 volatile unsigned char busy
[8]; /* index = target, bit = lun */
262 #if defined(REAL_DMA) || defined(REAL_DMA_POLL)
263 volatile int dma_len
; /* requested length of DMA */
265 volatile unsigned char last_message
; /* last message OUT */
266 volatile Scsi_Cmnd
*connected
; /* currently connected command */
267 volatile Scsi_Cmnd
*issue_queue
; /* waiting to be issued */
268 volatile Scsi_Cmnd
*disconnected_queue
; /* waiting for reconnect */
269 volatile int restart_select
; /* we have disconnected,
272 volatile unsigned aborted
:1; /* flag, says aborted */
274 unsigned long time_expires
; /* in jiffies, set prior to sleeping */
275 int select_time
; /* timer in select for target response */
276 volatile Scsi_Cmnd
*selecting
;
277 struct delayed_work coroutine
; /* our co-routine */
279 unsigned timebase
; /* Base for time calcs */
280 long time_read
[8]; /* time to do reads */
281 long time_write
[8]; /* time to do writes */
282 unsigned long bytes_read
[8]; /* bytes read */
283 unsigned long bytes_write
[8]; /* bytes written */
288 struct scsi_eh_save ses
;
298 #define dprintk(flg, fmt, ...) \
299 do { if ((NDEBUG) & (flg)) pr_debug(fmt, ## __VA_ARGS__); } while (0)
302 #define NCR5380_dprint(flg, arg) \
303 do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
304 #define NCR5380_dprint_phase(flg, arg) \
305 do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
306 static void NCR5380_print_phase(struct Scsi_Host
*instance
);
307 static void NCR5380_print(struct Scsi_Host
*instance
);
309 #define NCR5380_dprint(flg, arg) do {} while (0)
310 #define NCR5380_dprint_phase(flg, arg) do {} while (0)
313 #if defined(AUTOPROBE_IRQ)
314 static int NCR5380_probe_irq(struct Scsi_Host
*instance
, int possible
);
316 static int NCR5380_init(struct Scsi_Host
*instance
, int flags
);
317 static void NCR5380_exit(struct Scsi_Host
*instance
);
318 static void NCR5380_information_transfer(struct Scsi_Host
*instance
);
319 #ifndef DONT_USE_INTR
320 static irqreturn_t
NCR5380_intr(int irq
, void *dev_id
);
322 static void NCR5380_main(struct work_struct
*work
);
323 static void __maybe_unused
NCR5380_print_options(struct Scsi_Host
*instance
);
324 static int NCR5380_abort(Scsi_Cmnd
* cmd
);
325 static int NCR5380_bus_reset(Scsi_Cmnd
* cmd
);
326 static int NCR5380_queue_command(struct Scsi_Host
*, struct scsi_cmnd
*);
327 static int __maybe_unused
NCR5380_show_info(struct seq_file
*,
329 static int __maybe_unused
NCR5380_write_info(struct Scsi_Host
*instance
,
330 char *buffer
, int length
);
332 static void NCR5380_reselect(struct Scsi_Host
*instance
);
333 static int NCR5380_select(struct Scsi_Host
*instance
, Scsi_Cmnd
* cmd
, int tag
);
334 #if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
335 static int NCR5380_transfer_dma(struct Scsi_Host
*instance
, unsigned char *phase
, int *count
, unsigned char **data
);
337 static int NCR5380_transfer_pio(struct Scsi_Host
*instance
, unsigned char *phase
, int *count
, unsigned char **data
);
339 #if (defined(REAL_DMA) || defined(REAL_DMA_POLL))
341 #if defined(i386) || defined(__alpha__)
344 * NCR5380_pc_dma_setup - setup ISA DMA
345 * @instance: adapter to set up
346 * @ptr: block to transfer (virtual address)
347 * @count: number of bytes to transfer
348 * @mode: DMA controller mode to use
350 * Program the DMA controller ready to perform an ISA DMA transfer
353 * Locks: takes and releases the ISA DMA lock.
356 static __inline__
int NCR5380_pc_dma_setup(struct Scsi_Host
*instance
, unsigned char *ptr
, unsigned int count
, unsigned char mode
)
359 unsigned long bus_addr
= virt_to_bus(ptr
);
362 if (instance
->dma_channel
<= 3) {
365 limit
= 65536 - (bus_addr
& 0xFFFF);
367 if (count
> 65536 * 2)
369 limit
= 65536 * 2 - (bus_addr
& 0x1FFFF);
375 if ((count
& 1) || (bus_addr
& 1))
376 panic("scsi%d : attempted unaligned DMA transfer\n", instance
->host_no
);
378 flags
=claim_dma_lock();
379 disable_dma(instance
->dma_channel
);
380 clear_dma_ff(instance
->dma_channel
);
381 set_dma_addr(instance
->dma_channel
, bus_addr
);
382 set_dma_count(instance
->dma_channel
, count
);
383 set_dma_mode(instance
->dma_channel
, mode
);
384 enable_dma(instance
->dma_channel
);
385 release_dma_lock(flags
);
391 * NCR5380_pc_dma_write_setup - setup ISA DMA write
392 * @instance: adapter to set up
393 * @ptr: block to transfer (virtual address)
394 * @count: number of bytes to transfer
396 * Program the DMA controller ready to perform an ISA DMA write to the
399 * Locks: called routines take and release the ISA DMA lock.
402 static __inline__
int NCR5380_pc_dma_write_setup(struct Scsi_Host
*instance
, unsigned char *src
, unsigned int count
)
404 return NCR5380_pc_dma_setup(instance
, src
, count
, DMA_MODE_WRITE
);
408 * NCR5380_pc_dma_read_setup - setup ISA DMA read
409 * @instance: adapter to set up
410 * @ptr: block to transfer (virtual address)
411 * @count: number of bytes to transfer
413 * Program the DMA controller ready to perform an ISA DMA read from the
416 * Locks: called routines take and release the ISA DMA lock.
419 static __inline__
int NCR5380_pc_dma_read_setup(struct Scsi_Host
*instance
, unsigned char *src
, unsigned int count
)
421 return NCR5380_pc_dma_setup(instance
, src
, count
, DMA_MODE_READ
);
425 * NCR5380_pc_dma_residual - return bytes left
428 * Reports the number of bytes left over after the DMA was terminated.
430 * Locks: takes and releases the ISA DMA lock.
433 static __inline__
int NCR5380_pc_dma_residual(struct Scsi_Host
*instance
)
438 flags
= claim_dma_lock();
439 clear_dma_ff(instance
->dma_channel
);
440 tmp
= get_dma_residue(instance
->dma_channel
);
441 release_dma_lock(flags
);
445 #endif /* defined(i386) || defined(__alpha__) */
446 #endif /* defined(REAL_DMA) */
447 #endif /* __KERNEL__ */
448 #endif /* ndef ASM */
449 #endif /* NCR5380_H */