drivers/staging/vt6656/rf.c

   1 /*
   2  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  *
  20  * File: rf.c
  21  *
  22  * Purpose: rf function code
  23  *
  24  * Author: Jerry Chen
  25  *
  26  * Date: Feb. 19, 2004
  27  *
  28  * Functions:
  29  *      IFRFbWriteEmbedded      - Embedded write RF register via MAC
  30  *
  31  * Revision History:
  32  *      RF_VT3226: RobertYu:20051111, VT3226C0 and before
  33  *      RF_VT3226D0: RobertYu:20051228
  34  *      RF_VT3342A0: RobertYu:20060609
  35  *
  36  */
  37
  38 #include "mac.h"
  39 #include "rf.h"
  40 #include "baseband.h"
  41 #include "control.h"
  42 #include "rndis.h"
  43 #include "datarate.h"
  44
  45 static int          msglevel                =MSG_LEVEL_INFO;
  46 //static int          msglevel                =MSG_LEVEL_DEBUG;
  47 #define BY_AL2230_REG_LEN     23 //24bit
  48 #define CB_AL2230_INIT_SEQ    15
  49 #define AL2230_PWR_IDX_LEN    64
  50
  51 #define BY_AL7230_REG_LEN     23 //24bit
  52 #define CB_AL7230_INIT_SEQ    16
  53 #define AL7230_PWR_IDX_LEN    64
  54
  55 //{{RobertYu:20051111
  56 #define BY_VT3226_REG_LEN     23
  57 #define CB_VT3226_INIT_SEQ    11
  58 #define VT3226_PWR_IDX_LEN    64
  59 //}}
  60
  61 //{{RobertYu:20060609
  62 #define BY_VT3342_REG_LEN     23
  63 #define CB_VT3342_INIT_SEQ    13
  64 #define VT3342_PWR_IDX_LEN    64
  65 //}}
  66
  67 static u8 al2230_init_table[CB_AL2230_INIT_SEQ][3] = {
  68     {0x03, 0xF7, 0x90},
  69     {0x03, 0x33, 0x31},
  70     {0x01, 0xB8, 0x02},
  71     {0x00, 0xFF, 0xF3},
  72     {0x00, 0x05, 0xA4},
  73     {0x0F, 0x4D, 0xC5},   //RobertYu:20060814
  74     {0x08, 0x05, 0xB6},
  75     {0x01, 0x47, 0xC7},
  76     {0x00, 0x06, 0x88},
  77     {0x04, 0x03, 0xB9},
  78     {0x00, 0xDB, 0xBA},
  79     {0x00, 0x09, 0x9B},
  80     {0x0B, 0xDF, 0xFC},
  81     {0x00, 0x00, 0x0D},
  82     {0x00, 0x58, 0x0F}
  83     };
  84
  85 static u8 al2230_channel_table0[CB_MAX_CHANNEL_24G][3] = {
  86     {0x03, 0xF7, 0x90}, // channel = 1, Tf = 2412MHz
  87     {0x03, 0xF7, 0x90}, // channel = 2, Tf = 2417MHz
  88     {0x03, 0xE7, 0x90}, // channel = 3, Tf = 2422MHz
  89     {0x03, 0xE7, 0x90}, // channel = 4, Tf = 2427MHz
  90     {0x03, 0xF7, 0xA0}, // channel = 5, Tf = 2432MHz
  91     {0x03, 0xF7, 0xA0}, // channel = 6, Tf = 2437MHz
  92     {0x03, 0xE7, 0xA0}, // channel = 7, Tf = 2442MHz
  93     {0x03, 0xE7, 0xA0}, // channel = 8, Tf = 2447MHz
  94     {0x03, 0xF7, 0xB0}, // channel = 9, Tf = 2452MHz
  95     {0x03, 0xF7, 0xB0}, // channel = 10, Tf = 2457MHz
  96     {0x03, 0xE7, 0xB0}, // channel = 11, Tf = 2462MHz
  97     {0x03, 0xE7, 0xB0}, // channel = 12, Tf = 2467MHz
  98     {0x03, 0xF7, 0xC0}, // channel = 13, Tf = 2472MHz
  99     {0x03, 0xE7, 0xC0}  // channel = 14, Tf = 2412M
 100     };
 101
 102 static u8 al2230_channel_table1[CB_MAX_CHANNEL_24G][3] = {
 103     {0x03, 0x33, 0x31}, // channel = 1, Tf = 2412MHz
 104     {0x0B, 0x33, 0x31}, // channel = 2, Tf = 2417MHz
 105     {0x03, 0x33, 0x31}, // channel = 3, Tf = 2422MHz
 106     {0x0B, 0x33, 0x31}, // channel = 4, Tf = 2427MHz
 107     {0x03, 0x33, 0x31}, // channel = 5, Tf = 2432MHz
 108     {0x0B, 0x33, 0x31}, // channel = 6, Tf = 2437MHz
 109     {0x03, 0x33, 0x31}, // channel = 7, Tf = 2442MHz
 110     {0x0B, 0x33, 0x31}, // channel = 8, Tf = 2447MHz
 111     {0x03, 0x33, 0x31}, // channel = 9, Tf = 2452MHz
 112     {0x0B, 0x33, 0x31}, // channel = 10, Tf = 2457MHz
 113     {0x03, 0x33, 0x31}, // channel = 11, Tf = 2462MHz
 114     {0x0B, 0x33, 0x31}, // channel = 12, Tf = 2467MHz
 115     {0x03, 0x33, 0x31}, // channel = 13, Tf = 2472MHz
 116     {0x06, 0x66, 0x61}  // channel = 14, Tf = 2412M
 117     };
 118
 119 // 40MHz reference frequency
 120 // Need to Pull PLLON(PE3) low when writing channel registers through 3-wire.
 121 static u8 al7230_init_table[CB_AL7230_INIT_SEQ][3] = {
 122     {0x20, 0x37, 0x90}, // Channel1 // Need modify for 11a
 123     {0x13, 0x33, 0x31}, // Channel1 // Need modify for 11a
 124     {0x84, 0x1F, 0xF2}, // Need modify for 11a: 451FE2
 125     {0x3F, 0xDF, 0xA3}, // Need modify for 11a: 5FDFA3
 126     {0x7F, 0xD7, 0x84}, // 11b/g    // Need modify for 11a
 127     //0x802B4500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B45
 128     // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
 129     {0x80, 0x2B, 0x55}, // Need modify for 11a: 8D1B55
 130     {0x56, 0xAF, 0x36},
 131     {0xCE, 0x02, 0x07}, // Need modify for 11a: 860207
 132     {0x6E, 0xBC, 0x98},
 133     {0x22, 0x1B, 0xB9},
 134     {0xE0, 0x00, 0x0A}, // Need modify for 11a: E0600A
 135     {0x08, 0x03, 0x1B}, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
 136     //0x00093C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C
 137     // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
 138     {0x00, 0x0A, 0x3C}, // Need modify for 11a: 00143C
 139     {0xFF, 0xFF, 0xFD},
 140     {0x00, 0x00, 0x0E},
 141     {0x1A, 0xBA, 0x8F} // Need modify for 11a: 12BACF
 142     };
 143
 144 static u8 al7230_init_table_amode[CB_AL7230_INIT_SEQ][3] = {
 145     {0x2F, 0xF5, 0x20}, // Channel184 // Need modify for 11b/g
 146     {0x00, 0x00, 0x01}, // Channel184 // Need modify for 11b/g
 147     {0x45, 0x1F, 0xE2}, // Need modify for 11b/g
 148     {0x5F, 0xDF, 0xA3}, // Need modify for 11b/g
 149     {0x6F, 0xD7, 0x84}, // 11a    // Need modify for 11b/g
 150     {0x85, 0x3F, 0x55}, // Need modify for 11b/g, RoberYu:20050113
 151     {0x56, 0xAF, 0x36},
 152     {0xCE, 0x02, 0x07}, // Need modify for 11b/g
 153     {0x6E, 0xBC, 0x98},
 154     {0x22, 0x1B, 0xB9},
 155     {0xE0, 0x60, 0x0A}, // Need modify for 11b/g
 156     {0x08, 0x03, 0x1B}, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
 157     {0x00, 0x14, 0x7C}, // Need modify for 11b/g
 158     {0xFF, 0xFF, 0xFD},
 159     {0x00, 0x00, 0x0E},
 160     {0x12, 0xBA, 0xCF} // Need modify for 11b/g
 161     };
 162
 163 static u8 al7230_channel_table0[CB_MAX_CHANNEL][3] = {
 164     {0x20, 0x37, 0x90}, // channel =  1, Tf = 2412MHz
 165     {0x20, 0x37, 0x90}, // channel =  2, Tf = 2417MHz
 166     {0x20, 0x37, 0x90}, // channel =  3, Tf = 2422MHz
 167     {0x20, 0x37, 0x90}, // channel =  4, Tf = 2427MHz
 168     {0x20, 0x37, 0xA0}, // channel =  5, Tf = 2432MHz
 169     {0x20, 0x37, 0xA0}, // channel =  6, Tf = 2437MHz
 170     {0x20, 0x37, 0xA0}, // channel =  7, Tf = 2442MHz
 171     {0x20, 0x37, 0xA0}, // channel =  8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49
 172     {0x20, 0x37, 0xB0}, // channel =  9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49
 173     {0x20, 0x37, 0xB0}, // channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49
 174     {0x20, 0x37, 0xB0}, // channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49
 175     {0x20, 0x37, 0xB0}, // channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49
 176     {0x20, 0x37, 0xC0}, // channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49
 177     {0x20, 0x37, 0xC0}, // channel = 14, Tf = 2484MHz
 178
 179     // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
 180     {0x0F, 0xF5, 0x20}, // channel = 183, Tf = 4915MHz (15)
 181     {0x2F, 0xF5, 0x20}, // channel = 184, Tf = 4920MHz (16)
 182     {0x0F, 0xF5, 0x20}, // channel = 185, Tf = 4925MHz (17)
 183     {0x0F, 0xF5, 0x20}, // channel = 187, Tf = 4935MHz (18)
 184     {0x2F, 0xF5, 0x20}, // channel = 188, Tf = 4940MHz (19)
 185     {0x0F, 0xF5, 0x20}, // channel = 189, Tf = 4945MHz (20)
 186     {0x2F, 0xF5, 0x30}, // channel = 192, Tf = 4960MHz (21)
 187     {0x2F, 0xF5, 0x30}, // channel = 196, Tf = 4980MHz (22)
 188
 189     // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
 190     // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
 191
 192     {0x0F, 0xF5, 0x40}, // channel =   7, Tf = 5035MHz (23)
 193     {0x2F, 0xF5, 0x40}, // channel =   8, Tf = 5040MHz (24)
 194     {0x0F, 0xF5, 0x40}, // channel =   9, Tf = 5045MHz (25)
 195     {0x0F, 0xF5, 0x40}, // channel =  11, Tf = 5055MHz (26)
 196     {0x2F, 0xF5, 0x40}, // channel =  12, Tf = 5060MHz (27)
 197     {0x2F, 0xF5, 0x50}, // channel =  16, Tf = 5080MHz (28)
 198     {0x2F, 0xF5, 0x60}, // channel =  34, Tf = 5170MHz (29)
 199     {0x2F, 0xF5, 0x60}, // channel =  36, Tf = 5180MHz (30)
 200     {0x2F, 0xF5, 0x70}, // channel =  38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49
 201     {0x2F, 0xF5, 0x70}, // channel =  40, Tf = 5200MHz (32)
 202     {0x2F, 0xF5, 0x70}, // channel =  42, Tf = 5210MHz (33)
 203     {0x2F, 0xF5, 0x70}, // channel =  44, Tf = 5220MHz (34)
 204     {0x2F, 0xF5, 0x70}, // channel =  46, Tf = 5230MHz (35)
 205     {0x2F, 0xF5, 0x70}, // channel =  48, Tf = 5240MHz (36)
 206     {0x2F, 0xF5, 0x80}, // channel =  52, Tf = 5260MHz (37)
 207     {0x2F, 0xF5, 0x80}, // channel =  56, Tf = 5280MHz (38)
 208     {0x2F, 0xF5, 0x80}, // channel =  60, Tf = 5300MHz (39)
 209     {0x2F, 0xF5, 0x90}, // channel =  64, Tf = 5320MHz (40)
 210
 211     {0x2F, 0xF5, 0xC0}, // channel = 100, Tf = 5500MHz (41)
 212     {0x2F, 0xF5, 0xC0}, // channel = 104, Tf = 5520MHz (42)
 213     {0x2F, 0xF5, 0xC0}, // channel = 108, Tf = 5540MHz (43)
 214     {0x2F, 0xF5, 0xD0}, // channel = 112, Tf = 5560MHz (44)
 215     {0x2F, 0xF5, 0xD0}, // channel = 116, Tf = 5580MHz (45)
 216     {0x2F, 0xF5, 0xD0}, // channel = 120, Tf = 5600MHz (46)
 217     {0x2F, 0xF5, 0xE0}, // channel = 124, Tf = 5620MHz (47)
 218     {0x2F, 0xF5, 0xE0}, // channel = 128, Tf = 5640MHz (48)
 219     {0x2F, 0xF5, 0xE0}, // channel = 132, Tf = 5660MHz (49)
 220     {0x2F, 0xF5, 0xF0}, // channel = 136, Tf = 5680MHz (50)
 221     {0x2F, 0xF5, 0xF0}, // channel = 140, Tf = 5700MHz (51)
 222     {0x2F, 0xF6, 0x00}, // channel = 149, Tf = 5745MHz (52)
 223     {0x2F, 0xF6, 0x00}, // channel = 153, Tf = 5765MHz (53)
 224     {0x2F, 0xF6, 0x00}, // channel = 157, Tf = 5785MHz (54)
 225     {0x2F, 0xF6, 0x10}, // channel = 161, Tf = 5805MHz (55)
 226     {0x2F, 0xF6, 0x10} // channel = 165, Tf = 5825MHz (56)
 227     };
 228
 229 static u8 al7230_channel_table1[CB_MAX_CHANNEL][3] = {
 230     {0x13, 0x33, 0x31}, // channel =  1, Tf = 2412MHz
 231     {0x1B, 0x33, 0x31}, // channel =  2, Tf = 2417MHz
 232     {0x03, 0x33, 0x31}, // channel =  3, Tf = 2422MHz
 233     {0x0B, 0x33, 0x31}, // channel =  4, Tf = 2427MHz
 234     {0x13, 0x33, 0x31}, // channel =  5, Tf = 2432MHz
 235     {0x1B, 0x33, 0x31}, // channel =  6, Tf = 2437MHz
 236     {0x03, 0x33, 0x31}, // channel =  7, Tf = 2442MHz
 237     {0x0B, 0x33, 0x31}, // channel =  8, Tf = 2447MHz
 238     {0x13, 0x33, 0x31}, // channel =  9, Tf = 2452MHz
 239     {0x1B, 0x33, 0x31}, // channel = 10, Tf = 2457MHz
 240     {0x03, 0x33, 0x31}, // channel = 11, Tf = 2462MHz
 241     {0x0B, 0x33, 0x31}, // channel = 12, Tf = 2467MHz
 242     {0x13, 0x33, 0x31}, // channel = 13, Tf = 2472MHz
 243     {0x06, 0x66, 0x61}, // channel = 14, Tf = 2484MHz
 244
 245     // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
 246     {0x1D, 0x55, 0x51}, // channel = 183, Tf = 4915MHz (15)
 247     {0x00, 0x00, 0x01}, // channel = 184, Tf = 4920MHz (16)
 248     {0x02, 0xAA, 0xA1}, // channel = 185, Tf = 4925MHz (17)
 249     {0x08, 0x00, 0x01}, // channel = 187, Tf = 4935MHz (18)
 250     {0x0A, 0xAA, 0xA1}, // channel = 188, Tf = 4940MHz (19)
 251     {0x0D, 0x55, 0x51}, // channel = 189, Tf = 4945MHz (20)
 252     {0x15, 0x55, 0x51}, // channel = 192, Tf = 4960MHz (21)
 253     {0x00, 0x00, 0x01}, // channel = 196, Tf = 4980MHz (22)
 254
 255     // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
 256     // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
 257     {0x1D, 0x55, 0x51}, // channel =   7, Tf = 5035MHz (23)
 258     {0x00, 0x00, 0x01}, // channel =   8, Tf = 5040MHz (24)
 259     {0x02, 0xAA, 0xA1}, // channel =   9, Tf = 5045MHz (25)
 260     {0x08, 0x00, 0x01}, // channel =  11, Tf = 5055MHz (26)
 261     {0x0A, 0xAA, 0xA1}, // channel =  12, Tf = 5060MHz (27)
 262     {0x15, 0x55, 0x51}, // channel =  16, Tf = 5080MHz (28)
 263     {0x05, 0x55, 0x51}, // channel =  34, Tf = 5170MHz (29)
 264     {0x0A, 0xAA, 0xA1}, // channel =  36, Tf = 5180MHz (30)
 265     {0x10, 0x00, 0x01}, // channel =  38, Tf = 5190MHz (31)
 266     {0x15, 0x55, 0x51}, // channel =  40, Tf = 5200MHz (32)
 267     {0x1A, 0xAA, 0xA1}, // channel =  42, Tf = 5210MHz (33)
 268     {0x00, 0x00, 0x01}, // channel =  44, Tf = 5220MHz (34)
 269     {0x05, 0x55, 0x51}, // channel =  46, Tf = 5230MHz (35)
 270     {0x0A, 0xAA, 0xA1}, // channel =  48, Tf = 5240MHz (36)
 271     {0x15, 0x55, 0x51}, // channel =  52, Tf = 5260MHz (37)
 272     {0x00, 0x00, 0x01}, // channel =  56, Tf = 5280MHz (38)
 273     {0x0A, 0xAA, 0xA1}, // channel =  60, Tf = 5300MHz (39)
 274     {0x15, 0x55, 0x51}, // channel =  64, Tf = 5320MHz (40)
 275     {0x15, 0x55, 0x51}, // channel = 100, Tf = 5500MHz (41)
 276     {0x00, 0x00, 0x01}, // channel = 104, Tf = 5520MHz (42)
 277     {0x0A, 0xAA, 0xA1}, // channel = 108, Tf = 5540MHz (43)
 278     {0x15, 0x55, 0x51}, // channel = 112, Tf = 5560MHz (44)
 279     {0x00, 0x00, 0x01}, // channel = 116, Tf = 5580MHz (45)
 280     {0x0A, 0xAA, 0xA1}, // channel = 120, Tf = 5600MHz (46)
 281     {0x15, 0x55, 0x51}, // channel = 124, Tf = 5620MHz (47)
 282     {0x00, 0x00, 0x01}, // channel = 128, Tf = 5640MHz (48)
 283     {0x0A, 0xAA, 0xA1}, // channel = 132, Tf = 5660MHz (49)
 284     {0x15, 0x55, 0x51}, // channel = 136, Tf = 5680MHz (50)
 285     {0x00, 0x00, 0x01}, // channel = 140, Tf = 5700MHz (51)
 286     {0x18, 0x00, 0x01}, // channel = 149, Tf = 5745MHz (52)
 287     {0x02, 0xAA, 0xA1}, // channel = 153, Tf = 5765MHz (53)
 288     {0x0D, 0x55, 0x51}, // channel = 157, Tf = 5785MHz (54)
 289     {0x18, 0x00, 0x01}, // channel = 161, Tf = 5805MHz (55)
 290     {0x02, 0xAA, 0xB1}  // channel = 165, Tf = 5825MHz (56)
 291     };
 292
 293 static u8 al7230_channel_table2[CB_MAX_CHANNEL][3] = {
 294     {0x7F, 0xD7, 0x84}, // channel =  1, Tf = 2412MHz
 295     {0x7F, 0xD7, 0x84}, // channel =  2, Tf = 2417MHz
 296     {0x7F, 0xD7, 0x84}, // channel =  3, Tf = 2422MHz
 297     {0x7F, 0xD7, 0x84}, // channel =  4, Tf = 2427MHz
 298     {0x7F, 0xD7, 0x84}, // channel =  5, Tf = 2432MHz
 299     {0x7F, 0xD7, 0x84}, // channel =  6, Tf = 2437MHz
 300     {0x7F, 0xD7, 0x84}, // channel =  7, Tf = 2442MHz
 301     {0x7F, 0xD7, 0x84}, // channel =  8, Tf = 2447MHz
 302     {0x7F, 0xD7, 0x84}, // channel =  9, Tf = 2452MHz
 303     {0x7F, 0xD7, 0x84}, // channel = 10, Tf = 2457MHz
 304     {0x7F, 0xD7, 0x84}, // channel = 11, Tf = 2462MHz
 305     {0x7F, 0xD7, 0x84}, // channel = 12, Tf = 2467MHz
 306     {0x7F, 0xD7, 0x84}, // channel = 13, Tf = 2472MHz
 307     {0x7F, 0xD7, 0x84}, // channel = 14, Tf = 2484MHz
 308
 309     // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
 310     {0x7F, 0xD7, 0x84}, // channel = 183, Tf = 4915MHz (15)
 311     {0x6F, 0xD7, 0x84}, // channel = 184, Tf = 4920MHz (16)
 312     {0x7F, 0xD7, 0x84}, // channel = 185, Tf = 4925MHz (17)
 313     {0x7F, 0xD7, 0x84}, // channel = 187, Tf = 4935MHz (18)
 314     {0x7F, 0xD7, 0x84}, // channel = 188, Tf = 4940MHz (19)
 315     {0x7F, 0xD7, 0x84}, // channel = 189, Tf = 4945MHz (20)
 316     {0x7F, 0xD7, 0x84}, // channel = 192, Tf = 4960MHz (21)
 317     {0x6F, 0xD7, 0x84}, // channel = 196, Tf = 4980MHz (22)
 318
 319     // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
 320     // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
 321     {0x7F, 0xD7, 0x84}, // channel =   7, Tf = 5035MHz (23)
 322     {0x6F, 0xD7, 0x84}, // channel =   8, Tf = 5040MHz (24)
 323     {0x7F, 0xD7, 0x84}, // channel =   9, Tf = 5045MHz (25)
 324     {0x7F, 0xD7, 0x84}, // channel =  11, Tf = 5055MHz (26)
 325     {0x7F, 0xD7, 0x84}, // channel =  12, Tf = 5060MHz (27)
 326     {0x7F, 0xD7, 0x84}, // channel =  16, Tf = 5080MHz (28)
 327     {0x7F, 0xD7, 0x84}, // channel =  34, Tf = 5170MHz (29)
 328     {0x7F, 0xD7, 0x84}, // channel =  36, Tf = 5180MHz (30)
 329     {0x7F, 0xD7, 0x84}, // channel =  38, Tf = 5190MHz (31)
 330     {0x7F, 0xD7, 0x84}, // channel =  40, Tf = 5200MHz (32)
 331     {0x7F, 0xD7, 0x84}, // channel =  42, Tf = 5210MHz (33)
 332     {0x6F, 0xD7, 0x84}, // channel =  44, Tf = 5220MHz (34)
 333     {0x7F, 0xD7, 0x84}, // channel =  46, Tf = 5230MHz (35)
 334     {0x7F, 0xD7, 0x84}, // channel =  48, Tf = 5240MHz (36)
 335     {0x7F, 0xD7, 0x84}, // channel =  52, Tf = 5260MHz (37)
 336     {0x6F, 0xD7, 0x84}, // channel =  56, Tf = 5280MHz (38)
 337     {0x7F, 0xD7, 0x84}, // channel =  60, Tf = 5300MHz (39)
 338     {0x7F, 0xD7, 0x84}, // channel =  64, Tf = 5320MHz (40)
 339     {0x7F, 0xD7, 0x84}, // channel = 100, Tf = 5500MHz (41)
 340     {0x6F, 0xD7, 0x84}, // channel = 104, Tf = 5520MHz (42)
 341     {0x7F, 0xD7, 0x84}, // channel = 108, Tf = 5540MHz (43)
 342     {0x7F, 0xD7, 0x84}, // channel = 112, Tf = 5560MHz (44)
 343     {0x6F, 0xD7, 0x84}, // channel = 116, Tf = 5580MHz (45)
 344     {0x7F, 0xD7, 0x84}, // channel = 120, Tf = 5600MHz (46)
 345     {0x7F, 0xD7, 0x84}, // channel = 124, Tf = 5620MHz (47)
 346     {0x6F, 0xD7, 0x84}, // channel = 128, Tf = 5640MHz (48)
 347     {0x7F, 0xD7, 0x84}, // channel = 132, Tf = 5660MHz (49)
 348     {0x7F, 0xD7, 0x84}, // channel = 136, Tf = 5680MHz (50)
 349     {0x6F, 0xD7, 0x84}, // channel = 140, Tf = 5700MHz (51)
 350     {0x7F, 0xD7, 0x84}, // channel = 149, Tf = 5745MHz (52)
 351     {0x7F, 0xD7, 0x84}, // channel = 153, Tf = 5765MHz (53)
 352     {0x7F, 0xD7, 0x84}, // channel = 157, Tf = 5785MHz (54)
 353     {0x7F, 0xD7, 0x84}, // channel = 161, Tf = 5805MHz (55)
 354     {0x7F, 0xD7, 0x84}  // channel = 165, Tf = 5825MHz (56)
 355     };
 356
 357 ///{{RobertYu:20051111
 358 static u8 at3226_init_table[CB_VT3226_INIT_SEQ][3] = {
 359     {0x03, 0xFF, 0x80},
 360     {0x02, 0x82, 0xA1},
 361     {0x03, 0xC6, 0xA2},
 362     {0x01, 0x97, 0x93},
 363     {0x03, 0x66, 0x64},
 364     {0x00, 0x61, 0xA5},
 365     {0x01, 0x7B, 0xD6},
 366     {0x00, 0x80, 0x17},
 367     {0x03, 0xF8, 0x08},
 368     {0x00, 0x02, 0x39},   //RobertYu:20051116
 369     {0x02, 0x00, 0x2A}
 370     };
 371
 372 static u8 at3226d0_init_table[CB_VT3226_INIT_SEQ][3] = {
 373     {0x03, 0xFF, 0x80},
 374     {0x03, 0x02, 0x21}, //RobertYu:20060327
 375     {0x03, 0xC6, 0xA2},
 376     {0x01, 0x97, 0x93},
 377     {0x03, 0x66, 0x64},
 378     {0x00, 0x71, 0xA5}, //RobertYu:20060103
 379     {0x01, 0x15, 0xC6}, //RobertYu:20060420
 380     {0x01, 0x2E, 0x07}, //RobertYu:20060420
 381     {0x00, 0x58, 0x08}, //RobertYu:20060111
 382     {0x00, 0x02, 0x79}, //RobertYu:20060420
 383     {0x02, 0x01, 0xAA}  //RobertYu:20060523
 384     };
 385
 386 static u8 vt3226_channel_table0[CB_MAX_CHANNEL_24G][3] = {
 387     {0x01, 0x97, 0x83}, // channel = 1, Tf = 2412MHz
 388     {0x01, 0x97, 0x83}, // channel = 2, Tf = 2417MHz
 389     {0x01, 0x97, 0x93}, // channel = 3, Tf = 2422MHz
 390     {0x01, 0x97, 0x93}, // channel = 4, Tf = 2427MHz
 391     {0x01, 0x97, 0x93}, // channel = 5, Tf = 2432MHz
 392     {0x01, 0x97, 0x93}, // channel = 6, Tf = 2437MHz
 393     {0x01, 0x97, 0xA3}, // channel = 7, Tf = 2442MHz
 394     {0x01, 0x97, 0xA3}, // channel = 8, Tf = 2447MHz
 395     {0x01, 0x97, 0xA3}, // channel = 9, Tf = 2452MHz
 396     {0x01, 0x97, 0xA3}, // channel = 10, Tf = 2457MHz
 397     {0x01, 0x97, 0xB3}, // channel = 11, Tf = 2462MHz
 398     {0x01, 0x97, 0xB3}, // channel = 12, Tf = 2467MHz
 399     {0x01, 0x97, 0xB3}, // channel = 13, Tf = 2472MHz
 400     {0x03, 0x37, 0xC3}  // channel = 14, Tf = 2484MHz
 401     };
 402
 403 static u8 vt3226_channel_table1[CB_MAX_CHANNEL_24G][3] = {
 404     {0x02, 0x66, 0x64}, // channel = 1, Tf = 2412MHz
 405     {0x03, 0x66, 0x64}, // channel = 2, Tf = 2417MHz
 406     {0x00, 0x66, 0x64}, // channel = 3, Tf = 2422MHz
 407     {0x01, 0x66, 0x64}, // channel = 4, Tf = 2427MHz
 408     {0x02, 0x66, 0x64}, // channel = 5, Tf = 2432MHz
 409     {0x03, 0x66, 0x64}, // channel = 6, Tf = 2437MHz
 410     {0x00, 0x66, 0x64}, // channel = 7, Tf = 2442MHz
 411     {0x01, 0x66, 0x64}, // channel = 8, Tf = 2447MHz
 412     {0x02, 0x66, 0x64}, // channel = 9, Tf = 2452MHz
 413     {0x03, 0x66, 0x64}, // channel = 10, Tf = 2457MHz
 414     {0x00, 0x66, 0x64}, // channel = 11, Tf = 2462MHz
 415     {0x01, 0x66, 0x64}, // channel = 12, Tf = 2467MHz
 416     {0x02, 0x66, 0x64}, // channel = 13, Tf = 2472MHz
 417     {0x00, 0xCC, 0xC4}  // channel = 14, Tf = 2484MHz
 418     };
 419 ///}}RobertYu
 420
 421 //{{RobertYu:20060502, TWIF 1.14, LO Current for 11b mode
 422 const u32 vt3226d0_lo_current_table[CB_MAX_CHANNEL_24G] = {
 423     0x0135C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
 424     0x0135C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
 425     0x0235C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
 426     0x0235C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
 427     0x0235C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
 428     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
 429     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
 430     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
 431     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
 432     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
 433     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
 434     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
 435     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
 436     0x0135C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW  // channel = 14, Tf = 2484MHz
 437 };
 438 //}}
 439
 440 //{{RobertYu:20060609
 441 static u8 vt3342a0_init_table[CB_VT3342_INIT_SEQ][3] = { /* 11b/g mode */
 442     {0x03, 0xFF, 0x80}, //update for mode//
 443     {0x02, 0x08, 0x81},
 444     {0x00, 0xC6, 0x02},
 445     {0x03, 0xC5, 0x13}, // channel6
 446     {0x00, 0xEE, 0xE4}, // channel6
 447     {0x00, 0x71, 0xA5},
 448     {0x01, 0x75, 0x46},
 449     {0x01, 0x40, 0x27},
 450     {0x01, 0x54, 0x08},
 451     {0x00, 0x01, 0x69},
 452     {0x02, 0x00, 0xAA},
 453     {0x00, 0x08, 0xCB},
 454     {0x01, 0x70, 0x0C}
 455     };
 456
 457  //11b/g mode: 0x03, 0xFF, 0x80,
 458  //11a mode:   0x03, 0xFF, 0xC0,
 459
 460  // channel44, 5220MHz  0x00C402
 461  // channel56, 5280MHz  0x00C402 for disable Frac
 462  // other channels 0x00C602
 463
 464 static u8 vt3342_channel_table0[CB_MAX_CHANNEL][3] = {
 465     {0x02, 0x05, 0x03}, // channel = 1, Tf = 2412MHz
 466     {0x01, 0x15, 0x03}, // channel = 2, Tf = 2417MHz
 467     {0x03, 0xC5, 0x03}, // channel = 3, Tf = 2422MHz
 468     {0x02, 0x65, 0x03}, // channel = 4, Tf = 2427MHz
 469     {0x01, 0x15, 0x13}, // channel = 5, Tf = 2432MHz
 470     {0x03, 0xC5, 0x13}, // channel = 6, Tf = 2437MHz
 471     {0x02, 0x05, 0x13}, // channel = 7, Tf = 2442MHz
 472     {0x01, 0x15, 0x13}, // channel = 8, Tf = 2447MHz
 473     {0x03, 0xC5, 0x13}, // channel = 9, Tf = 2452MHz
 474     {0x02, 0x65, 0x13}, // channel = 10, Tf = 2457MHz
 475     {0x01, 0x15, 0x23}, // channel = 11, Tf = 2462MHz
 476     {0x03, 0xC5, 0x23}, // channel = 12, Tf = 2467MHz
 477     {0x02, 0x05, 0x23}, // channel = 13, Tf = 2472MHz
 478     {0x00, 0xD5, 0x23}, // channel = 14, Tf = 2484MHz
 479
 480     // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
 481     {0x01, 0x15, 0x13}, // channel = 183, Tf = 4915MHz (15), TBD
 482     {0x01, 0x15, 0x13}, // channel = 184, Tf = 4920MHz (16), TBD
 483     {0x01, 0x15, 0x13}, // channel = 185, Tf = 4925MHz (17), TBD
 484     {0x01, 0x15, 0x13}, // channel = 187, Tf = 4935MHz (18), TBD
 485     {0x01, 0x15, 0x13}, // channel = 188, Tf = 4940MHz (19), TBD
 486     {0x01, 0x15, 0x13}, // channel = 189, Tf = 4945MHz (20), TBD
 487     {0x01, 0x15, 0x13}, // channel = 192, Tf = 4960MHz (21), TBD
 488     {0x01, 0x15, 0x13}, // channel = 196, Tf = 4980MHz (22), TBD
 489
 490     // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
 491     // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
 492     {0x01, 0x15, 0x13}, // channel =   7, Tf = 5035MHz (23), TBD
 493     {0x01, 0x15, 0x13}, // channel =   8, Tf = 5040MHz (24), TBD
 494     {0x01, 0x15, 0x13}, // channel =   9, Tf = 5045MHz (25), TBD
 495     {0x01, 0x15, 0x13}, // channel =  11, Tf = 5055MHz (26), TBD
 496     {0x01, 0x15, 0x13}, // channel =  12, Tf = 5060MHz (27), TBD
 497     {0x01, 0x15, 0x13}, // channel =  16, Tf = 5080MHz (28), TBD
 498     {0x01, 0x15, 0x13}, // channel =  34, Tf = 5170MHz (29), TBD
 499     {0x01, 0x55, 0x63}, // channel =  36, Tf = 5180MHz (30)
 500     {0x01, 0x55, 0x63}, // channel =  38, Tf = 5190MHz (31), TBD
 501     {0x02, 0xA5, 0x63}, // channel =  40, Tf = 5200MHz (32)
 502     {0x02, 0xA5, 0x63}, // channel =  42, Tf = 5210MHz (33), TBD
 503     {0x00, 0x05, 0x73}, // channel =  44, Tf = 5220MHz (34)
 504     {0x00, 0x05, 0x73}, // channel =  46, Tf = 5230MHz (35), TBD
 505     {0x01, 0x55, 0x73}, // channel =  48, Tf = 5240MHz (36)
 506     {0x02, 0xA5, 0x73}, // channel =  52, Tf = 5260MHz (37)
 507     {0x00, 0x05, 0x83}, // channel =  56, Tf = 5280MHz (38)
 508     {0x01, 0x55, 0x83}, // channel =  60, Tf = 5300MHz (39)
 509     {0x02, 0xA5, 0x83}, // channel =  64, Tf = 5320MHz (40)
 510
 511     {0x02, 0xA5, 0x83}, // channel = 100, Tf = 5500MHz (41), TBD
 512     {0x02, 0xA5, 0x83}, // channel = 104, Tf = 5520MHz (42), TBD
 513     {0x02, 0xA5, 0x83}, // channel = 108, Tf = 5540MHz (43), TBD
 514     {0x02, 0xA5, 0x83}, // channel = 112, Tf = 5560MHz (44), TBD
 515     {0x02, 0xA5, 0x83}, // channel = 116, Tf = 5580MHz (45), TBD
 516     {0x02, 0xA5, 0x83}, // channel = 120, Tf = 5600MHz (46), TBD
 517     {0x02, 0xA5, 0x83}, // channel = 124, Tf = 5620MHz (47), TBD
 518     {0x02, 0xA5, 0x83}, // channel = 128, Tf = 5640MHz (48), TBD
 519     {0x02, 0xA5, 0x83}, // channel = 132, Tf = 5660MHz (49), TBD
 520     {0x02, 0xA5, 0x83}, // channel = 136, Tf = 5680MHz (50), TBD
 521     {0x02, 0xA5, 0x83}, // channel = 140, Tf = 5700MHz (51), TBD
 522
 523     {0x00, 0x05, 0xF3}, // channel = 149, Tf = 5745MHz (52)
 524     {0x01, 0x56, 0x03}, // channel = 153, Tf = 5765MHz (53)
 525     {0x02, 0xA6, 0x03}, // channel = 157, Tf = 5785MHz (54)
 526     {0x00, 0x06, 0x03}, // channel = 161, Tf = 5805MHz (55)
 527     {0x00, 0x06, 0x03}  // channel = 165, Tf = 5825MHz (56), TBD
 528     };
 529
 530 static u8 vt3342_channel_table1[CB_MAX_CHANNEL][3] = {
 531     {0x01, 0x99, 0x94}, // channel = 1, Tf = 2412MHz
 532     {0x02, 0x44, 0x44}, // channel = 2, Tf = 2417MHz
 533     {0x02, 0xEE, 0xE4}, // channel = 3, Tf = 2422MHz
 534     {0x03, 0x99, 0x94}, // channel = 4, Tf = 2427MHz
 535     {0x00, 0x44, 0x44}, // channel = 5, Tf = 2432MHz
 536     {0x00, 0xEE, 0xE4}, // channel = 6, Tf = 2437MHz
 537     {0x01, 0x99, 0x94}, // channel = 7, Tf = 2442MHz
 538     {0x02, 0x44, 0x44}, // channel = 8, Tf = 2447MHz
 539     {0x02, 0xEE, 0xE4}, // channel = 9, Tf = 2452MHz
 540     {0x03, 0x99, 0x94}, // channel = 10, Tf = 2457MHz
 541     {0x00, 0x44, 0x44}, // channel = 11, Tf = 2462MHz
 542     {0x00, 0xEE, 0xE4}, // channel = 12, Tf = 2467MHz
 543     {0x01, 0x99, 0x94}, // channel = 13, Tf = 2472MHz
 544     {0x03, 0x33, 0x34}, // channel = 14, Tf = 2484MHz
 545
 546     // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
 547     {0x00, 0x44, 0x44}, // channel = 183, Tf = 4915MHz (15), TBD
 548     {0x00, 0x44, 0x44}, // channel = 184, Tf = 4920MHz (16), TBD
 549     {0x00, 0x44, 0x44}, // channel = 185, Tf = 4925MHz (17), TBD
 550     {0x00, 0x44, 0x44}, // channel = 187, Tf = 4935MHz (18), TBD
 551     {0x00, 0x44, 0x44}, // channel = 188, Tf = 4940MHz (19), TBD
 552     {0x00, 0x44, 0x44}, // channel = 189, Tf = 4945MHz (20), TBD
 553     {0x00, 0x44, 0x44}, // channel = 192, Tf = 4960MHz (21), TBD
 554     {0x00, 0x44, 0x44}, // channel = 196, Tf = 4980MHz (22), TBD
 555
 556     // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
 557     // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
 558     {0x00, 0x44, 0x44}, // channel =   7, Tf = 5035MHz (23), TBD
 559     {0x00, 0x44, 0x44}, // channel =   8, Tf = 5040MHz (24), TBD
 560     {0x00, 0x44, 0x44}, // channel =   9, Tf = 5045MHz (25), TBD
 561     {0x00, 0x44, 0x44}, // channel =  11, Tf = 5055MHz (26), TBD
 562     {0x00, 0x44, 0x44}, // channel =  12, Tf = 5060MHz (27), TBD
 563     {0x00, 0x44, 0x44}, // channel =  16, Tf = 5080MHz (28), TBD
 564     {0x00, 0x44, 0x44}, // channel =  34, Tf = 5170MHz (29), TBD
 565     {0x01, 0x55, 0x54}, // channel =  36, Tf = 5180MHz (30)
 566     {0x01, 0x55, 0x54}, // channel =  38, Tf = 5190MHz (31), TBD
 567     {0x02, 0xAA, 0xA4}, // channel =  40, Tf = 5200MHz (32)
 568     {0x02, 0xAA, 0xA4}, // channel =  42, Tf = 5210MHz (33), TBD
 569     {0x00, 0x00, 0x04}, // channel =  44, Tf = 5220MHz (34)
 570     {0x00, 0x00, 0x04}, // channel =  46, Tf = 5230MHz (35), TBD
 571     {0x01, 0x55, 0x54}, // channel =  48, Tf = 5240MHz (36)
 572     {0x02, 0xAA, 0xA4}, // channel =  52, Tf = 5260MHz (37)
 573     {0x00, 0x00, 0x04}, // channel =  56, Tf = 5280MHz (38)
 574     {0x01, 0x55, 0x54}, // channel =  60, Tf = 5300MHz (39)
 575     {0x02, 0xAA, 0xA4}, // channel =  64, Tf = 5320MHz (40)
 576     {0x02, 0xAA, 0xA4}, // channel = 100, Tf = 5500MHz (41), TBD
 577     {0x02, 0xAA, 0xA4}, // channel = 104, Tf = 5520MHz (42), TBD
 578     {0x02, 0xAA, 0xA4}, // channel = 108, Tf = 5540MHz (43), TBD
 579     {0x02, 0xAA, 0xA4}, // channel = 112, Tf = 5560MHz (44), TBD
 580     {0x02, 0xAA, 0xA4}, // channel = 116, Tf = 5580MHz (45), TBD
 581     {0x02, 0xAA, 0xA4}, // channel = 120, Tf = 5600MHz (46), TBD
 582     {0x02, 0xAA, 0xA4}, // channel = 124, Tf = 5620MHz (47), TBD
 583     {0x02, 0xAA, 0xA4}, // channel = 128, Tf = 5640MHz (48), TBD
 584     {0x02, 0xAA, 0xA4}, // channel = 132, Tf = 5660MHz (49), TBD
 585     {0x02, 0xAA, 0xA4}, // channel = 136, Tf = 5680MHz (50), TBD
 586     {0x02, 0xAA, 0xA4}, // channel = 140, Tf = 5700MHz (51), TBD
 587     {0x03, 0x00, 0x04}, // channel = 149, Tf = 5745MHz (52)
 588     {0x00, 0x55, 0x54}, // channel = 153, Tf = 5765MHz (53)
 589     {0x01, 0xAA, 0xA4}, // channel = 157, Tf = 5785MHz (54)
 590     {0x03, 0x00, 0x04}, // channel = 161, Tf = 5805MHz (55)
 591     {0x03, 0x00, 0x04}  // channel = 165, Tf = 5825MHz (56), TBD
 592     };
 593
 594 /*+
 595  *
 596  * Power Table
 597  *
 598 -*/
 599
 600 const u32 al2230_power_table[AL2230_PWR_IDX_LEN] = {
 601     0x04040900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 602     0x04041900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 603     0x04042900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 604     0x04043900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 605     0x04044900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 606     0x04045900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 607     0x04046900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 608     0x04047900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 609     0x04048900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 610     0x04049900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 611     0x0404A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 612     0x0404B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 613     0x0404C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 614     0x0404D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 615     0x0404E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 616     0x0404F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 617     0x04050900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 618     0x04051900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 619     0x04052900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 620     0x04053900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 621     0x04054900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 622     0x04055900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 623     0x04056900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 624     0x04057900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 625     0x04058900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 626     0x04059900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 627     0x0405A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 628     0x0405B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 629     0x0405C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 630     0x0405D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 631     0x0405E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 632     0x0405F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 633     0x04060900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 634     0x04061900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 635     0x04062900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 636     0x04063900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 637     0x04064900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 638     0x04065900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 639     0x04066900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 640     0x04067900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 641     0x04068900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 642     0x04069900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 643     0x0406A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 644     0x0406B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 645     0x0406C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 646     0x0406D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 647     0x0406E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 648     0x0406F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 649     0x04070900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 650     0x04071900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 651     0x04072900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 652     0x04073900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 653     0x04074900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 654     0x04075900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 655     0x04076900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 656     0x04077900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 657     0x04078900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 658     0x04079900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 659     0x0407A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 660     0x0407B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 661     0x0407C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 662     0x0407D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 663     0x0407E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
 664     0x0407F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW
 665     };
 666
 667 //{{ RobertYu:20050103, Channel 11a Number To Index
 668 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
 669 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
 670 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
 671
 672 const u8 RFaby11aChannelIndex[200] = {
 673   // 1   2   3   4   5   6   7   8   9  10
 674     00, 00, 00, 00, 00, 00, 23, 24, 25, 00,  // 10
 675     26, 27, 00, 00, 00, 28, 00, 00, 00, 00,  // 20
 676     00, 00, 00, 00, 00, 00, 00, 00, 00, 00,  // 30
 677     00, 00, 00, 29, 00, 30, 00, 31, 00, 32,  // 40
 678     00, 33, 00, 34, 00, 35, 00, 36, 00, 00,  // 50
 679     00, 37, 00, 00, 00, 38, 00, 00, 00, 39,  // 60
 680     00, 00, 00, 40, 00, 00, 00, 00, 00, 00,  // 70
 681     00, 00, 00, 00, 00, 00, 00, 00, 00, 00,  // 80
 682     00, 00, 00, 00, 00, 00, 00, 00, 00, 00,  // 90
 683     00, 00, 00, 00, 00, 00, 00, 00, 00, 41,  //100
 684
 685     00, 00, 00, 42, 00, 00, 00, 43, 00, 00,  //110
 686     00, 44, 00, 00, 00, 45, 00, 00, 00, 46,  //120
 687     00, 00, 00, 47, 00, 00, 00, 48, 00, 00,  //130
 688     00, 49, 00, 00, 00, 50, 00, 00, 00, 51,  //140
 689     00, 00, 00, 00, 00, 00, 00, 00, 52, 00,  //150
 690     00, 00, 53, 00, 00, 00, 54, 00, 00, 00,  //160
 691     55, 00, 00, 00, 56, 00, 00, 00, 00, 00,  //170
 692     00, 00, 00, 00, 00, 00, 00, 00, 00, 00,  //180
 693     00, 00, 15, 16, 17, 00, 18, 19, 20, 00,  //190
 694     00, 21, 00, 00, 00, 22, 00, 00, 00, 00   //200
 695 };
 696 //}} RobertYu
 697
 698 /*
 699  * Description: Write to IF/RF, by embedded programming
 700  *
 701  * Parameters:
 702  *  In:
 703  *      dwData      - data to write
 704  *  Out:
 705  *      none
 706  *
 707  * Return Value: true if succeeded; false if failed.
 708  *
 709  */
 710 int IFRFbWriteEmbedded(struct vnt_private *pDevice, u32 dwData)
 711 {
 712         u8 pbyData[4];
 713
 714         pbyData[0] = (u8)dwData;
 715         pbyData[1] = (u8)(dwData >> 8);
 716         pbyData[2] = (u8)(dwData >> 16);
 717         pbyData[3] = (u8)(dwData >> 24);
 718
 719         CONTROLnsRequestOut(pDevice,
 720                 MESSAGE_TYPE_WRITE_IFRF, 0, 0, 4, pbyData);
 721
 722         return true;
 723 }
 724
 725 /*
 726  * Description: Set Tx power
 727  *
 728  * Parameters:
 729  *  In:
 730  *      dwIoBase       - I/O base address
 731  *      dwRFPowerTable - RF Tx Power Setting
 732  *  Out:
 733  *      none
 734  *
 735  * Return Value: true if succeeded; false if failed.
 736  *
 737  */
 738 int RFbSetPower(struct vnt_private *priv, u32 rate, u32 channel)
 739 {
 740         int ret = true;
 741         u8 power = priv->byCCKPwr;
 742
 743         if (priv->dwDiagRefCount)
 744                 return true;
 745
 746         if (channel == 0)
 747                 return -EINVAL;
 748
 749         switch (rate) {
 750         case RATE_1M:
 751         case RATE_2M:
 752         case RATE_5M:
 753         case RATE_11M:
 754                 power = priv->abyCCKPwrTbl[channel-1];
 755                 break;
 756         case RATE_6M:
 757         case RATE_9M:
 758         case RATE_18M:
 759         case RATE_24M:
 760         case RATE_36M:
 761         case RATE_48M:
 762         case RATE_54M:
 763                 if (channel > CB_MAX_CHANNEL_24G)
 764                         power = priv->abyOFDMAPwrTbl[channel-15];
 765                 else
 766                         power = priv->abyOFDMPwrTbl[channel-1];
 767                 break;
 768         }
 769
 770         ret = RFbRawSetPower(priv, power, rate);
 771
 772         return ret;
 773 }
 774
 775 /*
 776  * Description: Set Tx power
 777  *
 778  * Parameters:
 779  *  In:
 780  *      dwIoBase       - I/O base address
 781  *      dwRFPowerTable - RF Tx Power Setting
 782  *  Out:
 783  *      none
 784  *
 785  * Return Value: true if succeeded; false if failed.
 786  *
 787  */
 788
 789 int RFbRawSetPower(struct vnt_private *priv, u8 power, u32 rate)
 790 {
 791         u32 power_setting = 0;
 792         int ret = true;
 793
 794         if (priv->byCurPwr == power)
 795                 return true;
 796
 797         priv->byCurPwr = power;
 798
 799         switch (priv->byRFType) {
 800         case RF_AL2230:
 801                 if (priv->byCurPwr >= AL2230_PWR_IDX_LEN)
 802                         return false;
 803
 804                 ret &= IFRFbWriteEmbedded(priv,
 805                         al2230_power_table[priv->byCurPwr]);
 806
 807                 if (rate <= RATE_11M)
 808                         ret &= IFRFbWriteEmbedded(priv, 0x0001b400 +
 809                                 (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
 810                 else
 811                         ret &= IFRFbWriteEmbedded(priv, 0x0005a400 +
 812                                 (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
 813                 break;
 814         case RF_AL2230S:
 815                 if (priv->byCurPwr >= AL2230_PWR_IDX_LEN)
 816                         return false;
 817
 818                 ret &= IFRFbWriteEmbedded(priv,
 819                         al2230_power_table[priv->byCurPwr]);
 820
 821                 if (rate <= RATE_11M) {
 822                         ret &= IFRFbWriteEmbedded(priv, 0x040c1400 +
 823                                 (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
 824                         ret &= IFRFbWriteEmbedded(priv, 0x00299b00 +
 825                                 (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
 826                 } else {
 827                         ret &= IFRFbWriteEmbedded(priv, 0x0005a400 +
 828                                 (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
 829                         ret &= IFRFbWriteEmbedded(priv, 0x00099b00 +
 830                                 (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
 831                 }
 832                 break;
 833
 834         case RF_AIROHA7230:
 835                 if (rate <= RATE_11M)
 836                         ret &= IFRFbWriteEmbedded(priv, 0x111bb900 +
 837                                 (BY_AL7230_REG_LEN << 3)+IFREGCTL_REGW);
 838                 else
 839                         ret &= IFRFbWriteEmbedded(priv, 0x221bb900 +
 840                                 (BY_AL7230_REG_LEN << 3)+IFREGCTL_REGW);
 841
 842                 if (priv->byCurPwr > AL7230_PWR_IDX_LEN)
 843                         return false;
 844
 845                 /*
 846                 * 0x080F1B00 for 3 wire control TxGain(D10)
 847                 * and 0x31 as TX Gain value
 848                 */
 849                 power_setting = 0x080c0b00 | ((priv->byCurPwr) << 12) |
 850                                 (BY_AL7230_REG_LEN << 3) | IFREGCTL_REGW;
 851
 852                 ret &= IFRFbWriteEmbedded(priv, power_setting);
 853
 854                 break;
 855
 856         case RF_VT3226:
 857                 if (priv->byCurPwr >= VT3226_PWR_IDX_LEN)
 858                         return false;
 859                 power_setting = ((0x3f - priv->byCurPwr) << 20) | (0x17 << 8) |
 860                                 (BY_VT3226_REG_LEN << 3) | IFREGCTL_REGW;
 861
 862                 ret &= IFRFbWriteEmbedded(priv, power_setting);
 863
 864                 break;
 865         case RF_VT3226D0:
 866                 if (priv->byCurPwr >= VT3226_PWR_IDX_LEN)
 867                         return false;
 868
 869                 if (rate <= RATE_11M) {
 870                         power_setting = ((0x3f-priv->byCurPwr) << 20) |
 871                                 (0xe07 << 8) | (BY_VT3226_REG_LEN << 3) |
 872                                                 IFREGCTL_REGW;
 873
 874                         ret &= IFRFbWriteEmbedded(priv, power_setting);
 875                         ret &= IFRFbWriteEmbedded(priv, 0x03c6a200 +
 876                                         (BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
 877
 878                         if (priv->vnt_mgmt.eScanState != WMAC_NO_SCANNING) {
 879                                 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO
 880                                 "RFbRawSetPower> 11B mode uCurrChannel[%d]\n",
 881                                                 priv->vnt_mgmt.uScanChannel);
 882                                 ret &= IFRFbWriteEmbedded(priv,
 883                                         vt3226d0_lo_current_table[priv->
 884                                                 vnt_mgmt.uScanChannel - 1]);
 885                         } else {
 886                                 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO
 887                                 "RFbRawSetPower> 11B mode uCurrChannel[%d]\n",
 888                                                 priv->vnt_mgmt.uCurrChannel);
 889                                 ret &= IFRFbWriteEmbedded(priv,
 890                                         vt3226d0_lo_current_table[priv->
 891                                                 vnt_mgmt.uCurrChannel - 1]);
 892                         }
 893
 894                         ret &= IFRFbWriteEmbedded(priv, 0x015C0800 +
 895                                 (BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
 896                 } else {
 897                         DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO
 898                                         "@@@@ RFbRawSetPower> 11G mode\n");
 899
 900                         power_setting = ((0x3f-priv->byCurPwr) << 20) |
 901                                 (0x7 << 8) | (BY_VT3226_REG_LEN << 3) |
 902                                         IFREGCTL_REGW;
 903
 904                         ret &= IFRFbWriteEmbedded(priv, power_setting);
 905                         ret &= IFRFbWriteEmbedded(priv, 0x00C6A200 +
 906                                 (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW);
 907                         ret &= IFRFbWriteEmbedded(priv, 0x016BC600 +
 908                                         (BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
 909                         ret &= IFRFbWriteEmbedded(priv, 0x00900800 +
 910                                         (BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
 911                 }
 912                 break;
 913
 914         case RF_VT3342A0:
 915                 if (priv->byCurPwr >= VT3342_PWR_IDX_LEN)
 916                         return false;
 917
 918                 power_setting =  ((0x3F-priv->byCurPwr) << 20) |
 919                         (0x27 << 8) | (BY_VT3342_REG_LEN << 3) |
 920                                         IFREGCTL_REGW;
 921
 922                 ret &= IFRFbWriteEmbedded(priv, power_setting);
 923
 924                 break;
 925         default:
 926                 break;
 927         }
 928         return ret;
 929 }
 930
 931 /*+
 932  *
 933  * Routine Description:
 934  *     Translate RSSI to dBm
 935  *
 936  * Parameters:
 937  *  In:
 938  *      pDevice         - The adapter to be translated
 939  *      byCurrRSSI      - RSSI to be translated
 940  *  Out:
 941  *      pdwdbm          - Translated dbm number
 942  *
 943  * Return Value: none
 944  *
 945 -*/
 946 void RFvRSSITodBm(struct vnt_private *priv, u8 rssi, long *dbm)
 947 {
 948         u8 idx = (((rssi & 0xc0) >> 6) & 0x03);
 949         long b = (rssi & 0x3f);
 950         long a = 0;
 951         u8 airoharf[4] = {0, 18, 0, 40};
 952
 953         switch (priv->byRFType) {
 954         case RF_AL2230:
 955         case RF_AL2230S:
 956         case RF_AIROHA7230:
 957         case RF_VT3226:
 958         case RF_VT3226D0:
 959         case RF_VT3342A0:
 960                 a = airoharf[idx];
 961                 break;
 962         default:
 963                 break;
 964         }
 965
 966         *dbm = -1 * (a + b * 2);
 967 }
 968
 969 void RFbRFTableDownload(struct vnt_private *priv)
 970 {
 971         u16 length1 = 0, length2 = 0, length3 = 0;
 972         u8 *addr1 = NULL, *addr2 = NULL, *addr3 = NULL;
 973         u16 length, value;
 974         u8 array[256];
 975
 976         switch (priv->byRFType) {
 977         case RF_AL2230:
 978         case RF_AL2230S:
 979                 length1 = CB_AL2230_INIT_SEQ * 3;
 980                 length2 = CB_MAX_CHANNEL_24G * 3;
 981                 length3 = CB_MAX_CHANNEL_24G * 3;
 982                 addr1 = &al2230_init_table[0][0];
 983                 addr2 = &al2230_channel_table0[0][0];
 984                 addr3 = &al2230_channel_table1[0][0];
 985                 break;
 986         case RF_AIROHA7230:
 987                 length1 = CB_AL7230_INIT_SEQ * 3;
 988                 length2 = CB_MAX_CHANNEL * 3;
 989                 length3 = CB_MAX_CHANNEL * 3;
 990                 addr1 = &al7230_init_table[0][0];
 991                 addr2 = &al7230_channel_table0[0][0];
 992                 addr3 = &al7230_channel_table1[0][0];
 993                 break;
 994         case RF_VT3226:
 995                 length1 = CB_VT3226_INIT_SEQ * 3;
 996                 length2 = CB_MAX_CHANNEL_24G * 3;
 997                 length3 = CB_MAX_CHANNEL_24G * 3;
 998                 addr1 = &at3226_init_table[0][0];
 999                 addr2 = &vt3226_channel_table0[0][0];
1000                 addr3 = &vt3226_channel_table1[0][0];
1001                 break;
1002         case RF_VT3226D0:
1003                 length1 = CB_VT3226_INIT_SEQ * 3;
1004                 length2 = CB_MAX_CHANNEL_24G * 3;
1005                 length3 = CB_MAX_CHANNEL_24G * 3;
1006                 addr1 = &at3226d0_init_table[0][0];
1007                 addr2 = &vt3226_channel_table0[0][0];
1008                 addr3 = &vt3226_channel_table1[0][0];
1009                 break;
1010         case RF_VT3342A0:
1011                 length1 = CB_VT3342_INIT_SEQ * 3;
1012                 length2 = CB_MAX_CHANNEL * 3;
1013                 length3 = CB_MAX_CHANNEL * 3;
1014                 addr1 = &vt3342a0_init_table[0][0];
1015                 addr2 = &vt3342_channel_table0[0][0];
1016                 addr3 = &vt3342_channel_table1[0][0];
1017                 break;
1018         }
1019
1020         /* Init Table */
1021         memcpy(array, addr1, length1);
1022
1023         CONTROLnsRequestOut(priv, MESSAGE_TYPE_WRITE, 0,
1024                 MESSAGE_REQUEST_RF_INIT, length1, array);
1025
1026         /* Channel Table 0 */
1027         value = 0;
1028         while (length2 > 0) {
1029                 if (length2 >= 64)
1030                         length = 64;
1031                 else
1032                         length = length2;
1033
1034                 memcpy(array, addr2, length);
1035
1036                 CONTROLnsRequestOut(priv, MESSAGE_TYPE_WRITE,
1037                         value, MESSAGE_REQUEST_RF_CH0, length, array);
1038
1039                 length2 -= length;
1040                 value += length;
1041                 addr2 += length;
1042         }
1043
1044         /* Channel table 1 */
1045         value = 0;
1046         while (length3 > 0) {
1047                 if (length3 >= 64)
1048                         length = 64;
1049                 else
1050                         length = length3;
1051
1052                 memcpy(array, addr3, length);
1053
1054                 CONTROLnsRequestOut(priv, MESSAGE_TYPE_WRITE,
1055                         value, MESSAGE_REQUEST_RF_CH1, length, array);
1056
1057                 length3 -= length;
1058                 value += length;
1059                 addr3 += length;
1060         }
1061
1062         if (priv->byRFType == RF_AIROHA7230) {
1063                 length1 = CB_AL7230_INIT_SEQ * 3;
1064                 length2 = CB_MAX_CHANNEL * 3;
1065                 addr1 = &(al7230_init_table_amode[0][0]);
1066                 addr2 = &(al7230_channel_table2[0][0]);
1067
1068                 memcpy(array, addr1, length1);
1069
1070                 /* Init Table 2 */
1071                 CONTROLnsRequestOut(priv, MESSAGE_TYPE_WRITE,
1072                         0, MESSAGE_REQUEST_RF_INIT2, length1, array);
1073
1074                 /* Channel Table 0 */
1075                 value = 0;
1076                 while (length2 > 0) {
1077                         if (length2 >= 64)
1078                                 length = 64;
1079                         else
1080                                 length = length2;
1081
1082                         memcpy(array, addr2, length);
1083
1084                         CONTROLnsRequestOut(priv, MESSAGE_TYPE_WRITE,
1085                                 value, MESSAGE_REQUEST_RF_CH2, length, array);
1086
1087                         length2 -= length;
1088                         value += length;
1089                         addr2 += length;
1090                 }
1091         }
1092 }