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Merge branch 'bpf-Allow-selecting-numa-node-during-map-creation'
[linux-2.6/btrfs-unstable.git] / drivers / hwmon / nct6775.c
blobc219e43b8f026faa69e4617cecc2b31e7449a064
1 /*
2 * nct6775 - Driver for the hardware monitoring functionality of
3 * Nuvoton NCT677x Super-I/O chips
4 *
5 * Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net>
6 *
7 * Derived from w83627ehf driver
8 * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
9 * Copyright (C) 2006 Yuan Mu (Winbond),
10 * Rudolf Marek <r.marek@assembler.cz>
11 * David Hubbard <david.c.hubbard@gmail.com>
12 * Daniel J Blueman <daniel.blueman@gmail.com>
13 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
14 *
15 * Shamelessly ripped from the w83627hf driver
16 * Copyright (C) 2003 Mark Studebaker
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 *
32 *
33 * Supports the following chips:
34 *
35 * Chip #vin #fan #pwm #temp chip IDs man ID
36 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
37 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
38 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
39 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
40 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
41 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
42 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
43 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
44 *
45 *
46 * #temp lists the number of monitored temperature sources (first value) plus
47 * the number of directly connectable temperature sensors (second value).
48 */
49
50 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
51
52 #include <linux/module.h>
53 #include <linux/init.h>
54 #include <linux/slab.h>
55 #include <linux/jiffies.h>
56 #include <linux/platform_device.h>
57 #include <linux/hwmon.h>
58 #include <linux/hwmon-sysfs.h>
59 #include <linux/hwmon-vid.h>
60 #include <linux/err.h>
61 #include <linux/mutex.h>
62 #include <linux/acpi.h>
63 #include <linux/bitops.h>
64 #include <linux/dmi.h>
65 #include <linux/io.h>
66 #include "lm75.h"
67
68 #define USE_ALTERNATE
69
70 enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
71 nct6795 };
72
73 /* used to set data->name = nct6775_device_names[data->sio_kind] */
74 static const char * const nct6775_device_names[] = {
75 "nct6106",
76 "nct6775",
77 "nct6776",
78 "nct6779",
79 "nct6791",
80 "nct6792",
81 "nct6793",
82 "nct6795",
83 };
84
85 static const char * const nct6775_sio_names[] __initconst = {
86 "NCT6106D",
87 "NCT6775F",
88 "NCT6776D/F",
89 "NCT6779D",
90 "NCT6791D",
91 "NCT6792D",
92 "NCT6793D",
93 "NCT6795D",
94 };
95
96 static unsigned short force_id;
97 module_param(force_id, ushort, 0);
98 MODULE_PARM_DESC(force_id, "Override the detected device ID");
99
100 static unsigned short fan_debounce;
101 module_param(fan_debounce, ushort, 0);
102 MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
103
104 #define DRVNAME "nct6775"
105
106 /*
107 * Super-I/O constants and functions
108 */
109
110 #define NCT6775_LD_ACPI 0x0a
111 #define NCT6775_LD_HWM 0x0b
112 #define NCT6775_LD_VID 0x0d
113 #define NCT6775_LD_12 0x12
114
115 #define SIO_REG_LDSEL 0x07 /* Logical device select */
116 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
117 #define SIO_REG_ENABLE 0x30 /* Logical device enable */
118 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
119
120 #define SIO_NCT6106_ID 0xc450
121 #define SIO_NCT6775_ID 0xb470
122 #define SIO_NCT6776_ID 0xc330
123 #define SIO_NCT6779_ID 0xc560
124 #define SIO_NCT6791_ID 0xc800
125 #define SIO_NCT6792_ID 0xc910
126 #define SIO_NCT6793_ID 0xd120
127 #define SIO_NCT6795_ID 0xd350
128 #define SIO_ID_MASK 0xFFF0
129
130 enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
131
132 static inline void
133 superio_outb(int ioreg, int reg, int val)
134 {
135 outb(reg, ioreg);
136 outb(val, ioreg + 1);
137 }
138
139 static inline int
140 superio_inb(int ioreg, int reg)
141 {
142 outb(reg, ioreg);
143 return inb(ioreg + 1);
144 }
145
146 static inline void
147 superio_select(int ioreg, int ld)
148 {
149 outb(SIO_REG_LDSEL, ioreg);
150 outb(ld, ioreg + 1);
151 }
152
153 static inline int
154 superio_enter(int ioreg)
155 {
156 /*
157 * Try to reserve <ioreg> and <ioreg + 1> for exclusive access.
158 */
159 if (!request_muxed_region(ioreg, 2, DRVNAME))
160 return -EBUSY;
161
162 outb(0x87, ioreg);
163 outb(0x87, ioreg);
164
165 return 0;
166 }
167
168 static inline void
169 superio_exit(int ioreg)
170 {
171 outb(0xaa, ioreg);
172 outb(0x02, ioreg);
173 outb(0x02, ioreg + 1);
174 release_region(ioreg, 2);
175 }
176
177 /*
178 * ISA constants
179 */
180
181 #define IOREGION_ALIGNMENT (~7)
182 #define IOREGION_OFFSET 5
183 #define IOREGION_LENGTH 2
184 #define ADDR_REG_OFFSET 0
185 #define DATA_REG_OFFSET 1
186
187 #define NCT6775_REG_BANK 0x4E
188 #define NCT6775_REG_CONFIG 0x40
189
190 /*
191 * Not currently used:
192 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
193 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
194 * REG_MAN_ID is at port 0x4f
195 * REG_CHIP_ID is at port 0x58
196 */
197
198 #define NUM_TEMP 10 /* Max number of temp attribute sets w/ limits*/
199 #define NUM_TEMP_FIXED 6 /* Max number of fixed temp attribute sets */
200
201 #define NUM_REG_ALARM 7 /* Max number of alarm registers */
202 #define NUM_REG_BEEP 5 /* Max number of beep registers */
203
204 #define NUM_FAN 6
205
206 #define TEMP_SOURCE_VIRTUAL 0x1f
207
208 /* Common and NCT6775 specific data */
209
210 /* Voltage min/max registers for nr=7..14 are in bank 5 */
211
212 static const u16 NCT6775_REG_IN_MAX[] = {
213 0x2b, 0x2d, 0x2f, 0x31, 0x33, 0x35, 0x37, 0x554, 0x556, 0x558, 0x55a,
214 0x55c, 0x55e, 0x560, 0x562 };
215 static const u16 NCT6775_REG_IN_MIN[] = {
216 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x555, 0x557, 0x559, 0x55b,
217 0x55d, 0x55f, 0x561, 0x563 };
218 static const u16 NCT6775_REG_IN[] = {
219 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x550, 0x551, 0x552
220 };
221
222 #define NCT6775_REG_VBAT 0x5D
223 #define NCT6775_REG_DIODE 0x5E
224 #define NCT6775_DIODE_MASK 0x02
225
226 #define NCT6775_REG_FANDIV1 0x506
227 #define NCT6775_REG_FANDIV2 0x507
228
229 #define NCT6775_REG_CR_FAN_DEBOUNCE 0xf0
230
231 static const u16 NCT6775_REG_ALARM[NUM_REG_ALARM] = { 0x459, 0x45A, 0x45B };
232
233 /* 0..15 voltages, 16..23 fans, 24..29 temperatures, 30..31 intrusion */
234
235 static const s8 NCT6775_ALARM_BITS[] = {
236 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
237 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
238 -1, /* unused */
239 6, 7, 11, -1, -1, /* fan1..fan5 */
240 -1, -1, -1, /* unused */
241 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
242 12, -1 }; /* intrusion0, intrusion1 */
243
244 #define FAN_ALARM_BASE 16
245 #define TEMP_ALARM_BASE 24
246 #define INTRUSION_ALARM_BASE 30
247
248 static const u16 NCT6775_REG_BEEP[NUM_REG_BEEP] = { 0x56, 0x57, 0x453, 0x4e };
249
250 /*
251 * 0..14 voltages, 15 global beep enable, 16..23 fans, 24..29 temperatures,
252 * 30..31 intrusion
253 */
254 static const s8 NCT6775_BEEP_BITS[] = {
255 0, 1, 2, 3, 8, 9, 10, 16, /* in0.. in7 */
256 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
257 21, /* global beep enable */
258 6, 7, 11, 28, -1, /* fan1..fan5 */
259 -1, -1, -1, /* unused */
260 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
261 12, -1 }; /* intrusion0, intrusion1 */
262
263 #define BEEP_ENABLE_BASE 15
264
265 static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee };
266 static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 };
267
268 /* DC or PWM output fan configuration */
269 static const u8 NCT6775_REG_PWM_MODE[] = { 0x04, 0x04, 0x12 };
270 static const u8 NCT6775_PWM_MODE_MASK[] = { 0x01, 0x02, 0x01 };
271
272 /* Advanced Fan control, some values are common for all fans */
273
274 static const u16 NCT6775_REG_TARGET[] = {
275 0x101, 0x201, 0x301, 0x801, 0x901, 0xa01 };
276 static const u16 NCT6775_REG_FAN_MODE[] = {
277 0x102, 0x202, 0x302, 0x802, 0x902, 0xa02 };
278 static const u16 NCT6775_REG_FAN_STEP_DOWN_TIME[] = {
279 0x103, 0x203, 0x303, 0x803, 0x903, 0xa03 };
280 static const u16 NCT6775_REG_FAN_STEP_UP_TIME[] = {
281 0x104, 0x204, 0x304, 0x804, 0x904, 0xa04 };
282 static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = {
283 0x105, 0x205, 0x305, 0x805, 0x905, 0xa05 };
284 static const u16 NCT6775_REG_FAN_START_OUTPUT[] = {
285 0x106, 0x206, 0x306, 0x806, 0x906, 0xa06 };
286 static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
287 static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
288
289 static const u16 NCT6775_REG_FAN_STOP_TIME[] = {
290 0x107, 0x207, 0x307, 0x807, 0x907, 0xa07 };
291 static const u16 NCT6775_REG_PWM[] = {
292 0x109, 0x209, 0x309, 0x809, 0x909, 0xa09 };
293 static const u16 NCT6775_REG_PWM_READ[] = {
294 0x01, 0x03, 0x11, 0x13, 0x15, 0xa09 };
295
296 static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
297 static const u16 NCT6775_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d };
298 static const u16 NCT6775_REG_FAN_PULSES[] = { 0x641, 0x642, 0x643, 0x644, 0 };
299 static const u16 NCT6775_FAN_PULSE_SHIFT[] = { 0, 0, 0, 0, 0, 0 };
300
301 static const u16 NCT6775_REG_TEMP[] = {
302 0x27, 0x150, 0x250, 0x62b, 0x62c, 0x62d };
303
304 static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77 };
305
306 static const u16 NCT6775_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
307 0, 0x152, 0x252, 0x628, 0x629, 0x62A };
308 static const u16 NCT6775_REG_TEMP_HYST[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
309 0x3a, 0x153, 0x253, 0x673, 0x678, 0x67D };
310 static const u16 NCT6775_REG_TEMP_OVER[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
311 0x39, 0x155, 0x255, 0x672, 0x677, 0x67C };
312
313 static const u16 NCT6775_REG_TEMP_SOURCE[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
314 0x621, 0x622, 0x623, 0x624, 0x625, 0x626 };
315
316 static const u16 NCT6775_REG_TEMP_SEL[] = {
317 0x100, 0x200, 0x300, 0x800, 0x900, 0xa00 };
318
319 static const u16 NCT6775_REG_WEIGHT_TEMP_SEL[] = {
320 0x139, 0x239, 0x339, 0x839, 0x939, 0xa39 };
321 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP[] = {
322 0x13a, 0x23a, 0x33a, 0x83a, 0x93a, 0xa3a };
323 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP_TOL[] = {
324 0x13b, 0x23b, 0x33b, 0x83b, 0x93b, 0xa3b };
325 static const u16 NCT6775_REG_WEIGHT_DUTY_STEP[] = {
326 0x13c, 0x23c, 0x33c, 0x83c, 0x93c, 0xa3c };
327 static const u16 NCT6775_REG_WEIGHT_TEMP_BASE[] = {
328 0x13d, 0x23d, 0x33d, 0x83d, 0x93d, 0xa3d };
329
330 static const u16 NCT6775_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
331
332 static const u16 NCT6775_REG_AUTO_TEMP[] = {
333 0x121, 0x221, 0x321, 0x821, 0x921, 0xa21 };
334 static const u16 NCT6775_REG_AUTO_PWM[] = {
335 0x127, 0x227, 0x327, 0x827, 0x927, 0xa27 };
336
337 #define NCT6775_AUTO_TEMP(data, nr, p) ((data)->REG_AUTO_TEMP[nr] + (p))
338 #define NCT6775_AUTO_PWM(data, nr, p) ((data)->REG_AUTO_PWM[nr] + (p))
339
340 static const u16 NCT6775_REG_CRITICAL_ENAB[] = { 0x134, 0x234, 0x334 };
341
342 static const u16 NCT6775_REG_CRITICAL_TEMP[] = {
343 0x135, 0x235, 0x335, 0x835, 0x935, 0xa35 };
344 static const u16 NCT6775_REG_CRITICAL_TEMP_TOLERANCE[] = {
345 0x138, 0x238, 0x338, 0x838, 0x938, 0xa38 };
346
347 static const char *const nct6775_temp_label[] = {
348 "",
349 "SYSTIN",
350 "CPUTIN",
351 "AUXTIN",
352 "AMD SB-TSI",
353 "PECI Agent 0",
354 "PECI Agent 1",
355 "PECI Agent 2",
356 "PECI Agent 3",
357 "PECI Agent 4",
358 "PECI Agent 5",
359 "PECI Agent 6",
360 "PECI Agent 7",
361 "PCH_CHIP_CPU_MAX_TEMP",
362 "PCH_CHIP_TEMP",
363 "PCH_CPU_TEMP",
364 "PCH_MCH_TEMP",
365 "PCH_DIM0_TEMP",
366 "PCH_DIM1_TEMP",
367 "PCH_DIM2_TEMP",
368 "PCH_DIM3_TEMP"
369 };
370
371 #define NCT6775_TEMP_MASK 0x001ffffe
372
373 static const u16 NCT6775_REG_TEMP_ALTERNATE[32] = {
374 [13] = 0x661,
375 [14] = 0x662,
376 [15] = 0x664,
377 };
378
379 static const u16 NCT6775_REG_TEMP_CRIT[32] = {
380 [4] = 0xa00,
381 [5] = 0xa01,
382 [6] = 0xa02,
383 [7] = 0xa03,
384 [8] = 0xa04,
385 [9] = 0xa05,
386 [10] = 0xa06,
387 [11] = 0xa07
388 };
389
390 /* NCT6776 specific data */
391
392 /* STEP_UP_TIME and STEP_DOWN_TIME regs are swapped for all chips but NCT6775 */
393 #define NCT6776_REG_FAN_STEP_UP_TIME NCT6775_REG_FAN_STEP_DOWN_TIME
394 #define NCT6776_REG_FAN_STEP_DOWN_TIME NCT6775_REG_FAN_STEP_UP_TIME
395
396 static const s8 NCT6776_ALARM_BITS[] = {
397 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
398 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
399 -1, /* unused */
400 6, 7, 11, 10, 23, /* fan1..fan5 */
401 -1, -1, -1, /* unused */
402 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
403 12, 9 }; /* intrusion0, intrusion1 */
404
405 static const u16 NCT6776_REG_BEEP[NUM_REG_BEEP] = { 0xb2, 0xb3, 0xb4, 0xb5 };
406
407 static const s8 NCT6776_BEEP_BITS[] = {
408 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
409 8, -1, -1, -1, -1, -1, -1, /* in8..in14 */
410 24, /* global beep enable */
411 25, 26, 27, 28, 29, /* fan1..fan5 */
412 -1, -1, -1, /* unused */
413 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
414 30, 31 }; /* intrusion0, intrusion1 */
415
416 static const u16 NCT6776_REG_TOLERANCE_H[] = {
417 0x10c, 0x20c, 0x30c, 0x80c, 0x90c, 0xa0c };
418
419 static const u8 NCT6776_REG_PWM_MODE[] = { 0x04, 0, 0, 0, 0, 0 };
420 static const u8 NCT6776_PWM_MODE_MASK[] = { 0x01, 0, 0, 0, 0, 0 };
421
422 static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642 };
423 static const u16 NCT6776_REG_FAN_PULSES[] = { 0x644, 0x645, 0x646, 0, 0 };
424
425 static const u16 NCT6776_REG_WEIGHT_DUTY_BASE[] = {
426 0x13e, 0x23e, 0x33e, 0x83e, 0x93e, 0xa3e };
427
428 static const u16 NCT6776_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
429 0x18, 0x152, 0x252, 0x628, 0x629, 0x62A };
430
431 static const char *const nct6776_temp_label[] = {
432 "",
433 "SYSTIN",
434 "CPUTIN",
435 "AUXTIN",
436 "SMBUSMASTER 0",
437 "SMBUSMASTER 1",
438 "SMBUSMASTER 2",
439 "SMBUSMASTER 3",
440 "SMBUSMASTER 4",
441 "SMBUSMASTER 5",
442 "SMBUSMASTER 6",
443 "SMBUSMASTER 7",
444 "PECI Agent 0",
445 "PECI Agent 1",
446 "PCH_CHIP_CPU_MAX_TEMP",
447 "PCH_CHIP_TEMP",
448 "PCH_CPU_TEMP",
449 "PCH_MCH_TEMP",
450 "PCH_DIM0_TEMP",
451 "PCH_DIM1_TEMP",
452 "PCH_DIM2_TEMP",
453 "PCH_DIM3_TEMP",
454 "BYTE_TEMP"
455 };
456
457 #define NCT6776_TEMP_MASK 0x007ffffe
458
459 static const u16 NCT6776_REG_TEMP_ALTERNATE[32] = {
460 [14] = 0x401,
461 [15] = 0x402,
462 [16] = 0x404,
463 };
464
465 static const u16 NCT6776_REG_TEMP_CRIT[32] = {
466 [11] = 0x709,
467 [12] = 0x70a,
468 };
469
470 /* NCT6779 specific data */
471
472 static const u16 NCT6779_REG_IN[] = {
473 0x480, 0x481, 0x482, 0x483, 0x484, 0x485, 0x486, 0x487,
474 0x488, 0x489, 0x48a, 0x48b, 0x48c, 0x48d, 0x48e };
475
476 static const u16 NCT6779_REG_ALARM[NUM_REG_ALARM] = {
477 0x459, 0x45A, 0x45B, 0x568 };
478
479 static const s8 NCT6779_ALARM_BITS[] = {
480 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
481 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
482 -1, /* unused */
483 6, 7, 11, 10, 23, /* fan1..fan5 */
484 -1, -1, -1, /* unused */
485 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
486 12, 9 }; /* intrusion0, intrusion1 */
487
488 static const s8 NCT6779_BEEP_BITS[] = {
489 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
490 8, 9, 10, 11, 12, 13, 14, /* in8..in14 */
491 24, /* global beep enable */
492 25, 26, 27, 28, 29, /* fan1..fan5 */
493 -1, -1, -1, /* unused */
494 16, 17, -1, -1, -1, -1, /* temp1..temp6 */
495 30, 31 }; /* intrusion0, intrusion1 */
496
497 static const u16 NCT6779_REG_FAN[] = {
498 0x4b0, 0x4b2, 0x4b4, 0x4b6, 0x4b8, 0x4ba };
499 static const u16 NCT6779_REG_FAN_PULSES[] = {
500 0x644, 0x645, 0x646, 0x647, 0x648, 0x649 };
501
502 static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = {
503 0x136, 0x236, 0x336, 0x836, 0x936, 0xa36 };
504 #define NCT6779_CRITICAL_PWM_ENABLE_MASK 0x01
505 static const u16 NCT6779_REG_CRITICAL_PWM[] = {
506 0x137, 0x237, 0x337, 0x837, 0x937, 0xa37 };
507
508 static const u16 NCT6779_REG_TEMP[] = { 0x27, 0x150 };
509 static const u16 NCT6779_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b };
510 static const u16 NCT6779_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
511 0x18, 0x152 };
512 static const u16 NCT6779_REG_TEMP_HYST[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
513 0x3a, 0x153 };
514 static const u16 NCT6779_REG_TEMP_OVER[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
515 0x39, 0x155 };
516
517 static const u16 NCT6779_REG_TEMP_OFFSET[] = {
518 0x454, 0x455, 0x456, 0x44a, 0x44b, 0x44c };
519
520 static const char *const nct6779_temp_label[] = {
521 "",
522 "SYSTIN",
523 "CPUTIN",
524 "AUXTIN0",
525 "AUXTIN1",
526 "AUXTIN2",
527 "AUXTIN3",
528 "",
529 "SMBUSMASTER 0",
530 "SMBUSMASTER 1",
531 "SMBUSMASTER 2",
532 "SMBUSMASTER 3",
533 "SMBUSMASTER 4",
534 "SMBUSMASTER 5",
535 "SMBUSMASTER 6",
536 "SMBUSMASTER 7",
537 "PECI Agent 0",
538 "PECI Agent 1",
539 "PCH_CHIP_CPU_MAX_TEMP",
540 "PCH_CHIP_TEMP",
541 "PCH_CPU_TEMP",
542 "PCH_MCH_TEMP",
543 "PCH_DIM0_TEMP",
544 "PCH_DIM1_TEMP",
545 "PCH_DIM2_TEMP",
546 "PCH_DIM3_TEMP",
547 "BYTE_TEMP",
548 "",
549 "",
550 "",
551 "",
552 "Virtual_TEMP"
553 };
554
555 #define NCT6779_TEMP_MASK 0x07ffff7e
556 #define NCT6791_TEMP_MASK 0x87ffff7e
557
558 static const u16 NCT6779_REG_TEMP_ALTERNATE[32]
559 = { 0x490, 0x491, 0x492, 0x493, 0x494, 0x495, 0, 0,
560 0, 0, 0, 0, 0, 0, 0, 0,
561 0, 0x400, 0x401, 0x402, 0x404, 0x405, 0x406, 0x407,
562 0x408, 0 };
563
564 static const u16 NCT6779_REG_TEMP_CRIT[32] = {
565 [15] = 0x709,
566 [16] = 0x70a,
567 };
568
569 /* NCT6791 specific data */
570
571 #define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28
572
573 static const u16 NCT6791_REG_WEIGHT_TEMP_SEL[6] = { 0, 0x239 };
574 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP[6] = { 0, 0x23a };
575 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP_TOL[6] = { 0, 0x23b };
576 static const u16 NCT6791_REG_WEIGHT_DUTY_STEP[6] = { 0, 0x23c };
577 static const u16 NCT6791_REG_WEIGHT_TEMP_BASE[6] = { 0, 0x23d };
578 static const u16 NCT6791_REG_WEIGHT_DUTY_BASE[6] = { 0, 0x23e };
579
580 static const u16 NCT6791_REG_ALARM[NUM_REG_ALARM] = {
581 0x459, 0x45A, 0x45B, 0x568, 0x45D };
582
583 static const s8 NCT6791_ALARM_BITS[] = {
584 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
585 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
586 -1, /* unused */
587 6, 7, 11, 10, 23, 33, /* fan1..fan6 */
588 -1, -1, /* unused */
589 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
590 12, 9 }; /* intrusion0, intrusion1 */
591
592 /* NCT6792/NCT6793 specific data */
593
594 static const u16 NCT6792_REG_TEMP_MON[] = {
595 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d };
596 static const u16 NCT6792_REG_BEEP[NUM_REG_BEEP] = {
597 0xb2, 0xb3, 0xb4, 0xb5, 0xbf };
598
599 static const char *const nct6792_temp_label[] = {
600 "",
601 "SYSTIN",
602 "CPUTIN",
603 "AUXTIN0",
604 "AUXTIN1",
605 "AUXTIN2",
606 "AUXTIN3",
607 "",
608 "SMBUSMASTER 0",
609 "SMBUSMASTER 1",
610 "SMBUSMASTER 2",
611 "SMBUSMASTER 3",
612 "SMBUSMASTER 4",
613 "SMBUSMASTER 5",
614 "SMBUSMASTER 6",
615 "SMBUSMASTER 7",
616 "PECI Agent 0",
617 "PECI Agent 1",
618 "PCH_CHIP_CPU_MAX_TEMP",
619 "PCH_CHIP_TEMP",
620 "PCH_CPU_TEMP",
621 "PCH_MCH_TEMP",
622 "PCH_DIM0_TEMP",
623 "PCH_DIM1_TEMP",
624 "PCH_DIM2_TEMP",
625 "PCH_DIM3_TEMP",
626 "BYTE_TEMP",
627 "PECI Agent 0 Calibration",
628 "PECI Agent 1 Calibration",
629 "",
630 "",
631 "Virtual_TEMP"
632 };
633
634 #define NCT6792_TEMP_MASK 0x9fffff7e
635
636 static const char *const nct6793_temp_label[] = {
637 "",
638 "SYSTIN",
639 "CPUTIN",
640 "AUXTIN0",
641 "AUXTIN1",
642 "AUXTIN2",
643 "AUXTIN3",
644 "",
645 "SMBUSMASTER 0",
646 "SMBUSMASTER 1",
647 "",
648 "",
649 "",
650 "",
651 "",
652 "",
653 "PECI Agent 0",
654 "PECI Agent 1",
655 "PCH_CHIP_CPU_MAX_TEMP",
656 "PCH_CHIP_TEMP",
657 "PCH_CPU_TEMP",
658 "PCH_MCH_TEMP",
659 "Agent0 Dimm0 ",
660 "Agent0 Dimm1",
661 "Agent1 Dimm0",
662 "Agent1 Dimm1",
663 "BYTE_TEMP0",
664 "BYTE_TEMP1",
665 "PECI Agent 0 Calibration",
666 "PECI Agent 1 Calibration",
667 "",
668 "Virtual_TEMP"
669 };
670
671 #define NCT6793_TEMP_MASK 0xbfff037e
672
673 static const char *const nct6795_temp_label[] = {
674 "",
675 "SYSTIN",
676 "CPUTIN",
677 "AUXTIN0",
678 "AUXTIN1",
679 "AUXTIN2",
680 "AUXTIN3",
681 "",
682 "SMBUSMASTER 0",
683 "SMBUSMASTER 1",
684 "SMBUSMASTER 2",
685 "SMBUSMASTER 3",
686 "SMBUSMASTER 4",
687 "SMBUSMASTER 5",
688 "SMBUSMASTER 6",
689 "SMBUSMASTER 7",
690 "PECI Agent 0",
691 "PECI Agent 1",
692 "PCH_CHIP_CPU_MAX_TEMP",
693 "PCH_CHIP_TEMP",
694 "PCH_CPU_TEMP",
695 "PCH_MCH_TEMP",
696 "PCH_DIM0_TEMP",
697 "PCH_DIM1_TEMP",
698 "PCH_DIM2_TEMP",
699 "PCH_DIM3_TEMP",
700 "BYTE_TEMP0",
701 "BYTE_TEMP1",
702 "PECI Agent 0 Calibration",
703 "PECI Agent 1 Calibration",
704 "",
705 "Virtual_TEMP"
706 };
707
708 #define NCT6795_TEMP_MASK 0xbfffff7e
709
710 /* NCT6102D/NCT6106D specific data */
711
712 #define NCT6106_REG_VBAT 0x318
713 #define NCT6106_REG_DIODE 0x319
714 #define NCT6106_DIODE_MASK 0x01
715
716 static const u16 NCT6106_REG_IN_MAX[] = {
717 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9e, 0xa0, 0xa2 };
718 static const u16 NCT6106_REG_IN_MIN[] = {
719 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9f, 0xa1, 0xa3 };
720 static const u16 NCT6106_REG_IN[] = {
721 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09 };
722
723 static const u16 NCT6106_REG_TEMP[] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 };
724 static const u16 NCT6106_REG_TEMP_MON[] = { 0x18, 0x19, 0x1a };
725 static const u16 NCT6106_REG_TEMP_HYST[] = {
726 0xc3, 0xc7, 0xcb, 0xcf, 0xd3, 0xd7 };
727 static const u16 NCT6106_REG_TEMP_OVER[] = {
728 0xc2, 0xc6, 0xca, 0xce, 0xd2, 0xd6 };
729 static const u16 NCT6106_REG_TEMP_CRIT_L[] = {
730 0xc0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4 };
731 static const u16 NCT6106_REG_TEMP_CRIT_H[] = {
732 0xc1, 0xc5, 0xc9, 0xcf, 0xd1, 0xd5 };
733 static const u16 NCT6106_REG_TEMP_OFFSET[] = { 0x311, 0x312, 0x313 };
734 static const u16 NCT6106_REG_TEMP_CONFIG[] = {
735 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc };
736
737 static const u16 NCT6106_REG_FAN[] = { 0x20, 0x22, 0x24 };
738 static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 };
739 static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6, 0, 0 };
740 static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4, 0, 0 };
741
742 static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 };
743 static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 };
744 static const u16 NCT6106_REG_PWM[] = { 0x119, 0x129, 0x139 };
745 static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c };
746 static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 };
747 static const u16 NCT6106_REG_TEMP_SEL[] = { 0x110, 0x120, 0x130 };
748 static const u16 NCT6106_REG_TEMP_SOURCE[] = {
749 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 };
750
751 static const u16 NCT6106_REG_CRITICAL_TEMP[] = { 0x11a, 0x12a, 0x13a };
752 static const u16 NCT6106_REG_CRITICAL_TEMP_TOLERANCE[] = {
753 0x11b, 0x12b, 0x13b };
754
755 static const u16 NCT6106_REG_CRITICAL_PWM_ENABLE[] = { 0x11c, 0x12c, 0x13c };
756 #define NCT6106_CRITICAL_PWM_ENABLE_MASK 0x10
757 static const u16 NCT6106_REG_CRITICAL_PWM[] = { 0x11d, 0x12d, 0x13d };
758
759 static const u16 NCT6106_REG_FAN_STEP_UP_TIME[] = { 0x114, 0x124, 0x134 };
760 static const u16 NCT6106_REG_FAN_STEP_DOWN_TIME[] = { 0x115, 0x125, 0x135 };
761 static const u16 NCT6106_REG_FAN_STOP_OUTPUT[] = { 0x116, 0x126, 0x136 };
762 static const u16 NCT6106_REG_FAN_START_OUTPUT[] = { 0x117, 0x127, 0x137 };
763 static const u16 NCT6106_REG_FAN_STOP_TIME[] = { 0x118, 0x128, 0x138 };
764 static const u16 NCT6106_REG_TOLERANCE_H[] = { 0x112, 0x122, 0x132 };
765
766 static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 };
767
768 static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 };
769 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 };
770 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a };
771 static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x17c };
772 static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c };
773 static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d };
774
775 static const u16 NCT6106_REG_AUTO_TEMP[] = { 0x160, 0x170, 0x180 };
776 static const u16 NCT6106_REG_AUTO_PWM[] = { 0x164, 0x174, 0x184 };
777
778 static const u16 NCT6106_REG_ALARM[NUM_REG_ALARM] = {
779 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d };
780
781 static const s8 NCT6106_ALARM_BITS[] = {
782 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
783 9, -1, -1, -1, -1, -1, -1, /* in8..in14 */
784 -1, /* unused */
785 32, 33, 34, -1, -1, /* fan1..fan5 */
786 -1, -1, -1, /* unused */
787 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
788 48, -1 /* intrusion0, intrusion1 */
789 };
790
791 static const u16 NCT6106_REG_BEEP[NUM_REG_BEEP] = {
792 0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4 };
793
794 static const s8 NCT6106_BEEP_BITS[] = {
795 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
796 9, 10, 11, 12, -1, -1, -1, /* in8..in14 */
797 32, /* global beep enable */
798 24, 25, 26, 27, 28, /* fan1..fan5 */
799 -1, -1, -1, /* unused */
800 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
801 34, -1 /* intrusion0, intrusion1 */
802 };
803
804 static const u16 NCT6106_REG_TEMP_ALTERNATE[32] = {
805 [14] = 0x51,
806 [15] = 0x52,
807 [16] = 0x54,
808 };
809
810 static const u16 NCT6106_REG_TEMP_CRIT[32] = {
811 [11] = 0x204,
812 [12] = 0x205,
813 };
814
815 static enum pwm_enable reg_to_pwm_enable(int pwm, int mode)
816 {
817 if (mode == 0 && pwm == 255)
818 return off;
819 return mode + 1;
820 }
821
822 static int pwm_enable_to_reg(enum pwm_enable mode)
823 {
824 if (mode == off)
825 return 0;
826 return mode - 1;
827 }
828
829 /*
830 * Conversions
831 */
832
833 /* 1 is DC mode, output in ms */
834 static unsigned int step_time_from_reg(u8 reg, u8 mode)
835 {
836 return mode ? 400 * reg : 100 * reg;
837 }
838
839 static u8 step_time_to_reg(unsigned int msec, u8 mode)
840 {
841 return clamp_val((mode ? (msec + 200) / 400 :
842 (msec + 50) / 100), 1, 255);
843 }
844
845 static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
846 {
847 if (reg == 0 || reg == 255)
848 return 0;
849 return 1350000U / (reg << divreg);
850 }
851
852 static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
853 {
854 if ((reg & 0xff1f) == 0xff1f)
855 return 0;
856
857 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
858
859 if (reg == 0)
860 return 0;
861
862 return 1350000U / reg;
863 }
864
865 static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
866 {
867 if (reg == 0 || reg == 0xffff)
868 return 0;
869
870 /*
871 * Even though the registers are 16 bit wide, the fan divisor
872 * still applies.
873 */
874 return 1350000U / (reg << divreg);
875 }
876
877 static u16 fan_to_reg(u32 fan, unsigned int divreg)
878 {
879 if (!fan)
880 return 0;
881
882 return (1350000U / fan) >> divreg;
883 }
884
885 static inline unsigned int
886 div_from_reg(u8 reg)
887 {
888 return BIT(reg);
889 }
890
891 /*
892 * Some of the voltage inputs have internal scaling, the tables below
893 * contain 8 (the ADC LSB in mV) * scaling factor * 100
894 */
895 static const u16 scale_in[15] = {
896 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800, 800, 800, 800,
897 800, 800
898 };
899
900 static inline long in_from_reg(u8 reg, u8 nr)
901 {
902 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
903 }
904
905 static inline u8 in_to_reg(u32 val, u8 nr)
906 {
907 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
908 }
909
910 /*
911 * Data structures and manipulation thereof
912 */
913
914 struct nct6775_data {
915 int addr; /* IO base of hw monitor block */
916 int sioreg; /* SIO register address */
917 enum kinds kind;
918 const char *name;
919
920 const struct attribute_group *groups[6];
921
922 u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
923 * 3=temp_crit, 4=temp_lcrit
924 */
925 u8 temp_src[NUM_TEMP];
926 u16 reg_temp_config[NUM_TEMP];
927 const char * const *temp_label;
928 u32 temp_mask;
929
930 u16 REG_CONFIG;
931 u16 REG_VBAT;
932 u16 REG_DIODE;
933 u8 DIODE_MASK;
934
935 const s8 *ALARM_BITS;
936 const s8 *BEEP_BITS;
937
938 const u16 *REG_VIN;
939 const u16 *REG_IN_MINMAX[2];
940
941 const u16 *REG_TARGET;
942 const u16 *REG_FAN;
943 const u16 *REG_FAN_MODE;
944 const u16 *REG_FAN_MIN;
945 const u16 *REG_FAN_PULSES;
946 const u16 *FAN_PULSE_SHIFT;
947 const u16 *REG_FAN_TIME[3];
948
949 const u16 *REG_TOLERANCE_H;
950
951 const u8 *REG_PWM_MODE;
952 const u8 *PWM_MODE_MASK;
953
954 const u16 *REG_PWM[7]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
955 * [3]=pwm_max, [4]=pwm_step,
956 * [5]=weight_duty_step, [6]=weight_duty_base
957 */
958 const u16 *REG_PWM_READ;
959
960 const u16 *REG_CRITICAL_PWM_ENABLE;
961 u8 CRITICAL_PWM_ENABLE_MASK;
962 const u16 *REG_CRITICAL_PWM;
963
964 const u16 *REG_AUTO_TEMP;
965 const u16 *REG_AUTO_PWM;
966
967 const u16 *REG_CRITICAL_TEMP;
968 const u16 *REG_CRITICAL_TEMP_TOLERANCE;
969
970 const u16 *REG_TEMP_SOURCE; /* temp register sources */
971 const u16 *REG_TEMP_SEL;
972 const u16 *REG_WEIGHT_TEMP_SEL;
973 const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=tolerance, 2=step */
974
975 const u16 *REG_TEMP_OFFSET;
976
977 const u16 *REG_ALARM;
978 const u16 *REG_BEEP;
979
980 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
981 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
982
983 struct mutex update_lock;
984 bool valid; /* true if following fields are valid */
985 unsigned long last_updated; /* In jiffies */
986
987 /* Register values */
988 u8 bank; /* current register bank */
989 u8 in_num; /* number of in inputs we have */
990 u8 in[15][3]; /* [0]=in, [1]=in_max, [2]=in_min */
991 unsigned int rpm[NUM_FAN];
992 u16 fan_min[NUM_FAN];
993 u8 fan_pulses[NUM_FAN];
994 u8 fan_div[NUM_FAN];
995 u8 has_pwm;
996 u8 has_fan; /* some fan inputs can be disabled */
997 u8 has_fan_min; /* some fans don't have min register */
998 bool has_fan_div;
999
1000 u8 num_temp_alarms; /* 2, 3, or 6 */
1001 u8 num_temp_beeps; /* 2, 3, or 6 */
1002 u8 temp_fixed_num; /* 3 or 6 */
1003 u8 temp_type[NUM_TEMP_FIXED];
1004 s8 temp_offset[NUM_TEMP_FIXED];
1005 s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1006 * 3=temp_crit, 4=temp_lcrit */
1007 u64 alarms;
1008 u64 beeps;
1009
1010 u8 pwm_num; /* number of pwm */
1011 u8 pwm_mode[NUM_FAN]; /* 1->DC variable voltage,
1012 * 0->PWM variable duty cycle
1013 */
1014 enum pwm_enable pwm_enable[NUM_FAN];
1015 /* 0->off
1016 * 1->manual
1017 * 2->thermal cruise mode (also called SmartFan I)
1018 * 3->fan speed cruise mode
1019 * 4->SmartFan III
1020 * 5->enhanced variable thermal cruise (SmartFan IV)
1021 */
1022 u8 pwm[7][NUM_FAN]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1023 * [3]=pwm_max, [4]=pwm_step,
1024 * [5]=weight_duty_step, [6]=weight_duty_base
1025 */
1026
1027 u8 target_temp[NUM_FAN];
1028 u8 target_temp_mask;
1029 u32 target_speed[NUM_FAN];
1030 u32 target_speed_tolerance[NUM_FAN];
1031 u8 speed_tolerance_limit;
1032
1033 u8 temp_tolerance[2][NUM_FAN];
1034 u8 tolerance_mask;
1035
1036 u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */
1037
1038 /* Automatic fan speed control registers */
1039 int auto_pwm_num;
1040 u8 auto_pwm[NUM_FAN][7];
1041 u8 auto_temp[NUM_FAN][7];
1042 u8 pwm_temp_sel[NUM_FAN];
1043 u8 pwm_weight_temp_sel[NUM_FAN];
1044 u8 weight_temp[3][NUM_FAN]; /* 0->temp_step, 1->temp_step_tol,
1045 * 2->temp_base
1046 */
1047
1048 u8 vid;
1049 u8 vrm;
1050
1051 bool have_vid;
1052
1053 u16 have_temp;
1054 u16 have_temp_fixed;
1055 u16 have_in;
1056
1057 /* Remember extra register values over suspend/resume */
1058 u8 vbat;
1059 u8 fandiv1;
1060 u8 fandiv2;
1061 u8 sio_reg_enable;
1062 };
1063
1064 struct nct6775_sio_data {
1065 int sioreg;
1066 enum kinds kind;
1067 };
1068
1069 struct sensor_device_template {
1070 struct device_attribute dev_attr;
1071 union {
1072 struct {
1073 u8 nr;
1074 u8 index;
1075 } s;
1076 int index;
1077 } u;
1078 bool s2; /* true if both index and nr are used */
1079 };
1080
1081 struct sensor_device_attr_u {
1082 union {
1083 struct sensor_device_attribute a1;
1084 struct sensor_device_attribute_2 a2;
1085 } u;
1086 char name[32];
1087 };
1088
1089 #define __TEMPLATE_ATTR(_template, _mode, _show, _store) { \
1090 .attr = {.name = _template, .mode = _mode }, \
1091 .show = _show, \
1092 .store = _store, \
1093 }
1094
1095 #define SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, _index) \
1096 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1097 .u.index = _index, \
1098 .s2 = false }
1099
1100 #define SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1101 _nr, _index) \
1102 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1103 .u.s.index = _index, \
1104 .u.s.nr = _nr, \
1105 .s2 = true }
1106
1107 #define SENSOR_TEMPLATE(_name, _template, _mode, _show, _store, _index) \
1108 static struct sensor_device_template sensor_dev_template_##_name \
1109 = SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, \
1110 _index)
1111
1112 #define SENSOR_TEMPLATE_2(_name, _template, _mode, _show, _store, \
1113 _nr, _index) \
1114 static struct sensor_device_template sensor_dev_template_##_name \
1115 = SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1116 _nr, _index)
1117
1118 struct sensor_template_group {
1119 struct sensor_device_template **templates;
1120 umode_t (*is_visible)(struct kobject *, struct attribute *, int);
1121 int base;
1122 };
1123
1124 static struct attribute_group *
1125 nct6775_create_attr_group(struct device *dev,
1126 const struct sensor_template_group *tg,
1127 int repeat)
1128 {
1129 struct attribute_group *group;
1130 struct sensor_device_attr_u *su;
1131 struct sensor_device_attribute *a;
1132 struct sensor_device_attribute_2 *a2;
1133 struct attribute **attrs;
1134 struct sensor_device_template **t;
1135 int i, count;
1136
1137 if (repeat <= 0)
1138 return ERR_PTR(-EINVAL);
1139
1140 t = tg->templates;
1141 for (count = 0; *t; t++, count++)
1142 ;
1143
1144 if (count == 0)
1145 return ERR_PTR(-EINVAL);
1146
1147 group = devm_kzalloc(dev, sizeof(*group), GFP_KERNEL);
1148 if (group == NULL)
1149 return ERR_PTR(-ENOMEM);
1150
1151 attrs = devm_kzalloc(dev, sizeof(*attrs) * (repeat * count + 1),
1152 GFP_KERNEL);
1153 if (attrs == NULL)
1154 return ERR_PTR(-ENOMEM);
1155
1156 su = devm_kzalloc(dev, sizeof(*su) * repeat * count,
1157 GFP_KERNEL);
1158 if (su == NULL)
1159 return ERR_PTR(-ENOMEM);
1160
1161 group->attrs = attrs;
1162 group->is_visible = tg->is_visible;
1163
1164 for (i = 0; i < repeat; i++) {
1165 t = tg->templates;
1166 while (*t != NULL) {
1167 snprintf(su->name, sizeof(su->name),
1168 (*t)->dev_attr.attr.name, tg->base + i);
1169 if ((*t)->s2) {
1170 a2 = &su->u.a2;
1171 sysfs_attr_init(&a2->dev_attr.attr);
1172 a2->dev_attr.attr.name = su->name;
1173 a2->nr = (*t)->u.s.nr + i;
1174 a2->index = (*t)->u.s.index;
1175 a2->dev_attr.attr.mode =
1176 (*t)->dev_attr.attr.mode;
1177 a2->dev_attr.show = (*t)->dev_attr.show;
1178 a2->dev_attr.store = (*t)->dev_attr.store;
1179 *attrs = &a2->dev_attr.attr;
1180 } else {
1181 a = &su->u.a1;
1182 sysfs_attr_init(&a->dev_attr.attr);
1183 a->dev_attr.attr.name = su->name;
1184 a->index = (*t)->u.index + i;
1185 a->dev_attr.attr.mode =
1186 (*t)->dev_attr.attr.mode;
1187 a->dev_attr.show = (*t)->dev_attr.show;
1188 a->dev_attr.store = (*t)->dev_attr.store;
1189 *attrs = &a->dev_attr.attr;
1190 }
1191 attrs++;
1192 su++;
1193 t++;
1194 }
1195 }
1196
1197 return group;
1198 }
1199
1200 static bool is_word_sized(struct nct6775_data *data, u16 reg)
1201 {
1202 switch (data->kind) {
1203 case nct6106:
1204 return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
1205 reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
1206 reg == 0x111 || reg == 0x121 || reg == 0x131;
1207 case nct6775:
1208 return (((reg & 0xff00) == 0x100 ||
1209 (reg & 0xff00) == 0x200) &&
1210 ((reg & 0x00ff) == 0x50 ||
1211 (reg & 0x00ff) == 0x53 ||
1212 (reg & 0x00ff) == 0x55)) ||
1213 (reg & 0xfff0) == 0x630 ||
1214 reg == 0x640 || reg == 0x642 ||
1215 reg == 0x662 ||
1216 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1217 reg == 0x73 || reg == 0x75 || reg == 0x77;
1218 case nct6776:
1219 return (((reg & 0xff00) == 0x100 ||
1220 (reg & 0xff00) == 0x200) &&
1221 ((reg & 0x00ff) == 0x50 ||
1222 (reg & 0x00ff) == 0x53 ||
1223 (reg & 0x00ff) == 0x55)) ||
1224 (reg & 0xfff0) == 0x630 ||
1225 reg == 0x402 ||
1226 reg == 0x640 || reg == 0x642 ||
1227 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1228 reg == 0x73 || reg == 0x75 || reg == 0x77;
1229 case nct6779:
1230 case nct6791:
1231 case nct6792:
1232 case nct6793:
1233 case nct6795:
1234 return reg == 0x150 || reg == 0x153 || reg == 0x155 ||
1235 ((reg & 0xfff0) == 0x4b0 && (reg & 0x000f) < 0x0b) ||
1236 reg == 0x402 ||
1237 reg == 0x63a || reg == 0x63c || reg == 0x63e ||
1238 reg == 0x640 || reg == 0x642 ||
1239 reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 ||
1240 reg == 0x7b || reg == 0x7d;
1241 }
1242 return false;
1243 }
1244
1245 /*
1246 * On older chips, only registers 0x50-0x5f are banked.
1247 * On more recent chips, all registers are banked.
1248 * Assume that is the case and set the bank number for each access.
1249 * Cache the bank number so it only needs to be set if it changes.
1250 */
1251 static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg)
1252 {
1253 u8 bank = reg >> 8;
1254
1255 if (data->bank != bank) {
1256 outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET);
1257 outb_p(bank, data->addr + DATA_REG_OFFSET);
1258 data->bank = bank;
1259 }
1260 }
1261
1262 static u16 nct6775_read_value(struct nct6775_data *data, u16 reg)
1263 {
1264 int res, word_sized = is_word_sized(data, reg);
1265
1266 nct6775_set_bank(data, reg);
1267 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1268 res = inb_p(data->addr + DATA_REG_OFFSET);
1269 if (word_sized) {
1270 outb_p((reg & 0xff) + 1,
1271 data->addr + ADDR_REG_OFFSET);
1272 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
1273 }
1274 return res;
1275 }
1276
1277 static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
1278 {
1279 int word_sized = is_word_sized(data, reg);
1280
1281 nct6775_set_bank(data, reg);
1282 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1283 if (word_sized) {
1284 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
1285 outb_p((reg & 0xff) + 1,
1286 data->addr + ADDR_REG_OFFSET);
1287 }
1288 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
1289 return 0;
1290 }
1291
1292 /* We left-align 8-bit temperature values to make the code simpler */
1293 static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg)
1294 {
1295 u16 res;
1296
1297 res = nct6775_read_value(data, reg);
1298 if (!is_word_sized(data, reg))
1299 res <<= 8;
1300
1301 return res;
1302 }
1303
1304 static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
1305 {
1306 if (!is_word_sized(data, reg))
1307 value >>= 8;
1308 return nct6775_write_value(data, reg, value);
1309 }
1310
1311 /* This function assumes that the caller holds data->update_lock */
1312 static void nct6775_write_fan_div(struct nct6775_data *data, int nr)
1313 {
1314 u8 reg;
1315
1316 switch (nr) {
1317 case 0:
1318 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
1319 | (data->fan_div[0] & 0x7);
1320 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1321 break;
1322 case 1:
1323 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
1324 | ((data->fan_div[1] << 4) & 0x70);
1325 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1326 break;
1327 case 2:
1328 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
1329 | (data->fan_div[2] & 0x7);
1330 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1331 break;
1332 case 3:
1333 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
1334 | ((data->fan_div[3] << 4) & 0x70);
1335 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1336 break;
1337 }
1338 }
1339
1340 static void nct6775_write_fan_div_common(struct nct6775_data *data, int nr)
1341 {
1342 if (data->kind == nct6775)
1343 nct6775_write_fan_div(data, nr);
1344 }
1345
1346 static void nct6775_update_fan_div(struct nct6775_data *data)
1347 {
1348 u8 i;
1349
1350 i = nct6775_read_value(data, NCT6775_REG_FANDIV1);
1351 data->fan_div[0] = i & 0x7;
1352 data->fan_div[1] = (i & 0x70) >> 4;
1353 i = nct6775_read_value(data, NCT6775_REG_FANDIV2);
1354 data->fan_div[2] = i & 0x7;
1355 if (data->has_fan & BIT(3))
1356 data->fan_div[3] = (i & 0x70) >> 4;
1357 }
1358
1359 static void nct6775_update_fan_div_common(struct nct6775_data *data)
1360 {
1361 if (data->kind == nct6775)
1362 nct6775_update_fan_div(data);
1363 }
1364
1365 static void nct6775_init_fan_div(struct nct6775_data *data)
1366 {
1367 int i;
1368
1369 nct6775_update_fan_div_common(data);
1370 /*
1371 * For all fans, start with highest divider value if the divider
1372 * register is not initialized. This ensures that we get a
1373 * reading from the fan count register, even if it is not optimal.
1374 * We'll compute a better divider later on.
1375 */
1376 for (i = 0; i < ARRAY_SIZE(data->fan_div); i++) {
1377 if (!(data->has_fan & BIT(i)))
1378 continue;
1379 if (data->fan_div[i] == 0) {
1380 data->fan_div[i] = 7;
1381 nct6775_write_fan_div_common(data, i);
1382 }
1383 }
1384 }
1385
1386 static void nct6775_init_fan_common(struct device *dev,
1387 struct nct6775_data *data)
1388 {
1389 int i;
1390 u8 reg;
1391
1392 if (data->has_fan_div)
1393 nct6775_init_fan_div(data);
1394
1395 /*
1396 * If fan_min is not set (0), set it to 0xff to disable it. This
1397 * prevents the unnecessary warning when fanX_min is reported as 0.
1398 */
1399 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
1400 if (data->has_fan_min & BIT(i)) {
1401 reg = nct6775_read_value(data, data->REG_FAN_MIN[i]);
1402 if (!reg)
1403 nct6775_write_value(data, data->REG_FAN_MIN[i],
1404 data->has_fan_div ? 0xff
1405 : 0xff1f);
1406 }
1407 }
1408 }
1409
1410 static void nct6775_select_fan_div(struct device *dev,
1411 struct nct6775_data *data, int nr, u16 reg)
1412 {
1413 u8 fan_div = data->fan_div[nr];
1414 u16 fan_min;
1415
1416 if (!data->has_fan_div)
1417 return;
1418
1419 /*
1420 * If we failed to measure the fan speed, or the reported value is not
1421 * in the optimal range, and the clock divider can be modified,
1422 * let's try that for next time.
1423 */
1424 if (reg == 0x00 && fan_div < 0x07)
1425 fan_div++;
1426 else if (reg != 0x00 && reg < 0x30 && fan_div > 0)
1427 fan_div--;
1428
1429 if (fan_div != data->fan_div[nr]) {
1430 dev_dbg(dev, "Modifying fan%d clock divider from %u to %u\n",
1431 nr + 1, div_from_reg(data->fan_div[nr]),
1432 div_from_reg(fan_div));
1433
1434 /* Preserve min limit if possible */
1435 if (data->has_fan_min & BIT(nr)) {
1436 fan_min = data->fan_min[nr];
1437 if (fan_div > data->fan_div[nr]) {
1438 if (fan_min != 255 && fan_min > 1)
1439 fan_min >>= 1;
1440 } else {
1441 if (fan_min != 255) {
1442 fan_min <<= 1;
1443 if (fan_min > 254)
1444 fan_min = 254;
1445 }
1446 }
1447 if (fan_min != data->fan_min[nr]) {
1448 data->fan_min[nr] = fan_min;
1449 nct6775_write_value(data, data->REG_FAN_MIN[nr],
1450 fan_min);
1451 }
1452 }
1453 data->fan_div[nr] = fan_div;
1454 nct6775_write_fan_div_common(data, nr);
1455 }
1456 }
1457
1458 static void nct6775_update_pwm(struct device *dev)
1459 {
1460 struct nct6775_data *data = dev_get_drvdata(dev);
1461 int i, j;
1462 int fanmodecfg, reg;
1463 bool duty_is_dc;
1464
1465 for (i = 0; i < data->pwm_num; i++) {
1466 if (!(data->has_pwm & BIT(i)))
1467 continue;
1468
1469 duty_is_dc = data->REG_PWM_MODE[i] &&
1470 (nct6775_read_value(data, data->REG_PWM_MODE[i])
1471 & data->PWM_MODE_MASK[i]);
1472 data->pwm_mode[i] = duty_is_dc;
1473
1474 fanmodecfg = nct6775_read_value(data, data->REG_FAN_MODE[i]);
1475 for (j = 0; j < ARRAY_SIZE(data->REG_PWM); j++) {
1476 if (data->REG_PWM[j] && data->REG_PWM[j][i]) {
1477 data->pwm[j][i]
1478 = nct6775_read_value(data,
1479 data->REG_PWM[j][i]);
1480 }
1481 }
1482
1483 data->pwm_enable[i] = reg_to_pwm_enable(data->pwm[0][i],
1484 (fanmodecfg >> 4) & 7);
1485
1486 if (!data->temp_tolerance[0][i] ||
1487 data->pwm_enable[i] != speed_cruise)
1488 data->temp_tolerance[0][i] = fanmodecfg & 0x0f;
1489 if (!data->target_speed_tolerance[i] ||
1490 data->pwm_enable[i] == speed_cruise) {
1491 u8 t = fanmodecfg & 0x0f;
1492
1493 if (data->REG_TOLERANCE_H) {
1494 t |= (nct6775_read_value(data,
1495 data->REG_TOLERANCE_H[i]) & 0x70) >> 1;
1496 }
1497 data->target_speed_tolerance[i] = t;
1498 }
1499
1500 data->temp_tolerance[1][i] =
1501 nct6775_read_value(data,
1502 data->REG_CRITICAL_TEMP_TOLERANCE[i]);
1503
1504 reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]);
1505 data->pwm_temp_sel[i] = reg & 0x1f;
1506 /* If fan can stop, report floor as 0 */
1507 if (reg & 0x80)
1508 data->pwm[2][i] = 0;
1509
1510 if (!data->REG_WEIGHT_TEMP_SEL[i])
1511 continue;
1512
1513 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]);
1514 data->pwm_weight_temp_sel[i] = reg & 0x1f;
1515 /* If weight is disabled, report weight source as 0 */
1516 if (j == 1 && !(reg & 0x80))
1517 data->pwm_weight_temp_sel[i] = 0;
1518
1519 /* Weight temp data */
1520 for (j = 0; j < ARRAY_SIZE(data->weight_temp); j++) {
1521 data->weight_temp[j][i]
1522 = nct6775_read_value(data,
1523 data->REG_WEIGHT_TEMP[j][i]);
1524 }
1525 }
1526 }
1527
1528 static void nct6775_update_pwm_limits(struct device *dev)
1529 {
1530 struct nct6775_data *data = dev_get_drvdata(dev);
1531 int i, j;
1532 u8 reg;
1533 u16 reg_t;
1534
1535 for (i = 0; i < data->pwm_num; i++) {
1536 if (!(data->has_pwm & BIT(i)))
1537 continue;
1538
1539 for (j = 0; j < ARRAY_SIZE(data->fan_time); j++) {
1540 data->fan_time[j][i] =
1541 nct6775_read_value(data, data->REG_FAN_TIME[j][i]);
1542 }
1543
1544 reg_t = nct6775_read_value(data, data->REG_TARGET[i]);
1545 /* Update only in matching mode or if never updated */
1546 if (!data->target_temp[i] ||
1547 data->pwm_enable[i] == thermal_cruise)
1548 data->target_temp[i] = reg_t & data->target_temp_mask;
1549 if (!data->target_speed[i] ||
1550 data->pwm_enable[i] == speed_cruise) {
1551 if (data->REG_TOLERANCE_H) {
1552 reg_t |= (nct6775_read_value(data,
1553 data->REG_TOLERANCE_H[i]) & 0x0f) << 8;
1554 }
1555 data->target_speed[i] = reg_t;
1556 }
1557
1558 for (j = 0; j < data->auto_pwm_num; j++) {
1559 data->auto_pwm[i][j] =
1560 nct6775_read_value(data,
1561 NCT6775_AUTO_PWM(data, i, j));
1562 data->auto_temp[i][j] =
1563 nct6775_read_value(data,
1564 NCT6775_AUTO_TEMP(data, i, j));
1565 }
1566
1567 /* critical auto_pwm temperature data */
1568 data->auto_temp[i][data->auto_pwm_num] =
1569 nct6775_read_value(data, data->REG_CRITICAL_TEMP[i]);
1570
1571 switch (data->kind) {
1572 case nct6775:
1573 reg = nct6775_read_value(data,
1574 NCT6775_REG_CRITICAL_ENAB[i]);
1575 data->auto_pwm[i][data->auto_pwm_num] =
1576 (reg & 0x02) ? 0xff : 0x00;
1577 break;
1578 case nct6776:
1579 data->auto_pwm[i][data->auto_pwm_num] = 0xff;
1580 break;
1581 case nct6106:
1582 case nct6779:
1583 case nct6791:
1584 case nct6792:
1585 case nct6793:
1586 case nct6795:
1587 reg = nct6775_read_value(data,
1588 data->REG_CRITICAL_PWM_ENABLE[i]);
1589 if (reg & data->CRITICAL_PWM_ENABLE_MASK)
1590 reg = nct6775_read_value(data,
1591 data->REG_CRITICAL_PWM[i]);
1592 else
1593 reg = 0xff;
1594 data->auto_pwm[i][data->auto_pwm_num] = reg;
1595 break;
1596 }
1597 }
1598 }
1599
1600 static struct nct6775_data *nct6775_update_device(struct device *dev)
1601 {
1602 struct nct6775_data *data = dev_get_drvdata(dev);
1603 int i, j;
1604
1605 mutex_lock(&data->update_lock);
1606
1607 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1608 || !data->valid) {
1609 /* Fan clock dividers */
1610 nct6775_update_fan_div_common(data);
1611
1612 /* Measured voltages and limits */
1613 for (i = 0; i < data->in_num; i++) {
1614 if (!(data->have_in & BIT(i)))
1615 continue;
1616
1617 data->in[i][0] = nct6775_read_value(data,
1618 data->REG_VIN[i]);
1619 data->in[i][1] = nct6775_read_value(data,
1620 data->REG_IN_MINMAX[0][i]);
1621 data->in[i][2] = nct6775_read_value(data,
1622 data->REG_IN_MINMAX[1][i]);
1623 }
1624
1625 /* Measured fan speeds and limits */
1626 for (i = 0; i < ARRAY_SIZE(data->rpm); i++) {
1627 u16 reg;
1628
1629 if (!(data->has_fan & BIT(i)))
1630 continue;
1631
1632 reg = nct6775_read_value(data, data->REG_FAN[i]);
1633 data->rpm[i] = data->fan_from_reg(reg,
1634 data->fan_div[i]);
1635
1636 if (data->has_fan_min & BIT(i))
1637 data->fan_min[i] = nct6775_read_value(data,
1638 data->REG_FAN_MIN[i]);
1639 data->fan_pulses[i] =
1640 (nct6775_read_value(data, data->REG_FAN_PULSES[i])
1641 >> data->FAN_PULSE_SHIFT[i]) & 0x03;
1642
1643 nct6775_select_fan_div(dev, data, i, reg);
1644 }
1645
1646 nct6775_update_pwm(dev);
1647 nct6775_update_pwm_limits(dev);
1648
1649 /* Measured temperatures and limits */
1650 for (i = 0; i < NUM_TEMP; i++) {
1651 if (!(data->have_temp & BIT(i)))
1652 continue;
1653 for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) {
1654 if (data->reg_temp[j][i])
1655 data->temp[j][i]
1656 = nct6775_read_temp(data,
1657 data->reg_temp[j][i]);
1658 }
1659 if (i >= NUM_TEMP_FIXED ||
1660 !(data->have_temp_fixed & BIT(i)))
1661 continue;
1662 data->temp_offset[i]
1663 = nct6775_read_value(data, data->REG_TEMP_OFFSET[i]);
1664 }
1665
1666 data->alarms = 0;
1667 for (i = 0; i < NUM_REG_ALARM; i++) {
1668 u8 alarm;
1669
1670 if (!data->REG_ALARM[i])
1671 continue;
1672 alarm = nct6775_read_value(data, data->REG_ALARM[i]);
1673 data->alarms |= ((u64)alarm) << (i << 3);
1674 }
1675
1676 data->beeps = 0;
1677 for (i = 0; i < NUM_REG_BEEP; i++) {
1678 u8 beep;
1679
1680 if (!data->REG_BEEP[i])
1681 continue;
1682 beep = nct6775_read_value(data, data->REG_BEEP[i]);
1683 data->beeps |= ((u64)beep) << (i << 3);
1684 }
1685
1686 data->last_updated = jiffies;
1687 data->valid = true;
1688 }
1689
1690 mutex_unlock(&data->update_lock);
1691 return data;
1692 }
1693
1694 /*
1695 * Sysfs callback functions
1696 */
1697 static ssize_t
1698 show_in_reg(struct device *dev, struct device_attribute *attr, char *buf)
1699 {
1700 struct nct6775_data *data = nct6775_update_device(dev);
1701 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1702 int index = sattr->index;
1703 int nr = sattr->nr;
1704
1705 return sprintf(buf, "%ld\n", in_from_reg(data->in[nr][index], nr));
1706 }
1707
1708 static ssize_t
1709 store_in_reg(struct device *dev, struct device_attribute *attr, const char *buf,
1710 size_t count)
1711 {
1712 struct nct6775_data *data = dev_get_drvdata(dev);
1713 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1714 int index = sattr->index;
1715 int nr = sattr->nr;
1716 unsigned long val;
1717 int err;
1718
1719 err = kstrtoul(buf, 10, &val);
1720 if (err < 0)
1721 return err;
1722 mutex_lock(&data->update_lock);
1723 data->in[nr][index] = in_to_reg(val, nr);
1724 nct6775_write_value(data, data->REG_IN_MINMAX[index - 1][nr],
1725 data->in[nr][index]);
1726 mutex_unlock(&data->update_lock);
1727 return count;
1728 }
1729
1730 static ssize_t
1731 show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1732 {
1733 struct nct6775_data *data = nct6775_update_device(dev);
1734 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1735 int nr = data->ALARM_BITS[sattr->index];
1736
1737 return sprintf(buf, "%u\n",
1738 (unsigned int)((data->alarms >> nr) & 0x01));
1739 }
1740
1741 static int find_temp_source(struct nct6775_data *data, int index, int count)
1742 {
1743 int source = data->temp_src[index];
1744 int nr;
1745
1746 for (nr = 0; nr < count; nr++) {
1747 int src;
1748
1749 src = nct6775_read_value(data,
1750 data->REG_TEMP_SOURCE[nr]) & 0x1f;
1751 if (src == source)
1752 return nr;
1753 }
1754 return -ENODEV;
1755 }
1756
1757 static ssize_t
1758 show_temp_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1759 {
1760 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1761 struct nct6775_data *data = nct6775_update_device(dev);
1762 unsigned int alarm = 0;
1763 int nr;
1764
1765 /*
1766 * For temperatures, there is no fixed mapping from registers to alarm
1767 * bits. Alarm bits are determined by the temperature source mapping.
1768 */
1769 nr = find_temp_source(data, sattr->index, data->num_temp_alarms);
1770 if (nr >= 0) {
1771 int bit = data->ALARM_BITS[nr + TEMP_ALARM_BASE];
1772
1773 alarm = (data->alarms >> bit) & 0x01;
1774 }
1775 return sprintf(buf, "%u\n", alarm);
1776 }
1777
1778 static ssize_t
1779 show_beep(struct device *dev, struct device_attribute *attr, char *buf)
1780 {
1781 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1782 struct nct6775_data *data = nct6775_update_device(dev);
1783 int nr = data->BEEP_BITS[sattr->index];
1784
1785 return sprintf(buf, "%u\n",
1786 (unsigned int)((data->beeps >> nr) & 0x01));
1787 }
1788
1789 static ssize_t
1790 store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
1791 size_t count)
1792 {
1793 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1794 struct nct6775_data *data = dev_get_drvdata(dev);
1795 int nr = data->BEEP_BITS[sattr->index];
1796 int regindex = nr >> 3;
1797 unsigned long val;
1798 int err;
1799
1800 err = kstrtoul(buf, 10, &val);
1801 if (err < 0)
1802 return err;
1803 if (val > 1)
1804 return -EINVAL;
1805
1806 mutex_lock(&data->update_lock);
1807 if (val)
1808 data->beeps |= (1ULL << nr);
1809 else
1810 data->beeps &= ~(1ULL << nr);
1811 nct6775_write_value(data, data->REG_BEEP[regindex],
1812 (data->beeps >> (regindex << 3)) & 0xff);
1813 mutex_unlock(&data->update_lock);
1814 return count;
1815 }
1816
1817 static ssize_t
1818 show_temp_beep(struct device *dev, struct device_attribute *attr, char *buf)
1819 {
1820 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1821 struct nct6775_data *data = nct6775_update_device(dev);
1822 unsigned int beep = 0;
1823 int nr;
1824
1825 /*
1826 * For temperatures, there is no fixed mapping from registers to beep
1827 * enable bits. Beep enable bits are determined by the temperature
1828 * source mapping.
1829 */
1830 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1831 if (nr >= 0) {
1832 int bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1833
1834 beep = (data->beeps >> bit) & 0x01;
1835 }
1836 return sprintf(buf, "%u\n", beep);
1837 }
1838
1839 static ssize_t
1840 store_temp_beep(struct device *dev, struct device_attribute *attr,
1841 const char *buf, size_t count)
1842 {
1843 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1844 struct nct6775_data *data = dev_get_drvdata(dev);
1845 int nr, bit, regindex;
1846 unsigned long val;
1847 int err;
1848
1849 err = kstrtoul(buf, 10, &val);
1850 if (err < 0)
1851 return err;
1852 if (val > 1)
1853 return -EINVAL;
1854
1855 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1856 if (nr < 0)
1857 return nr;
1858
1859 bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1860 regindex = bit >> 3;
1861
1862 mutex_lock(&data->update_lock);
1863 if (val)
1864 data->beeps |= (1ULL << bit);
1865 else
1866 data->beeps &= ~(1ULL << bit);
1867 nct6775_write_value(data, data->REG_BEEP[regindex],
1868 (data->beeps >> (regindex << 3)) & 0xff);
1869 mutex_unlock(&data->update_lock);
1870
1871 return count;
1872 }
1873
1874 static umode_t nct6775_in_is_visible(struct kobject *kobj,
1875 struct attribute *attr, int index)
1876 {
1877 struct device *dev = container_of(kobj, struct device, kobj);
1878 struct nct6775_data *data = dev_get_drvdata(dev);
1879 int in = index / 5; /* voltage index */
1880
1881 if (!(data->have_in & BIT(in)))
1882 return 0;
1883
1884 return attr->mode;
1885 }
1886
1887 SENSOR_TEMPLATE_2(in_input, "in%d_input", S_IRUGO, show_in_reg, NULL, 0, 0);
1888 SENSOR_TEMPLATE(in_alarm, "in%d_alarm", S_IRUGO, show_alarm, NULL, 0);
1889 SENSOR_TEMPLATE(in_beep, "in%d_beep", S_IWUSR | S_IRUGO, show_beep, store_beep,
1890 0);
1891 SENSOR_TEMPLATE_2(in_min, "in%d_min", S_IWUSR | S_IRUGO, show_in_reg,
1892 store_in_reg, 0, 1);
1893 SENSOR_TEMPLATE_2(in_max, "in%d_max", S_IWUSR | S_IRUGO, show_in_reg,
1894 store_in_reg, 0, 2);
1895
1896 /*
1897 * nct6775_in_is_visible uses the index into the following array
1898 * to determine if attributes should be created or not.
1899 * Any change in order or content must be matched.
1900 */
1901 static struct sensor_device_template *nct6775_attributes_in_template[] = {
1902 &sensor_dev_template_in_input,
1903 &sensor_dev_template_in_alarm,
1904 &sensor_dev_template_in_beep,
1905 &sensor_dev_template_in_min,
1906 &sensor_dev_template_in_max,
1907 NULL
1908 };
1909
1910 static const struct sensor_template_group nct6775_in_template_group = {
1911 .templates = nct6775_attributes_in_template,
1912 .is_visible = nct6775_in_is_visible,
1913 };
1914
1915 static ssize_t
1916 show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1917 {
1918 struct nct6775_data *data = nct6775_update_device(dev);
1919 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1920 int nr = sattr->index;
1921
1922 return sprintf(buf, "%d\n", data->rpm[nr]);
1923 }
1924
1925 static ssize_t
1926 show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1927 {
1928 struct nct6775_data *data = nct6775_update_device(dev);
1929 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1930 int nr = sattr->index;
1931
1932 return sprintf(buf, "%d\n",
1933 data->fan_from_reg_min(data->fan_min[nr],
1934 data->fan_div[nr]));
1935 }
1936
1937 static ssize_t
1938 show_fan_div(struct device *dev, struct device_attribute *attr, char *buf)
1939 {
1940 struct nct6775_data *data = nct6775_update_device(dev);
1941 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1942 int nr = sattr->index;
1943
1944 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
1945 }
1946
1947 static ssize_t
1948 store_fan_min(struct device *dev, struct device_attribute *attr,
1949 const char *buf, size_t count)
1950 {
1951 struct nct6775_data *data = dev_get_drvdata(dev);
1952 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1953 int nr = sattr->index;
1954 unsigned long val;
1955 unsigned int reg;
1956 u8 new_div;
1957 int err;
1958
1959 err = kstrtoul(buf, 10, &val);
1960 if (err < 0)
1961 return err;
1962
1963 mutex_lock(&data->update_lock);
1964 if (!data->has_fan_div) {
1965 /* NCT6776F or NCT6779D; we know this is a 13 bit register */
1966 if (!val) {
1967 val = 0xff1f;
1968 } else {
1969 if (val > 1350000U)
1970 val = 135000U;
1971 val = 1350000U / val;
1972 val = (val & 0x1f) | ((val << 3) & 0xff00);
1973 }
1974 data->fan_min[nr] = val;
1975 goto write_min; /* Leave fan divider alone */
1976 }
1977 if (!val) {
1978 /* No min limit, alarm disabled */
1979 data->fan_min[nr] = 255;
1980 new_div = data->fan_div[nr]; /* No change */
1981 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
1982 goto write_div;
1983 }
1984 reg = 1350000U / val;
1985 if (reg >= 128 * 255) {
1986 /*
1987 * Speed below this value cannot possibly be represented,
1988 * even with the highest divider (128)
1989 */
1990 data->fan_min[nr] = 254;
1991 new_div = 7; /* 128 == BIT(7) */
1992 dev_warn(dev,
1993 "fan%u low limit %lu below minimum %u, set to minimum\n",
1994 nr + 1, val, data->fan_from_reg_min(254, 7));
1995 } else if (!reg) {
1996 /*
1997 * Speed above this value cannot possibly be represented,
1998 * even with the lowest divider (1)
1999 */
2000 data->fan_min[nr] = 1;
2001 new_div = 0; /* 1 == BIT(0) */
2002 dev_warn(dev,
2003 "fan%u low limit %lu above maximum %u, set to maximum\n",
2004 nr + 1, val, data->fan_from_reg_min(1, 0));
2005 } else {
2006 /*
2007 * Automatically pick the best divider, i.e. the one such
2008 * that the min limit will correspond to a register value
2009 * in the 96..192 range
2010 */
2011 new_div = 0;
2012 while (reg > 192 && new_div < 7) {
2013 reg >>= 1;
2014 new_div++;
2015 }
2016 data->fan_min[nr] = reg;
2017 }
2018
2019 write_div:
2020 /*
2021 * Write both the fan clock divider (if it changed) and the new
2022 * fan min (unconditionally)
2023 */
2024 if (new_div != data->fan_div[nr]) {
2025 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
2026 nr + 1, div_from_reg(data->fan_div[nr]),
2027 div_from_reg(new_div));
2028 data->fan_div[nr] = new_div;
2029 nct6775_write_fan_div_common(data, nr);
2030 /* Give the chip time to sample a new speed value */
2031 data->last_updated = jiffies;
2032 }
2033
2034 write_min:
2035 nct6775_write_value(data, data->REG_FAN_MIN[nr], data->fan_min[nr]);
2036 mutex_unlock(&data->update_lock);
2037
2038 return count;
2039 }
2040
2041 static ssize_t
2042 show_fan_pulses(struct device *dev, struct device_attribute *attr, char *buf)
2043 {
2044 struct nct6775_data *data = nct6775_update_device(dev);
2045 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2046 int p = data->fan_pulses[sattr->index];
2047
2048 return sprintf(buf, "%d\n", p ? : 4);
2049 }
2050
2051 static ssize_t
2052 store_fan_pulses(struct device *dev, struct device_attribute *attr,
2053 const char *buf, size_t count)
2054 {
2055 struct nct6775_data *data = dev_get_drvdata(dev);
2056 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2057 int nr = sattr->index;
2058 unsigned long val;
2059 int err;
2060 u8 reg;
2061
2062 err = kstrtoul(buf, 10, &val);
2063 if (err < 0)
2064 return err;
2065
2066 if (val > 4)
2067 return -EINVAL;
2068
2069 mutex_lock(&data->update_lock);
2070 data->fan_pulses[nr] = val & 3;
2071 reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]);
2072 reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]);
2073 reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr];
2074 nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg);
2075 mutex_unlock(&data->update_lock);
2076
2077 return count;
2078 }
2079
2080 static umode_t nct6775_fan_is_visible(struct kobject *kobj,
2081 struct attribute *attr, int index)
2082 {
2083 struct device *dev = container_of(kobj, struct device, kobj);
2084 struct nct6775_data *data = dev_get_drvdata(dev);
2085 int fan = index / 6; /* fan index */
2086 int nr = index % 6; /* attribute index */
2087
2088 if (!(data->has_fan & BIT(fan)))
2089 return 0;
2090
2091 if (nr == 1 && data->ALARM_BITS[FAN_ALARM_BASE + fan] == -1)
2092 return 0;
2093 if (nr == 2 && data->BEEP_BITS[FAN_ALARM_BASE + fan] == -1)
2094 return 0;
2095 if (nr == 4 && !(data->has_fan_min & BIT(fan)))
2096 return 0;
2097 if (nr == 5 && data->kind != nct6775)
2098 return 0;
2099
2100 return attr->mode;
2101 }
2102
2103 SENSOR_TEMPLATE(fan_input, "fan%d_input", S_IRUGO, show_fan, NULL, 0);
2104 SENSOR_TEMPLATE(fan_alarm, "fan%d_alarm", S_IRUGO, show_alarm, NULL,
2105 FAN_ALARM_BASE);
2106 SENSOR_TEMPLATE(fan_beep, "fan%d_beep", S_IWUSR | S_IRUGO, show_beep,
2107 store_beep, FAN_ALARM_BASE);
2108 SENSOR_TEMPLATE(fan_pulses, "fan%d_pulses", S_IWUSR | S_IRUGO, show_fan_pulses,
2109 store_fan_pulses, 0);
2110 SENSOR_TEMPLATE(fan_min, "fan%d_min", S_IWUSR | S_IRUGO, show_fan_min,
2111 store_fan_min, 0);
2112 SENSOR_TEMPLATE(fan_div, "fan%d_div", S_IRUGO, show_fan_div, NULL, 0);
2113
2114 /*
2115 * nct6775_fan_is_visible uses the index into the following array
2116 * to determine if attributes should be created or not.
2117 * Any change in order or content must be matched.
2118 */
2119 static struct sensor_device_template *nct6775_attributes_fan_template[] = {
2120 &sensor_dev_template_fan_input,
2121 &sensor_dev_template_fan_alarm, /* 1 */
2122 &sensor_dev_template_fan_beep, /* 2 */
2123 &sensor_dev_template_fan_pulses,
2124 &sensor_dev_template_fan_min, /* 4 */
2125 &sensor_dev_template_fan_div, /* 5 */
2126 NULL
2127 };
2128
2129 static const struct sensor_template_group nct6775_fan_template_group = {
2130 .templates = nct6775_attributes_fan_template,
2131 .is_visible = nct6775_fan_is_visible,
2132 .base = 1,
2133 };
2134
2135 static ssize_t
2136 show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
2137 {
2138 struct nct6775_data *data = nct6775_update_device(dev);
2139 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2140 int nr = sattr->index;
2141
2142 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
2143 }
2144
2145 static ssize_t
2146 show_temp(struct device *dev, struct device_attribute *attr, char *buf)
2147 {
2148 struct nct6775_data *data = nct6775_update_device(dev);
2149 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2150 int nr = sattr->nr;
2151 int index = sattr->index;
2152
2153 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->temp[index][nr]));
2154 }
2155
2156 static ssize_t
2157 store_temp(struct device *dev, struct device_attribute *attr, const char *buf,
2158 size_t count)
2159 {
2160 struct nct6775_data *data = dev_get_drvdata(dev);
2161 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2162 int nr = sattr->nr;
2163 int index = sattr->index;
2164 int err;
2165 long val;
2166
2167 err = kstrtol(buf, 10, &val);
2168 if (err < 0)
2169 return err;
2170
2171 mutex_lock(&data->update_lock);
2172 data->temp[index][nr] = LM75_TEMP_TO_REG(val);
2173 nct6775_write_temp(data, data->reg_temp[index][nr],
2174 data->temp[index][nr]);
2175 mutex_unlock(&data->update_lock);
2176 return count;
2177 }
2178
2179 static ssize_t
2180 show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
2181 {
2182 struct nct6775_data *data = nct6775_update_device(dev);
2183 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2184
2185 return sprintf(buf, "%d\n", data->temp_offset[sattr->index] * 1000);
2186 }
2187
2188 static ssize_t
2189 store_temp_offset(struct device *dev, struct device_attribute *attr,
2190 const char *buf, size_t count)
2191 {
2192 struct nct6775_data *data = dev_get_drvdata(dev);
2193 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2194 int nr = sattr->index;
2195 long val;
2196 int err;
2197
2198 err = kstrtol(buf, 10, &val);
2199 if (err < 0)
2200 return err;
2201
2202 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
2203
2204 mutex_lock(&data->update_lock);
2205 data->temp_offset[nr] = val;
2206 nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val);
2207 mutex_unlock(&data->update_lock);
2208
2209 return count;
2210 }
2211
2212 static ssize_t
2213 show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
2214 {
2215 struct nct6775_data *data = nct6775_update_device(dev);
2216 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2217 int nr = sattr->index;
2218
2219 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
2220 }
2221
2222 static ssize_t
2223 store_temp_type(struct device *dev, struct device_attribute *attr,
2224 const char *buf, size_t count)
2225 {
2226 struct nct6775_data *data = nct6775_update_device(dev);
2227 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2228 int nr = sattr->index;
2229 unsigned long val;
2230 int err;
2231 u8 vbat, diode, vbit, dbit;
2232
2233 err = kstrtoul(buf, 10, &val);
2234 if (err < 0)
2235 return err;
2236
2237 if (val != 1 && val != 3 && val != 4)
2238 return -EINVAL;
2239
2240 mutex_lock(&data->update_lock);
2241
2242 data->temp_type[nr] = val;
2243 vbit = 0x02 << nr;
2244 dbit = data->DIODE_MASK << nr;
2245 vbat = nct6775_read_value(data, data->REG_VBAT) & ~vbit;
2246 diode = nct6775_read_value(data, data->REG_DIODE) & ~dbit;
2247 switch (val) {
2248 case 1: /* CPU diode (diode, current mode) */
2249 vbat |= vbit;
2250 diode |= dbit;
2251 break;
2252 case 3: /* diode, voltage mode */
2253 vbat |= dbit;
2254 break;
2255 case 4: /* thermistor */
2256 break;
2257 }
2258 nct6775_write_value(data, data->REG_VBAT, vbat);
2259 nct6775_write_value(data, data->REG_DIODE, diode);
2260
2261 mutex_unlock(&data->update_lock);
2262 return count;
2263 }
2264
2265 static umode_t nct6775_temp_is_visible(struct kobject *kobj,
2266 struct attribute *attr, int index)
2267 {
2268 struct device *dev = container_of(kobj, struct device, kobj);
2269 struct nct6775_data *data = dev_get_drvdata(dev);
2270 int temp = index / 10; /* temp index */
2271 int nr = index % 10; /* attribute index */
2272
2273 if (!(data->have_temp & BIT(temp)))
2274 return 0;
2275
2276 if (nr == 1 && !data->temp_label)
2277 return 0;
2278
2279 if (nr == 2 && find_temp_source(data, temp, data->num_temp_alarms) < 0)
2280 return 0; /* alarm */
2281
2282 if (nr == 3 && find_temp_source(data, temp, data->num_temp_beeps) < 0)
2283 return 0; /* beep */
2284
2285 if (nr == 4 && !data->reg_temp[1][temp]) /* max */
2286 return 0;
2287
2288 if (nr == 5 && !data->reg_temp[2][temp]) /* max_hyst */
2289 return 0;
2290
2291 if (nr == 6 && !data->reg_temp[3][temp]) /* crit */
2292 return 0;
2293
2294 if (nr == 7 && !data->reg_temp[4][temp]) /* lcrit */
2295 return 0;
2296
2297 /* offset and type only apply to fixed sensors */
2298 if (nr > 7 && !(data->have_temp_fixed & BIT(temp)))
2299 return 0;
2300
2301 return attr->mode;
2302 }
2303
2304 SENSOR_TEMPLATE_2(temp_input, "temp%d_input", S_IRUGO, show_temp, NULL, 0, 0);
2305 SENSOR_TEMPLATE(temp_label, "temp%d_label", S_IRUGO, show_temp_label, NULL, 0);
2306 SENSOR_TEMPLATE_2(temp_max, "temp%d_max", S_IRUGO | S_IWUSR, show_temp,
2307 store_temp, 0, 1);
2308 SENSOR_TEMPLATE_2(temp_max_hyst, "temp%d_max_hyst", S_IRUGO | S_IWUSR,
2309 show_temp, store_temp, 0, 2);
2310 SENSOR_TEMPLATE_2(temp_crit, "temp%d_crit", S_IRUGO | S_IWUSR, show_temp,
2311 store_temp, 0, 3);
2312 SENSOR_TEMPLATE_2(temp_lcrit, "temp%d_lcrit", S_IRUGO | S_IWUSR, show_temp,
2313 store_temp, 0, 4);
2314 SENSOR_TEMPLATE(temp_offset, "temp%d_offset", S_IRUGO | S_IWUSR,
2315 show_temp_offset, store_temp_offset, 0);
2316 SENSOR_TEMPLATE(temp_type, "temp%d_type", S_IRUGO | S_IWUSR, show_temp_type,
2317 store_temp_type, 0);
2318 SENSOR_TEMPLATE(temp_alarm, "temp%d_alarm", S_IRUGO, show_temp_alarm, NULL, 0);
2319 SENSOR_TEMPLATE(temp_beep, "temp%d_beep", S_IRUGO | S_IWUSR, show_temp_beep,
2320 store_temp_beep, 0);
2321
2322 /*
2323 * nct6775_temp_is_visible uses the index into the following array
2324 * to determine if attributes should be created or not.
2325 * Any change in order or content must be matched.
2326 */
2327 static struct sensor_device_template *nct6775_attributes_temp_template[] = {
2328 &sensor_dev_template_temp_input,
2329 &sensor_dev_template_temp_label,
2330 &sensor_dev_template_temp_alarm, /* 2 */
2331 &sensor_dev_template_temp_beep, /* 3 */
2332 &sensor_dev_template_temp_max, /* 4 */
2333 &sensor_dev_template_temp_max_hyst, /* 5 */
2334 &sensor_dev_template_temp_crit, /* 6 */
2335 &sensor_dev_template_temp_lcrit, /* 7 */
2336 &sensor_dev_template_temp_offset, /* 8 */
2337 &sensor_dev_template_temp_type, /* 9 */
2338 NULL
2339 };
2340
2341 static const struct sensor_template_group nct6775_temp_template_group = {
2342 .templates = nct6775_attributes_temp_template,
2343 .is_visible = nct6775_temp_is_visible,
2344 .base = 1,
2345 };
2346
2347 static ssize_t
2348 show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf)
2349 {
2350 struct nct6775_data *data = nct6775_update_device(dev);
2351 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2352
2353 return sprintf(buf, "%d\n", !data->pwm_mode[sattr->index]);
2354 }
2355
2356 static ssize_t
2357 store_pwm_mode(struct device *dev, struct device_attribute *attr,
2358 const char *buf, size_t count)
2359 {
2360 struct nct6775_data *data = dev_get_drvdata(dev);
2361 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2362 int nr = sattr->index;
2363 unsigned long val;
2364 int err;
2365 u8 reg;
2366
2367 err = kstrtoul(buf, 10, &val);
2368 if (err < 0)
2369 return err;
2370
2371 if (val > 1)
2372 return -EINVAL;
2373
2374 /* Setting DC mode is not supported for all chips/channels */
2375 if (data->REG_PWM_MODE[nr] == 0) {
2376 if (val)
2377 return -EINVAL;
2378 return count;
2379 }
2380
2381 mutex_lock(&data->update_lock);
2382 data->pwm_mode[nr] = val;
2383 reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]);
2384 reg &= ~data->PWM_MODE_MASK[nr];
2385 if (val)
2386 reg |= data->PWM_MODE_MASK[nr];
2387 nct6775_write_value(data, data->REG_PWM_MODE[nr], reg);
2388 mutex_unlock(&data->update_lock);
2389 return count;
2390 }
2391
2392 static ssize_t
2393 show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2394 {
2395 struct nct6775_data *data = nct6775_update_device(dev);
2396 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2397 int nr = sattr->nr;
2398 int index = sattr->index;
2399 int pwm;
2400
2401 /*
2402 * For automatic fan control modes, show current pwm readings.
2403 * Otherwise, show the configured value.
2404 */
2405 if (index == 0 && data->pwm_enable[nr] > manual)
2406 pwm = nct6775_read_value(data, data->REG_PWM_READ[nr]);
2407 else
2408 pwm = data->pwm[index][nr];
2409
2410 return sprintf(buf, "%d\n", pwm);
2411 }
2412
2413 static ssize_t
2414 store_pwm(struct device *dev, struct device_attribute *attr, const char *buf,
2415 size_t count)
2416 {
2417 struct nct6775_data *data = dev_get_drvdata(dev);
2418 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2419 int nr = sattr->nr;
2420 int index = sattr->index;
2421 unsigned long val;
2422 int minval[7] = { 0, 1, 1, data->pwm[2][nr], 0, 0, 0 };
2423 int maxval[7]
2424 = { 255, 255, data->pwm[3][nr] ? : 255, 255, 255, 255, 255 };
2425 int err;
2426 u8 reg;
2427
2428 err = kstrtoul(buf, 10, &val);
2429 if (err < 0)
2430 return err;
2431 val = clamp_val(val, minval[index], maxval[index]);
2432
2433 mutex_lock(&data->update_lock);
2434 data->pwm[index][nr] = val;
2435 nct6775_write_value(data, data->REG_PWM[index][nr], val);
2436 if (index == 2) { /* floor: disable if val == 0 */
2437 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2438 reg &= 0x7f;
2439 if (val)
2440 reg |= 0x80;
2441 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2442 }
2443 mutex_unlock(&data->update_lock);
2444 return count;
2445 }
2446
2447 /* Returns 0 if OK, -EINVAL otherwise */
2448 static int check_trip_points(struct nct6775_data *data, int nr)
2449 {
2450 int i;
2451
2452 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2453 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
2454 return -EINVAL;
2455 }
2456 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2457 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
2458 return -EINVAL;
2459 }
2460 /* validate critical temperature and pwm if enabled (pwm > 0) */
2461 if (data->auto_pwm[nr][data->auto_pwm_num]) {
2462 if (data->auto_temp[nr][data->auto_pwm_num - 1] >
2463 data->auto_temp[nr][data->auto_pwm_num] ||
2464 data->auto_pwm[nr][data->auto_pwm_num - 1] >
2465 data->auto_pwm[nr][data->auto_pwm_num])
2466 return -EINVAL;
2467 }
2468 return 0;
2469 }
2470
2471 static void pwm_update_registers(struct nct6775_data *data, int nr)
2472 {
2473 u8 reg;
2474
2475 switch (data->pwm_enable[nr]) {
2476 case off:
2477 case manual:
2478 break;
2479 case speed_cruise:
2480 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2481 reg = (reg & ~data->tolerance_mask) |
2482 (data->target_speed_tolerance[nr] & data->tolerance_mask);
2483 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2484 nct6775_write_value(data, data->REG_TARGET[nr],
2485 data->target_speed[nr] & 0xff);
2486 if (data->REG_TOLERANCE_H) {
2487 reg = (data->target_speed[nr] >> 8) & 0x0f;
2488 reg |= (data->target_speed_tolerance[nr] & 0x38) << 1;
2489 nct6775_write_value(data,
2490 data->REG_TOLERANCE_H[nr],
2491 reg);
2492 }
2493 break;
2494 case thermal_cruise:
2495 nct6775_write_value(data, data->REG_TARGET[nr],
2496 data->target_temp[nr]);
2497 /* intentional */
2498 default:
2499 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2500 reg = (reg & ~data->tolerance_mask) |
2501 data->temp_tolerance[0][nr];
2502 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2503 break;
2504 }
2505 }
2506
2507 static ssize_t
2508 show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf)
2509 {
2510 struct nct6775_data *data = nct6775_update_device(dev);
2511 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2512
2513 return sprintf(buf, "%d\n", data->pwm_enable[sattr->index]);
2514 }
2515
2516 static ssize_t
2517 store_pwm_enable(struct device *dev, struct device_attribute *attr,
2518 const char *buf, size_t count)
2519 {
2520 struct nct6775_data *data = dev_get_drvdata(dev);
2521 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2522 int nr = sattr->index;
2523 unsigned long val;
2524 int err;
2525 u16 reg;
2526
2527 err = kstrtoul(buf, 10, &val);
2528 if (err < 0)
2529 return err;
2530
2531 if (val > sf4)
2532 return -EINVAL;
2533
2534 if (val == sf3 && data->kind != nct6775)
2535 return -EINVAL;
2536
2537 if (val == sf4 && check_trip_points(data, nr)) {
2538 dev_err(dev, "Inconsistent trip points, not switching to SmartFan IV mode\n");
2539 dev_err(dev, "Adjust trip points and try again\n");
2540 return -EINVAL;
2541 }
2542
2543 mutex_lock(&data->update_lock);
2544 data->pwm_enable[nr] = val;
2545 if (val == off) {
2546 /*
2547 * turn off pwm control: select manual mode, set pwm to maximum
2548 */
2549 data->pwm[0][nr] = 255;
2550 nct6775_write_value(data, data->REG_PWM[0][nr], 255);
2551 }
2552 pwm_update_registers(data, nr);
2553 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2554 reg &= 0x0f;
2555 reg |= pwm_enable_to_reg(val) << 4;
2556 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2557 mutex_unlock(&data->update_lock);
2558 return count;
2559 }
2560
2561 static ssize_t
2562 show_pwm_temp_sel_common(struct nct6775_data *data, char *buf, int src)
2563 {
2564 int i, sel = 0;
2565
2566 for (i = 0; i < NUM_TEMP; i++) {
2567 if (!(data->have_temp & BIT(i)))
2568 continue;
2569 if (src == data->temp_src[i]) {
2570 sel = i + 1;
2571 break;
2572 }
2573 }
2574
2575 return sprintf(buf, "%d\n", sel);
2576 }
2577
2578 static ssize_t
2579 show_pwm_temp_sel(struct device *dev, struct device_attribute *attr, char *buf)
2580 {
2581 struct nct6775_data *data = nct6775_update_device(dev);
2582 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2583 int index = sattr->index;
2584
2585 return show_pwm_temp_sel_common(data, buf, data->pwm_temp_sel[index]);
2586 }
2587
2588 static ssize_t
2589 store_pwm_temp_sel(struct device *dev, struct device_attribute *attr,
2590 const char *buf, size_t count)
2591 {
2592 struct nct6775_data *data = nct6775_update_device(dev);
2593 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2594 int nr = sattr->index;
2595 unsigned long val;
2596 int err, reg, src;
2597
2598 err = kstrtoul(buf, 10, &val);
2599 if (err < 0)
2600 return err;
2601 if (val == 0 || val > NUM_TEMP)
2602 return -EINVAL;
2603 if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1])
2604 return -EINVAL;
2605
2606 mutex_lock(&data->update_lock);
2607 src = data->temp_src[val - 1];
2608 data->pwm_temp_sel[nr] = src;
2609 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2610 reg &= 0xe0;
2611 reg |= src;
2612 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2613 mutex_unlock(&data->update_lock);
2614
2615 return count;
2616 }
2617
2618 static ssize_t
2619 show_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2620 char *buf)
2621 {
2622 struct nct6775_data *data = nct6775_update_device(dev);
2623 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2624 int index = sattr->index;
2625
2626 return show_pwm_temp_sel_common(data, buf,
2627 data->pwm_weight_temp_sel[index]);
2628 }
2629
2630 static ssize_t
2631 store_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2632 const char *buf, size_t count)
2633 {
2634 struct nct6775_data *data = nct6775_update_device(dev);
2635 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2636 int nr = sattr->index;
2637 unsigned long val;
2638 int err, reg, src;
2639
2640 err = kstrtoul(buf, 10, &val);
2641 if (err < 0)
2642 return err;
2643 if (val > NUM_TEMP)
2644 return -EINVAL;
2645 if (val && (!(data->have_temp & BIT(val - 1)) ||
2646 !data->temp_src[val - 1]))
2647 return -EINVAL;
2648
2649 mutex_lock(&data->update_lock);
2650 if (val) {
2651 src = data->temp_src[val - 1];
2652 data->pwm_weight_temp_sel[nr] = src;
2653 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2654 reg &= 0xe0;
2655 reg |= (src | 0x80);
2656 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2657 } else {
2658 data->pwm_weight_temp_sel[nr] = 0;
2659 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2660 reg &= 0x7f;
2661 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2662 }
2663 mutex_unlock(&data->update_lock);
2664
2665 return count;
2666 }
2667
2668 static ssize_t
2669 show_target_temp(struct device *dev, struct device_attribute *attr, char *buf)
2670 {
2671 struct nct6775_data *data = nct6775_update_device(dev);
2672 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2673
2674 return sprintf(buf, "%d\n", data->target_temp[sattr->index] * 1000);
2675 }
2676
2677 static ssize_t
2678 store_target_temp(struct device *dev, struct device_attribute *attr,
2679 const char *buf, size_t count)
2680 {
2681 struct nct6775_data *data = dev_get_drvdata(dev);
2682 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2683 int nr = sattr->index;
2684 unsigned long val;
2685 int err;
2686
2687 err = kstrtoul(buf, 10, &val);
2688 if (err < 0)
2689 return err;
2690
2691 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0,
2692 data->target_temp_mask);
2693
2694 mutex_lock(&data->update_lock);
2695 data->target_temp[nr] = val;
2696 pwm_update_registers(data, nr);
2697 mutex_unlock(&data->update_lock);
2698 return count;
2699 }
2700
2701 static ssize_t
2702 show_target_speed(struct device *dev, struct device_attribute *attr, char *buf)
2703 {
2704 struct nct6775_data *data = nct6775_update_device(dev);
2705 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2706 int nr = sattr->index;
2707
2708 return sprintf(buf, "%d\n",
2709 fan_from_reg16(data->target_speed[nr],
2710 data->fan_div[nr]));
2711 }
2712
2713 static ssize_t
2714 store_target_speed(struct device *dev, struct device_attribute *attr,
2715 const char *buf, size_t count)
2716 {
2717 struct nct6775_data *data = dev_get_drvdata(dev);
2718 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2719 int nr = sattr->index;
2720 unsigned long val;
2721 int err;
2722 u16 speed;
2723
2724 err = kstrtoul(buf, 10, &val);
2725 if (err < 0)
2726 return err;
2727
2728 val = clamp_val(val, 0, 1350000U);
2729 speed = fan_to_reg(val, data->fan_div[nr]);
2730
2731 mutex_lock(&data->update_lock);
2732 data->target_speed[nr] = speed;
2733 pwm_update_registers(data, nr);
2734 mutex_unlock(&data->update_lock);
2735 return count;
2736 }
2737
2738 static ssize_t
2739 show_temp_tolerance(struct device *dev, struct device_attribute *attr,
2740 char *buf)
2741 {
2742 struct nct6775_data *data = nct6775_update_device(dev);
2743 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2744 int nr = sattr->nr;
2745 int index = sattr->index;
2746
2747 return sprintf(buf, "%d\n", data->temp_tolerance[index][nr] * 1000);
2748 }
2749
2750 static ssize_t
2751 store_temp_tolerance(struct device *dev, struct device_attribute *attr,
2752 const char *buf, size_t count)
2753 {
2754 struct nct6775_data *data = dev_get_drvdata(dev);
2755 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2756 int nr = sattr->nr;
2757 int index = sattr->index;
2758 unsigned long val;
2759 int err;
2760
2761 err = kstrtoul(buf, 10, &val);
2762 if (err < 0)
2763 return err;
2764
2765 /* Limit tolerance as needed */
2766 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask);
2767
2768 mutex_lock(&data->update_lock);
2769 data->temp_tolerance[index][nr] = val;
2770 if (index)
2771 pwm_update_registers(data, nr);
2772 else
2773 nct6775_write_value(data,
2774 data->REG_CRITICAL_TEMP_TOLERANCE[nr],
2775 val);
2776 mutex_unlock(&data->update_lock);
2777 return count;
2778 }
2779
2780 /*
2781 * Fan speed tolerance is a tricky beast, since the associated register is
2782 * a tick counter, but the value is reported and configured as rpm.
2783 * Compute resulting low and high rpm values and report the difference.
2784 */
2785 static ssize_t
2786 show_speed_tolerance(struct device *dev, struct device_attribute *attr,
2787 char *buf)
2788 {
2789 struct nct6775_data *data = nct6775_update_device(dev);
2790 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2791 int nr = sattr->index;
2792 int low = data->target_speed[nr] - data->target_speed_tolerance[nr];
2793 int high = data->target_speed[nr] + data->target_speed_tolerance[nr];
2794 int tolerance;
2795
2796 if (low <= 0)
2797 low = 1;
2798 if (high > 0xffff)
2799 high = 0xffff;
2800 if (high < low)
2801 high = low;
2802
2803 tolerance = (fan_from_reg16(low, data->fan_div[nr])
2804 - fan_from_reg16(high, data->fan_div[nr])) / 2;
2805
2806 return sprintf(buf, "%d\n", tolerance);
2807 }
2808
2809 static ssize_t
2810 store_speed_tolerance(struct device *dev, struct device_attribute *attr,
2811 const char *buf, size_t count)
2812 {
2813 struct nct6775_data *data = dev_get_drvdata(dev);
2814 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2815 int nr = sattr->index;
2816 unsigned long val;
2817 int err;
2818 int low, high;
2819
2820 err = kstrtoul(buf, 10, &val);
2821 if (err < 0)
2822 return err;
2823
2824 high = fan_from_reg16(data->target_speed[nr],
2825 data->fan_div[nr]) + val;
2826 low = fan_from_reg16(data->target_speed[nr],
2827 data->fan_div[nr]) - val;
2828 if (low <= 0)
2829 low = 1;
2830 if (high < low)
2831 high = low;
2832
2833 val = (fan_to_reg(low, data->fan_div[nr]) -
2834 fan_to_reg(high, data->fan_div[nr])) / 2;
2835
2836 /* Limit tolerance as needed */
2837 val = clamp_val(val, 0, data->speed_tolerance_limit);
2838
2839 mutex_lock(&data->update_lock);
2840 data->target_speed_tolerance[nr] = val;
2841 pwm_update_registers(data, nr);
2842 mutex_unlock(&data->update_lock);
2843 return count;
2844 }
2845
2846 SENSOR_TEMPLATE_2(pwm, "pwm%d", S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 0);
2847 SENSOR_TEMPLATE(pwm_mode, "pwm%d_mode", S_IWUSR | S_IRUGO, show_pwm_mode,
2848 store_pwm_mode, 0);
2849 SENSOR_TEMPLATE(pwm_enable, "pwm%d_enable", S_IWUSR | S_IRUGO, show_pwm_enable,
2850 store_pwm_enable, 0);
2851 SENSOR_TEMPLATE(pwm_temp_sel, "pwm%d_temp_sel", S_IWUSR | S_IRUGO,
2852 show_pwm_temp_sel, store_pwm_temp_sel, 0);
2853 SENSOR_TEMPLATE(pwm_target_temp, "pwm%d_target_temp", S_IWUSR | S_IRUGO,
2854 show_target_temp, store_target_temp, 0);
2855 SENSOR_TEMPLATE(fan_target, "fan%d_target", S_IWUSR | S_IRUGO,
2856 show_target_speed, store_target_speed, 0);
2857 SENSOR_TEMPLATE(fan_tolerance, "fan%d_tolerance", S_IWUSR | S_IRUGO,
2858 show_speed_tolerance, store_speed_tolerance, 0);
2859
2860 /* Smart Fan registers */
2861
2862 static ssize_t
2863 show_weight_temp(struct device *dev, struct device_attribute *attr, char *buf)
2864 {
2865 struct nct6775_data *data = nct6775_update_device(dev);
2866 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2867 int nr = sattr->nr;
2868 int index = sattr->index;
2869
2870 return sprintf(buf, "%d\n", data->weight_temp[index][nr] * 1000);
2871 }
2872
2873 static ssize_t
2874 store_weight_temp(struct device *dev, struct device_attribute *attr,
2875 const char *buf, size_t count)
2876 {
2877 struct nct6775_data *data = dev_get_drvdata(dev);
2878 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2879 int nr = sattr->nr;
2880 int index = sattr->index;
2881 unsigned long val;
2882 int err;
2883
2884 err = kstrtoul(buf, 10, &val);
2885 if (err < 0)
2886 return err;
2887
2888 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255);
2889
2890 mutex_lock(&data->update_lock);
2891 data->weight_temp[index][nr] = val;
2892 nct6775_write_value(data, data->REG_WEIGHT_TEMP[index][nr], val);
2893 mutex_unlock(&data->update_lock);
2894 return count;
2895 }
2896
2897 SENSOR_TEMPLATE(pwm_weight_temp_sel, "pwm%d_weight_temp_sel", S_IWUSR | S_IRUGO,
2898 show_pwm_weight_temp_sel, store_pwm_weight_temp_sel, 0);
2899 SENSOR_TEMPLATE_2(pwm_weight_temp_step, "pwm%d_weight_temp_step",
2900 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 0);
2901 SENSOR_TEMPLATE_2(pwm_weight_temp_step_tol, "pwm%d_weight_temp_step_tol",
2902 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 1);
2903 SENSOR_TEMPLATE_2(pwm_weight_temp_step_base, "pwm%d_weight_temp_step_base",
2904 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 2);
2905 SENSOR_TEMPLATE_2(pwm_weight_duty_step, "pwm%d_weight_duty_step",
2906 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 5);
2907 SENSOR_TEMPLATE_2(pwm_weight_duty_base, "pwm%d_weight_duty_base",
2908 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 6);
2909
2910 static ssize_t
2911 show_fan_time(struct device *dev, struct device_attribute *attr, char *buf)
2912 {
2913 struct nct6775_data *data = nct6775_update_device(dev);
2914 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2915 int nr = sattr->nr;
2916 int index = sattr->index;
2917
2918 return sprintf(buf, "%d\n",
2919 step_time_from_reg(data->fan_time[index][nr],
2920 data->pwm_mode[nr]));
2921 }
2922
2923 static ssize_t
2924 store_fan_time(struct device *dev, struct device_attribute *attr,
2925 const char *buf, size_t count)
2926 {
2927 struct nct6775_data *data = dev_get_drvdata(dev);
2928 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2929 int nr = sattr->nr;
2930 int index = sattr->index;
2931 unsigned long val;
2932 int err;
2933
2934 err = kstrtoul(buf, 10, &val);
2935 if (err < 0)
2936 return err;
2937
2938 val = step_time_to_reg(val, data->pwm_mode[nr]);
2939 mutex_lock(&data->update_lock);
2940 data->fan_time[index][nr] = val;
2941 nct6775_write_value(data, data->REG_FAN_TIME[index][nr], val);
2942 mutex_unlock(&data->update_lock);
2943 return count;
2944 }
2945
2946 static ssize_t
2947 show_auto_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2948 {
2949 struct nct6775_data *data = nct6775_update_device(dev);
2950 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2951
2952 return sprintf(buf, "%d\n", data->auto_pwm[sattr->nr][sattr->index]);
2953 }
2954
2955 static ssize_t
2956 store_auto_pwm(struct device *dev, struct device_attribute *attr,
2957 const char *buf, size_t count)
2958 {
2959 struct nct6775_data *data = dev_get_drvdata(dev);
2960 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2961 int nr = sattr->nr;
2962 int point = sattr->index;
2963 unsigned long val;
2964 int err;
2965 u8 reg;
2966
2967 err = kstrtoul(buf, 10, &val);
2968 if (err < 0)
2969 return err;
2970 if (val > 255)
2971 return -EINVAL;
2972
2973 if (point == data->auto_pwm_num) {
2974 if (data->kind != nct6775 && !val)
2975 return -EINVAL;
2976 if (data->kind != nct6779 && val)
2977 val = 0xff;
2978 }
2979
2980 mutex_lock(&data->update_lock);
2981 data->auto_pwm[nr][point] = val;
2982 if (point < data->auto_pwm_num) {
2983 nct6775_write_value(data,
2984 NCT6775_AUTO_PWM(data, nr, point),
2985 data->auto_pwm[nr][point]);
2986 } else {
2987 switch (data->kind) {
2988 case nct6775:
2989 /* disable if needed (pwm == 0) */
2990 reg = nct6775_read_value(data,
2991 NCT6775_REG_CRITICAL_ENAB[nr]);
2992 if (val)
2993 reg |= 0x02;
2994 else
2995 reg &= ~0x02;
2996 nct6775_write_value(data, NCT6775_REG_CRITICAL_ENAB[nr],
2997 reg);
2998 break;
2999 case nct6776:
3000 break; /* always enabled, nothing to do */
3001 case nct6106:
3002 case nct6779:
3003 case nct6791:
3004 case nct6792:
3005 case nct6793:
3006 case nct6795:
3007 nct6775_write_value(data, data->REG_CRITICAL_PWM[nr],
3008 val);
3009 reg = nct6775_read_value(data,
3010 data->REG_CRITICAL_PWM_ENABLE[nr]);
3011 if (val == 255)
3012 reg &= ~data->CRITICAL_PWM_ENABLE_MASK;
3013 else
3014 reg |= data->CRITICAL_PWM_ENABLE_MASK;
3015 nct6775_write_value(data,
3016 data->REG_CRITICAL_PWM_ENABLE[nr],
3017 reg);
3018 break;
3019 }
3020 }
3021 mutex_unlock(&data->update_lock);
3022 return count;
3023 }
3024
3025 static ssize_t
3026 show_auto_temp(struct device *dev, struct device_attribute *attr, char *buf)
3027 {
3028 struct nct6775_data *data = nct6775_update_device(dev);
3029 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3030 int nr = sattr->nr;
3031 int point = sattr->index;
3032
3033 /*
3034 * We don't know for sure if the temperature is signed or unsigned.
3035 * Assume it is unsigned.
3036 */
3037 return sprintf(buf, "%d\n", data->auto_temp[nr][point] * 1000);
3038 }
3039
3040 static ssize_t
3041 store_auto_temp(struct device *dev, struct device_attribute *attr,
3042 const char *buf, size_t count)
3043 {
3044 struct nct6775_data *data = dev_get_drvdata(dev);
3045 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3046 int nr = sattr->nr;
3047 int point = sattr->index;
3048 unsigned long val;
3049 int err;
3050
3051 err = kstrtoul(buf, 10, &val);
3052 if (err)
3053 return err;
3054 if (val > 255000)
3055 return -EINVAL;
3056
3057 mutex_lock(&data->update_lock);
3058 data->auto_temp[nr][point] = DIV_ROUND_CLOSEST(val, 1000);
3059 if (point < data->auto_pwm_num) {
3060 nct6775_write_value(data,
3061 NCT6775_AUTO_TEMP(data, nr, point),
3062 data->auto_temp[nr][point]);
3063 } else {
3064 nct6775_write_value(data, data->REG_CRITICAL_TEMP[nr],
3065 data->auto_temp[nr][point]);
3066 }
3067 mutex_unlock(&data->update_lock);
3068 return count;
3069 }
3070
3071 static umode_t nct6775_pwm_is_visible(struct kobject *kobj,
3072 struct attribute *attr, int index)
3073 {
3074 struct device *dev = container_of(kobj, struct device, kobj);
3075 struct nct6775_data *data = dev_get_drvdata(dev);
3076 int pwm = index / 36; /* pwm index */
3077 int nr = index % 36; /* attribute index */
3078
3079 if (!(data->has_pwm & BIT(pwm)))
3080 return 0;
3081
3082 if ((nr >= 14 && nr <= 18) || nr == 21) /* weight */
3083 if (!data->REG_WEIGHT_TEMP_SEL[pwm])
3084 return 0;
3085 if (nr == 19 && data->REG_PWM[3] == NULL) /* pwm_max */
3086 return 0;
3087 if (nr == 20 && data->REG_PWM[4] == NULL) /* pwm_step */
3088 return 0;
3089 if (nr == 21 && data->REG_PWM[6] == NULL) /* weight_duty_base */
3090 return 0;
3091
3092 if (nr >= 22 && nr <= 35) { /* auto point */
3093 int api = (nr - 22) / 2; /* auto point index */
3094
3095 if (api > data->auto_pwm_num)
3096 return 0;
3097 }
3098 return attr->mode;
3099 }
3100
3101 SENSOR_TEMPLATE_2(pwm_stop_time, "pwm%d_stop_time", S_IWUSR | S_IRUGO,
3102 show_fan_time, store_fan_time, 0, 0);
3103 SENSOR_TEMPLATE_2(pwm_step_up_time, "pwm%d_step_up_time", S_IWUSR | S_IRUGO,
3104 show_fan_time, store_fan_time, 0, 1);
3105 SENSOR_TEMPLATE_2(pwm_step_down_time, "pwm%d_step_down_time", S_IWUSR | S_IRUGO,
3106 show_fan_time, store_fan_time, 0, 2);
3107 SENSOR_TEMPLATE_2(pwm_start, "pwm%d_start", S_IWUSR | S_IRUGO, show_pwm,
3108 store_pwm, 0, 1);
3109 SENSOR_TEMPLATE_2(pwm_floor, "pwm%d_floor", S_IWUSR | S_IRUGO, show_pwm,
3110 store_pwm, 0, 2);
3111 SENSOR_TEMPLATE_2(pwm_temp_tolerance, "pwm%d_temp_tolerance", S_IWUSR | S_IRUGO,
3112 show_temp_tolerance, store_temp_tolerance, 0, 0);
3113 SENSOR_TEMPLATE_2(pwm_crit_temp_tolerance, "pwm%d_crit_temp_tolerance",
3114 S_IWUSR | S_IRUGO, show_temp_tolerance, store_temp_tolerance,
3115 0, 1);
3116
3117 SENSOR_TEMPLATE_2(pwm_max, "pwm%d_max", S_IWUSR | S_IRUGO, show_pwm, store_pwm,
3118 0, 3);
3119
3120 SENSOR_TEMPLATE_2(pwm_step, "pwm%d_step", S_IWUSR | S_IRUGO, show_pwm,
3121 store_pwm, 0, 4);
3122
3123 SENSOR_TEMPLATE_2(pwm_auto_point1_pwm, "pwm%d_auto_point1_pwm",
3124 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 0);
3125 SENSOR_TEMPLATE_2(pwm_auto_point1_temp, "pwm%d_auto_point1_temp",
3126 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 0);
3127
3128 SENSOR_TEMPLATE_2(pwm_auto_point2_pwm, "pwm%d_auto_point2_pwm",
3129 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 1);
3130 SENSOR_TEMPLATE_2(pwm_auto_point2_temp, "pwm%d_auto_point2_temp",
3131 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 1);
3132
3133 SENSOR_TEMPLATE_2(pwm_auto_point3_pwm, "pwm%d_auto_point3_pwm",
3134 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 2);
3135 SENSOR_TEMPLATE_2(pwm_auto_point3_temp, "pwm%d_auto_point3_temp",
3136 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 2);
3137
3138 SENSOR_TEMPLATE_2(pwm_auto_point4_pwm, "pwm%d_auto_point4_pwm",
3139 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 3);
3140 SENSOR_TEMPLATE_2(pwm_auto_point4_temp, "pwm%d_auto_point4_temp",
3141 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 3);
3142
3143 SENSOR_TEMPLATE_2(pwm_auto_point5_pwm, "pwm%d_auto_point5_pwm",
3144 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 4);
3145 SENSOR_TEMPLATE_2(pwm_auto_point5_temp, "pwm%d_auto_point5_temp",
3146 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 4);
3147
3148 SENSOR_TEMPLATE_2(pwm_auto_point6_pwm, "pwm%d_auto_point6_pwm",
3149 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 5);
3150 SENSOR_TEMPLATE_2(pwm_auto_point6_temp, "pwm%d_auto_point6_temp",
3151 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 5);
3152
3153 SENSOR_TEMPLATE_2(pwm_auto_point7_pwm, "pwm%d_auto_point7_pwm",
3154 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 6);
3155 SENSOR_TEMPLATE_2(pwm_auto_point7_temp, "pwm%d_auto_point7_temp",
3156 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 6);
3157
3158 /*
3159 * nct6775_pwm_is_visible uses the index into the following array
3160 * to determine if attributes should be created or not.
3161 * Any change in order or content must be matched.
3162 */
3163 static struct sensor_device_template *nct6775_attributes_pwm_template[] = {
3164 &sensor_dev_template_pwm,
3165 &sensor_dev_template_pwm_mode,
3166 &sensor_dev_template_pwm_enable,
3167 &sensor_dev_template_pwm_temp_sel,
3168 &sensor_dev_template_pwm_temp_tolerance,
3169 &sensor_dev_template_pwm_crit_temp_tolerance,
3170 &sensor_dev_template_pwm_target_temp,
3171 &sensor_dev_template_fan_target,
3172 &sensor_dev_template_fan_tolerance,
3173 &sensor_dev_template_pwm_stop_time,
3174 &sensor_dev_template_pwm_step_up_time,
3175 &sensor_dev_template_pwm_step_down_time,
3176 &sensor_dev_template_pwm_start,
3177 &sensor_dev_template_pwm_floor,
3178 &sensor_dev_template_pwm_weight_temp_sel, /* 14 */
3179 &sensor_dev_template_pwm_weight_temp_step,
3180 &sensor_dev_template_pwm_weight_temp_step_tol,
3181 &sensor_dev_template_pwm_weight_temp_step_base,
3182 &sensor_dev_template_pwm_weight_duty_step, /* 18 */
3183 &sensor_dev_template_pwm_max, /* 19 */
3184 &sensor_dev_template_pwm_step, /* 20 */
3185 &sensor_dev_template_pwm_weight_duty_base, /* 21 */
3186 &sensor_dev_template_pwm_auto_point1_pwm, /* 22 */
3187 &sensor_dev_template_pwm_auto_point1_temp,
3188 &sensor_dev_template_pwm_auto_point2_pwm,
3189 &sensor_dev_template_pwm_auto_point2_temp,
3190 &sensor_dev_template_pwm_auto_point3_pwm,
3191 &sensor_dev_template_pwm_auto_point3_temp,
3192 &sensor_dev_template_pwm_auto_point4_pwm,
3193 &sensor_dev_template_pwm_auto_point4_temp,
3194 &sensor_dev_template_pwm_auto_point5_pwm,
3195 &sensor_dev_template_pwm_auto_point5_temp,
3196 &sensor_dev_template_pwm_auto_point6_pwm,
3197 &sensor_dev_template_pwm_auto_point6_temp,
3198 &sensor_dev_template_pwm_auto_point7_pwm,
3199 &sensor_dev_template_pwm_auto_point7_temp, /* 35 */
3200
3201 NULL
3202 };
3203
3204 static const struct sensor_template_group nct6775_pwm_template_group = {
3205 .templates = nct6775_attributes_pwm_template,
3206 .is_visible = nct6775_pwm_is_visible,
3207 .base = 1,
3208 };
3209
3210 static ssize_t
3211 cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
3212 {
3213 struct nct6775_data *data = dev_get_drvdata(dev);
3214
3215 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
3216 }
3217
3218 static DEVICE_ATTR_RO(cpu0_vid);
3219
3220 /* Case open detection */
3221
3222 static ssize_t
3223 clear_caseopen(struct device *dev, struct device_attribute *attr,
3224 const char *buf, size_t count)
3225 {
3226 struct nct6775_data *data = dev_get_drvdata(dev);
3227 int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE;
3228 unsigned long val;
3229 u8 reg;
3230 int ret;
3231
3232 if (kstrtoul(buf, 10, &val) || val != 0)
3233 return -EINVAL;
3234
3235 mutex_lock(&data->update_lock);
3236
3237 /*
3238 * Use CR registers to clear caseopen status.
3239 * The CR registers are the same for all chips, and not all chips
3240 * support clearing the caseopen status through "regular" registers.
3241 */
3242 ret = superio_enter(data->sioreg);
3243 if (ret) {
3244 count = ret;
3245 goto error;
3246 }
3247
3248 superio_select(data->sioreg, NCT6775_LD_ACPI);
3249 reg = superio_inb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]);
3250 reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3251 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3252 reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3253 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3254 superio_exit(data->sioreg);
3255
3256 data->valid = false; /* Force cache refresh */
3257 error:
3258 mutex_unlock(&data->update_lock);
3259 return count;
3260 }
3261
3262 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm,
3263 clear_caseopen, INTRUSION_ALARM_BASE);
3264 static SENSOR_DEVICE_ATTR(intrusion1_alarm, S_IWUSR | S_IRUGO, show_alarm,
3265 clear_caseopen, INTRUSION_ALARM_BASE + 1);
3266 static SENSOR_DEVICE_ATTR(intrusion0_beep, S_IWUSR | S_IRUGO, show_beep,
3267 store_beep, INTRUSION_ALARM_BASE);
3268 static SENSOR_DEVICE_ATTR(intrusion1_beep, S_IWUSR | S_IRUGO, show_beep,
3269 store_beep, INTRUSION_ALARM_BASE + 1);
3270 static SENSOR_DEVICE_ATTR(beep_enable, S_IWUSR | S_IRUGO, show_beep,
3271 store_beep, BEEP_ENABLE_BASE);
3272
3273 static umode_t nct6775_other_is_visible(struct kobject *kobj,
3274 struct attribute *attr, int index)
3275 {
3276 struct device *dev = container_of(kobj, struct device, kobj);
3277 struct nct6775_data *data = dev_get_drvdata(dev);
3278
3279 if (index == 0 && !data->have_vid)
3280 return 0;
3281
3282 if (index == 1 || index == 2) {
3283 if (data->ALARM_BITS[INTRUSION_ALARM_BASE + index - 1] < 0)
3284 return 0;
3285 }
3286
3287 if (index == 3 || index == 4) {
3288 if (data->BEEP_BITS[INTRUSION_ALARM_BASE + index - 3] < 0)
3289 return 0;
3290 }
3291
3292 return attr->mode;
3293 }
3294
3295 /*
3296 * nct6775_other_is_visible uses the index into the following array
3297 * to determine if attributes should be created or not.
3298 * Any change in order or content must be matched.
3299 */
3300 static struct attribute *nct6775_attributes_other[] = {
3301 &dev_attr_cpu0_vid.attr, /* 0 */
3302 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, /* 1 */
3303 &sensor_dev_attr_intrusion1_alarm.dev_attr.attr, /* 2 */
3304 &sensor_dev_attr_intrusion0_beep.dev_attr.attr, /* 3 */
3305 &sensor_dev_attr_intrusion1_beep.dev_attr.attr, /* 4 */
3306 &sensor_dev_attr_beep_enable.dev_attr.attr, /* 5 */
3307
3308 NULL
3309 };
3310
3311 static const struct attribute_group nct6775_group_other = {
3312 .attrs = nct6775_attributes_other,
3313 .is_visible = nct6775_other_is_visible,
3314 };
3315
3316 static inline void nct6775_init_device(struct nct6775_data *data)
3317 {
3318 int i;
3319 u8 tmp, diode;
3320
3321 /* Start monitoring if needed */
3322 if (data->REG_CONFIG) {
3323 tmp = nct6775_read_value(data, data->REG_CONFIG);
3324 if (!(tmp & 0x01))
3325 nct6775_write_value(data, data->REG_CONFIG, tmp | 0x01);
3326 }
3327
3328 /* Enable temperature sensors if needed */
3329 for (i = 0; i < NUM_TEMP; i++) {
3330 if (!(data->have_temp & BIT(i)))
3331 continue;
3332 if (!data->reg_temp_config[i])
3333 continue;
3334 tmp = nct6775_read_value(data, data->reg_temp_config[i]);
3335 if (tmp & 0x01)
3336 nct6775_write_value(data, data->reg_temp_config[i],
3337 tmp & 0xfe);
3338 }
3339
3340 /* Enable VBAT monitoring if needed */
3341 tmp = nct6775_read_value(data, data->REG_VBAT);
3342 if (!(tmp & 0x01))
3343 nct6775_write_value(data, data->REG_VBAT, tmp | 0x01);
3344
3345 diode = nct6775_read_value(data, data->REG_DIODE);
3346
3347 for (i = 0; i < data->temp_fixed_num; i++) {
3348 if (!(data->have_temp_fixed & BIT(i)))
3349 continue;
3350 if ((tmp & (data->DIODE_MASK << i))) /* diode */
3351 data->temp_type[i]
3352 = 3 - ((diode >> i) & data->DIODE_MASK);
3353 else /* thermistor */
3354 data->temp_type[i] = 4;
3355 }
3356 }
3357
3358 static void
3359 nct6775_check_fan_inputs(struct nct6775_data *data)
3360 {
3361 bool fan3pin, fan4pin, fan4min, fan5pin, fan6pin;
3362 bool pwm3pin, pwm4pin, pwm5pin, pwm6pin;
3363 int sioreg = data->sioreg;
3364 int regval;
3365
3366 /* Store SIO_REG_ENABLE for use during resume */
3367 superio_select(sioreg, NCT6775_LD_HWM);
3368 data->sio_reg_enable = superio_inb(sioreg, SIO_REG_ENABLE);
3369
3370 /* fan4 and fan5 share some pins with the GPIO and serial flash */
3371 if (data->kind == nct6775) {
3372 regval = superio_inb(sioreg, 0x2c);
3373
3374 fan3pin = regval & BIT(6);
3375 pwm3pin = regval & BIT(7);
3376
3377 /* On NCT6775, fan4 shares pins with the fdc interface */
3378 fan4pin = !(superio_inb(sioreg, 0x2A) & 0x80);
3379 fan4min = false;
3380 fan5pin = false;
3381 fan6pin = false;
3382 pwm4pin = false;
3383 pwm5pin = false;
3384 pwm6pin = false;
3385 } else if (data->kind == nct6776) {
3386 bool gpok = superio_inb(sioreg, 0x27) & 0x80;
3387 const char *board_vendor, *board_name;
3388
3389 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
3390 board_name = dmi_get_system_info(DMI_BOARD_NAME);
3391
3392 if (board_name && board_vendor &&
3393 !strcmp(board_vendor, "ASRock")) {
3394 /*
3395 * Auxiliary fan monitoring is not enabled on ASRock
3396 * Z77 Pro4-M if booted in UEFI Ultra-FastBoot mode.
3397 * Observed with BIOS version 2.00.
3398 */
3399 if (!strcmp(board_name, "Z77 Pro4-M")) {
3400 if ((data->sio_reg_enable & 0xe0) != 0xe0) {
3401 data->sio_reg_enable |= 0xe0;
3402 superio_outb(sioreg, SIO_REG_ENABLE,
3403 data->sio_reg_enable);
3404 }
3405 }
3406 }
3407
3408 if (data->sio_reg_enable & 0x80)
3409 fan3pin = gpok;
3410 else
3411 fan3pin = !(superio_inb(sioreg, 0x24) & 0x40);
3412
3413 if (data->sio_reg_enable & 0x40)
3414 fan4pin = gpok;
3415 else
3416 fan4pin = superio_inb(sioreg, 0x1C) & 0x01;
3417
3418 if (data->sio_reg_enable & 0x20)
3419 fan5pin = gpok;
3420 else
3421 fan5pin = superio_inb(sioreg, 0x1C) & 0x02;
3422
3423 fan4min = fan4pin;
3424 fan6pin = false;
3425 pwm3pin = fan3pin;
3426 pwm4pin = false;
3427 pwm5pin = false;
3428 pwm6pin = false;
3429 } else if (data->kind == nct6106) {
3430 regval = superio_inb(sioreg, 0x24);
3431 fan3pin = !(regval & 0x80);
3432 pwm3pin = regval & 0x08;
3433
3434 fan4pin = false;
3435 fan4min = false;
3436 fan5pin = false;
3437 fan6pin = false;
3438 pwm4pin = false;
3439 pwm5pin = false;
3440 pwm6pin = false;
3441 } else { /* NCT6779D, NCT6791D, NCT6792D, NCT6793D, or NCT6795D */
3442 int regval_1b, regval_2a, regval_eb;
3443
3444 regval = superio_inb(sioreg, 0x1c);
3445
3446 fan3pin = !(regval & BIT(5));
3447 fan4pin = !(regval & BIT(6));
3448 fan5pin = !(regval & BIT(7));
3449
3450 pwm3pin = !(regval & BIT(0));
3451 pwm4pin = !(regval & BIT(1));
3452 pwm5pin = !(regval & BIT(2));
3453
3454 regval = superio_inb(sioreg, 0x2d);
3455 switch (data->kind) {
3456 case nct6791:
3457 case nct6792:
3458 fan6pin = regval & BIT(1);
3459 pwm6pin = regval & BIT(0);
3460 break;
3461 case nct6793:
3462 case nct6795:
3463 regval_1b = superio_inb(sioreg, 0x1b);
3464 regval_2a = superio_inb(sioreg, 0x2a);
3465
3466 if (!pwm5pin)
3467 pwm5pin = regval & BIT(7);
3468 fan6pin = regval & BIT(1);
3469 pwm6pin = regval & BIT(0);
3470 if (!fan5pin)
3471 fan5pin = regval_1b & BIT(5);
3472
3473 superio_select(sioreg, NCT6775_LD_12);
3474 regval_eb = superio_inb(sioreg, 0xeb);
3475 if (!fan5pin)
3476 fan5pin = regval_eb & BIT(5);
3477 if (!pwm5pin)
3478 pwm5pin = (regval_eb & BIT(4)) &&
3479 !(regval_2a & BIT(0));
3480 if (!fan6pin)
3481 fan6pin = regval_eb & BIT(3);
3482 if (!pwm6pin)
3483 pwm6pin = regval_eb & BIT(2);
3484 break;
3485 default: /* NCT6779D */
3486 fan6pin = false;
3487 pwm6pin = false;
3488 break;
3489 }
3490
3491 fan4min = fan4pin;
3492 }
3493
3494 /* fan 1 and 2 (0x03) are always present */
3495 data->has_fan = 0x03 | (fan3pin << 2) | (fan4pin << 3) |
3496 (fan5pin << 4) | (fan6pin << 5);
3497 data->has_fan_min = 0x03 | (fan3pin << 2) | (fan4min << 3) |
3498 (fan5pin << 4);
3499 data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) |
3500 (pwm5pin << 4) | (pwm6pin << 5);
3501 }
3502
3503 static void add_temp_sensors(struct nct6775_data *data, const u16 *regp,
3504 int *available, int *mask)
3505 {
3506 int i;
3507 u8 src;
3508
3509 for (i = 0; i < data->pwm_num && *available; i++) {
3510 int index;
3511
3512 if (!regp[i])
3513 continue;
3514 src = nct6775_read_value(data, regp[i]);
3515 src &= 0x1f;
3516 if (!src || (*mask & BIT(src)))
3517 continue;
3518 if (!(data->temp_mask & BIT(src)))
3519 continue;
3520
3521 index = __ffs(*available);
3522 nct6775_write_value(data, data->REG_TEMP_SOURCE[index], src);
3523 *available &= ~BIT(index);
3524 *mask |= BIT(src);
3525 }
3526 }
3527
3528 static int nct6775_probe(struct platform_device *pdev)
3529 {
3530 struct device *dev = &pdev->dev;
3531 struct nct6775_sio_data *sio_data = dev_get_platdata(dev);
3532 struct nct6775_data *data;
3533 struct resource *res;
3534 int i, s, err = 0;
3535 int src, mask, available;
3536 const u16 *reg_temp, *reg_temp_over, *reg_temp_hyst, *reg_temp_config;
3537 const u16 *reg_temp_mon, *reg_temp_alternate, *reg_temp_crit;
3538 const u16 *reg_temp_crit_l = NULL, *reg_temp_crit_h = NULL;
3539 int num_reg_temp, num_reg_temp_mon;
3540 u8 cr2a;
3541 struct attribute_group *group;
3542 struct device *hwmon_dev;
3543 int num_attr_groups = 0;
3544
3545 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3546 if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH,
3547 DRVNAME))
3548 return -EBUSY;
3549
3550 data = devm_kzalloc(&pdev->dev, sizeof(struct nct6775_data),
3551 GFP_KERNEL);
3552 if (!data)
3553 return -ENOMEM;
3554
3555 data->kind = sio_data->kind;
3556 data->sioreg = sio_data->sioreg;
3557 data->addr = res->start;
3558 mutex_init(&data->update_lock);
3559 data->name = nct6775_device_names[data->kind];
3560 data->bank = 0xff; /* Force initial bank selection */
3561 platform_set_drvdata(pdev, data);
3562
3563 switch (data->kind) {
3564 case nct6106:
3565 data->in_num = 9;
3566 data->pwm_num = 3;
3567 data->auto_pwm_num = 4;
3568 data->temp_fixed_num = 3;
3569 data->num_temp_alarms = 6;
3570 data->num_temp_beeps = 6;
3571
3572 data->fan_from_reg = fan_from_reg13;
3573 data->fan_from_reg_min = fan_from_reg13;
3574
3575 data->temp_label = nct6776_temp_label;
3576 data->temp_mask = NCT6776_TEMP_MASK;
3577
3578 data->REG_VBAT = NCT6106_REG_VBAT;
3579 data->REG_DIODE = NCT6106_REG_DIODE;
3580 data->DIODE_MASK = NCT6106_DIODE_MASK;
3581 data->REG_VIN = NCT6106_REG_IN;
3582 data->REG_IN_MINMAX[0] = NCT6106_REG_IN_MIN;
3583 data->REG_IN_MINMAX[1] = NCT6106_REG_IN_MAX;
3584 data->REG_TARGET = NCT6106_REG_TARGET;
3585 data->REG_FAN = NCT6106_REG_FAN;
3586 data->REG_FAN_MODE = NCT6106_REG_FAN_MODE;
3587 data->REG_FAN_MIN = NCT6106_REG_FAN_MIN;
3588 data->REG_FAN_PULSES = NCT6106_REG_FAN_PULSES;
3589 data->FAN_PULSE_SHIFT = NCT6106_FAN_PULSE_SHIFT;
3590 data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME;
3591 data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME;
3592 data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME;
3593 data->REG_PWM[0] = NCT6106_REG_PWM;
3594 data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT;
3595 data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT;
3596 data->REG_PWM[5] = NCT6106_REG_WEIGHT_DUTY_STEP;
3597 data->REG_PWM[6] = NCT6106_REG_WEIGHT_DUTY_BASE;
3598 data->REG_PWM_READ = NCT6106_REG_PWM_READ;
3599 data->REG_PWM_MODE = NCT6106_REG_PWM_MODE;
3600 data->PWM_MODE_MASK = NCT6106_PWM_MODE_MASK;
3601 data->REG_AUTO_TEMP = NCT6106_REG_AUTO_TEMP;
3602 data->REG_AUTO_PWM = NCT6106_REG_AUTO_PWM;
3603 data->REG_CRITICAL_TEMP = NCT6106_REG_CRITICAL_TEMP;
3604 data->REG_CRITICAL_TEMP_TOLERANCE
3605 = NCT6106_REG_CRITICAL_TEMP_TOLERANCE;
3606 data->REG_CRITICAL_PWM_ENABLE = NCT6106_REG_CRITICAL_PWM_ENABLE;
3607 data->CRITICAL_PWM_ENABLE_MASK
3608 = NCT6106_CRITICAL_PWM_ENABLE_MASK;
3609 data->REG_CRITICAL_PWM = NCT6106_REG_CRITICAL_PWM;
3610 data->REG_TEMP_OFFSET = NCT6106_REG_TEMP_OFFSET;
3611 data->REG_TEMP_SOURCE = NCT6106_REG_TEMP_SOURCE;
3612 data->REG_TEMP_SEL = NCT6106_REG_TEMP_SEL;
3613 data->REG_WEIGHT_TEMP_SEL = NCT6106_REG_WEIGHT_TEMP_SEL;
3614 data->REG_WEIGHT_TEMP[0] = NCT6106_REG_WEIGHT_TEMP_STEP;
3615 data->REG_WEIGHT_TEMP[1] = NCT6106_REG_WEIGHT_TEMP_STEP_TOL;
3616 data->REG_WEIGHT_TEMP[2] = NCT6106_REG_WEIGHT_TEMP_BASE;
3617 data->REG_ALARM = NCT6106_REG_ALARM;
3618 data->ALARM_BITS = NCT6106_ALARM_BITS;
3619 data->REG_BEEP = NCT6106_REG_BEEP;
3620 data->BEEP_BITS = NCT6106_BEEP_BITS;
3621
3622 reg_temp = NCT6106_REG_TEMP;
3623 reg_temp_mon = NCT6106_REG_TEMP_MON;
3624 num_reg_temp = ARRAY_SIZE(NCT6106_REG_TEMP);
3625 num_reg_temp_mon = ARRAY_SIZE(NCT6106_REG_TEMP_MON);
3626 reg_temp_over = NCT6106_REG_TEMP_OVER;
3627 reg_temp_hyst = NCT6106_REG_TEMP_HYST;
3628 reg_temp_config = NCT6106_REG_TEMP_CONFIG;
3629 reg_temp_alternate = NCT6106_REG_TEMP_ALTERNATE;
3630 reg_temp_crit = NCT6106_REG_TEMP_CRIT;
3631 reg_temp_crit_l = NCT6106_REG_TEMP_CRIT_L;
3632 reg_temp_crit_h = NCT6106_REG_TEMP_CRIT_H;
3633
3634 break;
3635 case nct6775:
3636 data->in_num = 9;
3637 data->pwm_num = 3;
3638 data->auto_pwm_num = 6;
3639 data->has_fan_div = true;
3640 data->temp_fixed_num = 3;
3641 data->num_temp_alarms = 3;
3642 data->num_temp_beeps = 3;
3643
3644 data->ALARM_BITS = NCT6775_ALARM_BITS;
3645 data->BEEP_BITS = NCT6775_BEEP_BITS;
3646
3647 data->fan_from_reg = fan_from_reg16;
3648 data->fan_from_reg_min = fan_from_reg8;
3649 data->target_temp_mask = 0x7f;
3650 data->tolerance_mask = 0x0f;
3651 data->speed_tolerance_limit = 15;
3652
3653 data->temp_label = nct6775_temp_label;
3654 data->temp_mask = NCT6775_TEMP_MASK;
3655
3656 data->REG_CONFIG = NCT6775_REG_CONFIG;
3657 data->REG_VBAT = NCT6775_REG_VBAT;
3658 data->REG_DIODE = NCT6775_REG_DIODE;
3659 data->DIODE_MASK = NCT6775_DIODE_MASK;
3660 data->REG_VIN = NCT6775_REG_IN;
3661 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3662 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3663 data->REG_TARGET = NCT6775_REG_TARGET;
3664 data->REG_FAN = NCT6775_REG_FAN;
3665 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3666 data->REG_FAN_MIN = NCT6775_REG_FAN_MIN;
3667 data->REG_FAN_PULSES = NCT6775_REG_FAN_PULSES;
3668 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3669 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3670 data->REG_FAN_TIME[1] = NCT6775_REG_FAN_STEP_UP_TIME;
3671 data->REG_FAN_TIME[2] = NCT6775_REG_FAN_STEP_DOWN_TIME;
3672 data->REG_PWM[0] = NCT6775_REG_PWM;
3673 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3674 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3675 data->REG_PWM[3] = NCT6775_REG_FAN_MAX_OUTPUT;
3676 data->REG_PWM[4] = NCT6775_REG_FAN_STEP_OUTPUT;
3677 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3678 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3679 data->REG_PWM_MODE = NCT6775_REG_PWM_MODE;
3680 data->PWM_MODE_MASK = NCT6775_PWM_MODE_MASK;
3681 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3682 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3683 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3684 data->REG_CRITICAL_TEMP_TOLERANCE
3685 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3686 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3687 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3688 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3689 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3690 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3691 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3692 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3693 data->REG_ALARM = NCT6775_REG_ALARM;
3694 data->REG_BEEP = NCT6775_REG_BEEP;
3695
3696 reg_temp = NCT6775_REG_TEMP;
3697 reg_temp_mon = NCT6775_REG_TEMP_MON;
3698 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3699 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3700 reg_temp_over = NCT6775_REG_TEMP_OVER;
3701 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3702 reg_temp_config = NCT6775_REG_TEMP_CONFIG;
3703 reg_temp_alternate = NCT6775_REG_TEMP_ALTERNATE;
3704 reg_temp_crit = NCT6775_REG_TEMP_CRIT;
3705
3706 break;
3707 case nct6776:
3708 data->in_num = 9;
3709 data->pwm_num = 3;
3710 data->auto_pwm_num = 4;
3711 data->has_fan_div = false;
3712 data->temp_fixed_num = 3;
3713 data->num_temp_alarms = 3;
3714 data->num_temp_beeps = 6;
3715
3716 data->ALARM_BITS = NCT6776_ALARM_BITS;
3717 data->BEEP_BITS = NCT6776_BEEP_BITS;
3718
3719 data->fan_from_reg = fan_from_reg13;
3720 data->fan_from_reg_min = fan_from_reg13;
3721 data->target_temp_mask = 0xff;
3722 data->tolerance_mask = 0x07;
3723 data->speed_tolerance_limit = 63;
3724
3725 data->temp_label = nct6776_temp_label;
3726 data->temp_mask = NCT6776_TEMP_MASK;
3727
3728 data->REG_CONFIG = NCT6775_REG_CONFIG;
3729 data->REG_VBAT = NCT6775_REG_VBAT;
3730 data->REG_DIODE = NCT6775_REG_DIODE;
3731 data->DIODE_MASK = NCT6775_DIODE_MASK;
3732 data->REG_VIN = NCT6775_REG_IN;
3733 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3734 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3735 data->REG_TARGET = NCT6775_REG_TARGET;
3736 data->REG_FAN = NCT6775_REG_FAN;
3737 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3738 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3739 data->REG_FAN_PULSES = NCT6776_REG_FAN_PULSES;
3740 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3741 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3742 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3743 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3744 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3745 data->REG_PWM[0] = NCT6775_REG_PWM;
3746 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3747 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3748 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3749 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3750 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3751 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3752 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3753 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3754 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3755 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3756 data->REG_CRITICAL_TEMP_TOLERANCE
3757 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3758 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3759 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3760 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3761 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3762 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3763 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3764 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3765 data->REG_ALARM = NCT6775_REG_ALARM;
3766 data->REG_BEEP = NCT6776_REG_BEEP;
3767
3768 reg_temp = NCT6775_REG_TEMP;
3769 reg_temp_mon = NCT6775_REG_TEMP_MON;
3770 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3771 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3772 reg_temp_over = NCT6775_REG_TEMP_OVER;
3773 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3774 reg_temp_config = NCT6776_REG_TEMP_CONFIG;
3775 reg_temp_alternate = NCT6776_REG_TEMP_ALTERNATE;
3776 reg_temp_crit = NCT6776_REG_TEMP_CRIT;
3777
3778 break;
3779 case nct6779:
3780 data->in_num = 15;
3781 data->pwm_num = 5;
3782 data->auto_pwm_num = 4;
3783 data->has_fan_div = false;
3784 data->temp_fixed_num = 6;
3785 data->num_temp_alarms = 2;
3786 data->num_temp_beeps = 2;
3787
3788 data->ALARM_BITS = NCT6779_ALARM_BITS;
3789 data->BEEP_BITS = NCT6779_BEEP_BITS;
3790
3791 data->fan_from_reg = fan_from_reg13;
3792 data->fan_from_reg_min = fan_from_reg13;
3793 data->target_temp_mask = 0xff;
3794 data->tolerance_mask = 0x07;
3795 data->speed_tolerance_limit = 63;
3796
3797 data->temp_label = nct6779_temp_label;
3798 data->temp_mask = NCT6779_TEMP_MASK;
3799
3800 data->REG_CONFIG = NCT6775_REG_CONFIG;
3801 data->REG_VBAT = NCT6775_REG_VBAT;
3802 data->REG_DIODE = NCT6775_REG_DIODE;
3803 data->DIODE_MASK = NCT6775_DIODE_MASK;
3804 data->REG_VIN = NCT6779_REG_IN;
3805 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3806 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3807 data->REG_TARGET = NCT6775_REG_TARGET;
3808 data->REG_FAN = NCT6779_REG_FAN;
3809 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3810 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3811 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3812 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3813 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3814 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3815 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3816 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3817 data->REG_PWM[0] = NCT6775_REG_PWM;
3818 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3819 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3820 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3821 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3822 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3823 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3824 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3825 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3826 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3827 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3828 data->REG_CRITICAL_TEMP_TOLERANCE
3829 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3830 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
3831 data->CRITICAL_PWM_ENABLE_MASK
3832 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
3833 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
3834 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
3835 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3836 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3837 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3838 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3839 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3840 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3841 data->REG_ALARM = NCT6779_REG_ALARM;
3842 data->REG_BEEP = NCT6776_REG_BEEP;
3843
3844 reg_temp = NCT6779_REG_TEMP;
3845 reg_temp_mon = NCT6779_REG_TEMP_MON;
3846 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
3847 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
3848 reg_temp_over = NCT6779_REG_TEMP_OVER;
3849 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
3850 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
3851 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
3852 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
3853
3854 break;
3855 case nct6791:
3856 case nct6792:
3857 case nct6793:
3858 case nct6795:
3859 data->in_num = 15;
3860 data->pwm_num = 6;
3861 data->auto_pwm_num = 4;
3862 data->has_fan_div = false;
3863 data->temp_fixed_num = 6;
3864 data->num_temp_alarms = 2;
3865 data->num_temp_beeps = 2;
3866
3867 data->ALARM_BITS = NCT6791_ALARM_BITS;
3868 data->BEEP_BITS = NCT6779_BEEP_BITS;
3869
3870 data->fan_from_reg = fan_from_reg13;
3871 data->fan_from_reg_min = fan_from_reg13;
3872 data->target_temp_mask = 0xff;
3873 data->tolerance_mask = 0x07;
3874 data->speed_tolerance_limit = 63;
3875
3876 switch (data->kind) {
3877 default:
3878 case nct6791:
3879 data->temp_label = nct6779_temp_label;
3880 data->temp_mask = NCT6791_TEMP_MASK;
3881 break;
3882 case nct6792:
3883 data->temp_label = nct6792_temp_label;
3884 data->temp_mask = NCT6792_TEMP_MASK;
3885 break;
3886 case nct6793:
3887 data->temp_label = nct6793_temp_label;
3888 data->temp_mask = NCT6793_TEMP_MASK;
3889 break;
3890 case nct6795:
3891 data->temp_label = nct6795_temp_label;
3892 data->temp_mask = NCT6795_TEMP_MASK;
3893 break;
3894 }
3895
3896 data->REG_CONFIG = NCT6775_REG_CONFIG;
3897 data->REG_VBAT = NCT6775_REG_VBAT;
3898 data->REG_DIODE = NCT6775_REG_DIODE;
3899 data->DIODE_MASK = NCT6775_DIODE_MASK;
3900 data->REG_VIN = NCT6779_REG_IN;
3901 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3902 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3903 data->REG_TARGET = NCT6775_REG_TARGET;
3904 data->REG_FAN = NCT6779_REG_FAN;
3905 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3906 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3907 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3908 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3909 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3910 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3911 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3912 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3913 data->REG_PWM[0] = NCT6775_REG_PWM;
3914 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3915 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3916 data->REG_PWM[5] = NCT6791_REG_WEIGHT_DUTY_STEP;
3917 data->REG_PWM[6] = NCT6791_REG_WEIGHT_DUTY_BASE;
3918 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3919 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3920 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3921 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3922 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3923 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3924 data->REG_CRITICAL_TEMP_TOLERANCE
3925 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3926 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
3927 data->CRITICAL_PWM_ENABLE_MASK
3928 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
3929 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
3930 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
3931 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3932 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3933 data->REG_WEIGHT_TEMP_SEL = NCT6791_REG_WEIGHT_TEMP_SEL;
3934 data->REG_WEIGHT_TEMP[0] = NCT6791_REG_WEIGHT_TEMP_STEP;
3935 data->REG_WEIGHT_TEMP[1] = NCT6791_REG_WEIGHT_TEMP_STEP_TOL;
3936 data->REG_WEIGHT_TEMP[2] = NCT6791_REG_WEIGHT_TEMP_BASE;
3937 data->REG_ALARM = NCT6791_REG_ALARM;
3938 if (data->kind == nct6791)
3939 data->REG_BEEP = NCT6776_REG_BEEP;
3940 else
3941 data->REG_BEEP = NCT6792_REG_BEEP;
3942
3943 reg_temp = NCT6779_REG_TEMP;
3944 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
3945 if (data->kind == nct6791) {
3946 reg_temp_mon = NCT6779_REG_TEMP_MON;
3947 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
3948 } else {
3949 reg_temp_mon = NCT6792_REG_TEMP_MON;
3950 num_reg_temp_mon = ARRAY_SIZE(NCT6792_REG_TEMP_MON);
3951 }
3952 reg_temp_over = NCT6779_REG_TEMP_OVER;
3953 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
3954 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
3955 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
3956 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
3957
3958 break;
3959 default:
3960 return -ENODEV;
3961 }
3962 data->have_in = BIT(data->in_num) - 1;
3963 data->have_temp = 0;
3964
3965 /*
3966 * On some boards, not all available temperature sources are monitored,
3967 * even though some of the monitoring registers are unused.
3968 * Get list of unused monitoring registers, then detect if any fan
3969 * controls are configured to use unmonitored temperature sources.
3970 * If so, assign the unmonitored temperature sources to available
3971 * monitoring registers.
3972 */
3973 mask = 0;
3974 available = 0;
3975 for (i = 0; i < num_reg_temp; i++) {
3976 if (reg_temp[i] == 0)
3977 continue;
3978
3979 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
3980 if (!src || (mask & BIT(src)))
3981 available |= BIT(i);
3982
3983 mask |= BIT(src);
3984 }
3985
3986 /*
3987 * Now find unmonitored temperature registers and enable monitoring
3988 * if additional monitoring registers are available.
3989 */
3990 add_temp_sensors(data, data->REG_TEMP_SEL, &available, &mask);
3991 add_temp_sensors(data, data->REG_WEIGHT_TEMP_SEL, &available, &mask);
3992
3993 mask = 0;
3994 s = NUM_TEMP_FIXED; /* First dynamic temperature attribute */
3995 for (i = 0; i < num_reg_temp; i++) {
3996 if (reg_temp[i] == 0)
3997 continue;
3998
3999 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4000 if (!src || (mask & BIT(src)))
4001 continue;
4002
4003 if (!(data->temp_mask & BIT(src))) {
4004 dev_info(dev,
4005 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4006 src, i, data->REG_TEMP_SOURCE[i], reg_temp[i]);
4007 continue;
4008 }
4009
4010 mask |= BIT(src);
4011
4012 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4013 if (src <= data->temp_fixed_num) {
4014 data->have_temp |= BIT(src - 1);
4015 data->have_temp_fixed |= BIT(src - 1);
4016 data->reg_temp[0][src - 1] = reg_temp[i];
4017 data->reg_temp[1][src - 1] = reg_temp_over[i];
4018 data->reg_temp[2][src - 1] = reg_temp_hyst[i];
4019 if (reg_temp_crit_h && reg_temp_crit_h[i])
4020 data->reg_temp[3][src - 1] = reg_temp_crit_h[i];
4021 else if (reg_temp_crit[src - 1])
4022 data->reg_temp[3][src - 1]
4023 = reg_temp_crit[src - 1];
4024 if (reg_temp_crit_l && reg_temp_crit_l[i])
4025 data->reg_temp[4][src - 1] = reg_temp_crit_l[i];
4026 data->reg_temp_config[src - 1] = reg_temp_config[i];
4027 data->temp_src[src - 1] = src;
4028 continue;
4029 }
4030
4031 if (s >= NUM_TEMP)
4032 continue;
4033
4034 /* Use dynamic index for other sources */
4035 data->have_temp |= BIT(s);
4036 data->reg_temp[0][s] = reg_temp[i];
4037 data->reg_temp[1][s] = reg_temp_over[i];
4038 data->reg_temp[2][s] = reg_temp_hyst[i];
4039 data->reg_temp_config[s] = reg_temp_config[i];
4040 if (reg_temp_crit_h && reg_temp_crit_h[i])
4041 data->reg_temp[3][s] = reg_temp_crit_h[i];
4042 else if (reg_temp_crit[src - 1])
4043 data->reg_temp[3][s] = reg_temp_crit[src - 1];
4044 if (reg_temp_crit_l && reg_temp_crit_l[i])
4045 data->reg_temp[4][s] = reg_temp_crit_l[i];
4046
4047 data->temp_src[s] = src;
4048 s++;
4049 }
4050
4051 /*
4052 * Repeat with temperatures used for fan control.
4053 * This set of registers does not support limits.
4054 */
4055 for (i = 0; i < num_reg_temp_mon; i++) {
4056 if (reg_temp_mon[i] == 0)
4057 continue;
4058
4059 src = nct6775_read_value(data, data->REG_TEMP_SEL[i]) & 0x1f;
4060 if (!src)
4061 continue;
4062
4063 if (!(data->temp_mask & BIT(src))) {
4064 dev_info(dev,
4065 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4066 src, i, data->REG_TEMP_SEL[i],
4067 reg_temp_mon[i]);
4068 continue;
4069 }
4070
4071 /*
4072 * For virtual temperature sources, the 'virtual' temperature
4073 * for each fan reflects a different temperature, and there
4074 * are no duplicates.
4075 */
4076 if (src != TEMP_SOURCE_VIRTUAL) {
4077 if (mask & BIT(src))
4078 continue;
4079 mask |= BIT(src);
4080 }
4081
4082 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4083 if (src <= data->temp_fixed_num) {
4084 if (data->have_temp & BIT(src - 1))
4085 continue;
4086 data->have_temp |= BIT(src - 1);
4087 data->have_temp_fixed |= BIT(src - 1);
4088 data->reg_temp[0][src - 1] = reg_temp_mon[i];
4089 data->temp_src[src - 1] = src;
4090 continue;
4091 }
4092
4093 if (s >= NUM_TEMP)
4094 continue;
4095
4096 /* Use dynamic index for other sources */
4097 data->have_temp |= BIT(s);
4098 data->reg_temp[0][s] = reg_temp_mon[i];
4099 data->temp_src[s] = src;
4100 s++;
4101 }
4102
4103 #ifdef USE_ALTERNATE
4104 /*
4105 * Go through the list of alternate temp registers and enable
4106 * if possible.
4107 * The temperature is already monitored if the respective bit in <mask>
4108 * is set.
4109 */
4110 for (i = 0; i < 32; i++) {
4111 if (!(data->temp_mask & BIT(i + 1)))
4112 continue;
4113 if (!reg_temp_alternate[i])
4114 continue;
4115 if (mask & BIT(i + 1))
4116 continue;
4117 if (i < data->temp_fixed_num) {
4118 if (data->have_temp & BIT(i))
4119 continue;
4120 data->have_temp |= BIT(i);
4121 data->have_temp_fixed |= BIT(i);
4122 data->reg_temp[0][i] = reg_temp_alternate[i];
4123 if (i < num_reg_temp) {
4124 data->reg_temp[1][i] = reg_temp_over[i];
4125 data->reg_temp[2][i] = reg_temp_hyst[i];
4126 }
4127 data->temp_src[i] = i + 1;
4128 continue;
4129 }
4130
4131 if (s >= NUM_TEMP) /* Abort if no more space */
4132 break;
4133
4134 data->have_temp |= BIT(s);
4135 data->reg_temp[0][s] = reg_temp_alternate[i];
4136 data->temp_src[s] = i + 1;
4137 s++;
4138 }
4139 #endif /* USE_ALTERNATE */
4140
4141 /* Initialize the chip */
4142 nct6775_init_device(data);
4143
4144 err = superio_enter(sio_data->sioreg);
4145 if (err)
4146 return err;
4147
4148 cr2a = superio_inb(sio_data->sioreg, 0x2a);
4149 switch (data->kind) {
4150 case nct6775:
4151 data->have_vid = (cr2a & 0x40);
4152 break;
4153 case nct6776:
4154 data->have_vid = (cr2a & 0x60) == 0x40;
4155 break;
4156 case nct6106:
4157 case nct6779:
4158 case nct6791:
4159 case nct6792:
4160 case nct6793:
4161 case nct6795:
4162 break;
4163 }
4164
4165 /*
4166 * Read VID value
4167 * We can get the VID input values directly at logical device D 0xe3.
4168 */
4169 if (data->have_vid) {
4170 superio_select(sio_data->sioreg, NCT6775_LD_VID);
4171 data->vid = superio_inb(sio_data->sioreg, 0xe3);
4172 data->vrm = vid_which_vrm();
4173 }
4174
4175 if (fan_debounce) {
4176 u8 tmp;
4177
4178 superio_select(sio_data->sioreg, NCT6775_LD_HWM);
4179 tmp = superio_inb(sio_data->sioreg,
4180 NCT6775_REG_CR_FAN_DEBOUNCE);
4181 switch (data->kind) {
4182 case nct6106:
4183 tmp |= 0xe0;
4184 break;
4185 case nct6775:
4186 tmp |= 0x1e;
4187 break;
4188 case nct6776:
4189 case nct6779:
4190 tmp |= 0x3e;
4191 break;
4192 case nct6791:
4193 case nct6792:
4194 case nct6793:
4195 case nct6795:
4196 tmp |= 0x7e;
4197 break;
4198 }
4199 superio_outb(sio_data->sioreg, NCT6775_REG_CR_FAN_DEBOUNCE,
4200 tmp);
4201 dev_info(&pdev->dev, "Enabled fan debounce for chip %s\n",
4202 data->name);
4203 }
4204
4205 nct6775_check_fan_inputs(data);
4206
4207 superio_exit(sio_data->sioreg);
4208
4209 /* Read fan clock dividers immediately */
4210 nct6775_init_fan_common(dev, data);
4211
4212 /* Register sysfs hooks */
4213 group = nct6775_create_attr_group(dev, &nct6775_pwm_template_group,
4214 data->pwm_num);
4215 if (IS_ERR(group))
4216 return PTR_ERR(group);
4217
4218 data->groups[num_attr_groups++] = group;
4219
4220 group = nct6775_create_attr_group(dev, &nct6775_in_template_group,
4221 fls(data->have_in));
4222 if (IS_ERR(group))
4223 return PTR_ERR(group);
4224
4225 data->groups[num_attr_groups++] = group;
4226
4227 group = nct6775_create_attr_group(dev, &nct6775_fan_template_group,
4228 fls(data->has_fan));
4229 if (IS_ERR(group))
4230 return PTR_ERR(group);
4231
4232 data->groups[num_attr_groups++] = group;
4233
4234 group = nct6775_create_attr_group(dev, &nct6775_temp_template_group,
4235 fls(data->have_temp));
4236 if (IS_ERR(group))
4237 return PTR_ERR(group);
4238
4239 data->groups[num_attr_groups++] = group;
4240 data->groups[num_attr_groups++] = &nct6775_group_other;
4241
4242 hwmon_dev = devm_hwmon_device_register_with_groups(dev, data->name,
4243 data, data->groups);
4244 return PTR_ERR_OR_ZERO(hwmon_dev);
4245 }
4246
4247 static void nct6791_enable_io_mapping(int sioaddr)
4248 {
4249 int val;
4250
4251 val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE);
4252 if (val & 0x10) {
4253 pr_info("Enabling hardware monitor logical device mappings.\n");
4254 superio_outb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE,
4255 val & ~0x10);
4256 }
4257 }
4258
4259 static int __maybe_unused nct6775_suspend(struct device *dev)
4260 {
4261 struct nct6775_data *data = nct6775_update_device(dev);
4262
4263 mutex_lock(&data->update_lock);
4264 data->vbat = nct6775_read_value(data, data->REG_VBAT);
4265 if (data->kind == nct6775) {
4266 data->fandiv1 = nct6775_read_value(data, NCT6775_REG_FANDIV1);
4267 data->fandiv2 = nct6775_read_value(data, NCT6775_REG_FANDIV2);
4268 }
4269 mutex_unlock(&data->update_lock);
4270
4271 return 0;
4272 }
4273
4274 static int __maybe_unused nct6775_resume(struct device *dev)
4275 {
4276 struct nct6775_data *data = dev_get_drvdata(dev);
4277 int sioreg = data->sioreg;
4278 int i, j, err = 0;
4279 u8 reg;
4280
4281 mutex_lock(&data->update_lock);
4282 data->bank = 0xff; /* Force initial bank selection */
4283
4284 err = superio_enter(sioreg);
4285 if (err)
4286 goto abort;
4287
4288 superio_select(sioreg, NCT6775_LD_HWM);
4289 reg = superio_inb(sioreg, SIO_REG_ENABLE);
4290 if (reg != data->sio_reg_enable)
4291 superio_outb(sioreg, SIO_REG_ENABLE, data->sio_reg_enable);
4292
4293 if (data->kind == nct6791 || data->kind == nct6792 ||
4294 data->kind == nct6793 || data->kind == nct6795)
4295 nct6791_enable_io_mapping(sioreg);
4296
4297 superio_exit(sioreg);
4298
4299 /* Restore limits */
4300 for (i = 0; i < data->in_num; i++) {
4301 if (!(data->have_in & BIT(i)))
4302 continue;
4303
4304 nct6775_write_value(data, data->REG_IN_MINMAX[0][i],
4305 data->in[i][1]);
4306 nct6775_write_value(data, data->REG_IN_MINMAX[1][i],
4307 data->in[i][2]);
4308 }
4309
4310 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
4311 if (!(data->has_fan_min & BIT(i)))
4312 continue;
4313
4314 nct6775_write_value(data, data->REG_FAN_MIN[i],
4315 data->fan_min[i]);
4316 }
4317
4318 for (i = 0; i < NUM_TEMP; i++) {
4319 if (!(data->have_temp & BIT(i)))
4320 continue;
4321
4322 for (j = 1; j < ARRAY_SIZE(data->reg_temp); j++)
4323 if (data->reg_temp[j][i])
4324 nct6775_write_temp(data, data->reg_temp[j][i],
4325 data->temp[j][i]);
4326 }
4327
4328 /* Restore other settings */
4329 nct6775_write_value(data, data->REG_VBAT, data->vbat);
4330 if (data->kind == nct6775) {
4331 nct6775_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
4332 nct6775_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
4333 }
4334
4335 abort:
4336 /* Force re-reading all values */
4337 data->valid = false;
4338 mutex_unlock(&data->update_lock);
4339
4340 return err;
4341 }
4342
4343 static SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume);
4344
4345 static struct platform_driver nct6775_driver = {
4346 .driver = {
4347 .name = DRVNAME,
4348 .pm = &nct6775_dev_pm_ops,
4349 },
4350 .probe = nct6775_probe,
4351 };
4352
4353 /* nct6775_find() looks for a '627 in the Super-I/O config space */
4354 static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data)
4355 {
4356 u16 val;
4357 int err;
4358 int addr;
4359
4360 err = superio_enter(sioaddr);
4361 if (err)
4362 return err;
4363
4364 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) |
4365 superio_inb(sioaddr, SIO_REG_DEVID + 1);
4366 if (force_id && val != 0xffff)
4367 val = force_id;
4368
4369 switch (val & SIO_ID_MASK) {
4370 case SIO_NCT6106_ID:
4371 sio_data->kind = nct6106;
4372 break;
4373 case SIO_NCT6775_ID:
4374 sio_data->kind = nct6775;
4375 break;
4376 case SIO_NCT6776_ID:
4377 sio_data->kind = nct6776;
4378 break;
4379 case SIO_NCT6779_ID:
4380 sio_data->kind = nct6779;
4381 break;
4382 case SIO_NCT6791_ID:
4383 sio_data->kind = nct6791;
4384 break;
4385 case SIO_NCT6792_ID:
4386 sio_data->kind = nct6792;
4387 break;
4388 case SIO_NCT6793_ID:
4389 sio_data->kind = nct6793;
4390 break;
4391 case SIO_NCT6795_ID:
4392 sio_data->kind = nct6795;
4393 break;
4394 default:
4395 if (val != 0xffff)
4396 pr_debug("unsupported chip ID: 0x%04x\n", val);
4397 superio_exit(sioaddr);
4398 return -ENODEV;
4399 }
4400
4401 /* We have a known chip, find the HWM I/O address */
4402 superio_select(sioaddr, NCT6775_LD_HWM);
4403 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
4404 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
4405 addr = val & IOREGION_ALIGNMENT;
4406 if (addr == 0) {
4407 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
4408 superio_exit(sioaddr);
4409 return -ENODEV;
4410 }
4411
4412 /* Activate logical device if needed */
4413 val = superio_inb(sioaddr, SIO_REG_ENABLE);
4414 if (!(val & 0x01)) {
4415 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
4416 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
4417 }
4418
4419 if (sio_data->kind == nct6791 || sio_data->kind == nct6792 ||
4420 sio_data->kind == nct6793 || sio_data->kind == nct6795)
4421 nct6791_enable_io_mapping(sioaddr);
4422
4423 superio_exit(sioaddr);
4424 pr_info("Found %s or compatible chip at %#x:%#x\n",
4425 nct6775_sio_names[sio_data->kind], sioaddr, addr);
4426 sio_data->sioreg = sioaddr;
4427
4428 return addr;
4429 }
4430
4431 /*
4432 * when Super-I/O functions move to a separate file, the Super-I/O
4433 * bus will manage the lifetime of the device and this module will only keep
4434 * track of the nct6775 driver. But since we use platform_device_alloc(), we
4435 * must keep track of the device
4436 */
4437 static struct platform_device *pdev[2];
4438
4439 static int __init sensors_nct6775_init(void)
4440 {
4441 int i, err;
4442 bool found = false;
4443 int address;
4444 struct resource res;
4445 struct nct6775_sio_data sio_data;
4446 int sioaddr[2] = { 0x2e, 0x4e };
4447
4448 err = platform_driver_register(&nct6775_driver);
4449 if (err)
4450 return err;
4451
4452 /*
4453 * initialize sio_data->kind and sio_data->sioreg.
4454 *
4455 * when Super-I/O functions move to a separate file, the Super-I/O
4456 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
4457 * nct6775 hardware monitor, and call probe()
4458 */
4459 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4460 address = nct6775_find(sioaddr[i], &sio_data);
4461 if (address <= 0)
4462 continue;
4463
4464 found = true;
4465
4466 pdev[i] = platform_device_alloc(DRVNAME, address);
4467 if (!pdev[i]) {
4468 err = -ENOMEM;
4469 goto exit_device_unregister;
4470 }
4471
4472 err = platform_device_add_data(pdev[i], &sio_data,
4473 sizeof(struct nct6775_sio_data));
4474 if (err)
4475 goto exit_device_put;
4476
4477 memset(&res, 0, sizeof(res));
4478 res.name = DRVNAME;
4479 res.start = address + IOREGION_OFFSET;
4480 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
4481 res.flags = IORESOURCE_IO;
4482
4483 err = acpi_check_resource_conflict(&res);
4484 if (err) {
4485 platform_device_put(pdev[i]);
4486 pdev[i] = NULL;
4487 continue;
4488 }
4489
4490 err = platform_device_add_resources(pdev[i], &res, 1);
4491 if (err)
4492 goto exit_device_put;
4493
4494 /* platform_device_add calls probe() */
4495 err = platform_device_add(pdev[i]);
4496 if (err)
4497 goto exit_device_put;
4498 }
4499 if (!found) {
4500 err = -ENODEV;
4501 goto exit_unregister;
4502 }
4503
4504 return 0;
4505
4506 exit_device_put:
4507 platform_device_put(pdev[i]);
4508 exit_device_unregister:
4509 while (--i >= 0) {
4510 if (pdev[i])
4511 platform_device_unregister(pdev[i]);
4512 }
4513 exit_unregister:
4514 platform_driver_unregister(&nct6775_driver);
4515 return err;
4516 }
4517
4518 static void __exit sensors_nct6775_exit(void)
4519 {
4520 int i;
4521
4522 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4523 if (pdev[i])
4524 platform_device_unregister(pdev[i]);
4525 }
4526 platform_driver_unregister(&nct6775_driver);
4527 }
4528
4529 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
4530 MODULE_DESCRIPTION("Driver for NCT6775F and compatible chips");
4531 MODULE_LICENSE("GPL");
4532
4533 module_init(sensors_nct6775_init);
4534 module_exit(sensors_nct6775_exit);
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