4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CONTEXT_TRACKING
34 select HAVE_C_RECORDMCOUNT
35 select HAVE_CC_STACKPROTECTOR
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_GENERIC_SPINLOCK
172 config RWSEM_XCHGADD_ALGORITHM
175 config ARCH_HAS_ILOG2_U32
178 config ARCH_HAS_ILOG2_U64
181 config ARCH_HAS_CPUFREQ
184 Internal node to signify that the ARCH has CPUFREQ support
185 and that the relevant menu configurations are displayed for
188 config ARCH_HAS_BANDGAP
191 config GENERIC_HWEIGHT
195 config GENERIC_CALIBRATE_DELAY
199 config ARCH_MAY_HAVE_PC_FDC
205 config NEED_DMA_MAP_STATE
208 config ARCH_SUPPORTS_UPROBES
211 config ARCH_HAS_DMA_SET_COHERENT_MASK
214 config GENERIC_ISA_DMA
220 config NEED_RET_TO_USER
228 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
229 default DRAM_BASE if REMAP_VECTORS_TO_RAM
232 The base address of exception vectors. This must be two pages
235 config ARM_PATCH_PHYS_VIRT
236 bool "Patch physical to virtual translations at runtime" if EMBEDDED
238 depends on !XIP_KERNEL && MMU
239 depends on !ARCH_REALVIEW || !SPARSEMEM
241 Patch phys-to-virt and virt-to-phys translation functions at
242 boot and module load time according to the position of the
243 kernel in system memory.
245 This can only be used with non-XIP MMU kernels where the base
246 of physical memory is at a 16MB boundary.
248 Only disable this option if you know that you do not require
249 this feature (eg, building a kernel for a single machine) and
250 you need to shrink the kernel to the minimal size.
252 config NEED_MACH_GPIO_H
255 Select this when mach/gpio.h is required to provide special
256 definitions for this platform. The need for mach/gpio.h should
257 be avoided when possible.
259 config NEED_MACH_IO_H
262 Select this when mach/io.h is required to provide special
263 definitions for this platform. The need for mach/io.h should
264 be avoided when possible.
266 config NEED_MACH_MEMORY_H
269 Select this when mach/memory.h is required to provide special
270 definitions for this platform. The need for mach/memory.h should
271 be avoided when possible.
274 hex "Physical address of main memory" if MMU
275 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
276 default DRAM_BASE if !MMU
278 Please provide the physical address corresponding to the
279 location of main memory in your system.
285 source "init/Kconfig"
287 source "kernel/Kconfig.freezer"
292 bool "MMU-based Paged Memory Management Support"
295 Select if you want MMU-based virtualised addressing space
296 support by paged memory management. If unsure, say 'Y'.
299 # The "ARM system type" choice list is ordered alphabetically by option
300 # text. Please add new entries in the option alphabetic order.
303 prompt "ARM system type"
304 default ARCH_VERSATILE if !MMU
305 default ARCH_MULTIPLATFORM if MMU
307 config ARCH_MULTIPLATFORM
308 bool "Allow multiple platforms to be selected"
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select ARM_HAS_SG_CHAIN
312 select ARM_PATCH_PHYS_VIRT
315 select GENERIC_CLOCKEVENTS
316 select MULTI_IRQ_HANDLER
320 config ARCH_INTEGRATOR
321 bool "ARM Ltd. Integrator family"
322 select ARCH_HAS_CPUFREQ
324 select ARM_PATCH_PHYS_VIRT
327 select COMMON_CLK_VERSATILE
328 select GENERIC_CLOCKEVENTS
331 select MULTI_IRQ_HANDLER
332 select NEED_MACH_MEMORY_H
333 select PLAT_VERSATILE
336 select VERSATILE_FPGA_IRQ
338 Support for ARM's Integrator platform.
341 bool "ARM Ltd. RealView family"
342 select ARCH_WANT_OPTIONAL_GPIOLIB
344 select ARM_TIMER_SP804
346 select COMMON_CLK_VERSATILE
347 select GENERIC_CLOCKEVENTS
348 select GPIO_PL061 if GPIOLIB
350 select NEED_MACH_MEMORY_H
351 select PLAT_VERSATILE
352 select PLAT_VERSATILE_CLCD
354 This enables support for ARM Ltd RealView boards.
356 config ARCH_VERSATILE
357 bool "ARM Ltd. Versatile family"
358 select ARCH_WANT_OPTIONAL_GPIOLIB
360 select ARM_TIMER_SP804
363 select GENERIC_CLOCKEVENTS
364 select HAVE_MACH_CLKDEV
366 select PLAT_VERSATILE
367 select PLAT_VERSATILE_CLCD
368 select PLAT_VERSATILE_CLOCK
369 select VERSATILE_FPGA_IRQ
371 This enables support for ARM Ltd Versatile board.
375 select ARCH_REQUIRE_GPIOLIB
378 select NEED_MACH_GPIO_H
379 select NEED_MACH_IO_H if PCCARD
381 select PINCTRL_AT91 if USE_OF
383 This enables support for systems based on Atmel
384 AT91RM9200 and AT91SAM9* processors.
387 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
388 select ARCH_REQUIRE_GPIOLIB
393 select GENERIC_CLOCKEVENTS
396 Support for Cirrus Logic 711x/721x/731x based boards.
399 bool "Cortina Systems Gemini"
400 select ARCH_REQUIRE_GPIOLIB
403 select GENERIC_CLOCKEVENTS
405 Support for the Cortina Systems Gemini family SoCs
409 select ARCH_USES_GETTIMEOFFSET
412 select NEED_MACH_IO_H
413 select NEED_MACH_MEMORY_H
416 This is an evaluation board for the StrongARM processor available
417 from Digital. It has limited hardware on-board, including an
418 Ethernet interface, two PCMCIA sockets, two serial ports and a
422 bool "Energy Micro efm32"
424 select ARCH_REQUIRE_GPIOLIB
430 select GENERIC_CLOCKEVENTS
436 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
441 select ARCH_HAS_HOLES_MEMORYMODEL
442 select ARCH_REQUIRE_GPIOLIB
443 select ARCH_USES_GETTIMEOFFSET
448 select NEED_MACH_MEMORY_H
450 This enables support for the Cirrus EP93xx series of CPUs.
452 config ARCH_FOOTBRIDGE
456 select GENERIC_CLOCKEVENTS
458 select NEED_MACH_IO_H if !MMU
459 select NEED_MACH_MEMORY_H
461 Support for systems based on the DC21285 companion chip
462 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
465 bool "Hilscher NetX based"
469 select GENERIC_CLOCKEVENTS
471 This enables support for systems based on the Hilscher NetX Soc
477 select NEED_MACH_MEMORY_H
478 select NEED_RET_TO_USER
483 Support for Intel's IOP13XX (XScale) family of processors.
488 select ARCH_REQUIRE_GPIOLIB
491 select NEED_RET_TO_USER
495 Support for Intel's 80219 and IOP32X (XScale) family of
501 select ARCH_REQUIRE_GPIOLIB
504 select NEED_RET_TO_USER
508 Support for Intel's IOP33X (XScale) family of processors.
513 select ARCH_HAS_DMA_SET_COHERENT_MASK
514 select ARCH_SUPPORTS_BIG_ENDIAN
515 select ARCH_REQUIRE_GPIOLIB
518 select DMABOUNCE if PCI
519 select GENERIC_CLOCKEVENTS
520 select MIGHT_HAVE_PCI
521 select NEED_MACH_IO_H
522 select USB_EHCI_BIG_ENDIAN_DESC
523 select USB_EHCI_BIG_ENDIAN_MMIO
525 Support for Intel's IXP4XX (XScale) family of processors.
529 select ARCH_REQUIRE_GPIOLIB
531 select GENERIC_CLOCKEVENTS
532 select MIGHT_HAVE_PCI
536 select PLAT_ORION_LEGACY
538 Support for the Marvell Dove SoC 88AP510
541 bool "Marvell Kirkwood"
542 select ARCH_HAS_CPUFREQ
543 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
550 select PINCTRL_KIRKWOOD
551 select PLAT_ORION_LEGACY
553 Support for the following Marvell Kirkwood series SoCs:
554 88F6180, 88F6192 and 88F6281.
557 bool "Marvell MV78xx0"
558 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_CLOCKEVENTS
563 select PLAT_ORION_LEGACY
565 Support for the following Marvell MV78xx0 series SoCs:
571 select ARCH_REQUIRE_GPIOLIB
573 select GENERIC_CLOCKEVENTS
576 select PLAT_ORION_LEGACY
578 Support for the following Marvell Orion 5x series SoCs:
579 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
580 Orion-2 (5281), Orion-1-90 (6183).
583 bool "Marvell PXA168/910/MMP2"
585 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_ALLOCATOR
588 select GENERIC_CLOCKEVENTS
591 select MULTI_IRQ_HANDLER
596 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
599 bool "Micrel/Kendin KS8695"
600 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
604 select NEED_MACH_MEMORY_H
606 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
607 System-on-Chip devices.
610 bool "Nuvoton W90X900 CPU"
611 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
617 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
618 At present, the w90x900 has been renamed nuc900, regarding
619 the ARM series product line, you can login the following
620 link address to know more.
622 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
623 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
627 select ARCH_REQUIRE_GPIOLIB
632 select GENERIC_CLOCKEVENTS
636 Support for the NXP LPC32XX family of processors
639 bool "PXA2xx/PXA3xx-based"
641 select ARCH_HAS_CPUFREQ
643 select ARCH_REQUIRE_GPIOLIB
644 select ARM_CPU_SUSPEND if PM
648 select GENERIC_CLOCKEVENTS
651 select MULTI_IRQ_HANDLER
655 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
658 bool "Qualcomm MSM (non-multiplatform)"
659 select ARCH_REQUIRE_GPIOLIB
661 select GENERIC_CLOCKEVENTS
663 Support for Qualcomm MSM/QSD based systems. This runs on the
664 apps processor of the MSM/QSD and depends on a shared memory
665 interface to the modem processor which runs the baseband
666 stack and controls some vital subsystems
667 (clock and power control, etc).
669 config ARCH_SHMOBILE_LEGACY
670 bool "Renesas ARM SoCs (non-multiplatform)"
672 select ARM_PATCH_PHYS_VIRT
674 select GENERIC_CLOCKEVENTS
675 select HAVE_ARM_SCU if SMP
676 select HAVE_ARM_TWD if SMP
677 select HAVE_MACH_CLKDEV
679 select MIGHT_HAVE_CACHE_L2X0
680 select MULTI_IRQ_HANDLER
683 select PM_GENERIC_DOMAINS if PM
686 Support for Renesas ARM SoC platforms using a non-multiplatform
687 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
693 select ARCH_MAY_HAVE_PC_FDC
694 select ARCH_SPARSEMEM_ENABLE
695 select ARCH_USES_GETTIMEOFFSET
699 select HAVE_PATA_PLATFORM
701 select NEED_MACH_IO_H
702 select NEED_MACH_MEMORY_H
706 On the Acorn Risc-PC, Linux can support the internal IDE disk and
707 CD-ROM interface, serial and parallel port, and the floppy drive.
711 select ARCH_HAS_CPUFREQ
713 select ARCH_REQUIRE_GPIOLIB
714 select ARCH_SPARSEMEM_ENABLE
719 select GENERIC_CLOCKEVENTS
722 select NEED_MACH_MEMORY_H
725 Support for StrongARM 11x0 based boards.
728 bool "Samsung S3C24XX SoCs"
729 select ARCH_HAS_CPUFREQ
730 select ARCH_REQUIRE_GPIOLIB
733 select CLKSRC_SAMSUNG_PWM
734 select GENERIC_CLOCKEVENTS
736 select HAVE_S3C2410_I2C if I2C
737 select HAVE_S3C2410_WATCHDOG if WATCHDOG
738 select HAVE_S3C_RTC if RTC_CLASS
739 select MULTI_IRQ_HANDLER
740 select NEED_MACH_IO_H
743 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
744 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
745 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
746 Samsung SMDK2410 development board (and derivatives).
749 bool "Samsung S3C64XX"
750 select ARCH_HAS_CPUFREQ
751 select ARCH_REQUIRE_GPIOLIB
756 select CLKSRC_SAMSUNG_PWM
759 select GENERIC_CLOCKEVENTS
761 select HAVE_S3C2410_I2C if I2C
762 select HAVE_S3C2410_WATCHDOG if WATCHDOG
766 select PM_GENERIC_DOMAINS if PM
768 select S3C_GPIO_TRACK
770 select SAMSUNG_WAKEMASK
771 select SAMSUNG_WDT_RESET
773 Samsung S3C64XX series based systems
776 bool "Samsung S5P6440 S5P6450"
779 select CLKSRC_SAMSUNG_PWM
781 select GENERIC_CLOCKEVENTS
783 select HAVE_S3C2410_I2C if I2C
784 select HAVE_S3C2410_WATCHDOG if WATCHDOG
785 select HAVE_S3C_RTC if RTC_CLASS
786 select NEED_MACH_GPIO_H
788 select SAMSUNG_WDT_RESET
790 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
794 bool "Samsung S5PC100"
795 select ARCH_REQUIRE_GPIOLIB
798 select CLKSRC_SAMSUNG_PWM
800 select GENERIC_CLOCKEVENTS
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C2410_WATCHDOG if WATCHDOG
804 select HAVE_S3C_RTC if RTC_CLASS
805 select NEED_MACH_GPIO_H
807 select SAMSUNG_WDT_RESET
809 Samsung S5PC100 series based systems
812 bool "Samsung S5PV210/S5PC110"
813 select ARCH_HAS_CPUFREQ
814 select ARCH_HAS_HOLES_MEMORYMODEL
815 select ARCH_SPARSEMEM_ENABLE
818 select CLKSRC_SAMSUNG_PWM
820 select GENERIC_CLOCKEVENTS
822 select HAVE_S3C2410_I2C if I2C
823 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 select HAVE_S3C_RTC if RTC_CLASS
825 select NEED_MACH_GPIO_H
826 select NEED_MACH_MEMORY_H
829 Samsung S5PV210/S5PC110 series based systems
832 bool "Samsung EXYNOS"
833 select ARCH_HAS_CPUFREQ
834 select ARCH_HAS_HOLES_MEMORYMODEL
835 select ARCH_REQUIRE_GPIOLIB
836 select ARCH_SPARSEMEM_ENABLE
840 select GENERIC_CLOCKEVENTS
841 select HAVE_S3C2410_I2C if I2C
842 select HAVE_S3C2410_WATCHDOG if WATCHDOG
843 select HAVE_S3C_RTC if RTC_CLASS
844 select NEED_MACH_MEMORY_H
848 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
852 select ARCH_HAS_HOLES_MEMORYMODEL
853 select ARCH_REQUIRE_GPIOLIB
855 select GENERIC_ALLOCATOR
856 select GENERIC_CLOCKEVENTS
857 select GENERIC_IRQ_CHIP
863 Support for TI's DaVinci platform.
868 select ARCH_HAS_CPUFREQ
869 select ARCH_HAS_HOLES_MEMORYMODEL
871 select ARCH_REQUIRE_GPIOLIB
874 select GENERIC_CLOCKEVENTS
875 select GENERIC_IRQ_CHIP
878 select NEED_MACH_IO_H if PCCARD
879 select NEED_MACH_MEMORY_H
881 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
885 menu "Multiple platform selection"
886 depends on ARCH_MULTIPLATFORM
888 comment "CPU Core family selection"
891 bool "ARMv4 based platforms (FA526)"
892 depends on !ARCH_MULTI_V6_V7
893 select ARCH_MULTI_V4_V5
896 config ARCH_MULTI_V4T
897 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
898 depends on !ARCH_MULTI_V6_V7
899 select ARCH_MULTI_V4_V5
900 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
901 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
902 CPU_ARM925T || CPU_ARM940T)
905 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
906 depends on !ARCH_MULTI_V6_V7
907 select ARCH_MULTI_V4_V5
908 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
909 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
910 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
912 config ARCH_MULTI_V4_V5
916 bool "ARMv6 based platforms (ARM11)"
917 select ARCH_MULTI_V6_V7
921 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
923 select ARCH_MULTI_V6_V7
927 config ARCH_MULTI_V6_V7
929 select MIGHT_HAVE_CACHE_L2X0
931 config ARCH_MULTI_CPU_AUTO
932 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
938 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
942 select HAVE_ARM_ARCH_TIMER
945 # This is sorted alphabetically by mach-* pathname. However, plat-*
946 # Kconfigs may be included either alphabetically (according to the
947 # plat- suffix) or along side the corresponding mach-* source.
949 source "arch/arm/mach-mvebu/Kconfig"
951 source "arch/arm/mach-at91/Kconfig"
953 source "arch/arm/mach-bcm/Kconfig"
955 source "arch/arm/mach-berlin/Kconfig"
957 source "arch/arm/mach-clps711x/Kconfig"
959 source "arch/arm/mach-cns3xxx/Kconfig"
961 source "arch/arm/mach-davinci/Kconfig"
963 source "arch/arm/mach-dove/Kconfig"
965 source "arch/arm/mach-ep93xx/Kconfig"
967 source "arch/arm/mach-footbridge/Kconfig"
969 source "arch/arm/mach-gemini/Kconfig"
971 source "arch/arm/mach-highbank/Kconfig"
973 source "arch/arm/mach-hisi/Kconfig"
975 source "arch/arm/mach-integrator/Kconfig"
977 source "arch/arm/mach-iop32x/Kconfig"
979 source "arch/arm/mach-iop33x/Kconfig"
981 source "arch/arm/mach-iop13xx/Kconfig"
983 source "arch/arm/mach-ixp4xx/Kconfig"
985 source "arch/arm/mach-keystone/Kconfig"
987 source "arch/arm/mach-kirkwood/Kconfig"
989 source "arch/arm/mach-ks8695/Kconfig"
991 source "arch/arm/mach-msm/Kconfig"
993 source "arch/arm/mach-moxart/Kconfig"
995 source "arch/arm/mach-mv78xx0/Kconfig"
997 source "arch/arm/mach-imx/Kconfig"
999 source "arch/arm/mach-mxs/Kconfig"
1001 source "arch/arm/mach-netx/Kconfig"
1003 source "arch/arm/mach-nomadik/Kconfig"
1005 source "arch/arm/mach-nspire/Kconfig"
1007 source "arch/arm/plat-omap/Kconfig"
1009 source "arch/arm/mach-omap1/Kconfig"
1011 source "arch/arm/mach-omap2/Kconfig"
1013 source "arch/arm/mach-orion5x/Kconfig"
1015 source "arch/arm/mach-picoxcell/Kconfig"
1017 source "arch/arm/mach-pxa/Kconfig"
1018 source "arch/arm/plat-pxa/Kconfig"
1020 source "arch/arm/mach-mmp/Kconfig"
1022 source "arch/arm/mach-qcom/Kconfig"
1024 source "arch/arm/mach-realview/Kconfig"
1026 source "arch/arm/mach-rockchip/Kconfig"
1028 source "arch/arm/mach-sa1100/Kconfig"
1030 source "arch/arm/plat-samsung/Kconfig"
1032 source "arch/arm/mach-socfpga/Kconfig"
1034 source "arch/arm/mach-spear/Kconfig"
1036 source "arch/arm/mach-sti/Kconfig"
1038 source "arch/arm/mach-s3c24xx/Kconfig"
1040 source "arch/arm/mach-s3c64xx/Kconfig"
1042 source "arch/arm/mach-s5p64x0/Kconfig"
1044 source "arch/arm/mach-s5pc100/Kconfig"
1046 source "arch/arm/mach-s5pv210/Kconfig"
1048 source "arch/arm/mach-exynos/Kconfig"
1050 source "arch/arm/mach-shmobile/Kconfig"
1052 source "arch/arm/mach-sunxi/Kconfig"
1054 source "arch/arm/mach-prima2/Kconfig"
1056 source "arch/arm/mach-tegra/Kconfig"
1058 source "arch/arm/mach-u300/Kconfig"
1060 source "arch/arm/mach-ux500/Kconfig"
1062 source "arch/arm/mach-versatile/Kconfig"
1064 source "arch/arm/mach-vexpress/Kconfig"
1065 source "arch/arm/plat-versatile/Kconfig"
1067 source "arch/arm/mach-vt8500/Kconfig"
1069 source "arch/arm/mach-w90x900/Kconfig"
1071 source "arch/arm/mach-zynq/Kconfig"
1073 # Definitions to make life easier
1079 select GENERIC_CLOCKEVENTS
1085 select GENERIC_IRQ_CHIP
1088 config PLAT_ORION_LEGACY
1095 config PLAT_VERSATILE
1098 config ARM_TIMER_SP804
1101 select CLKSRC_OF if OF
1103 source "arch/arm/firmware/Kconfig"
1105 source arch/arm/mm/Kconfig
1109 default 16 if ARCH_EP93XX
1113 bool "Enable iWMMXt support" if !CPU_PJ4
1114 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1115 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1117 Enable support for iWMMXt context switching at run time if
1118 running on a CPU that supports it.
1120 config MULTI_IRQ_HANDLER
1123 Allow each machine to specify it's own IRQ handler at run time.
1126 source "arch/arm/Kconfig-nommu"
1129 config PJ4B_ERRATA_4742
1130 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1131 depends on CPU_PJ4B && MACH_ARMADA_370
1134 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1135 Event (WFE) IDLE states, a specific timing sensitivity exists between
1136 the retiring WFI/WFE instructions and the newly issued subsequent
1137 instructions. This sensitivity can result in a CPU hang scenario.
1139 The software must insert either a Data Synchronization Barrier (DSB)
1140 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1143 config ARM_ERRATA_326103
1144 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1147 Executing a SWP instruction to read-only memory does not set bit 11
1148 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1149 treat the access as a read, preventing a COW from occurring and
1150 causing the faulting task to livelock.
1152 config ARM_ERRATA_411920
1153 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1154 depends on CPU_V6 || CPU_V6K
1156 Invalidation of the Instruction Cache operation can
1157 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1158 It does not affect the MPCore. This option enables the ARM Ltd.
1159 recommended workaround.
1161 config ARM_ERRATA_430973
1162 bool "ARM errata: Stale prediction on replaced interworking branch"
1165 This option enables the workaround for the 430973 Cortex-A8
1166 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1167 interworking branch is replaced with another code sequence at the
1168 same virtual address, whether due to self-modifying code or virtual
1169 to physical address re-mapping, Cortex-A8 does not recover from the
1170 stale interworking branch prediction. This results in Cortex-A8
1171 executing the new code sequence in the incorrect ARM or Thumb state.
1172 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1173 and also flushes the branch target cache at every context switch.
1174 Note that setting specific bits in the ACTLR register may not be
1175 available in non-secure mode.
1177 config ARM_ERRATA_458693
1178 bool "ARM errata: Processor deadlock when a false hazard is created"
1180 depends on !ARCH_MULTIPLATFORM
1182 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1183 erratum. For very specific sequences of memory operations, it is
1184 possible for a hazard condition intended for a cache line to instead
1185 be incorrectly associated with a different cache line. This false
1186 hazard might then cause a processor deadlock. The workaround enables
1187 the L1 caching of the NEON accesses and disables the PLD instruction
1188 in the ACTLR register. Note that setting specific bits in the ACTLR
1189 register may not be available in non-secure mode.
1191 config ARM_ERRATA_460075
1192 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1194 depends on !ARCH_MULTIPLATFORM
1196 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1197 erratum. Any asynchronous access to the L2 cache may encounter a
1198 situation in which recent store transactions to the L2 cache are lost
1199 and overwritten with stale memory contents from external memory. The
1200 workaround disables the write-allocate mode for the L2 cache via the
1201 ACTLR register. Note that setting specific bits in the ACTLR register
1202 may not be available in non-secure mode.
1204 config ARM_ERRATA_742230
1205 bool "ARM errata: DMB operation may be faulty"
1206 depends on CPU_V7 && SMP
1207 depends on !ARCH_MULTIPLATFORM
1209 This option enables the workaround for the 742230 Cortex-A9
1210 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1211 between two write operations may not ensure the correct visibility
1212 ordering of the two writes. This workaround sets a specific bit in
1213 the diagnostic register of the Cortex-A9 which causes the DMB
1214 instruction to behave as a DSB, ensuring the correct behaviour of
1217 config ARM_ERRATA_742231
1218 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1219 depends on CPU_V7 && SMP
1220 depends on !ARCH_MULTIPLATFORM
1222 This option enables the workaround for the 742231 Cortex-A9
1223 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1224 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1225 accessing some data located in the same cache line, may get corrupted
1226 data due to bad handling of the address hazard when the line gets
1227 replaced from one of the CPUs at the same time as another CPU is
1228 accessing it. This workaround sets specific bits in the diagnostic
1229 register of the Cortex-A9 which reduces the linefill issuing
1230 capabilities of the processor.
1232 config PL310_ERRATA_588369
1233 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1234 depends on CACHE_L2X0
1236 The PL310 L2 cache controller implements three types of Clean &
1237 Invalidate maintenance operations: by Physical Address
1238 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1239 They are architecturally defined to behave as the execution of a
1240 clean operation followed immediately by an invalidate operation,
1241 both performing to the same memory location. This functionality
1242 is not correctly implemented in PL310 as clean lines are not
1243 invalidated as a result of these operations.
1245 config ARM_ERRATA_643719
1246 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1247 depends on CPU_V7 && SMP
1249 This option enables the workaround for the 643719 Cortex-A9 (prior to
1250 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1251 register returns zero when it should return one. The workaround
1252 corrects this value, ensuring cache maintenance operations which use
1253 it behave as intended and avoiding data corruption.
1255 config ARM_ERRATA_720789
1256 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1259 This option enables the workaround for the 720789 Cortex-A9 (prior to
1260 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1261 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1262 As a consequence of this erratum, some TLB entries which should be
1263 invalidated are not, resulting in an incoherency in the system page
1264 tables. The workaround changes the TLB flushing routines to invalidate
1265 entries regardless of the ASID.
1267 config PL310_ERRATA_727915
1268 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1269 depends on CACHE_L2X0
1271 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1272 operation (offset 0x7FC). This operation runs in background so that
1273 PL310 can handle normal accesses while it is in progress. Under very
1274 rare circumstances, due to this erratum, write data can be lost when
1275 PL310 treats a cacheable write transaction during a Clean &
1276 Invalidate by Way operation.
1278 config ARM_ERRATA_743622
1279 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1281 depends on !ARCH_MULTIPLATFORM
1283 This option enables the workaround for the 743622 Cortex-A9
1284 (r2p*) erratum. Under very rare conditions, a faulty
1285 optimisation in the Cortex-A9 Store Buffer may lead to data
1286 corruption. This workaround sets a specific bit in the diagnostic
1287 register of the Cortex-A9 which disables the Store Buffer
1288 optimisation, preventing the defect from occurring. This has no
1289 visible impact on the overall performance or power consumption of the
1292 config ARM_ERRATA_751472
1293 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1295 depends on !ARCH_MULTIPLATFORM
1297 This option enables the workaround for the 751472 Cortex-A9 (prior
1298 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1299 completion of a following broadcasted operation if the second
1300 operation is received by a CPU before the ICIALLUIS has completed,
1301 potentially leading to corrupted entries in the cache or TLB.
1303 config PL310_ERRATA_753970
1304 bool "PL310 errata: cache sync operation may be faulty"
1305 depends on CACHE_PL310
1307 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1309 Under some condition the effect of cache sync operation on
1310 the store buffer still remains when the operation completes.
1311 This means that the store buffer is always asked to drain and
1312 this prevents it from merging any further writes. The workaround
1313 is to replace the normal offset of cache sync operation (0x730)
1314 by another offset targeting an unmapped PL310 register 0x740.
1315 This has the same effect as the cache sync operation: store buffer
1316 drain and waiting for all buffers empty.
1318 config ARM_ERRATA_754322
1319 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1322 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1323 r3p*) erratum. A speculative memory access may cause a page table walk
1324 which starts prior to an ASID switch but completes afterwards. This
1325 can populate the micro-TLB with a stale entry which may be hit with
1326 the new ASID. This workaround places two dsb instructions in the mm
1327 switching code so that no page table walks can cross the ASID switch.
1329 config ARM_ERRATA_754327
1330 bool "ARM errata: no automatic Store Buffer drain"
1331 depends on CPU_V7 && SMP
1333 This option enables the workaround for the 754327 Cortex-A9 (prior to
1334 r2p0) erratum. The Store Buffer does not have any automatic draining
1335 mechanism and therefore a livelock may occur if an external agent
1336 continuously polls a memory location waiting to observe an update.
1337 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1338 written polling loops from denying visibility of updates to memory.
1340 config ARM_ERRATA_364296
1341 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1344 This options enables the workaround for the 364296 ARM1136
1345 r0p2 erratum (possible cache data corruption with
1346 hit-under-miss enabled). It sets the undocumented bit 31 in
1347 the auxiliary control register and the FI bit in the control
1348 register, thus disabling hit-under-miss without putting the
1349 processor into full low interrupt latency mode. ARM11MPCore
1352 config ARM_ERRATA_764369
1353 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1354 depends on CPU_V7 && SMP
1356 This option enables the workaround for erratum 764369
1357 affecting Cortex-A9 MPCore with two or more processors (all
1358 current revisions). Under certain timing circumstances, a data
1359 cache line maintenance operation by MVA targeting an Inner
1360 Shareable memory region may fail to proceed up to either the
1361 Point of Coherency or to the Point of Unification of the
1362 system. This workaround adds a DSB instruction before the
1363 relevant cache maintenance functions and sets a specific bit
1364 in the diagnostic control register of the SCU.
1366 config PL310_ERRATA_769419
1367 bool "PL310 errata: no automatic Store Buffer drain"
1368 depends on CACHE_L2X0
1370 On revisions of the PL310 prior to r3p2, the Store Buffer does
1371 not automatically drain. This can cause normal, non-cacheable
1372 writes to be retained when the memory system is idle, leading
1373 to suboptimal I/O performance for drivers using coherent DMA.
1374 This option adds a write barrier to the cpu_idle loop so that,
1375 on systems with an outer cache, the store buffer is drained
1378 config ARM_ERRATA_775420
1379 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1382 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1383 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1384 operation aborts with MMU exception, it might cause the processor
1385 to deadlock. This workaround puts DSB before executing ISB if
1386 an abort may occur on cache maintenance.
1388 config ARM_ERRATA_798181
1389 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1390 depends on CPU_V7 && SMP
1392 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1393 adequately shooting down all use of the old entries. This
1394 option enables the Linux kernel workaround for this erratum
1395 which sends an IPI to the CPUs that are running the same ASID
1396 as the one being invalidated.
1398 config ARM_ERRATA_773022
1399 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1402 This option enables the workaround for the 773022 Cortex-A15
1403 (up to r0p4) erratum. In certain rare sequences of code, the
1404 loop buffer may deliver incorrect instructions. This
1405 workaround disables the loop buffer to avoid the erratum.
1409 source "arch/arm/common/Kconfig"
1419 Find out whether you have ISA slots on your motherboard. ISA is the
1420 name of a bus system, i.e. the way the CPU talks to the other stuff
1421 inside your box. Other bus systems are PCI, EISA, MicroChannel
1422 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1423 newer boards don't support it. If you have ISA, say Y, otherwise N.
1425 # Select ISA DMA controller support
1430 # Select ISA DMA interface
1435 bool "PCI support" if MIGHT_HAVE_PCI
1437 Find out whether you have a PCI motherboard. PCI is the name of a
1438 bus system, i.e. the way the CPU talks to the other stuff inside
1439 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1440 VESA. If you have PCI, say Y, otherwise N.
1446 config PCI_NANOENGINE
1447 bool "BSE nanoEngine PCI support"
1448 depends on SA1100_NANOENGINE
1450 Enable PCI on the BSE nanoEngine board.
1455 config PCI_HOST_ITE8152
1457 depends on PCI && MACH_ARMCORE
1461 source "drivers/pci/Kconfig"
1462 source "drivers/pci/pcie/Kconfig"
1464 source "drivers/pcmcia/Kconfig"
1468 menu "Kernel Features"
1473 This option should be selected by machines which have an SMP-
1476 The only effect of this option is to make the SMP-related
1477 options available to the user for configuration.
1480 bool "Symmetric Multi-Processing"
1481 depends on CPU_V6K || CPU_V7
1482 depends on GENERIC_CLOCKEVENTS
1484 depends on MMU || ARM_MPU
1486 This enables support for systems with more than one CPU. If you have
1487 a system with only one CPU, say N. If you have a system with more
1488 than one CPU, say Y.
1490 If you say N here, the kernel will run on uni- and multiprocessor
1491 machines, but will use only one CPU of a multiprocessor machine. If
1492 you say Y here, the kernel will run on many, but not all,
1493 uniprocessor machines. On a uniprocessor machine, the kernel
1494 will run faster if you say N here.
1496 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1497 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1498 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1500 If you don't know what to do here, say N.
1503 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1504 depends on SMP && !XIP_KERNEL && MMU
1507 SMP kernels contain instructions which fail on non-SMP processors.
1508 Enabling this option allows the kernel to modify itself to make
1509 these instructions safe. Disabling it allows about 1K of space
1512 If you don't know what to do here, say Y.
1514 config ARM_CPU_TOPOLOGY
1515 bool "Support cpu topology definition"
1516 depends on SMP && CPU_V7
1519 Support ARM cpu topology definition. The MPIDR register defines
1520 affinity between processors which is then used to describe the cpu
1521 topology of an ARM System.
1524 bool "Multi-core scheduler support"
1525 depends on ARM_CPU_TOPOLOGY
1527 Multi-core scheduler support improves the CPU scheduler's decision
1528 making when dealing with multi-core CPU chips at a cost of slightly
1529 increased overhead in some places. If unsure say N here.
1532 bool "SMT scheduler support"
1533 depends on ARM_CPU_TOPOLOGY
1535 Improves the CPU scheduler's decision making when dealing with
1536 MultiThreading at a cost of slightly increased overhead in some
1537 places. If unsure say N here.
1542 This option enables support for the ARM system coherency unit
1544 config HAVE_ARM_ARCH_TIMER
1545 bool "Architected timer support"
1547 select ARM_ARCH_TIMER
1548 select GENERIC_CLOCKEVENTS
1550 This option enables support for the ARM architected timer
1555 select CLKSRC_OF if OF
1557 This options enables support for the ARM timer and watchdog unit
1560 bool "Multi-Cluster Power Management"
1561 depends on CPU_V7 && SMP
1563 This option provides the common power management infrastructure
1564 for (multi-)cluster based systems, such as big.LITTLE based
1568 bool "big.LITTLE support (Experimental)"
1569 depends on CPU_V7 && SMP
1572 This option enables support selections for the big.LITTLE
1573 system architecture.
1576 bool "big.LITTLE switcher support"
1577 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1579 select ARM_CPU_SUSPEND
1581 The big.LITTLE "switcher" provides the core functionality to
1582 transparently handle transition between a cluster of A15's
1583 and a cluster of A7's in a big.LITTLE system.
1585 config BL_SWITCHER_DUMMY_IF
1586 tristate "Simple big.LITTLE switcher user interface"
1587 depends on BL_SWITCHER && DEBUG_KERNEL
1589 This is a simple and dummy char dev interface to control
1590 the big.LITTLE switcher core code. It is meant for
1591 debugging purposes only.
1594 prompt "Memory split"
1598 Select the desired split between kernel and user memory.
1600 If you are not absolutely sure what you are doing, leave this
1604 bool "3G/1G user/kernel split"
1606 bool "2G/2G user/kernel split"
1608 bool "1G/3G user/kernel split"
1613 default PHYS_OFFSET if !MMU
1614 default 0x40000000 if VMSPLIT_1G
1615 default 0x80000000 if VMSPLIT_2G
1619 int "Maximum number of CPUs (2-32)"
1625 bool "Support for hot-pluggable CPUs"
1628 Say Y here to experiment with turning CPUs off and on. CPUs
1629 can be controlled through /sys/devices/system/cpu.
1632 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1635 Say Y here if you want Linux to communicate with system firmware
1636 implementing the PSCI specification for CPU-centric power
1637 management operations described in ARM document number ARM DEN
1638 0022A ("Power State Coordination Interface System Software on
1641 # The GPIO number here must be sorted by descending number. In case of
1642 # a multiplatform kernel, we just want the highest value required by the
1643 # selected platforms.
1646 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1647 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1648 default 392 if ARCH_U8500
1649 default 352 if ARCH_VT8500
1650 default 288 if ARCH_SUNXI
1651 default 264 if MACH_H4700
1654 Maximum number of GPIOs in the system.
1656 If unsure, leave the default value.
1658 source kernel/Kconfig.preempt
1662 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1663 ARCH_S5PV210 || ARCH_EXYNOS4
1664 default AT91_TIMER_HZ if ARCH_AT91
1665 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1669 depends on HZ_FIXED = 0
1670 prompt "Timer frequency"
1694 default HZ_FIXED if HZ_FIXED != 0
1695 default 100 if HZ_100
1696 default 200 if HZ_200
1697 default 250 if HZ_250
1698 default 300 if HZ_300
1699 default 500 if HZ_500
1703 def_bool HIGH_RES_TIMERS
1705 config THUMB2_KERNEL
1706 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1707 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1708 default y if CPU_THUMBONLY
1710 select ARM_ASM_UNIFIED
1713 By enabling this option, the kernel will be compiled in
1714 Thumb-2 mode. A compiler/assembler that understand the unified
1715 ARM-Thumb syntax is needed.
1719 config THUMB2_AVOID_R_ARM_THM_JUMP11
1720 bool "Work around buggy Thumb-2 short branch relocations in gas"
1721 depends on THUMB2_KERNEL && MODULES
1724 Various binutils versions can resolve Thumb-2 branches to
1725 locally-defined, preemptible global symbols as short-range "b.n"
1726 branch instructions.
1728 This is a problem, because there's no guarantee the final
1729 destination of the symbol, or any candidate locations for a
1730 trampoline, are within range of the branch. For this reason, the
1731 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1732 relocation in modules at all, and it makes little sense to add
1735 The symptom is that the kernel fails with an "unsupported
1736 relocation" error when loading some modules.
1738 Until fixed tools are available, passing
1739 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1740 code which hits this problem, at the cost of a bit of extra runtime
1741 stack usage in some cases.
1743 The problem is described in more detail at:
1744 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1746 Only Thumb-2 kernels are affected.
1748 Unless you are sure your tools don't have this problem, say Y.
1750 config ARM_ASM_UNIFIED
1754 bool "Use the ARM EABI to compile the kernel"
1756 This option allows for the kernel to be compiled using the latest
1757 ARM ABI (aka EABI). This is only useful if you are using a user
1758 space environment that is also compiled with EABI.
1760 Since there are major incompatibilities between the legacy ABI and
1761 EABI, especially with regard to structure member alignment, this
1762 option also changes the kernel syscall calling convention to
1763 disambiguate both ABIs and allow for backward compatibility support
1764 (selected with CONFIG_OABI_COMPAT).
1766 To use this you need GCC version 4.0.0 or later.
1769 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1770 depends on AEABI && !THUMB2_KERNEL
1772 This option preserves the old syscall interface along with the
1773 new (ARM EABI) one. It also provides a compatibility layer to
1774 intercept syscalls that have structure arguments which layout
1775 in memory differs between the legacy ABI and the new ARM EABI
1776 (only for non "thumb" binaries). This option adds a tiny
1777 overhead to all syscalls and produces a slightly larger kernel.
1779 The seccomp filter system will not be available when this is
1780 selected, since there is no way yet to sensibly distinguish
1781 between calling conventions during filtering.
1783 If you know you'll be using only pure EABI user space then you
1784 can say N here. If this option is not selected and you attempt
1785 to execute a legacy ABI binary then the result will be
1786 UNPREDICTABLE (in fact it can be predicted that it won't work
1787 at all). If in doubt say N.
1789 config ARCH_HAS_HOLES_MEMORYMODEL
1792 config ARCH_SPARSEMEM_ENABLE
1795 config ARCH_SPARSEMEM_DEFAULT
1796 def_bool ARCH_SPARSEMEM_ENABLE
1798 config ARCH_SELECT_MEMORY_MODEL
1799 def_bool ARCH_SPARSEMEM_ENABLE
1801 config HAVE_ARCH_PFN_VALID
1802 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1805 bool "High Memory Support"
1808 The address space of ARM processors is only 4 Gigabytes large
1809 and it has to accommodate user address space, kernel address
1810 space as well as some memory mapped IO. That means that, if you
1811 have a large amount of physical memory and/or IO, not all of the
1812 memory can be "permanently mapped" by the kernel. The physical
1813 memory that is not permanently mapped is called "high memory".
1815 Depending on the selected kernel/user memory split, minimum
1816 vmalloc space and actual amount of RAM, you may not need this
1817 option which should result in a slightly faster kernel.
1822 bool "Allocate 2nd-level pagetables from highmem"
1825 config HW_PERF_EVENTS
1826 bool "Enable hardware performance counter support for perf events"
1827 depends on PERF_EVENTS
1830 Enable hardware performance counter support for perf events. If
1831 disabled, perf events will use software events only.
1833 config SYS_SUPPORTS_HUGETLBFS
1837 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1841 config ARCH_WANT_GENERAL_HUGETLB
1846 config FORCE_MAX_ZONEORDER
1847 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1848 range 11 64 if ARCH_SHMOBILE_LEGACY
1849 default "12" if SOC_AM33XX
1850 default "9" if SA1111 || ARCH_EFM32
1853 The kernel memory allocator divides physically contiguous memory
1854 blocks into "zones", where each zone is a power of two number of
1855 pages. This option selects the largest power of two that the kernel
1856 keeps in the memory allocator. If you need to allocate very large
1857 blocks of physically contiguous memory, then you may need to
1858 increase this value.
1860 This config option is actually maximum order plus one. For example,
1861 a value of 11 means that the largest free memory block is 2^10 pages.
1863 config ALIGNMENT_TRAP
1865 depends on CPU_CP15_MMU
1866 default y if !ARCH_EBSA110
1867 select HAVE_PROC_CPU if PROC_FS
1869 ARM processors cannot fetch/store information which is not
1870 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1871 address divisible by 4. On 32-bit ARM processors, these non-aligned
1872 fetch/store instructions will be emulated in software if you say
1873 here, which has a severe performance impact. This is necessary for
1874 correct operation of some network protocols. With an IP-only
1875 configuration it is safe to say N, otherwise say Y.
1877 config UACCESS_WITH_MEMCPY
1878 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1880 default y if CPU_FEROCEON
1882 Implement faster copy_to_user and clear_user methods for CPU
1883 cores where a 8-word STM instruction give significantly higher
1884 memory write throughput than a sequence of individual 32bit stores.
1886 A possible side effect is a slight increase in scheduling latency
1887 between threads sharing the same address space if they invoke
1888 such copy operations with large buffers.
1890 However, if the CPU data cache is using a write-allocate mode,
1891 this option is unlikely to provide any performance gain.
1895 prompt "Enable seccomp to safely compute untrusted bytecode"
1897 This kernel feature is useful for number crunching applications
1898 that may need to compute untrusted bytecode during their
1899 execution. By using pipes or other transports made available to
1900 the process as file descriptors supporting the read/write
1901 syscalls, it's possible to isolate those applications in
1902 their own address space using seccomp. Once seccomp is
1903 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1904 and the task is only allowed to execute a few safe syscalls
1905 defined by each seccomp mode.
1918 bool "Xen guest support on ARM (EXPERIMENTAL)"
1919 depends on ARM && AEABI && OF
1920 depends on CPU_V7 && !CPU_V6
1921 depends on !GENERIC_ATOMIC64
1925 select ARCH_DMA_ADDR_T_64BIT
1927 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1934 bool "Flattened Device Tree support"
1937 select OF_EARLY_FLATTREE
1938 select OF_RESERVED_MEM
1940 Include support for flattened device tree machine descriptions.
1943 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1946 This is the traditional way of passing data to the kernel at boot
1947 time. If you are solely relying on the flattened device tree (or
1948 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1949 to remove ATAGS support from your kernel binary. If unsure,
1952 config DEPRECATED_PARAM_STRUCT
1953 bool "Provide old way to pass kernel parameters"
1956 This was deprecated in 2001 and announced to live on for 5 years.
1957 Some old boot loaders still use this way.
1959 # Compressed boot loader in ROM. Yes, we really want to ask about
1960 # TEXT and BSS so we preserve their values in the config files.
1961 config ZBOOT_ROM_TEXT
1962 hex "Compressed ROM boot loader base address"
1965 The physical address at which the ROM-able zImage is to be
1966 placed in the target. Platforms which normally make use of
1967 ROM-able zImage formats normally set this to a suitable
1968 value in their defconfig file.
1970 If ZBOOT_ROM is not enabled, this has no effect.
1972 config ZBOOT_ROM_BSS
1973 hex "Compressed ROM boot loader BSS address"
1976 The base address of an area of read/write memory in the target
1977 for the ROM-able zImage which must be available while the
1978 decompressor is running. It must be large enough to hold the
1979 entire decompressed kernel plus an additional 128 KiB.
1980 Platforms which normally make use of ROM-able zImage formats
1981 normally set this to a suitable value in their defconfig file.
1983 If ZBOOT_ROM is not enabled, this has no effect.
1986 bool "Compressed boot loader in ROM/flash"
1987 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1988 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1990 Say Y here if you intend to execute your compressed kernel image
1991 (zImage) directly from ROM or flash. If unsure, say N.
1994 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1995 depends on ZBOOT_ROM && ARCH_SH7372
1996 default ZBOOT_ROM_NONE
1998 Include experimental SD/MMC loading code in the ROM-able zImage.
1999 With this enabled it is possible to write the ROM-able zImage
2000 kernel image to an MMC or SD card and boot the kernel straight
2001 from the reset vector. At reset the processor Mask ROM will load
2002 the first part of the ROM-able zImage which in turn loads the
2003 rest the kernel image to RAM.
2005 config ZBOOT_ROM_NONE
2006 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2008 Do not load image from SD or MMC
2010 config ZBOOT_ROM_MMCIF
2011 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2013 Load image from MMCIF hardware block.
2015 config ZBOOT_ROM_SH_MOBILE_SDHI
2016 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2018 Load image from SDHI hardware block
2022 config ARM_APPENDED_DTB
2023 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2026 With this option, the boot code will look for a device tree binary
2027 (DTB) appended to zImage
2028 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2030 This is meant as a backward compatibility convenience for those
2031 systems with a bootloader that can't be upgraded to accommodate
2032 the documented boot protocol using a device tree.
2034 Beware that there is very little in terms of protection against
2035 this option being confused by leftover garbage in memory that might
2036 look like a DTB header after a reboot if no actual DTB is appended
2037 to zImage. Do not leave this option active in a production kernel
2038 if you don't intend to always append a DTB. Proper passing of the
2039 location into r2 of a bootloader provided DTB is always preferable
2042 config ARM_ATAG_DTB_COMPAT
2043 bool "Supplement the appended DTB with traditional ATAG information"
2044 depends on ARM_APPENDED_DTB
2046 Some old bootloaders can't be updated to a DTB capable one, yet
2047 they provide ATAGs with memory configuration, the ramdisk address,
2048 the kernel cmdline string, etc. Such information is dynamically
2049 provided by the bootloader and can't always be stored in a static
2050 DTB. To allow a device tree enabled kernel to be used with such
2051 bootloaders, this option allows zImage to extract the information
2052 from the ATAG list and store it at run time into the appended DTB.
2055 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2056 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2058 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2059 bool "Use bootloader kernel arguments if available"
2061 Uses the command-line options passed by the boot loader instead of
2062 the device tree bootargs property. If the boot loader doesn't provide
2063 any, the device tree bootargs property will be used.
2065 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2066 bool "Extend with bootloader kernel arguments"
2068 The command-line arguments provided by the boot loader will be
2069 appended to the the device tree bootargs property.
2074 string "Default kernel command string"
2077 On some architectures (EBSA110 and CATS), there is currently no way
2078 for the boot loader to pass arguments to the kernel. For these
2079 architectures, you should supply some command-line options at build
2080 time by entering them here. As a minimum, you should specify the
2081 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2084 prompt "Kernel command line type" if CMDLINE != ""
2085 default CMDLINE_FROM_BOOTLOADER
2088 config CMDLINE_FROM_BOOTLOADER
2089 bool "Use bootloader kernel arguments if available"
2091 Uses the command-line options passed by the boot loader. If
2092 the boot loader doesn't provide any, the default kernel command
2093 string provided in CMDLINE will be used.
2095 config CMDLINE_EXTEND
2096 bool "Extend bootloader kernel arguments"
2098 The command-line arguments provided by the boot loader will be
2099 appended to the default kernel command string.
2101 config CMDLINE_FORCE
2102 bool "Always use the default kernel command string"
2104 Always use the default kernel command string, even if the boot
2105 loader passes other arguments to the kernel.
2106 This is useful if you cannot or don't want to change the
2107 command-line options your boot loader passes to the kernel.
2111 bool "Kernel Execute-In-Place from ROM"
2112 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2114 Execute-In-Place allows the kernel to run from non-volatile storage
2115 directly addressable by the CPU, such as NOR flash. This saves RAM
2116 space since the text section of the kernel is not loaded from flash
2117 to RAM. Read-write sections, such as the data section and stack,
2118 are still copied to RAM. The XIP kernel is not compressed since
2119 it has to run directly from flash, so it will take more space to
2120 store it. The flash address used to link the kernel object files,
2121 and for storing it, is configuration dependent. Therefore, if you
2122 say Y here, you must know the proper physical address where to
2123 store the kernel image depending on your own flash memory usage.
2125 Also note that the make target becomes "make xipImage" rather than
2126 "make zImage" or "make Image". The final kernel binary to put in
2127 ROM memory will be arch/arm/boot/xipImage.
2131 config XIP_PHYS_ADDR
2132 hex "XIP Kernel Physical Location"
2133 depends on XIP_KERNEL
2134 default "0x00080000"
2136 This is the physical address in your flash memory the kernel will
2137 be linked for and stored to. This address is dependent on your
2141 bool "Kexec system call (EXPERIMENTAL)"
2142 depends on (!SMP || PM_SLEEP_SMP)
2144 kexec is a system call that implements the ability to shutdown your
2145 current kernel, and to start another kernel. It is like a reboot
2146 but it is independent of the system firmware. And like a reboot
2147 you can start any kernel with it, not just Linux.
2149 It is an ongoing process to be certain the hardware in a machine
2150 is properly shutdown, so do not be surprised if this code does not
2151 initially work for you.
2154 bool "Export atags in procfs"
2155 depends on ATAGS && KEXEC
2158 Should the atags used to boot the kernel be exported in an "atags"
2159 file in procfs. Useful with kexec.
2162 bool "Build kdump crash kernel (EXPERIMENTAL)"
2164 Generate crash dump after being started by kexec. This should
2165 be normally only set in special crash dump kernels which are
2166 loaded in the main kernel with kexec-tools into a specially
2167 reserved region and then later executed after a crash by
2168 kdump/kexec. The crash dump kernel must be compiled to a
2169 memory address not used by the main kernel
2171 For more details see Documentation/kdump/kdump.txt
2173 config AUTO_ZRELADDR
2174 bool "Auto calculation of the decompressed kernel image address"
2176 ZRELADDR is the physical address where the decompressed kernel
2177 image will be placed. If AUTO_ZRELADDR is selected, the address
2178 will be determined at run-time by masking the current IP with
2179 0xf8000000. This assumes the zImage being placed in the first 128MB
2180 from start of memory.
2184 menu "CPU Power Management"
2187 source "drivers/cpufreq/Kconfig"
2190 source "drivers/cpuidle/Kconfig"
2194 menu "Floating point emulation"
2196 comment "At least one emulation must be selected"
2199 bool "NWFPE math emulation"
2200 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2202 Say Y to include the NWFPE floating point emulator in the kernel.
2203 This is necessary to run most binaries. Linux does not currently
2204 support floating point hardware so you need to say Y here even if
2205 your machine has an FPA or floating point co-processor podule.
2207 You may say N here if you are going to load the Acorn FPEmulator
2208 early in the bootup.
2211 bool "Support extended precision"
2212 depends on FPE_NWFPE
2214 Say Y to include 80-bit support in the kernel floating-point
2215 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2216 Note that gcc does not generate 80-bit operations by default,
2217 so in most cases this option only enlarges the size of the
2218 floating point emulator without any good reason.
2220 You almost surely want to say N here.
2223 bool "FastFPE math emulation (EXPERIMENTAL)"
2224 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2226 Say Y here to include the FAST floating point emulator in the kernel.
2227 This is an experimental much faster emulator which now also has full
2228 precision for the mantissa. It does not support any exceptions.
2229 It is very simple, and approximately 3-6 times faster than NWFPE.
2231 It should be sufficient for most programs. It may be not suitable
2232 for scientific calculations, but you have to check this for yourself.
2233 If you do not feel you need a faster FP emulation you should better
2237 bool "VFP-format floating point maths"
2238 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2240 Say Y to include VFP support code in the kernel. This is needed
2241 if your hardware includes a VFP unit.
2243 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2244 release notes and additional status information.
2246 Say N if your target does not have VFP hardware.
2254 bool "Advanced SIMD (NEON) Extension support"
2255 depends on VFPv3 && CPU_V7
2257 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2260 config KERNEL_MODE_NEON
2261 bool "Support for NEON in kernel mode"
2262 depends on NEON && AEABI
2264 Say Y to include support for NEON in kernel mode.
2268 menu "Userspace binary formats"
2270 source "fs/Kconfig.binfmt"
2273 tristate "RISC OS personality"
2276 Say Y here to include the kernel code necessary if you want to run
2277 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2278 experimental; if this sounds frightening, say N and sleep in peace.
2279 You can also say M here to compile this support as a module (which
2280 will be called arthur).
2284 menu "Power management options"
2286 source "kernel/power/Kconfig"
2288 config ARCH_SUSPEND_POSSIBLE
2289 depends on !ARCH_S5PC100
2290 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2291 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2294 config ARM_CPU_SUSPEND
2299 source "net/Kconfig"
2301 source "drivers/Kconfig"
2305 source "arch/arm/Kconfig.debug"
2307 source "security/Kconfig"
2309 source "crypto/Kconfig"
2311 source "lib/Kconfig"
2313 source "arch/arm/kvm/Kconfig"