2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
70 #include "xhci-trace.h"
72 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
73 struct xhci_virt_device
*virt_dev
,
74 struct xhci_event_cmd
*event
);
77 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
80 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
83 unsigned long segment_offset
;
85 if (!seg
|| !trb
|| trb
< seg
->trbs
)
88 segment_offset
= trb
- seg
->trbs
;
89 if (segment_offset
> TRBS_PER_SEGMENT
)
91 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
94 /* Does this link TRB point to the first segment in a ring,
95 * or was the previous TRB the last TRB on the last segment in the ERST?
97 static bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
98 struct xhci_segment
*seg
, union xhci_trb
*trb
)
100 if (ring
== xhci
->event_ring
)
101 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
102 (seg
->next
== xhci
->event_ring
->first_seg
);
104 return le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
;
107 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
108 * segment? I.e. would the updated event TRB pointer step off the end of the
111 static int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
112 struct xhci_segment
*seg
, union xhci_trb
*trb
)
114 if (ring
== xhci
->event_ring
)
115 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
117 return TRB_TYPE_LINK_LE32(trb
->link
.control
);
120 static int enqueue_is_link_trb(struct xhci_ring
*ring
)
122 struct xhci_link_trb
*link
= &ring
->enqueue
->link
;
123 return TRB_TYPE_LINK_LE32(link
->control
);
126 union xhci_trb
*xhci_find_next_enqueue(struct xhci_ring
*ring
)
128 /* Enqueue pointer can be left pointing to the link TRB,
129 * we must handle that
131 if (TRB_TYPE_LINK_LE32(ring
->enqueue
->link
.control
))
132 return ring
->enq_seg
->next
->trbs
;
133 return ring
->enqueue
;
136 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
137 * TRB is in a new segment. This does not skip over link TRBs, and it does not
138 * effect the ring dequeue or enqueue pointers.
140 static void next_trb(struct xhci_hcd
*xhci
,
141 struct xhci_ring
*ring
,
142 struct xhci_segment
**seg
,
143 union xhci_trb
**trb
)
145 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
147 *trb
= ((*seg
)->trbs
);
154 * See Cycle bit rules. SW is the consumer for the event ring only.
155 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
157 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
159 unsigned long long addr
;
164 * If this is not event ring, and the dequeue pointer
165 * is not on a link TRB, there is one more usable TRB
167 if (ring
->type
!= TYPE_EVENT
&&
168 !last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
))
169 ring
->num_trbs_free
++;
173 * Update the dequeue pointer further if that was a link TRB or
174 * we're at the end of an event ring segment (which doesn't have
177 if (last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
)) {
178 if (ring
->type
== TYPE_EVENT
&&
179 last_trb_on_last_seg(xhci
, ring
,
180 ring
->deq_seg
, ring
->dequeue
)) {
181 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
183 ring
->deq_seg
= ring
->deq_seg
->next
;
184 ring
->dequeue
= ring
->deq_seg
->trbs
;
188 } while (last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
));
190 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
194 * See Cycle bit rules. SW is the consumer for the event ring only.
195 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
197 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
198 * chain bit is set), then set the chain bit in all the following link TRBs.
199 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
200 * have their chain bit cleared (so that each Link TRB is a separate TD).
202 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
203 * set, but other sections talk about dealing with the chain bit set. This was
204 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
205 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
207 * @more_trbs_coming: Will you enqueue more TRBs before calling
208 * prepare_transfer()?
210 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
211 bool more_trbs_coming
)
214 union xhci_trb
*next
;
215 unsigned long long addr
;
217 chain
= le32_to_cpu(ring
->enqueue
->generic
.field
[3]) & TRB_CHAIN
;
218 /* If this is not event ring, there is one less usable TRB */
219 if (ring
->type
!= TYPE_EVENT
&&
220 !last_trb(xhci
, ring
, ring
->enq_seg
, ring
->enqueue
))
221 ring
->num_trbs_free
--;
222 next
= ++(ring
->enqueue
);
225 /* Update the dequeue pointer further if that was a link TRB or we're at
226 * the end of an event ring segment (which doesn't have link TRBS)
228 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
229 if (ring
->type
!= TYPE_EVENT
) {
231 * If the caller doesn't plan on enqueueing more
232 * TDs before ringing the doorbell, then we
233 * don't want to give the link TRB to the
234 * hardware just yet. We'll give the link TRB
235 * back in prepare_ring() just before we enqueue
236 * the TD at the top of the ring.
238 if (!chain
&& !more_trbs_coming
)
241 /* If we're not dealing with 0.95 hardware or
242 * isoc rings on AMD 0.96 host,
243 * carry over the chain bit of the previous TRB
244 * (which may mean the chain bit is cleared).
246 if (!(ring
->type
== TYPE_ISOC
&&
247 (xhci
->quirks
& XHCI_AMD_0x96_HOST
))
248 && !xhci_link_trb_quirk(xhci
)) {
249 next
->link
.control
&=
250 cpu_to_le32(~TRB_CHAIN
);
251 next
->link
.control
|=
254 /* Give this link TRB to the hardware */
256 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
258 /* Toggle the cycle bit after the last ring segment. */
259 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
260 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
263 ring
->enq_seg
= ring
->enq_seg
->next
;
264 ring
->enqueue
= ring
->enq_seg
->trbs
;
265 next
= ring
->enqueue
;
267 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
271 * Check to see if there's room to enqueue num_trbs on the ring and make sure
272 * enqueue pointer will not advance into dequeue segment. See rules above.
274 static inline int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
275 unsigned int num_trbs
)
277 int num_trbs_in_deq_seg
;
279 if (ring
->num_trbs_free
< num_trbs
)
282 if (ring
->type
!= TYPE_COMMAND
&& ring
->type
!= TYPE_EVENT
) {
283 num_trbs_in_deq_seg
= ring
->dequeue
- ring
->deq_seg
->trbs
;
284 if (ring
->num_trbs_free
< num_trbs
+ num_trbs_in_deq_seg
)
291 /* Ring the host controller doorbell after placing a command on the ring */
292 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
294 if (!(xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
))
297 xhci_dbg(xhci
, "// Ding dong!\n");
298 xhci_writel(xhci
, DB_VALUE_HOST
, &xhci
->dba
->doorbell
[0]);
299 /* Flush PCI posted writes */
300 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
303 static int xhci_abort_cmd_ring(struct xhci_hcd
*xhci
)
308 xhci_dbg(xhci
, "Abort command ring\n");
310 if (!(xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
)) {
311 xhci_dbg(xhci
, "The command ring isn't running, "
312 "Have the command ring been stopped?\n");
316 temp_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
317 if (!(temp_64
& CMD_RING_RUNNING
)) {
318 xhci_dbg(xhci
, "Command ring had been stopped\n");
321 xhci
->cmd_ring_state
= CMD_RING_STATE_ABORTED
;
322 xhci_write_64(xhci
, temp_64
| CMD_RING_ABORT
,
323 &xhci
->op_regs
->cmd_ring
);
325 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
326 * time the completion od all xHCI commands, including
327 * the Command Abort operation. If software doesn't see
328 * CRR negated in a timely manner (e.g. longer than 5
329 * seconds), then it should assume that the there are
330 * larger problems with the xHC and assert HCRST.
332 ret
= xhci_handshake(xhci
, &xhci
->op_regs
->cmd_ring
,
333 CMD_RING_RUNNING
, 0, 5 * 1000 * 1000);
335 xhci_err(xhci
, "Stopped the command ring failed, "
336 "maybe the host is dead\n");
337 xhci
->xhc_state
|= XHCI_STATE_DYING
;
346 static int xhci_queue_cd(struct xhci_hcd
*xhci
,
347 struct xhci_command
*command
,
348 union xhci_trb
*cmd_trb
)
351 cd
= kzalloc(sizeof(struct xhci_cd
), GFP_ATOMIC
);
354 INIT_LIST_HEAD(&cd
->cancel_cmd_list
);
356 cd
->command
= command
;
357 cd
->cmd_trb
= cmd_trb
;
358 list_add_tail(&cd
->cancel_cmd_list
, &xhci
->cancel_cmd_list
);
364 * Cancel the command which has issue.
366 * Some commands may hang due to waiting for acknowledgement from
367 * usb device. It is outside of the xHC's ability to control and
368 * will cause the command ring is blocked. When it occurs software
369 * should intervene to recover the command ring.
370 * See Section 4.6.1.1 and 4.6.1.2
372 int xhci_cancel_cmd(struct xhci_hcd
*xhci
, struct xhci_command
*command
,
373 union xhci_trb
*cmd_trb
)
378 spin_lock_irqsave(&xhci
->lock
, flags
);
380 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
381 xhci_warn(xhci
, "Abort the command ring,"
382 " but the xHCI is dead.\n");
387 /* queue the cmd desriptor to cancel_cmd_list */
388 retval
= xhci_queue_cd(xhci
, command
, cmd_trb
);
390 xhci_warn(xhci
, "Queuing command descriptor failed.\n");
394 /* abort command ring */
395 retval
= xhci_abort_cmd_ring(xhci
);
397 xhci_err(xhci
, "Abort command ring failed\n");
398 if (unlikely(retval
== -ESHUTDOWN
)) {
399 spin_unlock_irqrestore(&xhci
->lock
, flags
);
400 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
401 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
407 spin_unlock_irqrestore(&xhci
->lock
, flags
);
411 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
,
412 unsigned int slot_id
,
413 unsigned int ep_index
,
414 unsigned int stream_id
)
416 __le32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
417 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
418 unsigned int ep_state
= ep
->ep_state
;
420 /* Don't ring the doorbell for this endpoint if there are pending
421 * cancellations because we don't want to interrupt processing.
422 * We don't want to restart any stream rings if there's a set dequeue
423 * pointer command pending because the device can choose to start any
424 * stream once the endpoint is on the HW schedule.
425 * FIXME - check all the stream rings for pending cancellations.
427 if ((ep_state
& EP_HALT_PENDING
) || (ep_state
& SET_DEQ_PENDING
) ||
428 (ep_state
& EP_HALTED
))
430 xhci_writel(xhci
, DB_VALUE(ep_index
, stream_id
), db_addr
);
431 /* The CPU has better things to do at this point than wait for a
432 * write-posting flush. It'll get there soon enough.
436 /* Ring the doorbell for any rings with pending URBs */
437 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
438 unsigned int slot_id
,
439 unsigned int ep_index
)
441 unsigned int stream_id
;
442 struct xhci_virt_ep
*ep
;
444 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
446 /* A ring has pending URBs if its TD list is not empty */
447 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
448 if (ep
->ring
&& !(list_empty(&ep
->ring
->td_list
)))
449 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
453 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
455 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
456 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
457 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
,
463 * Find the segment that trb is in. Start searching in start_seg.
464 * If we must move past a segment that has a link TRB with a toggle cycle state
465 * bit set, then we will toggle the value pointed at by cycle_state.
467 static struct xhci_segment
*find_trb_seg(
468 struct xhci_segment
*start_seg
,
469 union xhci_trb
*trb
, int *cycle_state
)
471 struct xhci_segment
*cur_seg
= start_seg
;
472 struct xhci_generic_trb
*generic_trb
;
474 while (cur_seg
->trbs
> trb
||
475 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
476 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
477 if (generic_trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
))
479 cur_seg
= cur_seg
->next
;
480 if (cur_seg
== start_seg
)
481 /* Looped over the entire list. Oops! */
488 static struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
489 unsigned int slot_id
, unsigned int ep_index
,
490 unsigned int stream_id
)
492 struct xhci_virt_ep
*ep
;
494 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
495 /* Common case: no streams */
496 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
499 if (stream_id
== 0) {
501 "WARN: Slot ID %u, ep index %u has streams, "
502 "but URB has no stream ID.\n",
507 if (stream_id
< ep
->stream_info
->num_streams
)
508 return ep
->stream_info
->stream_rings
[stream_id
];
511 "WARN: Slot ID %u, ep index %u has "
512 "stream IDs 1 to %u allocated, "
513 "but stream ID %u is requested.\n",
515 ep
->stream_info
->num_streams
- 1,
520 /* Get the right ring for the given URB.
521 * If the endpoint supports streams, boundary check the URB's stream ID.
522 * If the endpoint doesn't support streams, return the singular endpoint ring.
524 static struct xhci_ring
*xhci_urb_to_transfer_ring(struct xhci_hcd
*xhci
,
527 return xhci_triad_to_transfer_ring(xhci
, urb
->dev
->slot_id
,
528 xhci_get_endpoint_index(&urb
->ep
->desc
), urb
->stream_id
);
532 * Move the xHC's endpoint ring dequeue pointer past cur_td.
533 * Record the new state of the xHC's endpoint ring dequeue segment,
534 * dequeue pointer, and new consumer cycle state in state.
535 * Update our internal representation of the ring's dequeue pointer.
537 * We do this in three jumps:
538 * - First we update our new ring state to be the same as when the xHC stopped.
539 * - Then we traverse the ring to find the segment that contains
540 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
541 * any link TRBs with the toggle cycle bit set.
542 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
543 * if we've moved it past a link TRB with the toggle cycle bit set.
545 * Some of the uses of xhci_generic_trb are grotty, but if they're done
546 * with correct __le32 accesses they should work fine. Only users of this are
549 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
550 unsigned int slot_id
, unsigned int ep_index
,
551 unsigned int stream_id
, struct xhci_td
*cur_td
,
552 struct xhci_dequeue_state
*state
)
554 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
555 struct xhci_ring
*ep_ring
;
556 struct xhci_generic_trb
*trb
;
557 struct xhci_ep_ctx
*ep_ctx
;
560 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
561 ep_index
, stream_id
);
563 xhci_warn(xhci
, "WARN can't find new dequeue state "
564 "for invalid stream ID %u.\n",
568 state
->new_cycle_state
= 0;
569 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
570 "Finding segment containing stopped TRB.");
571 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
572 dev
->eps
[ep_index
].stopped_trb
,
573 &state
->new_cycle_state
);
574 if (!state
->new_deq_seg
) {
579 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
580 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
581 "Finding endpoint context");
582 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
583 state
->new_cycle_state
= 0x1 & le64_to_cpu(ep_ctx
->deq
);
585 state
->new_deq_ptr
= cur_td
->last_trb
;
586 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
587 "Finding segment containing last TRB in TD.");
588 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
590 &state
->new_cycle_state
);
591 if (!state
->new_deq_seg
) {
596 trb
= &state
->new_deq_ptr
->generic
;
597 if (TRB_TYPE_LINK_LE32(trb
->field
[3]) &&
598 (trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
)))
599 state
->new_cycle_state
^= 0x1;
600 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
603 * If there is only one segment in a ring, find_trb_seg()'s while loop
604 * will not run, and it will return before it has a chance to see if it
605 * needs to toggle the cycle bit. It can't tell if the stalled transfer
606 * ended just before the link TRB on a one-segment ring, or if the TD
607 * wrapped around the top of the ring, because it doesn't have the TD in
608 * question. Look for the one-segment case where stalled TRB's address
609 * is greater than the new dequeue pointer address.
611 if (ep_ring
->first_seg
== ep_ring
->first_seg
->next
&&
612 state
->new_deq_ptr
< dev
->eps
[ep_index
].stopped_trb
)
613 state
->new_cycle_state
^= 0x1;
614 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
615 "Cycle state = 0x%x", state
->new_cycle_state
);
617 /* Don't update the ring cycle state for the producer (us). */
618 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
619 "New dequeue segment = %p (virtual)",
621 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
622 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
623 "New dequeue pointer = 0x%llx (DMA)",
624 (unsigned long long) addr
);
627 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
628 * (The last TRB actually points to the ring enqueue pointer, which is not part
629 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
631 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
632 struct xhci_td
*cur_td
, bool flip_cycle
)
634 struct xhci_segment
*cur_seg
;
635 union xhci_trb
*cur_trb
;
637 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
639 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
640 if (TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3])) {
641 /* Unchain any chained Link TRBs, but
642 * leave the pointers intact.
644 cur_trb
->generic
.field
[3] &= cpu_to_le32(~TRB_CHAIN
);
645 /* Flip the cycle bit (link TRBs can't be the first
649 cur_trb
->generic
.field
[3] ^=
650 cpu_to_le32(TRB_CYCLE
);
651 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
652 "Cancel (unchain) link TRB");
653 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
654 "Address = %p (0x%llx dma); "
655 "in seg %p (0x%llx dma)",
657 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
659 (unsigned long long)cur_seg
->dma
);
661 cur_trb
->generic
.field
[0] = 0;
662 cur_trb
->generic
.field
[1] = 0;
663 cur_trb
->generic
.field
[2] = 0;
664 /* Preserve only the cycle bit of this TRB */
665 cur_trb
->generic
.field
[3] &= cpu_to_le32(TRB_CYCLE
);
666 /* Flip the cycle bit except on the first or last TRB */
667 if (flip_cycle
&& cur_trb
!= cur_td
->first_trb
&&
668 cur_trb
!= cur_td
->last_trb
)
669 cur_trb
->generic
.field
[3] ^=
670 cpu_to_le32(TRB_CYCLE
);
671 cur_trb
->generic
.field
[3] |= cpu_to_le32(
672 TRB_TYPE(TRB_TR_NOOP
));
673 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
674 "TRB to noop at offset 0x%llx",
676 xhci_trb_virt_to_dma(cur_seg
, cur_trb
));
678 if (cur_trb
== cur_td
->last_trb
)
683 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
684 unsigned int ep_index
, unsigned int stream_id
,
685 struct xhci_segment
*deq_seg
,
686 union xhci_trb
*deq_ptr
, u32 cycle_state
);
688 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
689 unsigned int slot_id
, unsigned int ep_index
,
690 unsigned int stream_id
,
691 struct xhci_dequeue_state
*deq_state
)
693 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
695 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
696 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
697 "new deq ptr = %p (0x%llx dma), new cycle = %u",
698 deq_state
->new_deq_seg
,
699 (unsigned long long)deq_state
->new_deq_seg
->dma
,
700 deq_state
->new_deq_ptr
,
701 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
702 deq_state
->new_cycle_state
);
703 queue_set_tr_deq(xhci
, slot_id
, ep_index
, stream_id
,
704 deq_state
->new_deq_seg
,
705 deq_state
->new_deq_ptr
,
706 (u32
) deq_state
->new_cycle_state
);
707 /* Stop the TD queueing code from ringing the doorbell until
708 * this command completes. The HC won't set the dequeue pointer
709 * if the ring is running, and ringing the doorbell starts the
712 ep
->ep_state
|= SET_DEQ_PENDING
;
715 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
716 struct xhci_virt_ep
*ep
)
718 ep
->ep_state
&= ~EP_HALT_PENDING
;
719 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
720 * timer is running on another CPU, we don't decrement stop_cmds_pending
721 * (since we didn't successfully stop the watchdog timer).
723 if (del_timer(&ep
->stop_cmd_timer
))
724 ep
->stop_cmds_pending
--;
727 /* Must be called with xhci->lock held in interrupt context */
728 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
729 struct xhci_td
*cur_td
, int status
, char *adjective
)
733 struct urb_priv
*urb_priv
;
736 urb_priv
= urb
->hcpriv
;
738 hcd
= bus_to_hcd(urb
->dev
->bus
);
740 /* Only giveback urb when this is the last td in urb */
741 if (urb_priv
->td_cnt
== urb_priv
->length
) {
742 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
743 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
744 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
745 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
746 usb_amd_quirk_pll_enable();
749 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
751 spin_unlock(&xhci
->lock
);
752 usb_hcd_giveback_urb(hcd
, urb
, status
);
753 xhci_urb_free_priv(xhci
, urb_priv
);
754 spin_lock(&xhci
->lock
);
759 * When we get a command completion for a Stop Endpoint Command, we need to
760 * unlink any cancelled TDs from the ring. There are two ways to do that:
762 * 1. If the HW was in the middle of processing the TD that needs to be
763 * cancelled, then we must move the ring's dequeue pointer past the last TRB
764 * in the TD with a Set Dequeue Pointer Command.
765 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
766 * bit cleared) so that the HW will skip over them.
768 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
769 union xhci_trb
*trb
, struct xhci_event_cmd
*event
)
771 unsigned int slot_id
;
772 unsigned int ep_index
;
773 struct xhci_virt_device
*virt_dev
;
774 struct xhci_ring
*ep_ring
;
775 struct xhci_virt_ep
*ep
;
776 struct list_head
*entry
;
777 struct xhci_td
*cur_td
= NULL
;
778 struct xhci_td
*last_unlinked_td
;
780 struct xhci_dequeue_state deq_state
;
782 if (unlikely(TRB_TO_SUSPEND_PORT(
783 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])))) {
784 slot_id
= TRB_TO_SLOT_ID(
785 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
786 virt_dev
= xhci
->devs
[slot_id
];
788 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
,
791 xhci_warn(xhci
, "Stop endpoint command "
792 "completion for disabled slot %u\n",
797 memset(&deq_state
, 0, sizeof(deq_state
));
798 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
799 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
800 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
802 if (list_empty(&ep
->cancelled_td_list
)) {
803 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
804 ep
->stopped_td
= NULL
;
805 ep
->stopped_trb
= NULL
;
806 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
810 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
811 * We have the xHCI lock, so nothing can modify this list until we drop
812 * it. We're also in the event handler, so we can't get re-interrupted
813 * if another Stop Endpoint command completes
815 list_for_each(entry
, &ep
->cancelled_td_list
) {
816 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
817 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
818 "Removing canceled TD starting at 0x%llx (dma).",
819 (unsigned long long)xhci_trb_virt_to_dma(
820 cur_td
->start_seg
, cur_td
->first_trb
));
821 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
823 /* This shouldn't happen unless a driver is mucking
824 * with the stream ID after submission. This will
825 * leave the TD on the hardware ring, and the hardware
826 * will try to execute it, and may access a buffer
827 * that has already been freed. In the best case, the
828 * hardware will execute it, and the event handler will
829 * ignore the completion event for that TD, since it was
830 * removed from the td_list for that endpoint. In
831 * short, don't muck with the stream ID after
834 xhci_warn(xhci
, "WARN Cancelled URB %p "
835 "has invalid stream ID %u.\n",
837 cur_td
->urb
->stream_id
);
838 goto remove_finished_td
;
841 * If we stopped on the TD we need to cancel, then we have to
842 * move the xHC endpoint ring dequeue pointer past this TD.
844 if (cur_td
== ep
->stopped_td
)
845 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
,
846 cur_td
->urb
->stream_id
,
849 td_to_noop(xhci
, ep_ring
, cur_td
, false);
852 * The event handler won't see a completion for this TD anymore,
853 * so remove it from the endpoint ring's TD list. Keep it in
854 * the cancelled TD list for URB completion later.
856 list_del_init(&cur_td
->td_list
);
858 last_unlinked_td
= cur_td
;
859 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
861 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
862 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
863 xhci_queue_new_dequeue_state(xhci
,
865 ep
->stopped_td
->urb
->stream_id
,
867 xhci_ring_cmd_db(xhci
);
869 /* Otherwise ring the doorbell(s) to restart queued transfers */
870 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
873 /* Clear stopped_td and stopped_trb if endpoint is not halted */
874 if (!(ep
->ep_state
& EP_HALTED
)) {
875 ep
->stopped_td
= NULL
;
876 ep
->stopped_trb
= NULL
;
880 * Drop the lock and complete the URBs in the cancelled TD list.
881 * New TDs to be cancelled might be added to the end of the list before
882 * we can complete all the URBs for the TDs we already unlinked.
883 * So stop when we've completed the URB for the last TD we unlinked.
886 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
887 struct xhci_td
, cancelled_td_list
);
888 list_del_init(&cur_td
->cancelled_td_list
);
890 /* Clean up the cancelled URB */
891 /* Doesn't matter what we pass for status, since the core will
892 * just overwrite it (because the URB has been unlinked).
894 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0, "cancelled");
896 /* Stop processing the cancelled list if the watchdog timer is
899 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
901 } while (cur_td
!= last_unlinked_td
);
903 /* Return to the event handler with xhci->lock re-acquired */
906 /* Watchdog timer function for when a stop endpoint command fails to complete.
907 * In this case, we assume the host controller is broken or dying or dead. The
908 * host may still be completing some other events, so we have to be careful to
909 * let the event ring handler and the URB dequeueing/enqueueing functions know
910 * through xhci->state.
912 * The timer may also fire if the host takes a very long time to respond to the
913 * command, and the stop endpoint command completion handler cannot delete the
914 * timer before the timer function is called. Another endpoint cancellation may
915 * sneak in before the timer function can grab the lock, and that may queue
916 * another stop endpoint command and add the timer back. So we cannot use a
917 * simple flag to say whether there is a pending stop endpoint command for a
918 * particular endpoint.
920 * Instead we use a combination of that flag and a counter for the number of
921 * pending stop endpoint commands. If the timer is the tail end of the last
922 * stop endpoint command, and the endpoint's command is still pending, we assume
925 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
927 struct xhci_hcd
*xhci
;
928 struct xhci_virt_ep
*ep
;
929 struct xhci_virt_ep
*temp_ep
;
930 struct xhci_ring
*ring
;
931 struct xhci_td
*cur_td
;
935 ep
= (struct xhci_virt_ep
*) arg
;
938 spin_lock_irqsave(&xhci
->lock
, flags
);
940 ep
->stop_cmds_pending
--;
941 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
942 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
943 "Stop EP timer ran, but another timer marked "
944 "xHCI as DYING, exiting.");
945 spin_unlock_irqrestore(&xhci
->lock
, flags
);
948 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
949 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
950 "Stop EP timer ran, but no command pending, "
952 spin_unlock_irqrestore(&xhci
->lock
, flags
);
956 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
957 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
958 /* Oops, HC is dead or dying or at least not responding to the stop
961 xhci
->xhc_state
|= XHCI_STATE_DYING
;
962 /* Disable interrupts from the host controller and start halting it */
964 spin_unlock_irqrestore(&xhci
->lock
, flags
);
966 ret
= xhci_halt(xhci
);
968 spin_lock_irqsave(&xhci
->lock
, flags
);
970 /* This is bad; the host is not responding to commands and it's
971 * not allowing itself to be halted. At least interrupts are
972 * disabled. If we call usb_hc_died(), it will attempt to
973 * disconnect all device drivers under this host. Those
974 * disconnect() methods will wait for all URBs to be unlinked,
975 * so we must complete them.
977 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
978 xhci_warn(xhci
, "Completing active URBs anyway.\n");
979 /* We could turn all TDs on the rings to no-ops. This won't
980 * help if the host has cached part of the ring, and is slow if
981 * we want to preserve the cycle bit. Skip it and hope the host
982 * doesn't touch the memory.
985 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
988 for (j
= 0; j
< 31; j
++) {
989 temp_ep
= &xhci
->devs
[i
]->eps
[j
];
990 ring
= temp_ep
->ring
;
993 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
994 "Killing URBs for slot ID %u, "
995 "ep index %u", i
, j
);
996 while (!list_empty(&ring
->td_list
)) {
997 cur_td
= list_first_entry(&ring
->td_list
,
1000 list_del_init(&cur_td
->td_list
);
1001 if (!list_empty(&cur_td
->cancelled_td_list
))
1002 list_del_init(&cur_td
->cancelled_td_list
);
1003 xhci_giveback_urb_in_irq(xhci
, cur_td
,
1004 -ESHUTDOWN
, "killed");
1006 while (!list_empty(&temp_ep
->cancelled_td_list
)) {
1007 cur_td
= list_first_entry(
1008 &temp_ep
->cancelled_td_list
,
1011 list_del_init(&cur_td
->cancelled_td_list
);
1012 xhci_giveback_urb_in_irq(xhci
, cur_td
,
1013 -ESHUTDOWN
, "killed");
1017 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1018 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1019 "Calling usb_hc_died()");
1020 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
1021 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1022 "xHCI host controller is dead.");
1026 static void update_ring_for_set_deq_completion(struct xhci_hcd
*xhci
,
1027 struct xhci_virt_device
*dev
,
1028 struct xhci_ring
*ep_ring
,
1029 unsigned int ep_index
)
1031 union xhci_trb
*dequeue_temp
;
1032 int num_trbs_free_temp
;
1033 bool revert
= false;
1035 num_trbs_free_temp
= ep_ring
->num_trbs_free
;
1036 dequeue_temp
= ep_ring
->dequeue
;
1038 /* If we get two back-to-back stalls, and the first stalled transfer
1039 * ends just before a link TRB, the dequeue pointer will be left on
1040 * the link TRB by the code in the while loop. So we have to update
1041 * the dequeue pointer one segment further, or we'll jump off
1042 * the segment into la-la-land.
1044 if (last_trb(xhci
, ep_ring
, ep_ring
->deq_seg
, ep_ring
->dequeue
)) {
1045 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
1046 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
1049 while (ep_ring
->dequeue
!= dev
->eps
[ep_index
].queued_deq_ptr
) {
1050 /* We have more usable TRBs */
1051 ep_ring
->num_trbs_free
++;
1053 if (last_trb(xhci
, ep_ring
, ep_ring
->deq_seg
,
1054 ep_ring
->dequeue
)) {
1055 if (ep_ring
->dequeue
==
1056 dev
->eps
[ep_index
].queued_deq_ptr
)
1058 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
1059 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
1061 if (ep_ring
->dequeue
== dequeue_temp
) {
1068 xhci_dbg(xhci
, "Unable to find new dequeue pointer\n");
1069 ep_ring
->num_trbs_free
= num_trbs_free_temp
;
1074 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1075 * we need to clear the set deq pending flag in the endpoint ring state, so that
1076 * the TD queueing code can ring the doorbell again. We also need to ring the
1077 * endpoint doorbell to restart the ring, but only if there aren't more
1078 * cancellations pending.
1080 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
1081 struct xhci_event_cmd
*event
,
1082 union xhci_trb
*trb
)
1084 unsigned int slot_id
;
1085 unsigned int ep_index
;
1086 unsigned int stream_id
;
1087 struct xhci_ring
*ep_ring
;
1088 struct xhci_virt_device
*dev
;
1089 struct xhci_ep_ctx
*ep_ctx
;
1090 struct xhci_slot_ctx
*slot_ctx
;
1092 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
1093 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1094 stream_id
= TRB_TO_STREAM_ID(le32_to_cpu(trb
->generic
.field
[2]));
1095 dev
= xhci
->devs
[slot_id
];
1097 ep_ring
= xhci_stream_id_to_ring(dev
, ep_index
, stream_id
);
1099 xhci_warn(xhci
, "WARN Set TR deq ptr command for "
1100 "freed stream ID %u\n",
1102 /* XXX: Harmless??? */
1103 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
1107 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
1108 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
1110 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) != COMP_SUCCESS
) {
1111 unsigned int ep_state
;
1112 unsigned int slot_state
;
1114 switch (GET_COMP_CODE(le32_to_cpu(event
->status
))) {
1116 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
1117 "of stream ID configuration\n");
1119 case COMP_CTX_STATE
:
1120 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
1121 "to incorrect slot or ep state.\n");
1122 ep_state
= le32_to_cpu(ep_ctx
->ep_info
);
1123 ep_state
&= EP_STATE_MASK
;
1124 slot_state
= le32_to_cpu(slot_ctx
->dev_state
);
1125 slot_state
= GET_SLOT_STATE(slot_state
);
1126 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1127 "Slot state = %u, EP state = %u",
1128 slot_state
, ep_state
);
1131 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
1132 "slot %u was not enabled.\n", slot_id
);
1135 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
1136 "completion code of %u.\n",
1137 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1140 /* OK what do we do now? The endpoint state is hosed, and we
1141 * should never get to this point if the synchronization between
1142 * queueing, and endpoint state are correct. This might happen
1143 * if the device gets disconnected after we've finished
1144 * cancelling URBs, which might not be an error...
1147 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1148 "Successful Set TR Deq Ptr cmd, deq = @%08llx",
1149 le64_to_cpu(ep_ctx
->deq
));
1150 if (xhci_trb_virt_to_dma(dev
->eps
[ep_index
].queued_deq_seg
,
1151 dev
->eps
[ep_index
].queued_deq_ptr
) ==
1152 (le64_to_cpu(ep_ctx
->deq
) & ~(EP_CTX_CYCLE_MASK
))) {
1153 /* Update the ring's dequeue segment and dequeue pointer
1154 * to reflect the new position.
1156 update_ring_for_set_deq_completion(xhci
, dev
,
1159 xhci_warn(xhci
, "Mismatch between completed Set TR Deq "
1160 "Ptr command & xHCI internal state.\n");
1161 xhci_warn(xhci
, "ep deq seg = %p, deq ptr = %p\n",
1162 dev
->eps
[ep_index
].queued_deq_seg
,
1163 dev
->eps
[ep_index
].queued_deq_ptr
);
1167 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
1168 dev
->eps
[ep_index
].queued_deq_seg
= NULL
;
1169 dev
->eps
[ep_index
].queued_deq_ptr
= NULL
;
1170 /* Restart any rings with pending URBs */
1171 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1174 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
1175 struct xhci_event_cmd
*event
,
1176 union xhci_trb
*trb
)
1179 unsigned int ep_index
;
1181 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
1182 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1183 /* This command will only fail if the endpoint wasn't halted,
1184 * but we don't care.
1186 xhci_dbg_trace(xhci
, trace_xhci_dbg_reset_ep
,
1187 "Ignoring reset ep completion code of %u",
1188 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1190 /* HW with the reset endpoint quirk needs to have a configure endpoint
1191 * command complete before the endpoint can be used. Queue that here
1192 * because the HW can't handle two commands being queued in a row.
1194 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
1195 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1196 "Queueing configure endpoint command");
1197 xhci_queue_configure_endpoint(xhci
,
1198 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
1200 xhci_ring_cmd_db(xhci
);
1202 /* Clear our internal halted state and restart the ring(s) */
1203 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1204 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1208 /* Complete the command and detele it from the devcie's command queue.
1210 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
1211 struct xhci_command
*command
, u32 status
)
1213 command
->status
= status
;
1214 list_del(&command
->cmd_list
);
1215 if (command
->completion
)
1216 complete(command
->completion
);
1218 xhci_free_command(xhci
, command
);
1222 /* Check to see if a command in the device's command queue matches this one.
1223 * Signal the completion or free the command, and return 1. Return 0 if the
1224 * completed command isn't at the head of the command list.
1226 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
1227 struct xhci_virt_device
*virt_dev
,
1228 struct xhci_event_cmd
*event
)
1230 struct xhci_command
*command
;
1232 if (list_empty(&virt_dev
->cmd_list
))
1235 command
= list_entry(virt_dev
->cmd_list
.next
,
1236 struct xhci_command
, cmd_list
);
1237 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
1240 xhci_complete_cmd_in_cmd_wait_list(xhci
, command
,
1241 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1246 * Finding the command trb need to be cancelled and modifying it to
1247 * NO OP command. And if the command is in device's command wait
1248 * list, finishing and freeing it.
1250 * If we can't find the command trb, we think it had already been
1253 static void xhci_cmd_to_noop(struct xhci_hcd
*xhci
, struct xhci_cd
*cur_cd
)
1255 struct xhci_segment
*cur_seg
;
1256 union xhci_trb
*cmd_trb
;
1259 if (xhci
->cmd_ring
->dequeue
== xhci
->cmd_ring
->enqueue
)
1262 /* find the current segment of command ring */
1263 cur_seg
= find_trb_seg(xhci
->cmd_ring
->first_seg
,
1264 xhci
->cmd_ring
->dequeue
, &cycle_state
);
1267 xhci_warn(xhci
, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1268 xhci
->cmd_ring
->dequeue
,
1269 (unsigned long long)
1270 xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1271 xhci
->cmd_ring
->dequeue
));
1272 xhci_debug_ring(xhci
, xhci
->cmd_ring
);
1273 xhci_dbg_ring_ptrs(xhci
, xhci
->cmd_ring
);
1277 /* find the command trb matched by cd from command ring */
1278 for (cmd_trb
= xhci
->cmd_ring
->dequeue
;
1279 cmd_trb
!= xhci
->cmd_ring
->enqueue
;
1280 next_trb(xhci
, xhci
->cmd_ring
, &cur_seg
, &cmd_trb
)) {
1281 /* If the trb is link trb, continue */
1282 if (TRB_TYPE_LINK_LE32(cmd_trb
->generic
.field
[3]))
1285 if (cur_cd
->cmd_trb
== cmd_trb
) {
1287 /* If the command in device's command list, we should
1288 * finish it and free the command structure.
1290 if (cur_cd
->command
)
1291 xhci_complete_cmd_in_cmd_wait_list(xhci
,
1292 cur_cd
->command
, COMP_CMD_STOP
);
1294 /* get cycle state from the origin command trb */
1295 cycle_state
= le32_to_cpu(cmd_trb
->generic
.field
[3])
1298 /* modify the command trb to NO OP command */
1299 cmd_trb
->generic
.field
[0] = 0;
1300 cmd_trb
->generic
.field
[1] = 0;
1301 cmd_trb
->generic
.field
[2] = 0;
1302 cmd_trb
->generic
.field
[3] = cpu_to_le32(
1303 TRB_TYPE(TRB_CMD_NOOP
) | cycle_state
);
1309 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd
*xhci
)
1311 struct xhci_cd
*cur_cd
, *next_cd
;
1313 if (list_empty(&xhci
->cancel_cmd_list
))
1316 list_for_each_entry_safe(cur_cd
, next_cd
,
1317 &xhci
->cancel_cmd_list
, cancel_cmd_list
) {
1318 xhci_cmd_to_noop(xhci
, cur_cd
);
1319 list_del(&cur_cd
->cancel_cmd_list
);
1325 * traversing the cancel_cmd_list. If the command descriptor according
1326 * to cmd_trb is found, the function free it and return 1, otherwise
1329 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd
*xhci
,
1330 union xhci_trb
*cmd_trb
)
1332 struct xhci_cd
*cur_cd
, *next_cd
;
1334 if (list_empty(&xhci
->cancel_cmd_list
))
1337 list_for_each_entry_safe(cur_cd
, next_cd
,
1338 &xhci
->cancel_cmd_list
, cancel_cmd_list
) {
1339 if (cur_cd
->cmd_trb
== cmd_trb
) {
1340 if (cur_cd
->command
)
1341 xhci_complete_cmd_in_cmd_wait_list(xhci
,
1342 cur_cd
->command
, COMP_CMD_STOP
);
1343 list_del(&cur_cd
->cancel_cmd_list
);
1353 * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1354 * trb pointed by the command ring dequeue pointer is the trb we want to
1355 * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1356 * traverse the cancel_cmd_list to trun the all of the commands according
1357 * to command descriptor to NO-OP trb.
1359 static int handle_stopped_cmd_ring(struct xhci_hcd
*xhci
,
1360 int cmd_trb_comp_code
)
1362 int cur_trb_is_good
= 0;
1364 /* Searching the cmd trb pointed by the command ring dequeue
1365 * pointer in command descriptor list. If it is found, free it.
1367 cur_trb_is_good
= xhci_search_cmd_trb_in_cd_list(xhci
,
1368 xhci
->cmd_ring
->dequeue
);
1370 if (cmd_trb_comp_code
== COMP_CMD_ABORT
)
1371 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
1372 else if (cmd_trb_comp_code
== COMP_CMD_STOP
) {
1373 /* traversing the cancel_cmd_list and canceling
1374 * the command according to command descriptor
1376 xhci_cancel_cmd_in_cd_list(xhci
);
1378 xhci
->cmd_ring_state
= CMD_RING_STATE_RUNNING
;
1380 * ring command ring doorbell again to restart the
1383 if (xhci
->cmd_ring
->dequeue
!= xhci
->cmd_ring
->enqueue
)
1384 xhci_ring_cmd_db(xhci
);
1386 return cur_trb_is_good
;
1389 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1390 struct xhci_event_cmd
*event
)
1392 int slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1394 dma_addr_t cmd_dequeue_dma
;
1395 struct xhci_input_control_ctx
*ctrl_ctx
;
1396 struct xhci_virt_device
*virt_dev
;
1397 unsigned int ep_index
;
1398 struct xhci_ring
*ep_ring
;
1399 unsigned int ep_state
;
1401 cmd_dma
= le64_to_cpu(event
->cmd_trb
);
1402 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1403 xhci
->cmd_ring
->dequeue
);
1404 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1405 if (cmd_dequeue_dma
== 0) {
1406 xhci
->error_bitmask
|= 1 << 4;
1409 /* Does the DMA address match our internal dequeue pointer address? */
1410 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
1411 xhci
->error_bitmask
|= 1 << 5;
1415 trace_xhci_cmd_completion(&xhci
->cmd_ring
->dequeue
->generic
,
1416 (struct xhci_generic_trb
*) event
);
1418 if ((GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_CMD_ABORT
) ||
1419 (GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_CMD_STOP
)) {
1420 /* If the return value is 0, we think the trb pointed by
1421 * command ring dequeue pointer is a good trb. The good
1422 * trb means we don't want to cancel the trb, but it have
1423 * been stopped by host. So we should handle it normally.
1424 * Otherwise, driver should invoke inc_deq() and return.
1426 if (handle_stopped_cmd_ring(xhci
,
1427 GET_COMP_CODE(le32_to_cpu(event
->status
)))) {
1428 inc_deq(xhci
, xhci
->cmd_ring
);
1431 /* There is no command to handle if we get a stop event when the
1432 * command ring is empty, event->cmd_trb points to the next
1435 if (xhci
->cmd_ring
->dequeue
== xhci
->cmd_ring
->enqueue
)
1439 switch (le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])
1440 & TRB_TYPE_BITMASK
) {
1441 case TRB_TYPE(TRB_ENABLE_SLOT
):
1442 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_SUCCESS
)
1443 xhci
->slot_id
= slot_id
;
1446 complete(&xhci
->addr_dev
);
1448 case TRB_TYPE(TRB_DISABLE_SLOT
):
1449 if (xhci
->devs
[slot_id
]) {
1450 if (xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)
1451 /* Delete default control endpoint resources */
1452 xhci_free_device_endpoint_resources(xhci
,
1453 xhci
->devs
[slot_id
], true);
1454 xhci_free_virt_device(xhci
, slot_id
);
1457 case TRB_TYPE(TRB_CONFIG_EP
):
1458 virt_dev
= xhci
->devs
[slot_id
];
1459 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1462 * Configure endpoint commands can come from the USB core
1463 * configuration or alt setting changes, or because the HW
1464 * needed an extra configure endpoint command after a reset
1465 * endpoint command or streams were being configured.
1466 * If the command was for a halted endpoint, the xHCI driver
1467 * is not waiting on the configure endpoint command.
1469 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
1472 xhci_warn(xhci
, "Could not get input context, bad type.\n");
1475 /* Input ctx add_flags are the endpoint index plus one */
1476 ep_index
= xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx
->add_flags
)) - 1;
1477 /* A usb_set_interface() call directly after clearing a halted
1478 * condition may race on this quirky hardware. Not worth
1479 * worrying about, since this is prototype hardware. Not sure
1480 * if this will work for streams, but streams support was
1481 * untested on this prototype.
1483 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1484 ep_index
!= (unsigned int) -1 &&
1485 le32_to_cpu(ctrl_ctx
->add_flags
) - SLOT_FLAG
==
1486 le32_to_cpu(ctrl_ctx
->drop_flags
)) {
1487 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1488 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1489 if (!(ep_state
& EP_HALTED
))
1490 goto bandwidth_change
;
1491 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1492 "Completed config ep cmd - "
1493 "last ep index = %d, state = %d",
1494 ep_index
, ep_state
);
1495 /* Clear internal halted state and restart ring(s) */
1496 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
1498 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1502 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1503 "Completed config ep cmd");
1504 xhci
->devs
[slot_id
]->cmd_status
=
1505 GET_COMP_CODE(le32_to_cpu(event
->status
));
1506 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1508 case TRB_TYPE(TRB_EVAL_CONTEXT
):
1509 virt_dev
= xhci
->devs
[slot_id
];
1510 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1512 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1513 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1515 case TRB_TYPE(TRB_ADDR_DEV
):
1516 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1517 complete(&xhci
->addr_dev
);
1519 case TRB_TYPE(TRB_STOP_RING
):
1520 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
, event
);
1522 case TRB_TYPE(TRB_SET_DEQ
):
1523 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1525 case TRB_TYPE(TRB_CMD_NOOP
):
1527 case TRB_TYPE(TRB_RESET_EP
):
1528 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1530 case TRB_TYPE(TRB_RESET_DEV
):
1531 xhci_dbg(xhci
, "Completed reset device command.\n");
1532 slot_id
= TRB_TO_SLOT_ID(
1533 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
1534 virt_dev
= xhci
->devs
[slot_id
];
1536 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
);
1538 xhci_warn(xhci
, "Reset device command completion "
1539 "for disabled slot %u\n", slot_id
);
1541 case TRB_TYPE(TRB_NEC_GET_FW
):
1542 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1543 xhci
->error_bitmask
|= 1 << 6;
1546 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1547 "NEC firmware version %2x.%02x",
1548 NEC_FW_MAJOR(le32_to_cpu(event
->status
)),
1549 NEC_FW_MINOR(le32_to_cpu(event
->status
)));
1552 /* Skip over unknown commands on the event ring */
1553 xhci
->error_bitmask
|= 1 << 6;
1556 inc_deq(xhci
, xhci
->cmd_ring
);
1559 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1560 union xhci_trb
*event
)
1564 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(event
->generic
.field
[3]));
1565 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1566 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1567 handle_cmd_completion(xhci
, &event
->event_cmd
);
1570 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1571 * port registers -- USB 3.0 and USB 2.0).
1573 * Returns a zero-based port number, which is suitable for indexing into each of
1574 * the split roothubs' port arrays and bus state arrays.
1575 * Add one to it in order to call xhci_find_slot_id_by_port.
1577 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd
*hcd
,
1578 struct xhci_hcd
*xhci
, u32 port_id
)
1581 unsigned int num_similar_speed_ports
= 0;
1583 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1584 * and usb2_ports are 0-based indexes. Count the number of similar
1585 * speed ports, up to 1 port before this port.
1587 for (i
= 0; i
< (port_id
- 1); i
++) {
1588 u8 port_speed
= xhci
->port_array
[i
];
1591 * Skip ports that don't have known speeds, or have duplicate
1592 * Extended Capabilities port speed entries.
1594 if (port_speed
== 0 || port_speed
== DUPLICATE_ENTRY
)
1598 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1599 * 1.1 ports are under the USB 2.0 hub. If the port speed
1600 * matches the device speed, it's a similar speed port.
1602 if ((port_speed
== 0x03) == (hcd
->speed
== HCD_USB3
))
1603 num_similar_speed_ports
++;
1605 return num_similar_speed_ports
;
1608 static void handle_device_notification(struct xhci_hcd
*xhci
,
1609 union xhci_trb
*event
)
1612 struct usb_device
*udev
;
1614 slot_id
= TRB_TO_SLOT_ID(event
->generic
.field
[3]);
1615 if (!xhci
->devs
[slot_id
]) {
1616 xhci_warn(xhci
, "Device Notification event for "
1617 "unused slot %u\n", slot_id
);
1621 xhci_dbg(xhci
, "Device Wake Notification event for slot ID %u\n",
1623 udev
= xhci
->devs
[slot_id
]->udev
;
1624 if (udev
&& udev
->parent
)
1625 usb_wakeup_notification(udev
->parent
, udev
->portnum
);
1628 static void handle_port_status(struct xhci_hcd
*xhci
,
1629 union xhci_trb
*event
)
1631 struct usb_hcd
*hcd
;
1636 unsigned int faked_port_index
;
1638 struct xhci_bus_state
*bus_state
;
1639 __le32 __iomem
**port_array
;
1640 bool bogus_port_status
= false;
1642 /* Port status change events always have a successful completion code */
1643 if (GET_COMP_CODE(le32_to_cpu(event
->generic
.field
[2])) != COMP_SUCCESS
) {
1644 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1645 xhci
->error_bitmask
|= 1 << 8;
1647 port_id
= GET_PORT_ID(le32_to_cpu(event
->generic
.field
[0]));
1648 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1650 max_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1651 if ((port_id
<= 0) || (port_id
> max_ports
)) {
1652 xhci_warn(xhci
, "Invalid port id %d\n", port_id
);
1653 inc_deq(xhci
, xhci
->event_ring
);
1657 /* Figure out which usb_hcd this port is attached to:
1658 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1660 major_revision
= xhci
->port_array
[port_id
- 1];
1662 /* Find the right roothub. */
1663 hcd
= xhci_to_hcd(xhci
);
1664 if ((major_revision
== 0x03) != (hcd
->speed
== HCD_USB3
))
1665 hcd
= xhci
->shared_hcd
;
1667 if (major_revision
== 0) {
1668 xhci_warn(xhci
, "Event for port %u not in "
1669 "Extended Capabilities, ignoring.\n",
1671 bogus_port_status
= true;
1674 if (major_revision
== DUPLICATE_ENTRY
) {
1675 xhci_warn(xhci
, "Event for port %u duplicated in"
1676 "Extended Capabilities, ignoring.\n",
1678 bogus_port_status
= true;
1683 * Hardware port IDs reported by a Port Status Change Event include USB
1684 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1685 * resume event, but we first need to translate the hardware port ID
1686 * into the index into the ports on the correct split roothub, and the
1687 * correct bus_state structure.
1689 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1690 if (hcd
->speed
== HCD_USB3
)
1691 port_array
= xhci
->usb3_ports
;
1693 port_array
= xhci
->usb2_ports
;
1694 /* Find the faked port hub number */
1695 faked_port_index
= find_faked_portnum_from_hw_portnum(hcd
, xhci
,
1698 temp
= xhci_readl(xhci
, port_array
[faked_port_index
]);
1699 if (hcd
->state
== HC_STATE_SUSPENDED
) {
1700 xhci_dbg(xhci
, "resume root hub\n");
1701 usb_hcd_resume_root_hub(hcd
);
1704 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_RESUME
) {
1705 xhci_dbg(xhci
, "port resume event for port %d\n", port_id
);
1707 temp1
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1708 if (!(temp1
& CMD_RUN
)) {
1709 xhci_warn(xhci
, "xHC is not running.\n");
1713 if (DEV_SUPERSPEED(temp
)) {
1714 xhci_dbg(xhci
, "remote wake SS port %d\n", port_id
);
1715 /* Set a flag to say the port signaled remote wakeup,
1716 * so we can tell the difference between the end of
1717 * device and host initiated resume.
1719 bus_state
->port_remote_wakeup
|= 1 << faked_port_index
;
1720 xhci_test_and_clear_bit(xhci
, port_array
,
1721 faked_port_index
, PORT_PLC
);
1722 xhci_set_link_state(xhci
, port_array
, faked_port_index
,
1724 /* Need to wait until the next link state change
1725 * indicates the device is actually in U0.
1727 bogus_port_status
= true;
1730 xhci_dbg(xhci
, "resume HS port %d\n", port_id
);
1731 bus_state
->resume_done
[faked_port_index
] = jiffies
+
1732 msecs_to_jiffies(20);
1733 set_bit(faked_port_index
, &bus_state
->resuming_ports
);
1734 mod_timer(&hcd
->rh_timer
,
1735 bus_state
->resume_done
[faked_port_index
]);
1736 /* Do the rest in GetPortStatus */
1740 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_U0
&&
1741 DEV_SUPERSPEED(temp
)) {
1742 xhci_dbg(xhci
, "resume SS port %d finished\n", port_id
);
1743 /* We've just brought the device into U0 through either the
1744 * Resume state after a device remote wakeup, or through the
1745 * U3Exit state after a host-initiated resume. If it's a device
1746 * initiated remote wake, don't pass up the link state change,
1747 * so the roothub behavior is consistent with external
1748 * USB 3.0 hub behavior.
1750 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1751 faked_port_index
+ 1);
1752 if (slot_id
&& xhci
->devs
[slot_id
])
1753 xhci_ring_device(xhci
, slot_id
);
1754 if (bus_state
->port_remote_wakeup
& (1 << faked_port_index
)) {
1755 bus_state
->port_remote_wakeup
&=
1756 ~(1 << faked_port_index
);
1757 xhci_test_and_clear_bit(xhci
, port_array
,
1758 faked_port_index
, PORT_PLC
);
1759 usb_wakeup_notification(hcd
->self
.root_hub
,
1760 faked_port_index
+ 1);
1761 bogus_port_status
= true;
1767 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1768 * RExit to a disconnect state). If so, let the the driver know it's
1769 * out of the RExit state.
1771 if (!DEV_SUPERSPEED(temp
) &&
1772 test_and_clear_bit(faked_port_index
,
1773 &bus_state
->rexit_ports
)) {
1774 complete(&bus_state
->rexit_done
[faked_port_index
]);
1775 bogus_port_status
= true;
1779 if (hcd
->speed
!= HCD_USB3
)
1780 xhci_test_and_clear_bit(xhci
, port_array
, faked_port_index
,
1784 /* Update event ring dequeue pointer before dropping the lock */
1785 inc_deq(xhci
, xhci
->event_ring
);
1787 /* Don't make the USB core poll the roothub if we got a bad port status
1788 * change event. Besides, at that point we can't tell which roothub
1789 * (USB 2.0 or USB 3.0) to kick.
1791 if (bogus_port_status
)
1795 * xHCI port-status-change events occur when the "or" of all the
1796 * status-change bits in the portsc register changes from 0 to 1.
1797 * New status changes won't cause an event if any other change
1798 * bits are still set. When an event occurs, switch over to
1799 * polling to avoid losing status changes.
1801 xhci_dbg(xhci
, "%s: starting port polling.\n", __func__
);
1802 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1803 spin_unlock(&xhci
->lock
);
1804 /* Pass this up to the core */
1805 usb_hcd_poll_rh_status(hcd
);
1806 spin_lock(&xhci
->lock
);
1810 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1811 * at end_trb, which may be in another segment. If the suspect DMA address is a
1812 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1815 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
1816 union xhci_trb
*start_trb
,
1817 union xhci_trb
*end_trb
,
1818 dma_addr_t suspect_dma
)
1820 dma_addr_t start_dma
;
1821 dma_addr_t end_seg_dma
;
1822 dma_addr_t end_trb_dma
;
1823 struct xhci_segment
*cur_seg
;
1825 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1826 cur_seg
= start_seg
;
1831 /* We may get an event for a Link TRB in the middle of a TD */
1832 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1833 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1834 /* If the end TRB isn't in this segment, this is set to 0 */
1835 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1837 if (end_trb_dma
> 0) {
1838 /* The end TRB is in this segment, so suspect should be here */
1839 if (start_dma
<= end_trb_dma
) {
1840 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1843 /* Case for one segment with
1844 * a TD wrapped around to the top
1846 if ((suspect_dma
>= start_dma
&&
1847 suspect_dma
<= end_seg_dma
) ||
1848 (suspect_dma
>= cur_seg
->dma
&&
1849 suspect_dma
<= end_trb_dma
))
1854 /* Might still be somewhere in this segment */
1855 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1858 cur_seg
= cur_seg
->next
;
1859 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1860 } while (cur_seg
!= start_seg
);
1865 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1866 unsigned int slot_id
, unsigned int ep_index
,
1867 unsigned int stream_id
,
1868 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1870 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1871 ep
->ep_state
|= EP_HALTED
;
1872 ep
->stopped_td
= td
;
1873 ep
->stopped_trb
= event_trb
;
1874 ep
->stopped_stream
= stream_id
;
1876 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1877 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1879 ep
->stopped_td
= NULL
;
1880 ep
->stopped_trb
= NULL
;
1881 ep
->stopped_stream
= 0;
1883 xhci_ring_cmd_db(xhci
);
1886 /* Check if an error has halted the endpoint ring. The class driver will
1887 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1888 * However, a babble and other errors also halt the endpoint ring, and the class
1889 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1890 * Ring Dequeue Pointer command manually.
1892 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1893 struct xhci_ep_ctx
*ep_ctx
,
1894 unsigned int trb_comp_code
)
1896 /* TRB completion codes that may require a manual halt cleanup */
1897 if (trb_comp_code
== COMP_TX_ERR
||
1898 trb_comp_code
== COMP_BABBLE
||
1899 trb_comp_code
== COMP_SPLIT_ERR
)
1900 /* The 0.96 spec says a babbling control endpoint
1901 * is not halted. The 0.96 spec says it is. Some HW
1902 * claims to be 0.95 compliant, but it halts the control
1903 * endpoint anyway. Check if a babble halted the
1906 if ((ep_ctx
->ep_info
& cpu_to_le32(EP_STATE_MASK
)) ==
1907 cpu_to_le32(EP_STATE_HALTED
))
1913 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
1915 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1916 /* Vendor defined "informational" completion code,
1917 * treat as not-an-error.
1919 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1921 xhci_dbg(xhci
, "Treating code as success.\n");
1928 * Finish the td processing, remove the td from td list;
1929 * Return 1 if the urb can be given back.
1931 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1932 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1933 struct xhci_virt_ep
*ep
, int *status
, bool skip
)
1935 struct xhci_virt_device
*xdev
;
1936 struct xhci_ring
*ep_ring
;
1937 unsigned int slot_id
;
1939 struct urb
*urb
= NULL
;
1940 struct xhci_ep_ctx
*ep_ctx
;
1942 struct urb_priv
*urb_priv
;
1945 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1946 xdev
= xhci
->devs
[slot_id
];
1947 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1948 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1949 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1950 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1955 if (trb_comp_code
== COMP_STOP_INVAL
||
1956 trb_comp_code
== COMP_STOP
) {
1957 /* The Endpoint Stop Command completion will take care of any
1958 * stopped TDs. A stopped TD may be restarted, so don't update
1959 * the ring dequeue pointer or take this TD off any lists yet.
1961 ep
->stopped_td
= td
;
1962 ep
->stopped_trb
= event_trb
;
1965 if (trb_comp_code
== COMP_STALL
) {
1966 /* The transfer is completed from the driver's
1967 * perspective, but we need to issue a set dequeue
1968 * command for this stalled endpoint to move the dequeue
1969 * pointer past the TD. We can't do that here because
1970 * the halt condition must be cleared first. Let the
1971 * USB class driver clear the stall later.
1973 ep
->stopped_td
= td
;
1974 ep
->stopped_trb
= event_trb
;
1975 ep
->stopped_stream
= ep_ring
->stream_id
;
1976 } else if (xhci_requires_manual_halt_cleanup(xhci
,
1977 ep_ctx
, trb_comp_code
)) {
1978 /* Other types of errors halt the endpoint, but the
1979 * class driver doesn't call usb_reset_endpoint() unless
1980 * the error is -EPIPE. Clear the halted status in the
1981 * xHCI hardware manually.
1983 xhci_cleanup_halted_endpoint(xhci
,
1984 slot_id
, ep_index
, ep_ring
->stream_id
,
1987 /* Update ring dequeue pointer */
1988 while (ep_ring
->dequeue
!= td
->last_trb
)
1989 inc_deq(xhci
, ep_ring
);
1990 inc_deq(xhci
, ep_ring
);
1994 /* Clean up the endpoint's TD list */
1996 urb_priv
= urb
->hcpriv
;
1998 /* Do one last check of the actual transfer length.
1999 * If the host controller said we transferred more data than
2000 * the buffer length, urb->actual_length will be a very big
2001 * number (since it's unsigned). Play it safe and say we didn't
2002 * transfer anything.
2004 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
2005 xhci_warn(xhci
, "URB transfer length is wrong, "
2006 "xHC issue? req. len = %u, "
2008 urb
->transfer_buffer_length
,
2009 urb
->actual_length
);
2010 urb
->actual_length
= 0;
2011 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2012 *status
= -EREMOTEIO
;
2016 list_del_init(&td
->td_list
);
2017 /* Was this TD slated to be cancelled but completed anyway? */
2018 if (!list_empty(&td
->cancelled_td_list
))
2019 list_del_init(&td
->cancelled_td_list
);
2022 /* Giveback the urb when all the tds are completed */
2023 if (urb_priv
->td_cnt
== urb_priv
->length
) {
2025 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
2026 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
2027 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
2029 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
2030 usb_amd_quirk_pll_enable();
2040 * Process control tds, update urb status and actual_length.
2042 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2043 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
2044 struct xhci_virt_ep
*ep
, int *status
)
2046 struct xhci_virt_device
*xdev
;
2047 struct xhci_ring
*ep_ring
;
2048 unsigned int slot_id
;
2050 struct xhci_ep_ctx
*ep_ctx
;
2053 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
2054 xdev
= xhci
->devs
[slot_id
];
2055 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
2056 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2057 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2058 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2060 switch (trb_comp_code
) {
2062 if (event_trb
== ep_ring
->dequeue
) {
2063 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB "
2064 "without IOC set??\n");
2065 *status
= -ESHUTDOWN
;
2066 } else if (event_trb
!= td
->last_trb
) {
2067 xhci_warn(xhci
, "WARN: Success on ctrl data TRB "
2068 "without IOC set??\n");
2069 *status
= -ESHUTDOWN
;
2075 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2076 *status
= -EREMOTEIO
;
2080 case COMP_STOP_INVAL
:
2082 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2084 if (!xhci_requires_manual_halt_cleanup(xhci
,
2085 ep_ctx
, trb_comp_code
))
2087 xhci_dbg(xhci
, "TRB error code %u, "
2088 "halted endpoint index = %u\n",
2089 trb_comp_code
, ep_index
);
2090 /* else fall through */
2092 /* Did we transfer part of the data (middle) phase? */
2093 if (event_trb
!= ep_ring
->dequeue
&&
2094 event_trb
!= td
->last_trb
)
2095 td
->urb
->actual_length
=
2096 td
->urb
->transfer_buffer_length
-
2097 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2099 td
->urb
->actual_length
= 0;
2101 xhci_cleanup_halted_endpoint(xhci
,
2102 slot_id
, ep_index
, 0, td
, event_trb
);
2103 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, true);
2106 * Did we transfer any data, despite the errors that might have
2107 * happened? I.e. did we get past the setup stage?
2109 if (event_trb
!= ep_ring
->dequeue
) {
2110 /* The event was for the status stage */
2111 if (event_trb
== td
->last_trb
) {
2112 if (td
->urb
->actual_length
!= 0) {
2113 /* Don't overwrite a previously set error code
2115 if ((*status
== -EINPROGRESS
|| *status
== 0) &&
2116 (td
->urb
->transfer_flags
2117 & URB_SHORT_NOT_OK
))
2118 /* Did we already see a short data
2120 *status
= -EREMOTEIO
;
2122 td
->urb
->actual_length
=
2123 td
->urb
->transfer_buffer_length
;
2126 /* Maybe the event was for the data stage? */
2127 td
->urb
->actual_length
=
2128 td
->urb
->transfer_buffer_length
-
2129 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2130 xhci_dbg(xhci
, "Waiting for status "
2136 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2140 * Process isochronous tds, update urb packet status and actual_length.
2142 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2143 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
2144 struct xhci_virt_ep
*ep
, int *status
)
2146 struct xhci_ring
*ep_ring
;
2147 struct urb_priv
*urb_priv
;
2150 union xhci_trb
*cur_trb
;
2151 struct xhci_segment
*cur_seg
;
2152 struct usb_iso_packet_descriptor
*frame
;
2154 bool skip_td
= false;
2156 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2157 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2158 urb_priv
= td
->urb
->hcpriv
;
2159 idx
= urb_priv
->td_cnt
;
2160 frame
= &td
->urb
->iso_frame_desc
[idx
];
2162 /* handle completion code */
2163 switch (trb_comp_code
) {
2165 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0) {
2169 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
2170 trb_comp_code
= COMP_SHORT_TX
;
2172 frame
->status
= td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
?
2176 frame
->status
= -ECOMM
;
2179 case COMP_BUFF_OVER
:
2181 frame
->status
= -EOVERFLOW
;
2187 frame
->status
= -EPROTO
;
2191 case COMP_STOP_INVAL
:
2198 if (trb_comp_code
== COMP_SUCCESS
|| skip_td
) {
2199 frame
->actual_length
= frame
->length
;
2200 td
->urb
->actual_length
+= frame
->length
;
2202 for (cur_trb
= ep_ring
->dequeue
,
2203 cur_seg
= ep_ring
->deq_seg
; cur_trb
!= event_trb
;
2204 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
2205 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
2206 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
2207 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
2209 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
2210 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2212 if (trb_comp_code
!= COMP_STOP_INVAL
) {
2213 frame
->actual_length
= len
;
2214 td
->urb
->actual_length
+= len
;
2218 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2221 static int skip_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2222 struct xhci_transfer_event
*event
,
2223 struct xhci_virt_ep
*ep
, int *status
)
2225 struct xhci_ring
*ep_ring
;
2226 struct urb_priv
*urb_priv
;
2227 struct usb_iso_packet_descriptor
*frame
;
2230 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2231 urb_priv
= td
->urb
->hcpriv
;
2232 idx
= urb_priv
->td_cnt
;
2233 frame
= &td
->urb
->iso_frame_desc
[idx
];
2235 /* The transfer is partly done. */
2236 frame
->status
= -EXDEV
;
2238 /* calc actual length */
2239 frame
->actual_length
= 0;
2241 /* Update ring dequeue pointer */
2242 while (ep_ring
->dequeue
!= td
->last_trb
)
2243 inc_deq(xhci
, ep_ring
);
2244 inc_deq(xhci
, ep_ring
);
2246 return finish_td(xhci
, td
, NULL
, event
, ep
, status
, true);
2250 * Process bulk and interrupt tds, update urb status and actual_length.
2252 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2253 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
2254 struct xhci_virt_ep
*ep
, int *status
)
2256 struct xhci_ring
*ep_ring
;
2257 union xhci_trb
*cur_trb
;
2258 struct xhci_segment
*cur_seg
;
2261 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2262 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2264 switch (trb_comp_code
) {
2266 /* Double check that the HW transferred everything. */
2267 if (event_trb
!= td
->last_trb
||
2268 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
2269 xhci_warn(xhci
, "WARN Successful completion "
2271 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2272 *status
= -EREMOTEIO
;
2275 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
2276 trb_comp_code
= COMP_SHORT_TX
;
2282 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2283 *status
= -EREMOTEIO
;
2288 /* Others already handled above */
2291 if (trb_comp_code
== COMP_SHORT_TX
)
2292 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, "
2293 "%d bytes untransferred\n",
2294 td
->urb
->ep
->desc
.bEndpointAddress
,
2295 td
->urb
->transfer_buffer_length
,
2296 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)));
2297 /* Fast path - was this the last TRB in the TD for this URB? */
2298 if (event_trb
== td
->last_trb
) {
2299 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
2300 td
->urb
->actual_length
=
2301 td
->urb
->transfer_buffer_length
-
2302 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2303 if (td
->urb
->transfer_buffer_length
<
2304 td
->urb
->actual_length
) {
2305 xhci_warn(xhci
, "HC gave bad length "
2306 "of %d bytes left\n",
2307 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)));
2308 td
->urb
->actual_length
= 0;
2309 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2310 *status
= -EREMOTEIO
;
2314 /* Don't overwrite a previously set error code */
2315 if (*status
== -EINPROGRESS
) {
2316 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2317 *status
= -EREMOTEIO
;
2322 td
->urb
->actual_length
=
2323 td
->urb
->transfer_buffer_length
;
2324 /* Ignore a short packet completion if the
2325 * untransferred length was zero.
2327 if (*status
== -EREMOTEIO
)
2331 /* Slow path - walk the list, starting from the dequeue
2332 * pointer, to get the actual length transferred.
2334 td
->urb
->actual_length
= 0;
2335 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
2336 cur_trb
!= event_trb
;
2337 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
2338 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
2339 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
2340 td
->urb
->actual_length
+=
2341 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
2343 /* If the ring didn't stop on a Link or No-op TRB, add
2344 * in the actual bytes transferred from the Normal TRB
2346 if (trb_comp_code
!= COMP_STOP_INVAL
)
2347 td
->urb
->actual_length
+=
2348 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
2349 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2352 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2356 * If this function returns an error condition, it means it got a Transfer
2357 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2358 * At this point, the host controller is probably hosed and should be reset.
2360 static int handle_tx_event(struct xhci_hcd
*xhci
,
2361 struct xhci_transfer_event
*event
)
2362 __releases(&xhci
->lock
)
2363 __acquires(&xhci
->lock
)
2365 struct xhci_virt_device
*xdev
;
2366 struct xhci_virt_ep
*ep
;
2367 struct xhci_ring
*ep_ring
;
2368 unsigned int slot_id
;
2370 struct xhci_td
*td
= NULL
;
2371 dma_addr_t event_dma
;
2372 struct xhci_segment
*event_seg
;
2373 union xhci_trb
*event_trb
;
2374 struct urb
*urb
= NULL
;
2375 int status
= -EINPROGRESS
;
2376 struct urb_priv
*urb_priv
;
2377 struct xhci_ep_ctx
*ep_ctx
;
2378 struct list_head
*tmp
;
2383 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
2384 xdev
= xhci
->devs
[slot_id
];
2386 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
2387 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2388 (unsigned long long) xhci_trb_virt_to_dma(
2389 xhci
->event_ring
->deq_seg
,
2390 xhci
->event_ring
->dequeue
),
2391 lower_32_bits(le64_to_cpu(event
->buffer
)),
2392 upper_32_bits(le64_to_cpu(event
->buffer
)),
2393 le32_to_cpu(event
->transfer_len
),
2394 le32_to_cpu(event
->flags
));
2395 xhci_dbg(xhci
, "Event ring:\n");
2396 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2400 /* Endpoint ID is 1 based, our index is zero based */
2401 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
2402 ep
= &xdev
->eps
[ep_index
];
2403 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2404 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2406 (le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) ==
2407 EP_STATE_DISABLED
) {
2408 xhci_err(xhci
, "ERROR Transfer event for disabled endpoint "
2409 "or incorrect stream ring\n");
2410 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2411 (unsigned long long) xhci_trb_virt_to_dma(
2412 xhci
->event_ring
->deq_seg
,
2413 xhci
->event_ring
->dequeue
),
2414 lower_32_bits(le64_to_cpu(event
->buffer
)),
2415 upper_32_bits(le64_to_cpu(event
->buffer
)),
2416 le32_to_cpu(event
->transfer_len
),
2417 le32_to_cpu(event
->flags
));
2418 xhci_dbg(xhci
, "Event ring:\n");
2419 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2423 /* Count current td numbers if ep->skip is set */
2425 list_for_each(tmp
, &ep_ring
->td_list
)
2429 event_dma
= le64_to_cpu(event
->buffer
);
2430 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2431 /* Look for common error cases */
2432 switch (trb_comp_code
) {
2433 /* Skip codes that require special handling depending on
2437 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0)
2439 if (xhci
->quirks
& XHCI_TRUST_TX_LENGTH
)
2440 trb_comp_code
= COMP_SHORT_TX
;
2442 xhci_warn_ratelimited(xhci
,
2443 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2447 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
2449 case COMP_STOP_INVAL
:
2450 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
2453 xhci_dbg(xhci
, "Stalled endpoint\n");
2454 ep
->ep_state
|= EP_HALTED
;
2458 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
2461 case COMP_SPLIT_ERR
:
2463 xhci_dbg(xhci
, "Transfer error on endpoint\n");
2467 xhci_dbg(xhci
, "Babble error on endpoint\n");
2468 status
= -EOVERFLOW
;
2471 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
2475 xhci_warn(xhci
, "WARN: bandwidth overrun event on endpoint\n");
2477 case COMP_BUFF_OVER
:
2478 xhci_warn(xhci
, "WARN: buffer overrun event on endpoint\n");
2482 * When the Isoch ring is empty, the xHC will generate
2483 * a Ring Overrun Event for IN Isoch endpoint or Ring
2484 * Underrun Event for OUT Isoch endpoint.
2486 xhci_dbg(xhci
, "underrun event on endpoint\n");
2487 if (!list_empty(&ep_ring
->td_list
))
2488 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
2489 "still with TDs queued?\n",
2490 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2494 xhci_dbg(xhci
, "overrun event on endpoint\n");
2495 if (!list_empty(&ep_ring
->td_list
))
2496 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
2497 "still with TDs queued?\n",
2498 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2502 xhci_warn(xhci
, "WARN: detect an incompatible device");
2505 case COMP_MISSED_INT
:
2507 * When encounter missed service error, one or more isoc tds
2508 * may be missed by xHC.
2509 * Set skip flag of the ep_ring; Complete the missed tds as
2510 * short transfer when process the ep_ring next time.
2513 xhci_dbg(xhci
, "Miss service interval error, set skip flag\n");
2516 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
2520 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably "
2526 /* This TRB should be in the TD at the head of this ring's
2529 if (list_empty(&ep_ring
->td_list
)) {
2531 * A stopped endpoint may generate an extra completion
2532 * event if the device was suspended. Don't print
2535 if (!(trb_comp_code
== COMP_STOP
||
2536 trb_comp_code
== COMP_STOP_INVAL
)) {
2537 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2538 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2540 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
2541 (le32_to_cpu(event
->flags
) &
2542 TRB_TYPE_BITMASK
)>>10);
2543 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
2547 xhci_dbg(xhci
, "td_list is empty while skip "
2548 "flag set. Clear skip flag.\n");
2554 /* We've skipped all the TDs on the ep ring when ep->skip set */
2555 if (ep
->skip
&& td_num
== 0) {
2557 xhci_dbg(xhci
, "All tds on the ep_ring skipped. "
2558 "Clear skip flag.\n");
2563 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
2567 /* Is this a TRB in the currently executing TD? */
2568 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
2569 td
->last_trb
, event_dma
);
2572 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2573 * is not in the current TD pointed by ep_ring->dequeue because
2574 * that the hardware dequeue pointer still at the previous TRB
2575 * of the current TD. The previous TRB maybe a Link TD or the
2576 * last TRB of the previous TD. The command completion handle
2577 * will take care the rest.
2579 if (!event_seg
&& trb_comp_code
== COMP_STOP_INVAL
) {
2586 !usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
)) {
2587 /* Some host controllers give a spurious
2588 * successful event after a short transfer.
2591 if ((xhci
->quirks
& XHCI_SPURIOUS_SUCCESS
) &&
2592 ep_ring
->last_td_was_short
) {
2593 ep_ring
->last_td_was_short
= false;
2597 /* HC is busted, give up! */
2599 "ERROR Transfer event TRB DMA ptr not "
2600 "part of current TD\n");
2604 ret
= skip_isoc_td(xhci
, td
, event
, ep
, &status
);
2607 if (trb_comp_code
== COMP_SHORT_TX
)
2608 ep_ring
->last_td_was_short
= true;
2610 ep_ring
->last_td_was_short
= false;
2613 xhci_dbg(xhci
, "Found td. Clear skip flag.\n");
2617 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) /
2618 sizeof(*event_trb
)];
2620 * No-op TRB should not trigger interrupts.
2621 * If event_trb is a no-op TRB, it means the
2622 * corresponding TD has been cancelled. Just ignore
2625 if (TRB_TYPE_NOOP_LE32(event_trb
->generic
.field
[3])) {
2627 "event_trb is a no-op TRB. Skip it\n");
2631 /* Now update the urb's actual_length and give back to
2634 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
2635 ret
= process_ctrl_td(xhci
, td
, event_trb
, event
, ep
,
2637 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
2638 ret
= process_isoc_td(xhci
, td
, event_trb
, event
, ep
,
2641 ret
= process_bulk_intr_td(xhci
, td
, event_trb
, event
,
2646 * Do not update event ring dequeue pointer if ep->skip is set.
2647 * Will roll back to continue process missed tds.
2649 if (trb_comp_code
== COMP_MISSED_INT
|| !ep
->skip
) {
2650 inc_deq(xhci
, xhci
->event_ring
);
2655 urb_priv
= urb
->hcpriv
;
2656 /* Leave the TD around for the reset endpoint function
2657 * to use(but only if it's not a control endpoint,
2658 * since we already queued the Set TR dequeue pointer
2659 * command for stalled control endpoints).
2661 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
2662 (trb_comp_code
!= COMP_STALL
&&
2663 trb_comp_code
!= COMP_BABBLE
))
2664 xhci_urb_free_priv(xhci
, urb_priv
);
2668 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2669 if ((urb
->actual_length
!= urb
->transfer_buffer_length
&&
2670 (urb
->transfer_flags
&
2671 URB_SHORT_NOT_OK
)) ||
2673 !usb_endpoint_xfer_isoc(&urb
->ep
->desc
)))
2674 xhci_dbg(xhci
, "Giveback URB %p, len = %d, "
2675 "expected = %d, status = %d\n",
2676 urb
, urb
->actual_length
,
2677 urb
->transfer_buffer_length
,
2679 spin_unlock(&xhci
->lock
);
2680 /* EHCI, UHCI, and OHCI always unconditionally set the
2681 * urb->status of an isochronous endpoint to 0.
2683 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
2685 usb_hcd_giveback_urb(bus_to_hcd(urb
->dev
->bus
), urb
, status
);
2686 spin_lock(&xhci
->lock
);
2690 * If ep->skip is set, it means there are missed tds on the
2691 * endpoint ring need to take care of.
2692 * Process them as short transfer until reach the td pointed by
2695 } while (ep
->skip
&& trb_comp_code
!= COMP_MISSED_INT
);
2701 * This function handles all OS-owned events on the event ring. It may drop
2702 * xhci->lock between event processing (e.g. to pass up port status changes).
2703 * Returns >0 for "possibly more events to process" (caller should call again),
2704 * otherwise 0 if done. In future, <0 returns should indicate error code.
2706 static int xhci_handle_event(struct xhci_hcd
*xhci
)
2708 union xhci_trb
*event
;
2709 int update_ptrs
= 1;
2712 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
2713 xhci
->error_bitmask
|= 1 << 1;
2717 event
= xhci
->event_ring
->dequeue
;
2718 /* Does the HC or OS own the TRB? */
2719 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_CYCLE
) !=
2720 xhci
->event_ring
->cycle_state
) {
2721 xhci
->error_bitmask
|= 1 << 2;
2726 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2727 * speculative reads of the event's flags/data below.
2730 /* FIXME: Handle more event types. */
2731 switch ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
)) {
2732 case TRB_TYPE(TRB_COMPLETION
):
2733 handle_cmd_completion(xhci
, &event
->event_cmd
);
2735 case TRB_TYPE(TRB_PORT_STATUS
):
2736 handle_port_status(xhci
, event
);
2739 case TRB_TYPE(TRB_TRANSFER
):
2740 ret
= handle_tx_event(xhci
, &event
->trans_event
);
2742 xhci
->error_bitmask
|= 1 << 9;
2746 case TRB_TYPE(TRB_DEV_NOTE
):
2747 handle_device_notification(xhci
, event
);
2750 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
) >=
2752 handle_vendor_event(xhci
, event
);
2754 xhci
->error_bitmask
|= 1 << 3;
2756 /* Any of the above functions may drop and re-acquire the lock, so check
2757 * to make sure a watchdog timer didn't mark the host as non-responsive.
2759 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2760 xhci_dbg(xhci
, "xHCI host dying, returning from "
2761 "event handler.\n");
2766 /* Update SW event ring dequeue pointer */
2767 inc_deq(xhci
, xhci
->event_ring
);
2769 /* Are there more items on the event ring? Caller will call us again to
2776 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2777 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2778 * indicators of an event TRB error, but we check the status *first* to be safe.
2780 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
2782 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
2785 union xhci_trb
*event_ring_deq
;
2788 spin_lock(&xhci
->lock
);
2789 /* Check if the xHC generated the interrupt, or the irq is shared */
2790 status
= xhci_readl(xhci
, &xhci
->op_regs
->status
);
2791 if (status
== 0xffffffff)
2794 if (!(status
& STS_EINT
)) {
2795 spin_unlock(&xhci
->lock
);
2798 if (status
& STS_FATAL
) {
2799 xhci_warn(xhci
, "WARNING: Host System Error\n");
2802 spin_unlock(&xhci
->lock
);
2807 * Clear the op reg interrupt status first,
2808 * so we can receive interrupts from other MSI-X interrupters.
2809 * Write 1 to clear the interrupt status.
2812 xhci_writel(xhci
, status
, &xhci
->op_regs
->status
);
2813 /* FIXME when MSI-X is supported and there are multiple vectors */
2814 /* Clear the MSI-X event interrupt status */
2818 /* Acknowledge the PCI interrupt */
2819 irq_pending
= xhci_readl(xhci
, &xhci
->ir_set
->irq_pending
);
2820 irq_pending
|= IMAN_IP
;
2821 xhci_writel(xhci
, irq_pending
, &xhci
->ir_set
->irq_pending
);
2824 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2825 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. "
2826 "Shouldn't IRQs be disabled?\n");
2827 /* Clear the event handler busy flag (RW1C);
2828 * the event ring should be empty.
2830 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2831 xhci_write_64(xhci
, temp_64
| ERST_EHB
,
2832 &xhci
->ir_set
->erst_dequeue
);
2833 spin_unlock(&xhci
->lock
);
2838 event_ring_deq
= xhci
->event_ring
->dequeue
;
2839 /* FIXME this should be a delayed service routine
2840 * that clears the EHB.
2842 while (xhci_handle_event(xhci
) > 0) {}
2844 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2845 /* If necessary, update the HW's version of the event ring deq ptr. */
2846 if (event_ring_deq
!= xhci
->event_ring
->dequeue
) {
2847 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2848 xhci
->event_ring
->dequeue
);
2850 xhci_warn(xhci
, "WARN something wrong with SW event "
2851 "ring dequeue ptr.\n");
2852 /* Update HC event ring dequeue pointer */
2853 temp_64
&= ERST_PTR_MASK
;
2854 temp_64
|= ((u64
) deq
& (u64
) ~ERST_PTR_MASK
);
2857 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2858 temp_64
|= ERST_EHB
;
2859 xhci_write_64(xhci
, temp_64
, &xhci
->ir_set
->erst_dequeue
);
2861 spin_unlock(&xhci
->lock
);
2866 irqreturn_t
xhci_msi_irq(int irq
, void *hcd
)
2868 return xhci_irq(hcd
);
2871 /**** Endpoint Ring Operations ****/
2874 * Generic function for queueing a TRB on a ring.
2875 * The caller must have checked to make sure there's room on the ring.
2877 * @more_trbs_coming: Will you enqueue more TRBs before calling
2878 * prepare_transfer()?
2880 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2881 bool more_trbs_coming
,
2882 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
2884 struct xhci_generic_trb
*trb
;
2886 trb
= &ring
->enqueue
->generic
;
2887 trb
->field
[0] = cpu_to_le32(field1
);
2888 trb
->field
[1] = cpu_to_le32(field2
);
2889 trb
->field
[2] = cpu_to_le32(field3
);
2890 trb
->field
[3] = cpu_to_le32(field4
);
2891 inc_enq(xhci
, ring
, more_trbs_coming
);
2895 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2896 * FIXME allocate segments if the ring is full.
2898 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
2899 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
2901 unsigned int num_trbs_needed
;
2903 /* Make sure the endpoint has been added to xHC schedule */
2905 case EP_STATE_DISABLED
:
2907 * USB core changed config/interfaces without notifying us,
2908 * or hardware is reporting the wrong state.
2910 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
2912 case EP_STATE_ERROR
:
2913 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
2914 /* FIXME event handling code for error needs to clear it */
2915 /* XXX not sure if this should be -ENOENT or not */
2917 case EP_STATE_HALTED
:
2918 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
2919 case EP_STATE_STOPPED
:
2920 case EP_STATE_RUNNING
:
2923 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
2925 * FIXME issue Configure Endpoint command to try to get the HC
2926 * back into a known state.
2932 if (room_on_ring(xhci
, ep_ring
, num_trbs
))
2935 if (ep_ring
== xhci
->cmd_ring
) {
2936 xhci_err(xhci
, "Do not support expand command ring\n");
2940 xhci_dbg_trace(xhci
, trace_xhci_dbg_ring_expansion
,
2941 "ERROR no room on ep ring, try ring expansion");
2942 num_trbs_needed
= num_trbs
- ep_ring
->num_trbs_free
;
2943 if (xhci_ring_expansion(xhci
, ep_ring
, num_trbs_needed
,
2945 xhci_err(xhci
, "Ring expansion failed\n");
2950 if (enqueue_is_link_trb(ep_ring
)) {
2951 struct xhci_ring
*ring
= ep_ring
;
2952 union xhci_trb
*next
;
2954 next
= ring
->enqueue
;
2956 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
2957 /* If we're not dealing with 0.95 hardware or isoc rings
2958 * on AMD 0.96 host, clear the chain bit.
2960 if (!xhci_link_trb_quirk(xhci
) &&
2961 !(ring
->type
== TYPE_ISOC
&&
2962 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
2963 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
2965 next
->link
.control
|= cpu_to_le32(TRB_CHAIN
);
2968 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
2970 /* Toggle the cycle bit after the last ring segment. */
2971 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
2972 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
2974 ring
->enq_seg
= ring
->enq_seg
->next
;
2975 ring
->enqueue
= ring
->enq_seg
->trbs
;
2976 next
= ring
->enqueue
;
2983 static int prepare_transfer(struct xhci_hcd
*xhci
,
2984 struct xhci_virt_device
*xdev
,
2985 unsigned int ep_index
,
2986 unsigned int stream_id
,
2987 unsigned int num_trbs
,
2989 unsigned int td_index
,
2993 struct urb_priv
*urb_priv
;
2995 struct xhci_ring
*ep_ring
;
2996 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2998 ep_ring
= xhci_stream_id_to_ring(xdev
, ep_index
, stream_id
);
3000 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
3005 ret
= prepare_ring(xhci
, ep_ring
,
3006 le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
3007 num_trbs
, mem_flags
);
3011 urb_priv
= urb
->hcpriv
;
3012 td
= urb_priv
->td
[td_index
];
3014 INIT_LIST_HEAD(&td
->td_list
);
3015 INIT_LIST_HEAD(&td
->cancelled_td_list
);
3017 if (td_index
== 0) {
3018 ret
= usb_hcd_link_urb_to_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
3024 /* Add this TD to the tail of the endpoint ring's TD list */
3025 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
3026 td
->start_seg
= ep_ring
->enq_seg
;
3027 td
->first_trb
= ep_ring
->enqueue
;
3029 urb_priv
->td
[td_index
] = td
;
3034 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
3036 int num_sgs
, num_trbs
, running_total
, temp
, i
;
3037 struct scatterlist
*sg
;
3040 num_sgs
= urb
->num_mapped_sgs
;
3041 temp
= urb
->transfer_buffer_length
;
3044 for_each_sg(urb
->sg
, sg
, num_sgs
, i
) {
3045 unsigned int len
= sg_dma_len(sg
);
3047 /* Scatter gather list entries may cross 64KB boundaries */
3048 running_total
= TRB_MAX_BUFF_SIZE
-
3049 (sg_dma_address(sg
) & (TRB_MAX_BUFF_SIZE
- 1));
3050 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
3051 if (running_total
!= 0)
3054 /* How many more 64KB chunks to transfer, how many more TRBs? */
3055 while (running_total
< sg_dma_len(sg
) && running_total
< temp
) {
3057 running_total
+= TRB_MAX_BUFF_SIZE
;
3059 len
= min_t(int, len
, temp
);
3067 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
3070 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
3071 "TRBs, %d left\n", __func__
,
3072 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
3073 if (running_total
!= urb
->transfer_buffer_length
)
3074 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
3075 "queued %#x (%d), asked for %#x (%d)\n",
3077 urb
->ep
->desc
.bEndpointAddress
,
3078 running_total
, running_total
,
3079 urb
->transfer_buffer_length
,
3080 urb
->transfer_buffer_length
);
3083 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
3084 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
3085 struct xhci_generic_trb
*start_trb
)
3088 * Pass all the TRBs to the hardware at once and make sure this write
3093 start_trb
->field
[3] |= cpu_to_le32(start_cycle
);
3095 start_trb
->field
[3] &= cpu_to_le32(~TRB_CYCLE
);
3096 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
3100 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3101 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3102 * (comprised of sg list entries) can take several service intervals to
3105 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3106 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3108 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
3109 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
3113 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3114 ep_interval
= urb
->interval
;
3115 /* Convert to microframes */
3116 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3117 urb
->dev
->speed
== USB_SPEED_FULL
)
3119 /* FIXME change this to a warning and a suggestion to use the new API
3120 * to set the polling interval (once the API is added).
3122 if (xhci_interval
!= ep_interval
) {
3123 dev_dbg_ratelimited(&urb
->dev
->dev
,
3124 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3125 ep_interval
, ep_interval
== 1 ? "" : "s",
3126 xhci_interval
, xhci_interval
== 1 ? "" : "s");
3127 urb
->interval
= xhci_interval
;
3128 /* Convert back to frames for LS/FS devices */
3129 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3130 urb
->dev
->speed
== USB_SPEED_FULL
)
3133 return xhci_queue_bulk_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3137 * The TD size is the number of bytes remaining in the TD (including this TRB),
3138 * right shifted by 10.
3139 * It must fit in bits 21:17, so it can't be bigger than 31.
3141 static u32
xhci_td_remainder(unsigned int remainder
)
3143 u32 max
= (1 << (21 - 17 + 1)) - 1;
3145 if ((remainder
>> 10) >= max
)
3148 return (remainder
>> 10) << 17;
3152 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3153 * packets remaining in the TD (*not* including this TRB).
3155 * Total TD packet count = total_packet_count =
3156 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3158 * Packets transferred up to and including this TRB = packets_transferred =
3159 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3161 * TD size = total_packet_count - packets_transferred
3163 * It must fit in bits 21:17, so it can't be bigger than 31.
3164 * The last TRB in a TD must have the TD size set to zero.
3166 static u32
xhci_v1_0_td_remainder(int running_total
, int trb_buff_len
,
3167 unsigned int total_packet_count
, struct urb
*urb
,
3168 unsigned int num_trbs_left
)
3170 int packets_transferred
;
3172 /* One TRB with a zero-length data packet. */
3173 if (num_trbs_left
== 0 || (running_total
== 0 && trb_buff_len
== 0))
3176 /* All the TRB queueing functions don't count the current TRB in
3179 packets_transferred
= (running_total
+ trb_buff_len
) /
3180 GET_MAX_PACKET(usb_endpoint_maxp(&urb
->ep
->desc
));
3182 if ((total_packet_count
- packets_transferred
) > 31)
3184 return (total_packet_count
- packets_transferred
) << 17;
3187 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3188 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3190 struct xhci_ring
*ep_ring
;
3191 unsigned int num_trbs
;
3192 struct urb_priv
*urb_priv
;
3194 struct scatterlist
*sg
;
3196 int trb_buff_len
, this_sg_len
, running_total
;
3197 unsigned int total_packet_count
;
3200 bool more_trbs_coming
;
3202 struct xhci_generic_trb
*start_trb
;
3205 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3209 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
3210 num_sgs
= urb
->num_mapped_sgs
;
3211 total_packet_count
= DIV_ROUND_UP(urb
->transfer_buffer_length
,
3212 usb_endpoint_maxp(&urb
->ep
->desc
));
3214 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3215 ep_index
, urb
->stream_id
,
3216 num_trbs
, urb
, 0, mem_flags
);
3217 if (trb_buff_len
< 0)
3218 return trb_buff_len
;
3220 urb_priv
= urb
->hcpriv
;
3221 td
= urb_priv
->td
[0];
3224 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3225 * until we've finished creating all the other TRBs. The ring's cycle
3226 * state may change as we enqueue the other TRBs, so save it too.
3228 start_trb
= &ep_ring
->enqueue
->generic
;
3229 start_cycle
= ep_ring
->cycle_state
;
3233 * How much data is in the first TRB?
3235 * There are three forces at work for TRB buffer pointers and lengths:
3236 * 1. We don't want to walk off the end of this sg-list entry buffer.
3237 * 2. The transfer length that the driver requested may be smaller than
3238 * the amount of memory allocated for this scatter-gather list.
3239 * 3. TRBs buffers can't cross 64KB boundaries.
3242 addr
= (u64
) sg_dma_address(sg
);
3243 this_sg_len
= sg_dma_len(sg
);
3244 trb_buff_len
= TRB_MAX_BUFF_SIZE
- (addr
& (TRB_MAX_BUFF_SIZE
- 1));
3245 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
3246 if (trb_buff_len
> urb
->transfer_buffer_length
)
3247 trb_buff_len
= urb
->transfer_buffer_length
;
3250 /* Queue the first TRB, even if it's zero-length */
3253 u32 length_field
= 0;
3256 /* Don't change the cycle bit of the first TRB until later */
3259 if (start_cycle
== 0)
3262 field
|= ep_ring
->cycle_state
;
3264 /* Chain all the TRBs together; clear the chain bit in the last
3265 * TRB to indicate it's the last TRB in the chain.
3270 /* FIXME - add check for ZERO_PACKET flag before this */
3271 td
->last_trb
= ep_ring
->enqueue
;
3275 /* Only set interrupt on short packet for IN endpoints */
3276 if (usb_urb_dir_in(urb
))
3279 if (TRB_MAX_BUFF_SIZE
-
3280 (addr
& (TRB_MAX_BUFF_SIZE
- 1)) < trb_buff_len
) {
3281 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3282 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
3283 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
3284 (unsigned int) addr
+ trb_buff_len
);
3287 /* Set the TRB length, TD size, and interrupter fields. */
3288 if (xhci
->hci_version
< 0x100) {
3289 remainder
= xhci_td_remainder(
3290 urb
->transfer_buffer_length
-
3293 remainder
= xhci_v1_0_td_remainder(running_total
,
3294 trb_buff_len
, total_packet_count
, urb
,
3297 length_field
= TRB_LEN(trb_buff_len
) |
3302 more_trbs_coming
= true;
3304 more_trbs_coming
= false;
3305 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3306 lower_32_bits(addr
),
3307 upper_32_bits(addr
),
3309 field
| TRB_TYPE(TRB_NORMAL
));
3311 running_total
+= trb_buff_len
;
3313 /* Calculate length for next transfer --
3314 * Are we done queueing all the TRBs for this sg entry?
3316 this_sg_len
-= trb_buff_len
;
3317 if (this_sg_len
== 0) {
3322 addr
= (u64
) sg_dma_address(sg
);
3323 this_sg_len
= sg_dma_len(sg
);
3325 addr
+= trb_buff_len
;
3328 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3329 (addr
& (TRB_MAX_BUFF_SIZE
- 1));
3330 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
3331 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
3333 urb
->transfer_buffer_length
- running_total
;
3334 } while (running_total
< urb
->transfer_buffer_length
);
3336 check_trb_math(urb
, num_trbs
, running_total
);
3337 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3338 start_cycle
, start_trb
);
3342 /* This is very similar to what ehci-q.c qtd_fill() does */
3343 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3344 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3346 struct xhci_ring
*ep_ring
;
3347 struct urb_priv
*urb_priv
;
3350 struct xhci_generic_trb
*start_trb
;
3352 bool more_trbs_coming
;
3354 u32 field
, length_field
;
3356 int running_total
, trb_buff_len
, ret
;
3357 unsigned int total_packet_count
;
3361 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3363 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3368 /* How much data is (potentially) left before the 64KB boundary? */
3369 running_total
= TRB_MAX_BUFF_SIZE
-
3370 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
3371 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
3373 /* If there's some data on this 64KB chunk, or we have to send a
3374 * zero-length transfer, we need at least one TRB
3376 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
3378 /* How many more 64KB chunks to transfer, how many more TRBs? */
3379 while (running_total
< urb
->transfer_buffer_length
) {
3381 running_total
+= TRB_MAX_BUFF_SIZE
;
3383 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3385 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3386 ep_index
, urb
->stream_id
,
3387 num_trbs
, urb
, 0, mem_flags
);
3391 urb_priv
= urb
->hcpriv
;
3392 td
= urb_priv
->td
[0];
3395 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3396 * until we've finished creating all the other TRBs. The ring's cycle
3397 * state may change as we enqueue the other TRBs, so save it too.
3399 start_trb
= &ep_ring
->enqueue
->generic
;
3400 start_cycle
= ep_ring
->cycle_state
;
3403 total_packet_count
= DIV_ROUND_UP(urb
->transfer_buffer_length
,
3404 usb_endpoint_maxp(&urb
->ep
->desc
));
3405 /* How much data is in the first TRB? */
3406 addr
= (u64
) urb
->transfer_dma
;
3407 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3408 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
3409 if (trb_buff_len
> urb
->transfer_buffer_length
)
3410 trb_buff_len
= urb
->transfer_buffer_length
;
3414 /* Queue the first TRB, even if it's zero-length */
3419 /* Don't change the cycle bit of the first TRB until later */
3422 if (start_cycle
== 0)
3425 field
|= ep_ring
->cycle_state
;
3427 /* Chain all the TRBs together; clear the chain bit in the last
3428 * TRB to indicate it's the last TRB in the chain.
3433 /* FIXME - add check for ZERO_PACKET flag before this */
3434 td
->last_trb
= ep_ring
->enqueue
;
3438 /* Only set interrupt on short packet for IN endpoints */
3439 if (usb_urb_dir_in(urb
))
3442 /* Set the TRB length, TD size, and interrupter fields. */
3443 if (xhci
->hci_version
< 0x100) {
3444 remainder
= xhci_td_remainder(
3445 urb
->transfer_buffer_length
-
3448 remainder
= xhci_v1_0_td_remainder(running_total
,
3449 trb_buff_len
, total_packet_count
, urb
,
3452 length_field
= TRB_LEN(trb_buff_len
) |
3457 more_trbs_coming
= true;
3459 more_trbs_coming
= false;
3460 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3461 lower_32_bits(addr
),
3462 upper_32_bits(addr
),
3464 field
| TRB_TYPE(TRB_NORMAL
));
3466 running_total
+= trb_buff_len
;
3468 /* Calculate length for next transfer */
3469 addr
+= trb_buff_len
;
3470 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
3471 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
3472 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
3473 } while (running_total
< urb
->transfer_buffer_length
);
3475 check_trb_math(urb
, num_trbs
, running_total
);
3476 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3477 start_cycle
, start_trb
);
3481 /* Caller must have locked xhci->lock */
3482 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3483 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3485 struct xhci_ring
*ep_ring
;
3488 struct usb_ctrlrequest
*setup
;
3489 struct xhci_generic_trb
*start_trb
;
3491 u32 field
, length_field
;
3492 struct urb_priv
*urb_priv
;
3495 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3500 * Need to copy setup packet into setup TRB, so we can't use the setup
3503 if (!urb
->setup_packet
)
3506 /* 1 TRB for setup, 1 for status */
3509 * Don't need to check if we need additional event data and normal TRBs,
3510 * since data in control transfers will never get bigger than 16MB
3511 * XXX: can we get a buffer that crosses 64KB boundaries?
3513 if (urb
->transfer_buffer_length
> 0)
3515 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3516 ep_index
, urb
->stream_id
,
3517 num_trbs
, urb
, 0, mem_flags
);
3521 urb_priv
= urb
->hcpriv
;
3522 td
= urb_priv
->td
[0];
3525 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3526 * until we've finished creating all the other TRBs. The ring's cycle
3527 * state may change as we enqueue the other TRBs, so save it too.
3529 start_trb
= &ep_ring
->enqueue
->generic
;
3530 start_cycle
= ep_ring
->cycle_state
;
3532 /* Queue setup TRB - see section 6.4.1.2.1 */
3533 /* FIXME better way to translate setup_packet into two u32 fields? */
3534 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
3536 field
|= TRB_IDT
| TRB_TYPE(TRB_SETUP
);
3537 if (start_cycle
== 0)
3540 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3541 if (xhci
->hci_version
== 0x100) {
3542 if (urb
->transfer_buffer_length
> 0) {
3543 if (setup
->bRequestType
& USB_DIR_IN
)
3544 field
|= TRB_TX_TYPE(TRB_DATA_IN
);
3546 field
|= TRB_TX_TYPE(TRB_DATA_OUT
);
3550 queue_trb(xhci
, ep_ring
, true,
3551 setup
->bRequestType
| setup
->bRequest
<< 8 | le16_to_cpu(setup
->wValue
) << 16,
3552 le16_to_cpu(setup
->wIndex
) | le16_to_cpu(setup
->wLength
) << 16,
3553 TRB_LEN(8) | TRB_INTR_TARGET(0),
3554 /* Immediate data in pointer */
3557 /* If there's data, queue data TRBs */
3558 /* Only set interrupt on short packet for IN endpoints */
3559 if (usb_urb_dir_in(urb
))
3560 field
= TRB_ISP
| TRB_TYPE(TRB_DATA
);
3562 field
= TRB_TYPE(TRB_DATA
);
3564 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
3565 xhci_td_remainder(urb
->transfer_buffer_length
) |
3567 if (urb
->transfer_buffer_length
> 0) {
3568 if (setup
->bRequestType
& USB_DIR_IN
)
3569 field
|= TRB_DIR_IN
;
3570 queue_trb(xhci
, ep_ring
, true,
3571 lower_32_bits(urb
->transfer_dma
),
3572 upper_32_bits(urb
->transfer_dma
),
3574 field
| ep_ring
->cycle_state
);
3577 /* Save the DMA address of the last TRB in the TD */
3578 td
->last_trb
= ep_ring
->enqueue
;
3580 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3581 /* If the device sent data, the status stage is an OUT transfer */
3582 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
3586 queue_trb(xhci
, ep_ring
, false,
3590 /* Event on completion */
3591 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
3593 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
3594 start_cycle
, start_trb
);
3598 static int count_isoc_trbs_needed(struct xhci_hcd
*xhci
,
3599 struct urb
*urb
, int i
)
3604 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
3605 td_len
= urb
->iso_frame_desc
[i
].length
;
3607 num_trbs
= DIV_ROUND_UP(td_len
+ (addr
& (TRB_MAX_BUFF_SIZE
- 1)),
3616 * The transfer burst count field of the isochronous TRB defines the number of
3617 * bursts that are required to move all packets in this TD. Only SuperSpeed
3618 * devices can burst up to bMaxBurst number of packets per service interval.
3619 * This field is zero based, meaning a value of zero in the field means one
3620 * burst. Basically, for everything but SuperSpeed devices, this field will be
3621 * zero. Only xHCI 1.0 host controllers support this field.
3623 static unsigned int xhci_get_burst_count(struct xhci_hcd
*xhci
,
3624 struct usb_device
*udev
,
3625 struct urb
*urb
, unsigned int total_packet_count
)
3627 unsigned int max_burst
;
3629 if (xhci
->hci_version
< 0x100 || udev
->speed
!= USB_SPEED_SUPER
)
3632 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3633 return roundup(total_packet_count
, max_burst
+ 1) - 1;
3637 * Returns the number of packets in the last "burst" of packets. This field is
3638 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3639 * the last burst packet count is equal to the total number of packets in the
3640 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3641 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3642 * contain 1 to (bMaxBurst + 1) packets.
3644 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd
*xhci
,
3645 struct usb_device
*udev
,
3646 struct urb
*urb
, unsigned int total_packet_count
)
3648 unsigned int max_burst
;
3649 unsigned int residue
;
3651 if (xhci
->hci_version
< 0x100)
3654 switch (udev
->speed
) {
3655 case USB_SPEED_SUPER
:
3656 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3657 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3658 residue
= total_packet_count
% (max_burst
+ 1);
3659 /* If residue is zero, the last burst contains (max_burst + 1)
3660 * number of packets, but the TLBPC field is zero-based.
3666 if (total_packet_count
== 0)
3668 return total_packet_count
- 1;
3672 /* This is for isoc transfer */
3673 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3674 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3676 struct xhci_ring
*ep_ring
;
3677 struct urb_priv
*urb_priv
;
3679 int num_tds
, trbs_per_td
;
3680 struct xhci_generic_trb
*start_trb
;
3683 u32 field
, length_field
;
3684 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
3685 u64 start_addr
, addr
;
3687 bool more_trbs_coming
;
3689 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
3691 num_tds
= urb
->number_of_packets
;
3693 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
3697 start_addr
= (u64
) urb
->transfer_dma
;
3698 start_trb
= &ep_ring
->enqueue
->generic
;
3699 start_cycle
= ep_ring
->cycle_state
;
3701 urb_priv
= urb
->hcpriv
;
3702 /* Queue the first TRB, even if it's zero-length */
3703 for (i
= 0; i
< num_tds
; i
++) {
3704 unsigned int total_packet_count
;
3705 unsigned int burst_count
;
3706 unsigned int residue
;
3710 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
3711 td_len
= urb
->iso_frame_desc
[i
].length
;
3712 td_remain_len
= td_len
;
3713 total_packet_count
= DIV_ROUND_UP(td_len
,
3715 usb_endpoint_maxp(&urb
->ep
->desc
)));
3716 /* A zero-length transfer still involves at least one packet. */
3717 if (total_packet_count
== 0)
3718 total_packet_count
++;
3719 burst_count
= xhci_get_burst_count(xhci
, urb
->dev
, urb
,
3720 total_packet_count
);
3721 residue
= xhci_get_last_burst_packet_count(xhci
,
3722 urb
->dev
, urb
, total_packet_count
);
3724 trbs_per_td
= count_isoc_trbs_needed(xhci
, urb
, i
);
3726 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
3727 urb
->stream_id
, trbs_per_td
, urb
, i
, mem_flags
);
3734 td
= urb_priv
->td
[i
];
3735 for (j
= 0; j
< trbs_per_td
; j
++) {
3740 field
= TRB_TBC(burst_count
) |
3742 /* Queue the isoc TRB */
3743 field
|= TRB_TYPE(TRB_ISOC
);
3744 /* Assume URB_ISO_ASAP is set */
3747 if (start_cycle
== 0)
3750 field
|= ep_ring
->cycle_state
;
3753 /* Queue other normal TRBs */
3754 field
|= TRB_TYPE(TRB_NORMAL
);
3755 field
|= ep_ring
->cycle_state
;
3758 /* Only set interrupt on short packet for IN EPs */
3759 if (usb_urb_dir_in(urb
))
3762 /* Chain all the TRBs together; clear the chain bit in
3763 * the last TRB to indicate it's the last TRB in the
3766 if (j
< trbs_per_td
- 1) {
3768 more_trbs_coming
= true;
3770 td
->last_trb
= ep_ring
->enqueue
;
3772 if (xhci
->hci_version
== 0x100 &&
3775 /* Set BEI bit except for the last td */
3776 if (i
< num_tds
- 1)
3779 more_trbs_coming
= false;
3782 /* Calculate TRB length */
3783 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3784 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
3785 if (trb_buff_len
> td_remain_len
)
3786 trb_buff_len
= td_remain_len
;
3788 /* Set the TRB length, TD size, & interrupter fields. */
3789 if (xhci
->hci_version
< 0x100) {
3790 remainder
= xhci_td_remainder(
3791 td_len
- running_total
);
3793 remainder
= xhci_v1_0_td_remainder(
3794 running_total
, trb_buff_len
,
3795 total_packet_count
, urb
,
3796 (trbs_per_td
- j
- 1));
3798 length_field
= TRB_LEN(trb_buff_len
) |
3802 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3803 lower_32_bits(addr
),
3804 upper_32_bits(addr
),
3807 running_total
+= trb_buff_len
;
3809 addr
+= trb_buff_len
;
3810 td_remain_len
-= trb_buff_len
;
3813 /* Check TD length */
3814 if (running_total
!= td_len
) {
3815 xhci_err(xhci
, "ISOC TD length unmatch\n");
3821 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
3822 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
3823 usb_amd_quirk_pll_disable();
3825 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
++;
3827 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3828 start_cycle
, start_trb
);
3831 /* Clean up a partially enqueued isoc transfer. */
3833 for (i
--; i
>= 0; i
--)
3834 list_del_init(&urb_priv
->td
[i
]->td_list
);
3836 /* Use the first TD as a temporary variable to turn the TDs we've queued
3837 * into No-ops with a software-owned cycle bit. That way the hardware
3838 * won't accidentally start executing bogus TDs when we partially
3839 * overwrite them. td->first_trb and td->start_seg are already set.
3841 urb_priv
->td
[0]->last_trb
= ep_ring
->enqueue
;
3842 /* Every TRB except the first & last will have its cycle bit flipped. */
3843 td_to_noop(xhci
, ep_ring
, urb_priv
->td
[0], true);
3845 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3846 ep_ring
->enqueue
= urb_priv
->td
[0]->first_trb
;
3847 ep_ring
->enq_seg
= urb_priv
->td
[0]->start_seg
;
3848 ep_ring
->cycle_state
= start_cycle
;
3849 ep_ring
->num_trbs_free
= ep_ring
->num_trbs_free_temp
;
3850 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
3855 * Check transfer ring to guarantee there is enough room for the urb.
3856 * Update ISO URB start_frame and interval.
3857 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3858 * update the urb->start_frame by now.
3859 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3861 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3862 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3864 struct xhci_virt_device
*xdev
;
3865 struct xhci_ring
*ep_ring
;
3866 struct xhci_ep_ctx
*ep_ctx
;
3870 int num_tds
, num_trbs
, i
;
3873 xdev
= xhci
->devs
[slot_id
];
3874 ep_ring
= xdev
->eps
[ep_index
].ring
;
3875 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
3878 num_tds
= urb
->number_of_packets
;
3879 for (i
= 0; i
< num_tds
; i
++)
3880 num_trbs
+= count_isoc_trbs_needed(xhci
, urb
, i
);
3882 /* Check the ring to guarantee there is enough room for the whole urb.
3883 * Do not insert any td of the urb to the ring if the check failed.
3885 ret
= prepare_ring(xhci
, ep_ring
, le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
3886 num_trbs
, mem_flags
);
3890 start_frame
= xhci_readl(xhci
, &xhci
->run_regs
->microframe_index
);
3891 start_frame
&= 0x3fff;
3893 urb
->start_frame
= start_frame
;
3894 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3895 urb
->dev
->speed
== USB_SPEED_FULL
)
3896 urb
->start_frame
>>= 3;
3898 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3899 ep_interval
= urb
->interval
;
3900 /* Convert to microframes */
3901 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3902 urb
->dev
->speed
== USB_SPEED_FULL
)
3904 /* FIXME change this to a warning and a suggestion to use the new API
3905 * to set the polling interval (once the API is added).
3907 if (xhci_interval
!= ep_interval
) {
3908 dev_dbg_ratelimited(&urb
->dev
->dev
,
3909 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3910 ep_interval
, ep_interval
== 1 ? "" : "s",
3911 xhci_interval
, xhci_interval
== 1 ? "" : "s");
3912 urb
->interval
= xhci_interval
;
3913 /* Convert back to frames for LS/FS devices */
3914 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3915 urb
->dev
->speed
== USB_SPEED_FULL
)
3918 ep_ring
->num_trbs_free_temp
= ep_ring
->num_trbs_free
;
3920 return xhci_queue_isoc_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3923 /**** Command Ring Operations ****/
3925 /* Generic function for queueing a command TRB on the command ring.
3926 * Check to make sure there's room on the command ring for one command TRB.
3927 * Also check that there's room reserved for commands that must not fail.
3928 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3929 * then only check for the number of reserved spots.
3930 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3931 * because the command event handler may want to resubmit a failed command.
3933 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
3934 u32 field3
, u32 field4
, bool command_must_succeed
)
3936 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
3939 if (!command_must_succeed
)
3942 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
3943 reserved_trbs
, GFP_ATOMIC
);
3945 xhci_err(xhci
, "ERR: No room for command on command ring\n");
3946 if (command_must_succeed
)
3947 xhci_err(xhci
, "ERR: Reserved TRB counting for "
3948 "unfailable commands failed.\n");
3951 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
3952 field4
| xhci
->cmd_ring
->cycle_state
);
3956 /* Queue a slot enable or disable request on the command ring */
3957 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
3959 return queue_command(xhci
, 0, 0, 0,
3960 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
3963 /* Queue an address device command TRB */
3964 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3967 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3968 upper_32_bits(in_ctx_ptr
), 0,
3969 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3973 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
,
3974 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
3976 return queue_command(xhci
, field1
, field2
, field3
, field4
, false);
3979 /* Queue a reset device command TRB */
3980 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, u32 slot_id
)
3982 return queue_command(xhci
, 0, 0, 0,
3983 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3987 /* Queue a configure endpoint command TRB */
3988 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3989 u32 slot_id
, bool command_must_succeed
)
3991 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3992 upper_32_bits(in_ctx_ptr
), 0,
3993 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
3994 command_must_succeed
);
3997 /* Queue an evaluate context command TRB */
3998 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3999 u32 slot_id
, bool command_must_succeed
)
4001 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
4002 upper_32_bits(in_ctx_ptr
), 0,
4003 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
4004 command_must_succeed
);
4008 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4009 * activity on an endpoint that is about to be suspended.
4011 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
4012 unsigned int ep_index
, int suspend
)
4014 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4015 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4016 u32 type
= TRB_TYPE(TRB_STOP_RING
);
4017 u32 trb_suspend
= SUSPEND_PORT_FOR_TRB(suspend
);
4019 return queue_command(xhci
, 0, 0, 0,
4020 trb_slot_id
| trb_ep_index
| type
| trb_suspend
, false);
4023 /* Set Transfer Ring Dequeue Pointer command.
4024 * This should not be used for endpoints that have streams enabled.
4026 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
4027 unsigned int ep_index
, unsigned int stream_id
,
4028 struct xhci_segment
*deq_seg
,
4029 union xhci_trb
*deq_ptr
, u32 cycle_state
)
4032 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4033 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4034 u32 trb_stream_id
= STREAM_ID_FOR_TRB(stream_id
);
4035 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
4036 struct xhci_virt_ep
*ep
;
4038 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
4040 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
4041 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
4045 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
4046 if ((ep
->ep_state
& SET_DEQ_PENDING
)) {
4047 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
4048 xhci_warn(xhci
, "A Set TR Deq Ptr command is pending.\n");
4051 ep
->queued_deq_seg
= deq_seg
;
4052 ep
->queued_deq_ptr
= deq_ptr
;
4053 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
4054 upper_32_bits(addr
), trb_stream_id
,
4055 trb_slot_id
| trb_ep_index
| type
, false);
4058 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
4059 unsigned int ep_index
)
4061 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4062 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4063 u32 type
= TRB_TYPE(TRB_RESET_EP
);
4065 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,