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hwmon: (max31722) Add support for MAX31722/MAX31723 temperature sensors
[linux-2.6/btrfs-unstable.git] / drivers / crypto / hifn_795x.c
blobeee2c7e6c29984c2d258b65e9b424eee8a4ddc1b
1 /*
2 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/mm.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/scatterlist.h>
27 #include <linux/highmem.h>
28 #include <linux/crypto.h>
29 #include <linux/hw_random.h>
30 #include <linux/ktime.h>
31
32 #include <crypto/algapi.h>
33 #include <crypto/des.h>
34
35 static char hifn_pll_ref[sizeof("extNNN")] = "ext";
36 module_param_string(hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444);
37 MODULE_PARM_DESC(hifn_pll_ref,
38 "PLL reference clock (pci[freq] or ext[freq], default ext)");
39
40 static atomic_t hifn_dev_number;
41
42 #define ACRYPTO_OP_DECRYPT 0
43 #define ACRYPTO_OP_ENCRYPT 1
44 #define ACRYPTO_OP_HMAC 2
45 #define ACRYPTO_OP_RNG 3
46
47 #define ACRYPTO_MODE_ECB 0
48 #define ACRYPTO_MODE_CBC 1
49 #define ACRYPTO_MODE_CFB 2
50 #define ACRYPTO_MODE_OFB 3
51
52 #define ACRYPTO_TYPE_AES_128 0
53 #define ACRYPTO_TYPE_AES_192 1
54 #define ACRYPTO_TYPE_AES_256 2
55 #define ACRYPTO_TYPE_3DES 3
56 #define ACRYPTO_TYPE_DES 4
57
58 #define PCI_VENDOR_ID_HIFN 0x13A3
59 #define PCI_DEVICE_ID_HIFN_7955 0x0020
60 #define PCI_DEVICE_ID_HIFN_7956 0x001d
61
62 /* I/O region sizes */
63
64 #define HIFN_BAR0_SIZE 0x1000
65 #define HIFN_BAR1_SIZE 0x2000
66 #define HIFN_BAR2_SIZE 0x8000
67
68 /* DMA registres */
69
70 #define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */
71 #define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */
72 #define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */
73 #define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */
74 #define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */
75 #define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */
76 #define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */
77 #define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */
78 #define HIFN_CHIP_ID 0x98 /* Chip ID */
79
80 /*
81 * Processing Unit Registers (offset from BASEREG0)
82 */
83 #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
84 #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
85 #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
86 #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
87 #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
88 #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
89 #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
90 #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
91 #define HIFN_0_SPACESIZE 0x20 /* Register space size */
92
93 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
94 #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
95 #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */
96 #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */
97 #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */
98 #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */
99
100 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
101 #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */
102 #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */
103 #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
104 #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
105 #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */
106 #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */
107 #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */
108 #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */
109 #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */
110 #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */
111
112 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
113 #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */
114 #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */
115 #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */
116 #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
117 #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
118 #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
119 #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
120 #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
121 #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
122 #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */
123 #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */
124 #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */
125 #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */
126 #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */
127 #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */
128 #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */
129 #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */
130 #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */
131 #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */
132 #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */
133 #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */
134 #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */
135 #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */
136
137 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
138 #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */
139 #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */
140 #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
141 #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
142 #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */
143 #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */
144 #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */
145 #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */
146 #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */
147 #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */
148
149 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
150 #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */
151 #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */
152 #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
153 #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
154 #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */
155 #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */
156 #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */
157 #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */
158 #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */
159 #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */
160 #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */
161 #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */
162 #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */
163 #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */
164 #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */
165 #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */
166 #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
167
168 /* FIFO Status Register (HIFN_0_FIFOSTAT) */
169 #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */
170 #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
171
172 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
173 #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */
174
175 /*
176 * DMA Interface Registers (offset from BASEREG1)
177 */
178 #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
179 #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
180 #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */
181 #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
182 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
183 #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
184 #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
185 #define HIFN_1_PLL 0x4c /* 795x: PLL config */
186 #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */
187 #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
188 #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
189 #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */
190 #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
191 #define HIFN_1_REVID 0x98 /* Revision ID */
192 #define HIFN_1_UNLOCK_SECRET1 0xf4
193 #define HIFN_1_UNLOCK_SECRET2 0xfc
194 #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */
195 #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */
196 #define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */
197 #define HIFN_1_PUB_OP 0x308 /* Public Operand */
198 #define HIFN_1_PUB_STATUS 0x30c /* Public Status */
199 #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */
200 #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */
201 #define HIFN_1_RNG_DATA 0x318 /* RNG data */
202 #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */
203 #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */
204
205 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
206 #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
207 #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
208 #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */
209 #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */
210 #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
211 #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
212 #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
213 #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
214 #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
215 #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
216 #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
217 #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */
218 #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */
219 #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
220 #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
221 #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
222 #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
223 #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
224 #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
225 #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
226 #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */
227 #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */
228 #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
229 #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
230 #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
231 #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
232 #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */
233 #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */
234 #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
235 #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
236 #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */
237 #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */
238 #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
239 #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
240 #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
241 #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
242 #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */
243 #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */
244
245 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
246 #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
247 #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
248 #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
249 #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
250 #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
251 #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
252 #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
253 #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
254 #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
255 #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
256 #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
257 #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
258 #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
259 #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
260 #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */
261 #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */
262 #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
263 #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
264 #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
265 #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
266 #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */
267 #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */
268
269 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
270 #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */
271 #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */
272 #define HIFN_DMACNFG_UNLOCK 0x00000800
273 #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */
274 #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */
275 #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */
276 #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
277 #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
278
279 /* PLL configuration register */
280 #define HIFN_PLL_REF_CLK_HBI 0x00000000 /* HBI reference clock */
281 #define HIFN_PLL_REF_CLK_PLL 0x00000001 /* PLL reference clock */
282 #define HIFN_PLL_BP 0x00000002 /* Reference clock bypass */
283 #define HIFN_PLL_PK_CLK_HBI 0x00000000 /* PK engine HBI clock */
284 #define HIFN_PLL_PK_CLK_PLL 0x00000008 /* PK engine PLL clock */
285 #define HIFN_PLL_PE_CLK_HBI 0x00000000 /* PE engine HBI clock */
286 #define HIFN_PLL_PE_CLK_PLL 0x00000010 /* PE engine PLL clock */
287 #define HIFN_PLL_RESERVED_1 0x00000400 /* Reserved bit, must be 1 */
288 #define HIFN_PLL_ND_SHIFT 11 /* Clock multiplier shift */
289 #define HIFN_PLL_ND_MULT_2 0x00000000 /* PLL clock multiplier 2 */
290 #define HIFN_PLL_ND_MULT_4 0x00000800 /* PLL clock multiplier 4 */
291 #define HIFN_PLL_ND_MULT_6 0x00001000 /* PLL clock multiplier 6 */
292 #define HIFN_PLL_ND_MULT_8 0x00001800 /* PLL clock multiplier 8 */
293 #define HIFN_PLL_ND_MULT_10 0x00002000 /* PLL clock multiplier 10 */
294 #define HIFN_PLL_ND_MULT_12 0x00002800 /* PLL clock multiplier 12 */
295 #define HIFN_PLL_IS_1_8 0x00000000 /* charge pump (mult. 1-8) */
296 #define HIFN_PLL_IS_9_12 0x00010000 /* charge pump (mult. 9-12) */
297
298 #define HIFN_PLL_FCK_MAX 266 /* Maximum PLL frequency */
299
300 /* Public key reset register (HIFN_1_PUB_RESET) */
301 #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */
302
303 /* Public base address register (HIFN_1_PUB_BASE) */
304 #define HIFN_PUBBASE_ADDR 0x00003fff /* base address */
305
306 /* Public operand length register (HIFN_1_PUB_OPLEN) */
307 #define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */
308 #define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */
309 #define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */
310 #define HIFN_PUBOPLEN_EXP_S 7 /* exponent length shift */
311 #define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */
312 #define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */
313
314 /* Public operation register (HIFN_1_PUB_OP) */
315 #define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */
316 #define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */
317 #define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */
318 #define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */
319 #define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */
320 #define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */
321 #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */
322 #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */
323 #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */
324 #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */
325 #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */
326 #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */
327 #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */
328 #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */
329 #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */
330 #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */
331 #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */
332 #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */
333 #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */
334 #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */
335
336 /* Public status register (HIFN_1_PUB_STATUS) */
337 #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */
338 #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */
339
340 /* Public interrupt enable register (HIFN_1_PUB_IEN) */
341 #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */
342
343 /* Random number generator config register (HIFN_1_RNG_CONFIG) */
344 #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */
345
346 #define HIFN_NAMESIZE 32
347 #define HIFN_MAX_RESULT_ORDER 5
348
349 #define HIFN_D_CMD_RSIZE (24 * 1)
350 #define HIFN_D_SRC_RSIZE (80 * 1)
351 #define HIFN_D_DST_RSIZE (80 * 1)
352 #define HIFN_D_RES_RSIZE (24 * 1)
353
354 #define HIFN_D_DST_DALIGN 4
355
356 #define HIFN_QUEUE_LENGTH (HIFN_D_CMD_RSIZE - 1)
357
358 #define AES_MIN_KEY_SIZE 16
359 #define AES_MAX_KEY_SIZE 32
360
361 #define HIFN_DES_KEY_LENGTH 8
362 #define HIFN_3DES_KEY_LENGTH 24
363 #define HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE
364 #define HIFN_IV_LENGTH 8
365 #define HIFN_AES_IV_LENGTH 16
366 #define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH
367
368 #define HIFN_MAC_KEY_LENGTH 64
369 #define HIFN_MD5_LENGTH 16
370 #define HIFN_SHA1_LENGTH 20
371 #define HIFN_MAC_TRUNC_LENGTH 12
372
373 #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260)
374 #define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4)
375 #define HIFN_USED_RESULT 12
376
377 struct hifn_desc {
378 volatile __le32 l;
379 volatile __le32 p;
380 };
381
382 struct hifn_dma {
383 struct hifn_desc cmdr[HIFN_D_CMD_RSIZE + 1];
384 struct hifn_desc srcr[HIFN_D_SRC_RSIZE + 1];
385 struct hifn_desc dstr[HIFN_D_DST_RSIZE + 1];
386 struct hifn_desc resr[HIFN_D_RES_RSIZE + 1];
387
388 u8 command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
389 u8 result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
390
391 /*
392 * Our current positions for insertion and removal from the descriptor
393 * rings.
394 */
395 volatile int cmdi, srci, dsti, resi;
396 volatile int cmdu, srcu, dstu, resu;
397 int cmdk, srck, dstk, resk;
398 };
399
400 #define HIFN_FLAG_CMD_BUSY (1 << 0)
401 #define HIFN_FLAG_SRC_BUSY (1 << 1)
402 #define HIFN_FLAG_DST_BUSY (1 << 2)
403 #define HIFN_FLAG_RES_BUSY (1 << 3)
404 #define HIFN_FLAG_OLD_KEY (1 << 4)
405
406 #define HIFN_DEFAULT_ACTIVE_NUM 5
407
408 struct hifn_device {
409 char name[HIFN_NAMESIZE];
410
411 int irq;
412
413 struct pci_dev *pdev;
414 void __iomem *bar[3];
415
416 void *desc_virt;
417 dma_addr_t desc_dma;
418
419 u32 dmareg;
420
421 void *sa[HIFN_D_RES_RSIZE];
422
423 spinlock_t lock;
424
425 u32 flags;
426 int active, started;
427 struct delayed_work work;
428 unsigned long reset;
429 unsigned long success;
430 unsigned long prev_success;
431
432 u8 snum;
433
434 struct tasklet_struct tasklet;
435
436 struct crypto_queue queue;
437 struct list_head alg_list;
438
439 unsigned int pk_clk_freq;
440
441 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
442 unsigned int rng_wait_time;
443 ktime_t rngtime;
444 struct hwrng rng;
445 #endif
446 };
447
448 #define HIFN_D_LENGTH 0x0000ffff
449 #define HIFN_D_NOINVALID 0x01000000
450 #define HIFN_D_MASKDONEIRQ 0x02000000
451 #define HIFN_D_DESTOVER 0x04000000
452 #define HIFN_D_OVER 0x08000000
453 #define HIFN_D_LAST 0x20000000
454 #define HIFN_D_JUMP 0x40000000
455 #define HIFN_D_VALID 0x80000000
456
457 struct hifn_base_command {
458 volatile __le16 masks;
459 volatile __le16 session_num;
460 volatile __le16 total_source_count;
461 volatile __le16 total_dest_count;
462 };
463
464 #define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */
465 #define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */
466 #define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */
467 #define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */
468 #define HIFN_BASE_CMD_DECODE 0x2000
469 #define HIFN_BASE_CMD_SRCLEN_M 0xc000
470 #define HIFN_BASE_CMD_SRCLEN_S 14
471 #define HIFN_BASE_CMD_DSTLEN_M 0x3000
472 #define HIFN_BASE_CMD_DSTLEN_S 12
473 #define HIFN_BASE_CMD_LENMASK_HI 0x30000
474 #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff
475
476 /*
477 * Structure to help build up the command data structure.
478 */
479 struct hifn_crypt_command {
480 volatile __le16 masks;
481 volatile __le16 header_skip;
482 volatile __le16 source_count;
483 volatile __le16 reserved;
484 };
485
486 #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */
487 #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */
488 #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */
489 #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */
490 #define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */
491 #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */
492 #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */
493 #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */
494 #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */
495 #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */
496 #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */
497 #define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */
498 #define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */
499 #define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */
500 #define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */
501 #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */
502 #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */
503 #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000
504 #define HIFN_CRYPT_CMD_SRCLEN_S 14
505
506 /*
507 * Structure to help build up the command data structure.
508 */
509 struct hifn_mac_command {
510 volatile __le16 masks;
511 volatile __le16 header_skip;
512 volatile __le16 source_count;
513 volatile __le16 reserved;
514 };
515
516 #define HIFN_MAC_CMD_ALG_MASK 0x0001
517 #define HIFN_MAC_CMD_ALG_SHA1 0x0000
518 #define HIFN_MAC_CMD_ALG_MD5 0x0001
519 #define HIFN_MAC_CMD_MODE_MASK 0x000c
520 #define HIFN_MAC_CMD_MODE_HMAC 0x0000
521 #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004
522 #define HIFN_MAC_CMD_MODE_HASH 0x0008
523 #define HIFN_MAC_CMD_MODE_FULL 0x0004
524 #define HIFN_MAC_CMD_TRUNC 0x0010
525 #define HIFN_MAC_CMD_RESULT 0x0020
526 #define HIFN_MAC_CMD_APPEND 0x0040
527 #define HIFN_MAC_CMD_SRCLEN_M 0xc000
528 #define HIFN_MAC_CMD_SRCLEN_S 14
529
530 /*
531 * MAC POS IPsec initiates authentication after encryption on encodes
532 * and before decryption on decodes.
533 */
534 #define HIFN_MAC_CMD_POS_IPSEC 0x0200
535 #define HIFN_MAC_CMD_NEW_KEY 0x0800
536
537 struct hifn_comp_command {
538 volatile __le16 masks;
539 volatile __le16 header_skip;
540 volatile __le16 source_count;
541 volatile __le16 reserved;
542 };
543
544 #define HIFN_COMP_CMD_SRCLEN_M 0xc000
545 #define HIFN_COMP_CMD_SRCLEN_S 14
546 #define HIFN_COMP_CMD_ONE 0x0100 /* must be one */
547 #define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */
548 #define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */
549 #define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */
550 #define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */
551 #define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */
552 #define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */
553 #define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */
554
555 struct hifn_base_result {
556 volatile __le16 flags;
557 volatile __le16 session;
558 volatile __le16 src_cnt; /* 15:0 of source count */
559 volatile __le16 dst_cnt; /* 15:0 of dest count */
560 };
561
562 #define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */
563 #define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */
564 #define HIFN_BASE_RES_SRCLEN_S 14
565 #define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */
566 #define HIFN_BASE_RES_DSTLEN_S 12
567
568 struct hifn_comp_result {
569 volatile __le16 flags;
570 volatile __le16 crc;
571 };
572
573 #define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */
574 #define HIFN_COMP_RES_LCB_S 8
575 #define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */
576 #define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */
577 #define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */
578
579 struct hifn_mac_result {
580 volatile __le16 flags;
581 volatile __le16 reserved;
582 /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
583 };
584
585 #define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */
586 #define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */
587
588 struct hifn_crypt_result {
589 volatile __le16 flags;
590 volatile __le16 reserved;
591 };
592
593 #define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */
594
595 #ifndef HIFN_POLL_FREQUENCY
596 #define HIFN_POLL_FREQUENCY 0x1
597 #endif
598
599 #ifndef HIFN_POLL_SCALAR
600 #define HIFN_POLL_SCALAR 0x0
601 #endif
602
603 #define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
604 #define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */
605
606 struct hifn_crypto_alg {
607 struct list_head entry;
608 struct crypto_alg alg;
609 struct hifn_device *dev;
610 };
611
612 #define ASYNC_SCATTERLIST_CACHE 16
613
614 #define ASYNC_FLAGS_MISALIGNED (1 << 0)
615
616 struct hifn_cipher_walk {
617 struct scatterlist cache[ASYNC_SCATTERLIST_CACHE];
618 u32 flags;
619 int num;
620 };
621
622 struct hifn_context {
623 u8 key[HIFN_MAX_CRYPT_KEY_LENGTH];
624 struct hifn_device *dev;
625 unsigned int keysize;
626 };
627
628 struct hifn_request_context {
629 u8 *iv;
630 unsigned int ivsize;
631 u8 op, type, mode, unused;
632 struct hifn_cipher_walk walk;
633 };
634
635 #define crypto_alg_to_hifn(a) container_of(a, struct hifn_crypto_alg, alg)
636
637 static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg)
638 {
639 u32 ret;
640
641 ret = readl(dev->bar[0] + reg);
642
643 return ret;
644 }
645
646 static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg)
647 {
648 u32 ret;
649
650 ret = readl(dev->bar[1] + reg);
651
652 return ret;
653 }
654
655 static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val)
656 {
657 writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg);
658 }
659
660 static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)
661 {
662 writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg);
663 }
664
665 static void hifn_wait_puc(struct hifn_device *dev)
666 {
667 int i;
668 u32 ret;
669
670 for (i = 10000; i > 0; --i) {
671 ret = hifn_read_0(dev, HIFN_0_PUCTRL);
672 if (!(ret & HIFN_PUCTRL_RESET))
673 break;
674
675 udelay(1);
676 }
677
678 if (!i)
679 dev_err(&dev->pdev->dev, "Failed to reset PUC unit.\n");
680 }
681
682 static void hifn_reset_puc(struct hifn_device *dev)
683 {
684 hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
685 hifn_wait_puc(dev);
686 }
687
688 static void hifn_stop_device(struct hifn_device *dev)
689 {
690 hifn_write_1(dev, HIFN_1_DMA_CSR,
691 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
692 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS);
693 hifn_write_0(dev, HIFN_0_PUIER, 0);
694 hifn_write_1(dev, HIFN_1_DMA_IER, 0);
695 }
696
697 static void hifn_reset_dma(struct hifn_device *dev, int full)
698 {
699 hifn_stop_device(dev);
700
701 /*
702 * Setting poll frequency and others to 0.
703 */
704 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
705 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
706 mdelay(1);
707
708 /*
709 * Reset DMA.
710 */
711 if (full) {
712 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
713 mdelay(1);
714 } else {
715 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |
716 HIFN_DMACNFG_MSTRESET);
717 hifn_reset_puc(dev);
718 }
719
720 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
721 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
722
723 hifn_reset_puc(dev);
724 }
725
726 static u32 hifn_next_signature(u32 a, u_int cnt)
727 {
728 int i;
729 u32 v;
730
731 for (i = 0; i < cnt; i++) {
732 /* get the parity */
733 v = a & 0x80080125;
734 v ^= v >> 16;
735 v ^= v >> 8;
736 v ^= v >> 4;
737 v ^= v >> 2;
738 v ^= v >> 1;
739
740 a = (v & 1) ^ (a << 1);
741 }
742
743 return a;
744 }
745
746 static struct pci2id {
747 u_short pci_vendor;
748 u_short pci_prod;
749 char card_id[13];
750 } pci2id[] = {
751 {
752 PCI_VENDOR_ID_HIFN,
753 PCI_DEVICE_ID_HIFN_7955,
754 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
755 0x00, 0x00, 0x00, 0x00, 0x00 }
756 },
757 {
758 PCI_VENDOR_ID_HIFN,
759 PCI_DEVICE_ID_HIFN_7956,
760 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
761 0x00, 0x00, 0x00, 0x00, 0x00 }
762 }
763 };
764
765 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
766 static int hifn_rng_data_present(struct hwrng *rng, int wait)
767 {
768 struct hifn_device *dev = (struct hifn_device *)rng->priv;
769 s64 nsec;
770
771 nsec = ktime_to_ns(ktime_sub(ktime_get(), dev->rngtime));
772 nsec -= dev->rng_wait_time;
773 if (nsec <= 0)
774 return 1;
775 if (!wait)
776 return 0;
777 ndelay(nsec);
778 return 1;
779 }
780
781 static int hifn_rng_data_read(struct hwrng *rng, u32 *data)
782 {
783 struct hifn_device *dev = (struct hifn_device *)rng->priv;
784
785 *data = hifn_read_1(dev, HIFN_1_RNG_DATA);
786 dev->rngtime = ktime_get();
787 return 4;
788 }
789
790 static int hifn_register_rng(struct hifn_device *dev)
791 {
792 /*
793 * We must wait at least 256 Pk_clk cycles between two reads of the rng.
794 */
795 dev->rng_wait_time = DIV_ROUND_UP_ULL(NSEC_PER_SEC,
796 dev->pk_clk_freq) * 256;
797
798 dev->rng.name = dev->name;
799 dev->rng.data_present = hifn_rng_data_present,
800 dev->rng.data_read = hifn_rng_data_read,
801 dev->rng.priv = (unsigned long)dev;
802
803 return hwrng_register(&dev->rng);
804 }
805
806 static void hifn_unregister_rng(struct hifn_device *dev)
807 {
808 hwrng_unregister(&dev->rng);
809 }
810 #else
811 #define hifn_register_rng(dev) 0
812 #define hifn_unregister_rng(dev)
813 #endif
814
815 static int hifn_init_pubrng(struct hifn_device *dev)
816 {
817 int i;
818
819 hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
820 HIFN_PUBRST_RESET);
821
822 for (i = 100; i > 0; --i) {
823 mdelay(1);
824
825 if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0)
826 break;
827 }
828
829 if (!i) {
830 dev_err(&dev->pdev->dev, "Failed to initialise public key engine.\n");
831 } else {
832 hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
833 dev->dmareg |= HIFN_DMAIER_PUBDONE;
834 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
835
836 dev_dbg(&dev->pdev->dev, "Public key engine has been successfully initialised.\n");
837 }
838
839 /* Enable RNG engine. */
840
841 hifn_write_1(dev, HIFN_1_RNG_CONFIG,
842 hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA);
843 dev_dbg(&dev->pdev->dev, "RNG engine has been successfully initialised.\n");
844
845 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
846 /* First value must be discarded */
847 hifn_read_1(dev, HIFN_1_RNG_DATA);
848 dev->rngtime = ktime_get();
849 #endif
850 return 0;
851 }
852
853 static int hifn_enable_crypto(struct hifn_device *dev)
854 {
855 u32 dmacfg, addr;
856 char *offtbl = NULL;
857 int i;
858
859 for (i = 0; i < ARRAY_SIZE(pci2id); i++) {
860 if (pci2id[i].pci_vendor == dev->pdev->vendor &&
861 pci2id[i].pci_prod == dev->pdev->device) {
862 offtbl = pci2id[i].card_id;
863 break;
864 }
865 }
866
867 if (!offtbl) {
868 dev_err(&dev->pdev->dev, "Unknown card!\n");
869 return -ENODEV;
870 }
871
872 dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG);
873
874 hifn_write_1(dev, HIFN_1_DMA_CNFG,
875 HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET |
876 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
877 mdelay(1);
878 addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1);
879 mdelay(1);
880 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
881 mdelay(1);
882
883 for (i = 0; i < 12; ++i) {
884 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
885 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
886
887 mdelay(1);
888 }
889 hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
890
891 dev_dbg(&dev->pdev->dev, "%s %s.\n", dev->name, pci_name(dev->pdev));
892
893 return 0;
894 }
895
896 static void hifn_init_dma(struct hifn_device *dev)
897 {
898 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
899 u32 dptr = dev->desc_dma;
900 int i;
901
902 for (i = 0; i < HIFN_D_CMD_RSIZE; ++i)
903 dma->cmdr[i].p = __cpu_to_le32(dptr +
904 offsetof(struct hifn_dma, command_bufs[i][0]));
905 for (i = 0; i < HIFN_D_RES_RSIZE; ++i)
906 dma->resr[i].p = __cpu_to_le32(dptr +
907 offsetof(struct hifn_dma, result_bufs[i][0]));
908
909 /* Setup LAST descriptors. */
910 dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr +
911 offsetof(struct hifn_dma, cmdr[0]));
912 dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr +
913 offsetof(struct hifn_dma, srcr[0]));
914 dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr +
915 offsetof(struct hifn_dma, dstr[0]));
916 dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr +
917 offsetof(struct hifn_dma, resr[0]));
918
919 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
920 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
921 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
922 }
923
924 /*
925 * Initialize the PLL. We need to know the frequency of the reference clock
926 * to calculate the optimal multiplier. For PCI we assume 66MHz, since that
927 * allows us to operate without the risk of overclocking the chip. If it
928 * actually uses 33MHz, the chip will operate at half the speed, this can be
929 * overridden by specifying the frequency as module parameter (pci33).
930 *
931 * Unfortunately the PCI clock is not very suitable since the HIFN needs a
932 * stable clock and the PCI clock frequency may vary, so the default is the
933 * external clock. There is no way to find out its frequency, we default to
934 * 66MHz since according to Mike Ham of HiFn, almost every board in existence
935 * has an external crystal populated at 66MHz.
936 */
937 static void hifn_init_pll(struct hifn_device *dev)
938 {
939 unsigned int freq, m;
940 u32 pllcfg;
941
942 pllcfg = HIFN_1_PLL | HIFN_PLL_RESERVED_1;
943
944 if (strncmp(hifn_pll_ref, "ext", 3) == 0)
945 pllcfg |= HIFN_PLL_REF_CLK_PLL;
946 else
947 pllcfg |= HIFN_PLL_REF_CLK_HBI;
948
949 if (hifn_pll_ref[3] != '\0')
950 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
951 else {
952 freq = 66;
953 dev_info(&dev->pdev->dev, "assuming %uMHz clock speed, override with hifn_pll_ref=%.3s<frequency>\n",
954 freq, hifn_pll_ref);
955 }
956
957 m = HIFN_PLL_FCK_MAX / freq;
958
959 pllcfg |= (m / 2 - 1) << HIFN_PLL_ND_SHIFT;
960 if (m <= 8)
961 pllcfg |= HIFN_PLL_IS_1_8;
962 else
963 pllcfg |= HIFN_PLL_IS_9_12;
964
965 /* Select clock source and enable clock bypass */
966 hifn_write_1(dev, HIFN_1_PLL, pllcfg |
967 HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI | HIFN_PLL_BP);
968
969 /* Let the chip lock to the input clock */
970 mdelay(10);
971
972 /* Disable clock bypass */
973 hifn_write_1(dev, HIFN_1_PLL, pllcfg |
974 HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI);
975
976 /* Switch the engines to the PLL */
977 hifn_write_1(dev, HIFN_1_PLL, pllcfg |
978 HIFN_PLL_PK_CLK_PLL | HIFN_PLL_PE_CLK_PLL);
979
980 /*
981 * The Fpk_clk runs at half the total speed. Its frequency is needed to
982 * calculate the minimum time between two reads of the rng. Since 33MHz
983 * is actually 33.333... we overestimate the frequency here, resulting
984 * in slightly larger intervals.
985 */
986 dev->pk_clk_freq = 1000000 * (freq + 1) * m / 2;
987 }
988
989 static void hifn_init_registers(struct hifn_device *dev)
990 {
991 u32 dptr = dev->desc_dma;
992
993 /* Initialization magic... */
994 hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
995 hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
996 hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
997
998 /* write all 4 ring address registers */
999 hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr +
1000 offsetof(struct hifn_dma, cmdr[0]));
1001 hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr +
1002 offsetof(struct hifn_dma, srcr[0]));
1003 hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr +
1004 offsetof(struct hifn_dma, dstr[0]));
1005 hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr +
1006 offsetof(struct hifn_dma, resr[0]));
1007
1008 mdelay(2);
1009 #if 0
1010 hifn_write_1(dev, HIFN_1_DMA_CSR,
1011 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1012 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1013 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1014 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1015 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1016 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1017 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1018 HIFN_DMACSR_S_WAIT |
1019 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1020 HIFN_DMACSR_C_WAIT |
1021 HIFN_DMACSR_ENGINE |
1022 HIFN_DMACSR_PUBDONE);
1023 #else
1024 hifn_write_1(dev, HIFN_1_DMA_CSR,
1025 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1026 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA |
1027 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1028 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1029 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1030 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1031 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1032 HIFN_DMACSR_S_WAIT |
1033 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1034 HIFN_DMACSR_C_WAIT |
1035 HIFN_DMACSR_ENGINE |
1036 HIFN_DMACSR_PUBDONE);
1037 #endif
1038 hifn_read_1(dev, HIFN_1_DMA_CSR);
1039
1040 dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1041 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1042 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1043 HIFN_DMAIER_ENGINE;
1044 dev->dmareg &= ~HIFN_DMAIER_C_WAIT;
1045
1046 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1047 hifn_read_1(dev, HIFN_1_DMA_IER);
1048 #if 0
1049 hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG |
1050 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1051 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1052 HIFN_PUCNFG_DRAM);
1053 #else
1054 hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342);
1055 #endif
1056 hifn_init_pll(dev);
1057
1058 hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1059 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1060 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1061 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1062 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1063 }
1064
1065 static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf,
1066 unsigned dlen, unsigned slen, u16 mask, u8 snum)
1067 {
1068 struct hifn_base_command *base_cmd;
1069 u8 *buf_pos = buf;
1070
1071 base_cmd = (struct hifn_base_command *)buf_pos;
1072 base_cmd->masks = __cpu_to_le16(mask);
1073 base_cmd->total_source_count =
1074 __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO);
1075 base_cmd->total_dest_count =
1076 __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1077
1078 dlen >>= 16;
1079 slen >>= 16;
1080 base_cmd->session_num = __cpu_to_le16(snum |
1081 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1082 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1083
1084 return sizeof(struct hifn_base_command);
1085 }
1086
1087 static int hifn_setup_crypto_command(struct hifn_device *dev,
1088 u8 *buf, unsigned dlen, unsigned slen,
1089 u8 *key, int keylen, u8 *iv, int ivsize, u16 mode)
1090 {
1091 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1092 struct hifn_crypt_command *cry_cmd;
1093 u8 *buf_pos = buf;
1094 u16 cmd_len;
1095
1096 cry_cmd = (struct hifn_crypt_command *)buf_pos;
1097
1098 cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff);
1099 dlen >>= 16;
1100 cry_cmd->masks = __cpu_to_le16(mode |
1101 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) &
1102 HIFN_CRYPT_CMD_SRCLEN_M));
1103 cry_cmd->header_skip = 0;
1104 cry_cmd->reserved = 0;
1105
1106 buf_pos += sizeof(struct hifn_crypt_command);
1107
1108 dma->cmdu++;
1109 if (dma->cmdu > 1) {
1110 dev->dmareg |= HIFN_DMAIER_C_WAIT;
1111 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1112 }
1113
1114 if (keylen) {
1115 memcpy(buf_pos, key, keylen);
1116 buf_pos += keylen;
1117 }
1118 if (ivsize) {
1119 memcpy(buf_pos, iv, ivsize);
1120 buf_pos += ivsize;
1121 }
1122
1123 cmd_len = buf_pos - buf;
1124
1125 return cmd_len;
1126 }
1127
1128 static int hifn_setup_cmd_desc(struct hifn_device *dev,
1129 struct hifn_context *ctx, struct hifn_request_context *rctx,
1130 void *priv, unsigned int nbytes)
1131 {
1132 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1133 int cmd_len, sa_idx;
1134 u8 *buf, *buf_pos;
1135 u16 mask;
1136
1137 sa_idx = dma->cmdi;
1138 buf_pos = buf = dma->command_bufs[dma->cmdi];
1139
1140 mask = 0;
1141 switch (rctx->op) {
1142 case ACRYPTO_OP_DECRYPT:
1143 mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE;
1144 break;
1145 case ACRYPTO_OP_ENCRYPT:
1146 mask = HIFN_BASE_CMD_CRYPT;
1147 break;
1148 case ACRYPTO_OP_HMAC:
1149 mask = HIFN_BASE_CMD_MAC;
1150 break;
1151 default:
1152 goto err_out;
1153 }
1154
1155 buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes,
1156 nbytes, mask, dev->snum);
1157
1158 if (rctx->op == ACRYPTO_OP_ENCRYPT || rctx->op == ACRYPTO_OP_DECRYPT) {
1159 u16 md = 0;
1160
1161 if (ctx->keysize)
1162 md |= HIFN_CRYPT_CMD_NEW_KEY;
1163 if (rctx->iv && rctx->mode != ACRYPTO_MODE_ECB)
1164 md |= HIFN_CRYPT_CMD_NEW_IV;
1165
1166 switch (rctx->mode) {
1167 case ACRYPTO_MODE_ECB:
1168 md |= HIFN_CRYPT_CMD_MODE_ECB;
1169 break;
1170 case ACRYPTO_MODE_CBC:
1171 md |= HIFN_CRYPT_CMD_MODE_CBC;
1172 break;
1173 case ACRYPTO_MODE_CFB:
1174 md |= HIFN_CRYPT_CMD_MODE_CFB;
1175 break;
1176 case ACRYPTO_MODE_OFB:
1177 md |= HIFN_CRYPT_CMD_MODE_OFB;
1178 break;
1179 default:
1180 goto err_out;
1181 }
1182
1183 switch (rctx->type) {
1184 case ACRYPTO_TYPE_AES_128:
1185 if (ctx->keysize != 16)
1186 goto err_out;
1187 md |= HIFN_CRYPT_CMD_KSZ_128 |
1188 HIFN_CRYPT_CMD_ALG_AES;
1189 break;
1190 case ACRYPTO_TYPE_AES_192:
1191 if (ctx->keysize != 24)
1192 goto err_out;
1193 md |= HIFN_CRYPT_CMD_KSZ_192 |
1194 HIFN_CRYPT_CMD_ALG_AES;
1195 break;
1196 case ACRYPTO_TYPE_AES_256:
1197 if (ctx->keysize != 32)
1198 goto err_out;
1199 md |= HIFN_CRYPT_CMD_KSZ_256 |
1200 HIFN_CRYPT_CMD_ALG_AES;
1201 break;
1202 case ACRYPTO_TYPE_3DES:
1203 if (ctx->keysize != 24)
1204 goto err_out;
1205 md |= HIFN_CRYPT_CMD_ALG_3DES;
1206 break;
1207 case ACRYPTO_TYPE_DES:
1208 if (ctx->keysize != 8)
1209 goto err_out;
1210 md |= HIFN_CRYPT_CMD_ALG_DES;
1211 break;
1212 default:
1213 goto err_out;
1214 }
1215
1216 buf_pos += hifn_setup_crypto_command(dev, buf_pos,
1217 nbytes, nbytes, ctx->key, ctx->keysize,
1218 rctx->iv, rctx->ivsize, md);
1219 }
1220
1221 dev->sa[sa_idx] = priv;
1222 dev->started++;
1223
1224 cmd_len = buf_pos - buf;
1225 dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID |
1226 HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
1227
1228 if (++dma->cmdi == HIFN_D_CMD_RSIZE) {
1229 dma->cmdr[dma->cmdi].l = __cpu_to_le32(
1230 HIFN_D_VALID | HIFN_D_LAST |
1231 HIFN_D_MASKDONEIRQ | HIFN_D_JUMP);
1232 dma->cmdi = 0;
1233 } else {
1234 dma->cmdr[dma->cmdi - 1].l |= __cpu_to_le32(HIFN_D_VALID);
1235 }
1236
1237 if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) {
1238 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1239 dev->flags |= HIFN_FLAG_CMD_BUSY;
1240 }
1241 return 0;
1242
1243 err_out:
1244 return -EINVAL;
1245 }
1246
1247 static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page,
1248 unsigned int offset, unsigned int size, int last)
1249 {
1250 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1251 int idx;
1252 dma_addr_t addr;
1253
1254 addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE);
1255
1256 idx = dma->srci;
1257
1258 dma->srcr[idx].p = __cpu_to_le32(addr);
1259 dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
1260 HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
1261
1262 if (++idx == HIFN_D_SRC_RSIZE) {
1263 dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1264 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
1265 (last ? HIFN_D_LAST : 0));
1266 idx = 0;
1267 }
1268
1269 dma->srci = idx;
1270 dma->srcu++;
1271
1272 if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) {
1273 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1274 dev->flags |= HIFN_FLAG_SRC_BUSY;
1275 }
1276
1277 return size;
1278 }
1279
1280 static void hifn_setup_res_desc(struct hifn_device *dev)
1281 {
1282 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1283
1284 dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT |
1285 HIFN_D_VALID | HIFN_D_LAST);
1286 /*
1287 * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID |
1288 * HIFN_D_LAST);
1289 */
1290
1291 if (++dma->resi == HIFN_D_RES_RSIZE) {
1292 dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID |
1293 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
1294 dma->resi = 0;
1295 }
1296
1297 dma->resu++;
1298
1299 if (!(dev->flags & HIFN_FLAG_RES_BUSY)) {
1300 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
1301 dev->flags |= HIFN_FLAG_RES_BUSY;
1302 }
1303 }
1304
1305 static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page,
1306 unsigned offset, unsigned size, int last)
1307 {
1308 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1309 int idx;
1310 dma_addr_t addr;
1311
1312 addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE);
1313
1314 idx = dma->dsti;
1315 dma->dstr[idx].p = __cpu_to_le32(addr);
1316 dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
1317 HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
1318
1319 if (++idx == HIFN_D_DST_RSIZE) {
1320 dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1321 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
1322 (last ? HIFN_D_LAST : 0));
1323 idx = 0;
1324 }
1325 dma->dsti = idx;
1326 dma->dstu++;
1327
1328 if (!(dev->flags & HIFN_FLAG_DST_BUSY)) {
1329 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
1330 dev->flags |= HIFN_FLAG_DST_BUSY;
1331 }
1332 }
1333
1334 static int hifn_setup_dma(struct hifn_device *dev,
1335 struct hifn_context *ctx, struct hifn_request_context *rctx,
1336 struct scatterlist *src, struct scatterlist *dst,
1337 unsigned int nbytes, void *priv)
1338 {
1339 struct scatterlist *t;
1340 struct page *spage, *dpage;
1341 unsigned int soff, doff;
1342 unsigned int n, len;
1343
1344 n = nbytes;
1345 while (n) {
1346 spage = sg_page(src);
1347 soff = src->offset;
1348 len = min(src->length, n);
1349
1350 hifn_setup_src_desc(dev, spage, soff, len, n - len == 0);
1351
1352 src++;
1353 n -= len;
1354 }
1355
1356 t = &rctx->walk.cache[0];
1357 n = nbytes;
1358 while (n) {
1359 if (t->length && rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1360 BUG_ON(!sg_page(t));
1361 dpage = sg_page(t);
1362 doff = 0;
1363 len = t->length;
1364 } else {
1365 BUG_ON(!sg_page(dst));
1366 dpage = sg_page(dst);
1367 doff = dst->offset;
1368 len = dst->length;
1369 }
1370 len = min(len, n);
1371
1372 hifn_setup_dst_desc(dev, dpage, doff, len, n - len == 0);
1373
1374 dst++;
1375 t++;
1376 n -= len;
1377 }
1378
1379 hifn_setup_cmd_desc(dev, ctx, rctx, priv, nbytes);
1380 hifn_setup_res_desc(dev);
1381 return 0;
1382 }
1383
1384 static int hifn_cipher_walk_init(struct hifn_cipher_walk *w,
1385 int num, gfp_t gfp_flags)
1386 {
1387 int i;
1388
1389 num = min(ASYNC_SCATTERLIST_CACHE, num);
1390 sg_init_table(w->cache, num);
1391
1392 w->num = 0;
1393 for (i = 0; i < num; ++i) {
1394 struct page *page = alloc_page(gfp_flags);
1395 struct scatterlist *s;
1396
1397 if (!page)
1398 break;
1399
1400 s = &w->cache[i];
1401
1402 sg_set_page(s, page, PAGE_SIZE, 0);
1403 w->num++;
1404 }
1405
1406 return i;
1407 }
1408
1409 static void hifn_cipher_walk_exit(struct hifn_cipher_walk *w)
1410 {
1411 int i;
1412
1413 for (i = 0; i < w->num; ++i) {
1414 struct scatterlist *s = &w->cache[i];
1415
1416 __free_page(sg_page(s));
1417
1418 s->length = 0;
1419 }
1420
1421 w->num = 0;
1422 }
1423
1424 static int ablkcipher_add(unsigned int *drestp, struct scatterlist *dst,
1425 unsigned int size, unsigned int *nbytesp)
1426 {
1427 unsigned int copy, drest = *drestp, nbytes = *nbytesp;
1428 int idx = 0;
1429
1430 if (drest < size || size > nbytes)
1431 return -EINVAL;
1432
1433 while (size) {
1434 copy = min3(drest, size, dst->length);
1435
1436 size -= copy;
1437 drest -= copy;
1438 nbytes -= copy;
1439
1440 pr_debug("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
1441 __func__, copy, size, drest, nbytes);
1442
1443 dst++;
1444 idx++;
1445 }
1446
1447 *nbytesp = nbytes;
1448 *drestp = drest;
1449
1450 return idx;
1451 }
1452
1453 static int hifn_cipher_walk(struct ablkcipher_request *req,
1454 struct hifn_cipher_walk *w)
1455 {
1456 struct scatterlist *dst, *t;
1457 unsigned int nbytes = req->nbytes, offset, copy, diff;
1458 int idx, tidx, err;
1459
1460 tidx = idx = 0;
1461 offset = 0;
1462 while (nbytes) {
1463 if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED))
1464 return -EINVAL;
1465
1466 dst = &req->dst[idx];
1467
1468 pr_debug("\n%s: dlen: %u, doff: %u, offset: %u, nbytes: %u.\n",
1469 __func__, dst->length, dst->offset, offset, nbytes);
1470
1471 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
1472 !IS_ALIGNED(dst->length, HIFN_D_DST_DALIGN) ||
1473 offset) {
1474 unsigned slen = min(dst->length - offset, nbytes);
1475 unsigned dlen = PAGE_SIZE;
1476
1477 t = &w->cache[idx];
1478
1479 err = ablkcipher_add(&dlen, dst, slen, &nbytes);
1480 if (err < 0)
1481 return err;
1482
1483 idx += err;
1484
1485 copy = slen & ~(HIFN_D_DST_DALIGN - 1);
1486 diff = slen & (HIFN_D_DST_DALIGN - 1);
1487
1488 if (dlen < nbytes) {
1489 /*
1490 * Destination page does not have enough space
1491 * to put there additional blocksized chunk,
1492 * so we mark that page as containing only
1493 * blocksize aligned chunks:
1494 * t->length = (slen & ~(HIFN_D_DST_DALIGN - 1));
1495 * and increase number of bytes to be processed
1496 * in next chunk:
1497 * nbytes += diff;
1498 */
1499 nbytes += diff;
1500
1501 /*
1502 * Temporary of course...
1503 * Kick author if you will catch this one.
1504 */
1505 pr_err("%s: dlen: %u, nbytes: %u, slen: %u, offset: %u.\n",
1506 __func__, dlen, nbytes, slen, offset);
1507 pr_err("%s: please contact author to fix this "
1508 "issue, generally you should not catch "
1509 "this path under any condition but who "
1510 "knows how did you use crypto code.\n"
1511 "Thank you.\n", __func__);
1512 BUG();
1513 } else {
1514 copy += diff + nbytes;
1515
1516 dst = &req->dst[idx];
1517
1518 err = ablkcipher_add(&dlen, dst, nbytes, &nbytes);
1519 if (err < 0)
1520 return err;
1521
1522 idx += err;
1523 }
1524
1525 t->length = copy;
1526 t->offset = offset;
1527 } else {
1528 nbytes -= min(dst->length, nbytes);
1529 idx++;
1530 }
1531
1532 tidx++;
1533 }
1534
1535 return tidx;
1536 }
1537
1538 static int hifn_setup_session(struct ablkcipher_request *req)
1539 {
1540 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1541 struct hifn_request_context *rctx = ablkcipher_request_ctx(req);
1542 struct hifn_device *dev = ctx->dev;
1543 unsigned long dlen, flags;
1544 unsigned int nbytes = req->nbytes, idx = 0;
1545 int err = -EINVAL, sg_num;
1546 struct scatterlist *dst;
1547
1548 if (rctx->iv && !rctx->ivsize && rctx->mode != ACRYPTO_MODE_ECB)
1549 goto err_out_exit;
1550
1551 rctx->walk.flags = 0;
1552
1553 while (nbytes) {
1554 dst = &req->dst[idx];
1555 dlen = min(dst->length, nbytes);
1556
1557 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
1558 !IS_ALIGNED(dlen, HIFN_D_DST_DALIGN))
1559 rctx->walk.flags |= ASYNC_FLAGS_MISALIGNED;
1560
1561 nbytes -= dlen;
1562 idx++;
1563 }
1564
1565 if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1566 err = hifn_cipher_walk_init(&rctx->walk, idx, GFP_ATOMIC);
1567 if (err < 0)
1568 return err;
1569 }
1570
1571 sg_num = hifn_cipher_walk(req, &rctx->walk);
1572 if (sg_num < 0) {
1573 err = sg_num;
1574 goto err_out_exit;
1575 }
1576
1577 spin_lock_irqsave(&dev->lock, flags);
1578 if (dev->started + sg_num > HIFN_QUEUE_LENGTH) {
1579 err = -EAGAIN;
1580 goto err_out;
1581 }
1582
1583 err = hifn_setup_dma(dev, ctx, rctx, req->src, req->dst, req->nbytes, req);
1584 if (err)
1585 goto err_out;
1586
1587 dev->snum++;
1588
1589 dev->active = HIFN_DEFAULT_ACTIVE_NUM;
1590 spin_unlock_irqrestore(&dev->lock, flags);
1591
1592 return 0;
1593
1594 err_out:
1595 spin_unlock_irqrestore(&dev->lock, flags);
1596 err_out_exit:
1597 if (err) {
1598 dev_info(&dev->pdev->dev, "iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
1599 "type: %u, err: %d.\n",
1600 rctx->iv, rctx->ivsize,
1601 ctx->key, ctx->keysize,
1602 rctx->mode, rctx->op, rctx->type, err);
1603 }
1604
1605 return err;
1606 }
1607
1608 static int hifn_start_device(struct hifn_device *dev)
1609 {
1610 int err;
1611
1612 dev->started = dev->active = 0;
1613 hifn_reset_dma(dev, 1);
1614
1615 err = hifn_enable_crypto(dev);
1616 if (err)
1617 return err;
1618
1619 hifn_reset_puc(dev);
1620
1621 hifn_init_dma(dev);
1622
1623 hifn_init_registers(dev);
1624
1625 hifn_init_pubrng(dev);
1626
1627 return 0;
1628 }
1629
1630 static int ablkcipher_get(void *saddr, unsigned int *srestp, unsigned int offset,
1631 struct scatterlist *dst, unsigned int size, unsigned int *nbytesp)
1632 {
1633 unsigned int srest = *srestp, nbytes = *nbytesp, copy;
1634 void *daddr;
1635 int idx = 0;
1636
1637 if (srest < size || size > nbytes)
1638 return -EINVAL;
1639
1640 while (size) {
1641 copy = min3(srest, dst->length, size);
1642
1643 daddr = kmap_atomic(sg_page(dst));
1644 memcpy(daddr + dst->offset + offset, saddr, copy);
1645 kunmap_atomic(daddr);
1646
1647 nbytes -= copy;
1648 size -= copy;
1649 srest -= copy;
1650 saddr += copy;
1651 offset = 0;
1652
1653 pr_debug("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n",
1654 __func__, copy, size, srest, nbytes);
1655
1656 dst++;
1657 idx++;
1658 }
1659
1660 *nbytesp = nbytes;
1661 *srestp = srest;
1662
1663 return idx;
1664 }
1665
1666 static inline void hifn_complete_sa(struct hifn_device *dev, int i)
1667 {
1668 unsigned long flags;
1669
1670 spin_lock_irqsave(&dev->lock, flags);
1671 dev->sa[i] = NULL;
1672 dev->started--;
1673 if (dev->started < 0)
1674 dev_info(&dev->pdev->dev, "%s: started: %d.\n", __func__,
1675 dev->started);
1676 spin_unlock_irqrestore(&dev->lock, flags);
1677 BUG_ON(dev->started < 0);
1678 }
1679
1680 static void hifn_process_ready(struct ablkcipher_request *req, int error)
1681 {
1682 struct hifn_request_context *rctx = ablkcipher_request_ctx(req);
1683
1684 if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1685 unsigned int nbytes = req->nbytes;
1686 int idx = 0, err;
1687 struct scatterlist *dst, *t;
1688 void *saddr;
1689
1690 while (nbytes) {
1691 t = &rctx->walk.cache[idx];
1692 dst = &req->dst[idx];
1693
1694 pr_debug("\n%s: sg_page(t): %p, t->length: %u, "
1695 "sg_page(dst): %p, dst->length: %u, "
1696 "nbytes: %u.\n",
1697 __func__, sg_page(t), t->length,
1698 sg_page(dst), dst->length, nbytes);
1699
1700 if (!t->length) {
1701 nbytes -= min(dst->length, nbytes);
1702 idx++;
1703 continue;
1704 }
1705
1706 saddr = kmap_atomic(sg_page(t));
1707
1708 err = ablkcipher_get(saddr, &t->length, t->offset,
1709 dst, nbytes, &nbytes);
1710 if (err < 0) {
1711 kunmap_atomic(saddr);
1712 break;
1713 }
1714
1715 idx += err;
1716 kunmap_atomic(saddr);
1717 }
1718
1719 hifn_cipher_walk_exit(&rctx->walk);
1720 }
1721
1722 req->base.complete(&req->base, error);
1723 }
1724
1725 static void hifn_clear_rings(struct hifn_device *dev, int error)
1726 {
1727 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1728 int i, u;
1729
1730 dev_dbg(&dev->pdev->dev, "ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1731 "k: %d.%d.%d.%d.\n",
1732 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1733 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1734 dma->cmdk, dma->srck, dma->dstk, dma->resk);
1735
1736 i = dma->resk; u = dma->resu;
1737 while (u != 0) {
1738 if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID))
1739 break;
1740
1741 if (dev->sa[i]) {
1742 dev->success++;
1743 dev->reset = 0;
1744 hifn_process_ready(dev->sa[i], error);
1745 hifn_complete_sa(dev, i);
1746 }
1747
1748 if (++i == HIFN_D_RES_RSIZE)
1749 i = 0;
1750 u--;
1751 }
1752 dma->resk = i; dma->resu = u;
1753
1754 i = dma->srck; u = dma->srcu;
1755 while (u != 0) {
1756 if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID))
1757 break;
1758 if (++i == HIFN_D_SRC_RSIZE)
1759 i = 0;
1760 u--;
1761 }
1762 dma->srck = i; dma->srcu = u;
1763
1764 i = dma->cmdk; u = dma->cmdu;
1765 while (u != 0) {
1766 if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID))
1767 break;
1768 if (++i == HIFN_D_CMD_RSIZE)
1769 i = 0;
1770 u--;
1771 }
1772 dma->cmdk = i; dma->cmdu = u;
1773
1774 i = dma->dstk; u = dma->dstu;
1775 while (u != 0) {
1776 if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID))
1777 break;
1778 if (++i == HIFN_D_DST_RSIZE)
1779 i = 0;
1780 u--;
1781 }
1782 dma->dstk = i; dma->dstu = u;
1783
1784 dev_dbg(&dev->pdev->dev, "ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1785 "k: %d.%d.%d.%d.\n",
1786 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1787 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1788 dma->cmdk, dma->srck, dma->dstk, dma->resk);
1789 }
1790
1791 static void hifn_work(struct work_struct *work)
1792 {
1793 struct delayed_work *dw = to_delayed_work(work);
1794 struct hifn_device *dev = container_of(dw, struct hifn_device, work);
1795 unsigned long flags;
1796 int reset = 0;
1797 u32 r = 0;
1798
1799 spin_lock_irqsave(&dev->lock, flags);
1800 if (dev->active == 0) {
1801 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1802
1803 if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) {
1804 dev->flags &= ~HIFN_FLAG_CMD_BUSY;
1805 r |= HIFN_DMACSR_C_CTRL_DIS;
1806 }
1807 if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) {
1808 dev->flags &= ~HIFN_FLAG_SRC_BUSY;
1809 r |= HIFN_DMACSR_S_CTRL_DIS;
1810 }
1811 if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) {
1812 dev->flags &= ~HIFN_FLAG_DST_BUSY;
1813 r |= HIFN_DMACSR_D_CTRL_DIS;
1814 }
1815 if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) {
1816 dev->flags &= ~HIFN_FLAG_RES_BUSY;
1817 r |= HIFN_DMACSR_R_CTRL_DIS;
1818 }
1819 if (r)
1820 hifn_write_1(dev, HIFN_1_DMA_CSR, r);
1821 } else
1822 dev->active--;
1823
1824 if ((dev->prev_success == dev->success) && dev->started)
1825 reset = 1;
1826 dev->prev_success = dev->success;
1827 spin_unlock_irqrestore(&dev->lock, flags);
1828
1829 if (reset) {
1830 if (++dev->reset >= 5) {
1831 int i;
1832 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1833
1834 dev_info(&dev->pdev->dev,
1835 "r: %08x, active: %d, started: %d, "
1836 "success: %lu: qlen: %u/%u, reset: %d.\n",
1837 r, dev->active, dev->started,
1838 dev->success, dev->queue.qlen, dev->queue.max_qlen,
1839 reset);
1840
1841 dev_info(&dev->pdev->dev, "%s: res: ", __func__);
1842 for (i = 0; i < HIFN_D_RES_RSIZE; ++i) {
1843 pr_info("%x.%p ", dma->resr[i].l, dev->sa[i]);
1844 if (dev->sa[i]) {
1845 hifn_process_ready(dev->sa[i], -ENODEV);
1846 hifn_complete_sa(dev, i);
1847 }
1848 }
1849 pr_info("\n");
1850
1851 hifn_reset_dma(dev, 1);
1852 hifn_stop_device(dev);
1853 hifn_start_device(dev);
1854 dev->reset = 0;
1855 }
1856
1857 tasklet_schedule(&dev->tasklet);
1858 }
1859
1860 schedule_delayed_work(&dev->work, HZ);
1861 }
1862
1863 static irqreturn_t hifn_interrupt(int irq, void *data)
1864 {
1865 struct hifn_device *dev = (struct hifn_device *)data;
1866 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1867 u32 dmacsr, restart;
1868
1869 dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR);
1870
1871 dev_dbg(&dev->pdev->dev, "1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], "
1872 "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n",
1873 dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi,
1874 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1875 dma->cmdu, dma->srcu, dma->dstu, dma->resu);
1876
1877 if ((dmacsr & dev->dmareg) == 0)
1878 return IRQ_NONE;
1879
1880 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);
1881
1882 if (dmacsr & HIFN_DMACSR_ENGINE)
1883 hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR));
1884 if (dmacsr & HIFN_DMACSR_PUBDONE)
1885 hifn_write_1(dev, HIFN_1_PUB_STATUS,
1886 hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
1887
1888 restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER);
1889 if (restart) {
1890 u32 puisr = hifn_read_0(dev, HIFN_0_PUISR);
1891
1892 dev_warn(&dev->pdev->dev, "overflow: r: %d, d: %d, puisr: %08x, d: %u.\n",
1893 !!(dmacsr & HIFN_DMACSR_R_OVER),
1894 !!(dmacsr & HIFN_DMACSR_D_OVER),
1895 puisr, !!(puisr & HIFN_PUISR_DSTOVER));
1896 if (!!(puisr & HIFN_PUISR_DSTOVER))
1897 hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1898 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |
1899 HIFN_DMACSR_D_OVER));
1900 }
1901
1902 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
1903 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
1904 if (restart) {
1905 dev_warn(&dev->pdev->dev, "abort: c: %d, s: %d, d: %d, r: %d.\n",
1906 !!(dmacsr & HIFN_DMACSR_C_ABORT),
1907 !!(dmacsr & HIFN_DMACSR_S_ABORT),
1908 !!(dmacsr & HIFN_DMACSR_D_ABORT),
1909 !!(dmacsr & HIFN_DMACSR_R_ABORT));
1910 hifn_reset_dma(dev, 1);
1911 hifn_init_dma(dev);
1912 hifn_init_registers(dev);
1913 }
1914
1915 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
1916 dev_dbg(&dev->pdev->dev, "wait on command.\n");
1917 dev->dmareg &= ~(HIFN_DMAIER_C_WAIT);
1918 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1919 }
1920
1921 tasklet_schedule(&dev->tasklet);
1922
1923 return IRQ_HANDLED;
1924 }
1925
1926 static void hifn_flush(struct hifn_device *dev)
1927 {
1928 unsigned long flags;
1929 struct crypto_async_request *async_req;
1930 struct ablkcipher_request *req;
1931 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1932 int i;
1933
1934 for (i = 0; i < HIFN_D_RES_RSIZE; ++i) {
1935 struct hifn_desc *d = &dma->resr[i];
1936
1937 if (dev->sa[i]) {
1938 hifn_process_ready(dev->sa[i],
1939 (d->l & __cpu_to_le32(HIFN_D_VALID)) ? -ENODEV : 0);
1940 hifn_complete_sa(dev, i);
1941 }
1942 }
1943
1944 spin_lock_irqsave(&dev->lock, flags);
1945 while ((async_req = crypto_dequeue_request(&dev->queue))) {
1946 req = ablkcipher_request_cast(async_req);
1947 spin_unlock_irqrestore(&dev->lock, flags);
1948
1949 hifn_process_ready(req, -ENODEV);
1950
1951 spin_lock_irqsave(&dev->lock, flags);
1952 }
1953 spin_unlock_irqrestore(&dev->lock, flags);
1954 }
1955
1956 static int hifn_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
1957 unsigned int len)
1958 {
1959 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
1960 struct hifn_context *ctx = crypto_tfm_ctx(tfm);
1961 struct hifn_device *dev = ctx->dev;
1962
1963 if (len > HIFN_MAX_CRYPT_KEY_LENGTH) {
1964 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1965 return -1;
1966 }
1967
1968 if (len == HIFN_DES_KEY_LENGTH) {
1969 u32 tmp[DES_EXPKEY_WORDS];
1970 int ret = des_ekey(tmp, key);
1971
1972 if (unlikely(ret == 0) && (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
1973 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
1974 return -EINVAL;
1975 }
1976 }
1977
1978 dev->flags &= ~HIFN_FLAG_OLD_KEY;
1979
1980 memcpy(ctx->key, key, len);
1981 ctx->keysize = len;
1982
1983 return 0;
1984 }
1985
1986 static int hifn_handle_req(struct ablkcipher_request *req)
1987 {
1988 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1989 struct hifn_device *dev = ctx->dev;
1990 int err = -EAGAIN;
1991
1992 if (dev->started + DIV_ROUND_UP(req->nbytes, PAGE_SIZE) <= HIFN_QUEUE_LENGTH)
1993 err = hifn_setup_session(req);
1994
1995 if (err == -EAGAIN) {
1996 unsigned long flags;
1997
1998 spin_lock_irqsave(&dev->lock, flags);
1999 err = ablkcipher_enqueue_request(&dev->queue, req);
2000 spin_unlock_irqrestore(&dev->lock, flags);
2001 }
2002
2003 return err;
2004 }
2005
2006 static int hifn_setup_crypto_req(struct ablkcipher_request *req, u8 op,
2007 u8 type, u8 mode)
2008 {
2009 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2010 struct hifn_request_context *rctx = ablkcipher_request_ctx(req);
2011 unsigned ivsize;
2012
2013 ivsize = crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req));
2014
2015 if (req->info && mode != ACRYPTO_MODE_ECB) {
2016 if (type == ACRYPTO_TYPE_AES_128)
2017 ivsize = HIFN_AES_IV_LENGTH;
2018 else if (type == ACRYPTO_TYPE_DES)
2019 ivsize = HIFN_DES_KEY_LENGTH;
2020 else if (type == ACRYPTO_TYPE_3DES)
2021 ivsize = HIFN_3DES_KEY_LENGTH;
2022 }
2023
2024 if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) {
2025 if (ctx->keysize == 24)
2026 type = ACRYPTO_TYPE_AES_192;
2027 else if (ctx->keysize == 32)
2028 type = ACRYPTO_TYPE_AES_256;
2029 }
2030
2031 rctx->op = op;
2032 rctx->mode = mode;
2033 rctx->type = type;
2034 rctx->iv = req->info;
2035 rctx->ivsize = ivsize;
2036
2037 /*
2038 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2039 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2040 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2041 */
2042
2043 return hifn_handle_req(req);
2044 }
2045
2046 static int hifn_process_queue(struct hifn_device *dev)
2047 {
2048 struct crypto_async_request *async_req, *backlog;
2049 struct ablkcipher_request *req;
2050 unsigned long flags;
2051 int err = 0;
2052
2053 while (dev->started < HIFN_QUEUE_LENGTH) {
2054 spin_lock_irqsave(&dev->lock, flags);
2055 backlog = crypto_get_backlog(&dev->queue);
2056 async_req = crypto_dequeue_request(&dev->queue);
2057 spin_unlock_irqrestore(&dev->lock, flags);
2058
2059 if (!async_req)
2060 break;
2061
2062 if (backlog)
2063 backlog->complete(backlog, -EINPROGRESS);
2064
2065 req = ablkcipher_request_cast(async_req);
2066
2067 err = hifn_handle_req(req);
2068 if (err)
2069 break;
2070 }
2071
2072 return err;
2073 }
2074
2075 static int hifn_setup_crypto(struct ablkcipher_request *req, u8 op,
2076 u8 type, u8 mode)
2077 {
2078 int err;
2079 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2080 struct hifn_device *dev = ctx->dev;
2081
2082 err = hifn_setup_crypto_req(req, op, type, mode);
2083 if (err)
2084 return err;
2085
2086 if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
2087 hifn_process_queue(dev);
2088
2089 return -EINPROGRESS;
2090 }
2091
2092 /*
2093 * AES ecryption functions.
2094 */
2095 static inline int hifn_encrypt_aes_ecb(struct ablkcipher_request *req)
2096 {
2097 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2098 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2099 }
2100 static inline int hifn_encrypt_aes_cbc(struct ablkcipher_request *req)
2101 {
2102 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2103 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2104 }
2105 static inline int hifn_encrypt_aes_cfb(struct ablkcipher_request *req)
2106 {
2107 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2108 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2109 }
2110 static inline int hifn_encrypt_aes_ofb(struct ablkcipher_request *req)
2111 {
2112 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2113 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2114 }
2115
2116 /*
2117 * AES decryption functions.
2118 */
2119 static inline int hifn_decrypt_aes_ecb(struct ablkcipher_request *req)
2120 {
2121 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2122 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2123 }
2124 static inline int hifn_decrypt_aes_cbc(struct ablkcipher_request *req)
2125 {
2126 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2127 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2128 }
2129 static inline int hifn_decrypt_aes_cfb(struct ablkcipher_request *req)
2130 {
2131 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2132 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2133 }
2134 static inline int hifn_decrypt_aes_ofb(struct ablkcipher_request *req)
2135 {
2136 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2137 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2138 }
2139
2140 /*
2141 * DES ecryption functions.
2142 */
2143 static inline int hifn_encrypt_des_ecb(struct ablkcipher_request *req)
2144 {
2145 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2146 ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2147 }
2148 static inline int hifn_encrypt_des_cbc(struct ablkcipher_request *req)
2149 {
2150 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2151 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2152 }
2153 static inline int hifn_encrypt_des_cfb(struct ablkcipher_request *req)
2154 {
2155 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2156 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2157 }
2158 static inline int hifn_encrypt_des_ofb(struct ablkcipher_request *req)
2159 {
2160 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2161 ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2162 }
2163
2164 /*
2165 * DES decryption functions.
2166 */
2167 static inline int hifn_decrypt_des_ecb(struct ablkcipher_request *req)
2168 {
2169 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2170 ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2171 }
2172 static inline int hifn_decrypt_des_cbc(struct ablkcipher_request *req)
2173 {
2174 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2175 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2176 }
2177 static inline int hifn_decrypt_des_cfb(struct ablkcipher_request *req)
2178 {
2179 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2180 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2181 }
2182 static inline int hifn_decrypt_des_ofb(struct ablkcipher_request *req)
2183 {
2184 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2185 ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2186 }
2187
2188 /*
2189 * 3DES ecryption functions.
2190 */
2191 static inline int hifn_encrypt_3des_ecb(struct ablkcipher_request *req)
2192 {
2193 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2194 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2195 }
2196 static inline int hifn_encrypt_3des_cbc(struct ablkcipher_request *req)
2197 {
2198 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2199 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2200 }
2201 static inline int hifn_encrypt_3des_cfb(struct ablkcipher_request *req)
2202 {
2203 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2204 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2205 }
2206 static inline int hifn_encrypt_3des_ofb(struct ablkcipher_request *req)
2207 {
2208 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2209 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2210 }
2211
2212 /* 3DES decryption functions. */
2213 static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request *req)
2214 {
2215 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2216 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2217 }
2218 static inline int hifn_decrypt_3des_cbc(struct ablkcipher_request *req)
2219 {
2220 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2221 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2222 }
2223 static inline int hifn_decrypt_3des_cfb(struct ablkcipher_request *req)
2224 {
2225 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2226 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2227 }
2228 static inline int hifn_decrypt_3des_ofb(struct ablkcipher_request *req)
2229 {
2230 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2231 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2232 }
2233
2234 struct hifn_alg_template {
2235 char name[CRYPTO_MAX_ALG_NAME];
2236 char drv_name[CRYPTO_MAX_ALG_NAME];
2237 unsigned int bsize;
2238 struct ablkcipher_alg ablkcipher;
2239 };
2240
2241 static struct hifn_alg_template hifn_alg_templates[] = {
2242 /*
2243 * 3DES ECB, CBC, CFB and OFB modes.
2244 */
2245 {
2246 .name = "cfb(des3_ede)", .drv_name = "cfb-3des", .bsize = 8,
2247 .ablkcipher = {
2248 .min_keysize = HIFN_3DES_KEY_LENGTH,
2249 .max_keysize = HIFN_3DES_KEY_LENGTH,
2250 .setkey = hifn_setkey,
2251 .encrypt = hifn_encrypt_3des_cfb,
2252 .decrypt = hifn_decrypt_3des_cfb,
2253 },
2254 },
2255 {
2256 .name = "ofb(des3_ede)", .drv_name = "ofb-3des", .bsize = 8,
2257 .ablkcipher = {
2258 .min_keysize = HIFN_3DES_KEY_LENGTH,
2259 .max_keysize = HIFN_3DES_KEY_LENGTH,
2260 .setkey = hifn_setkey,
2261 .encrypt = hifn_encrypt_3des_ofb,
2262 .decrypt = hifn_decrypt_3des_ofb,
2263 },
2264 },
2265 {
2266 .name = "cbc(des3_ede)", .drv_name = "cbc-3des", .bsize = 8,
2267 .ablkcipher = {
2268 .ivsize = HIFN_IV_LENGTH,
2269 .min_keysize = HIFN_3DES_KEY_LENGTH,
2270 .max_keysize = HIFN_3DES_KEY_LENGTH,
2271 .setkey = hifn_setkey,
2272 .encrypt = hifn_encrypt_3des_cbc,
2273 .decrypt = hifn_decrypt_3des_cbc,
2274 },
2275 },
2276 {
2277 .name = "ecb(des3_ede)", .drv_name = "ecb-3des", .bsize = 8,
2278 .ablkcipher = {
2279 .min_keysize = HIFN_3DES_KEY_LENGTH,
2280 .max_keysize = HIFN_3DES_KEY_LENGTH,
2281 .setkey = hifn_setkey,
2282 .encrypt = hifn_encrypt_3des_ecb,
2283 .decrypt = hifn_decrypt_3des_ecb,
2284 },
2285 },
2286
2287 /*
2288 * DES ECB, CBC, CFB and OFB modes.
2289 */
2290 {
2291 .name = "cfb(des)", .drv_name = "cfb-des", .bsize = 8,
2292 .ablkcipher = {
2293 .min_keysize = HIFN_DES_KEY_LENGTH,
2294 .max_keysize = HIFN_DES_KEY_LENGTH,
2295 .setkey = hifn_setkey,
2296 .encrypt = hifn_encrypt_des_cfb,
2297 .decrypt = hifn_decrypt_des_cfb,
2298 },
2299 },
2300 {
2301 .name = "ofb(des)", .drv_name = "ofb-des", .bsize = 8,
2302 .ablkcipher = {
2303 .min_keysize = HIFN_DES_KEY_LENGTH,
2304 .max_keysize = HIFN_DES_KEY_LENGTH,
2305 .setkey = hifn_setkey,
2306 .encrypt = hifn_encrypt_des_ofb,
2307 .decrypt = hifn_decrypt_des_ofb,
2308 },
2309 },
2310 {
2311 .name = "cbc(des)", .drv_name = "cbc-des", .bsize = 8,
2312 .ablkcipher = {
2313 .ivsize = HIFN_IV_LENGTH,
2314 .min_keysize = HIFN_DES_KEY_LENGTH,
2315 .max_keysize = HIFN_DES_KEY_LENGTH,
2316 .setkey = hifn_setkey,
2317 .encrypt = hifn_encrypt_des_cbc,
2318 .decrypt = hifn_decrypt_des_cbc,
2319 },
2320 },
2321 {
2322 .name = "ecb(des)", .drv_name = "ecb-des", .bsize = 8,
2323 .ablkcipher = {
2324 .min_keysize = HIFN_DES_KEY_LENGTH,
2325 .max_keysize = HIFN_DES_KEY_LENGTH,
2326 .setkey = hifn_setkey,
2327 .encrypt = hifn_encrypt_des_ecb,
2328 .decrypt = hifn_decrypt_des_ecb,
2329 },
2330 },
2331
2332 /*
2333 * AES ECB, CBC, CFB and OFB modes.
2334 */
2335 {
2336 .name = "ecb(aes)", .drv_name = "ecb-aes", .bsize = 16,
2337 .ablkcipher = {
2338 .min_keysize = AES_MIN_KEY_SIZE,
2339 .max_keysize = AES_MAX_KEY_SIZE,
2340 .setkey = hifn_setkey,
2341 .encrypt = hifn_encrypt_aes_ecb,
2342 .decrypt = hifn_decrypt_aes_ecb,
2343 },
2344 },
2345 {
2346 .name = "cbc(aes)", .drv_name = "cbc-aes", .bsize = 16,
2347 .ablkcipher = {
2348 .ivsize = HIFN_AES_IV_LENGTH,
2349 .min_keysize = AES_MIN_KEY_SIZE,
2350 .max_keysize = AES_MAX_KEY_SIZE,
2351 .setkey = hifn_setkey,
2352 .encrypt = hifn_encrypt_aes_cbc,
2353 .decrypt = hifn_decrypt_aes_cbc,
2354 },
2355 },
2356 {
2357 .name = "cfb(aes)", .drv_name = "cfb-aes", .bsize = 16,
2358 .ablkcipher = {
2359 .min_keysize = AES_MIN_KEY_SIZE,
2360 .max_keysize = AES_MAX_KEY_SIZE,
2361 .setkey = hifn_setkey,
2362 .encrypt = hifn_encrypt_aes_cfb,
2363 .decrypt = hifn_decrypt_aes_cfb,
2364 },
2365 },
2366 {
2367 .name = "ofb(aes)", .drv_name = "ofb-aes", .bsize = 16,
2368 .ablkcipher = {
2369 .min_keysize = AES_MIN_KEY_SIZE,
2370 .max_keysize = AES_MAX_KEY_SIZE,
2371 .setkey = hifn_setkey,
2372 .encrypt = hifn_encrypt_aes_ofb,
2373 .decrypt = hifn_decrypt_aes_ofb,
2374 },
2375 },
2376 };
2377
2378 static int hifn_cra_init(struct crypto_tfm *tfm)
2379 {
2380 struct crypto_alg *alg = tfm->__crt_alg;
2381 struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg);
2382 struct hifn_context *ctx = crypto_tfm_ctx(tfm);
2383
2384 ctx->dev = ha->dev;
2385 tfm->crt_ablkcipher.reqsize = sizeof(struct hifn_request_context);
2386 return 0;
2387 }
2388
2389 static int hifn_alg_alloc(struct hifn_device *dev, struct hifn_alg_template *t)
2390 {
2391 struct hifn_crypto_alg *alg;
2392 int err;
2393
2394 alg = kzalloc(sizeof(*alg), GFP_KERNEL);
2395 if (!alg)
2396 return -ENOMEM;
2397
2398 snprintf(alg->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name);
2399 snprintf(alg->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-%s",
2400 t->drv_name, dev->name);
2401
2402 alg->alg.cra_priority = 300;
2403 alg->alg.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2404 CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC;
2405 alg->alg.cra_blocksize = t->bsize;
2406 alg->alg.cra_ctxsize = sizeof(struct hifn_context);
2407 alg->alg.cra_alignmask = 0;
2408 alg->alg.cra_type = &crypto_ablkcipher_type;
2409 alg->alg.cra_module = THIS_MODULE;
2410 alg->alg.cra_u.ablkcipher = t->ablkcipher;
2411 alg->alg.cra_init = hifn_cra_init;
2412
2413 alg->dev = dev;
2414
2415 list_add_tail(&alg->entry, &dev->alg_list);
2416
2417 err = crypto_register_alg(&alg->alg);
2418 if (err) {
2419 list_del(&alg->entry);
2420 kfree(alg);
2421 }
2422
2423 return err;
2424 }
2425
2426 static void hifn_unregister_alg(struct hifn_device *dev)
2427 {
2428 struct hifn_crypto_alg *a, *n;
2429
2430 list_for_each_entry_safe(a, n, &dev->alg_list, entry) {
2431 list_del(&a->entry);
2432 crypto_unregister_alg(&a->alg);
2433 kfree(a);
2434 }
2435 }
2436
2437 static int hifn_register_alg(struct hifn_device *dev)
2438 {
2439 int i, err;
2440
2441 for (i = 0; i < ARRAY_SIZE(hifn_alg_templates); ++i) {
2442 err = hifn_alg_alloc(dev, &hifn_alg_templates[i]);
2443 if (err)
2444 goto err_out_exit;
2445 }
2446
2447 return 0;
2448
2449 err_out_exit:
2450 hifn_unregister_alg(dev);
2451 return err;
2452 }
2453
2454 static void hifn_tasklet_callback(unsigned long data)
2455 {
2456 struct hifn_device *dev = (struct hifn_device *)data;
2457
2458 /*
2459 * This is ok to call this without lock being held,
2460 * althogh it modifies some parameters used in parallel,
2461 * (like dev->success), but they are used in process
2462 * context or update is atomic (like setting dev->sa[i] to NULL).
2463 */
2464 hifn_clear_rings(dev, 0);
2465
2466 if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
2467 hifn_process_queue(dev);
2468 }
2469
2470 static int hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2471 {
2472 int err, i;
2473 struct hifn_device *dev;
2474 char name[8];
2475
2476 err = pci_enable_device(pdev);
2477 if (err)
2478 return err;
2479 pci_set_master(pdev);
2480
2481 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2482 if (err)
2483 goto err_out_disable_pci_device;
2484
2485 snprintf(name, sizeof(name), "hifn%d",
2486 atomic_inc_return(&hifn_dev_number) - 1);
2487
2488 err = pci_request_regions(pdev, name);
2489 if (err)
2490 goto err_out_disable_pci_device;
2491
2492 if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE ||
2493 pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE ||
2494 pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) {
2495 dev_err(&pdev->dev, "Broken hardware - I/O regions are too small.\n");
2496 err = -ENODEV;
2497 goto err_out_free_regions;
2498 }
2499
2500 dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg),
2501 GFP_KERNEL);
2502 if (!dev) {
2503 err = -ENOMEM;
2504 goto err_out_free_regions;
2505 }
2506
2507 INIT_LIST_HEAD(&dev->alg_list);
2508
2509 snprintf(dev->name, sizeof(dev->name), "%s", name);
2510 spin_lock_init(&dev->lock);
2511
2512 for (i = 0; i < 3; ++i) {
2513 unsigned long addr, size;
2514
2515 addr = pci_resource_start(pdev, i);
2516 size = pci_resource_len(pdev, i);
2517
2518 dev->bar[i] = ioremap_nocache(addr, size);
2519 if (!dev->bar[i]) {
2520 err = -ENOMEM;
2521 goto err_out_unmap_bars;
2522 }
2523 }
2524
2525 dev->desc_virt = pci_zalloc_consistent(pdev, sizeof(struct hifn_dma),
2526 &dev->desc_dma);
2527 if (!dev->desc_virt) {
2528 dev_err(&pdev->dev, "Failed to allocate descriptor rings.\n");
2529 err = -ENOMEM;
2530 goto err_out_unmap_bars;
2531 }
2532
2533 dev->pdev = pdev;
2534 dev->irq = pdev->irq;
2535
2536 for (i = 0; i < HIFN_D_RES_RSIZE; ++i)
2537 dev->sa[i] = NULL;
2538
2539 pci_set_drvdata(pdev, dev);
2540
2541 tasklet_init(&dev->tasklet, hifn_tasklet_callback, (unsigned long)dev);
2542
2543 crypto_init_queue(&dev->queue, 1);
2544
2545 err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev);
2546 if (err) {
2547 dev_err(&pdev->dev, "Failed to request IRQ%d: err: %d.\n",
2548 dev->irq, err);
2549 dev->irq = 0;
2550 goto err_out_free_desc;
2551 }
2552
2553 err = hifn_start_device(dev);
2554 if (err)
2555 goto err_out_free_irq;
2556
2557 err = hifn_register_rng(dev);
2558 if (err)
2559 goto err_out_stop_device;
2560
2561 err = hifn_register_alg(dev);
2562 if (err)
2563 goto err_out_unregister_rng;
2564
2565 INIT_DELAYED_WORK(&dev->work, hifn_work);
2566 schedule_delayed_work(&dev->work, HZ);
2567
2568 dev_dbg(&pdev->dev, "HIFN crypto accelerator card at %s has been "
2569 "successfully registered as %s.\n",
2570 pci_name(pdev), dev->name);
2571
2572 return 0;
2573
2574 err_out_unregister_rng:
2575 hifn_unregister_rng(dev);
2576 err_out_stop_device:
2577 hifn_reset_dma(dev, 1);
2578 hifn_stop_device(dev);
2579 err_out_free_irq:
2580 free_irq(dev->irq, dev);
2581 tasklet_kill(&dev->tasklet);
2582 err_out_free_desc:
2583 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2584 dev->desc_virt, dev->desc_dma);
2585
2586 err_out_unmap_bars:
2587 for (i = 0; i < 3; ++i)
2588 if (dev->bar[i])
2589 iounmap(dev->bar[i]);
2590
2591 err_out_free_regions:
2592 pci_release_regions(pdev);
2593
2594 err_out_disable_pci_device:
2595 pci_disable_device(pdev);
2596
2597 return err;
2598 }
2599
2600 static void hifn_remove(struct pci_dev *pdev)
2601 {
2602 int i;
2603 struct hifn_device *dev;
2604
2605 dev = pci_get_drvdata(pdev);
2606
2607 if (dev) {
2608 cancel_delayed_work_sync(&dev->work);
2609
2610 hifn_unregister_rng(dev);
2611 hifn_unregister_alg(dev);
2612 hifn_reset_dma(dev, 1);
2613 hifn_stop_device(dev);
2614
2615 free_irq(dev->irq, dev);
2616 tasklet_kill(&dev->tasklet);
2617
2618 hifn_flush(dev);
2619
2620 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2621 dev->desc_virt, dev->desc_dma);
2622 for (i = 0; i < 3; ++i)
2623 if (dev->bar[i])
2624 iounmap(dev->bar[i]);
2625
2626 kfree(dev);
2627 }
2628
2629 pci_release_regions(pdev);
2630 pci_disable_device(pdev);
2631 }
2632
2633 static struct pci_device_id hifn_pci_tbl[] = {
2634 { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) },
2635 { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) },
2636 { 0 }
2637 };
2638 MODULE_DEVICE_TABLE(pci, hifn_pci_tbl);
2639
2640 static struct pci_driver hifn_pci_driver = {
2641 .name = "hifn795x",
2642 .id_table = hifn_pci_tbl,
2643 .probe = hifn_probe,
2644 .remove = hifn_remove,
2645 };
2646
2647 static int __init hifn_init(void)
2648 {
2649 unsigned int freq;
2650 int err;
2651
2652 /* HIFN supports only 32-bit addresses */
2653 BUILD_BUG_ON(sizeof(dma_addr_t) != 4);
2654
2655 if (strncmp(hifn_pll_ref, "ext", 3) &&
2656 strncmp(hifn_pll_ref, "pci", 3)) {
2657 pr_err("hifn795x: invalid hifn_pll_ref clock, must be pci or ext");
2658 return -EINVAL;
2659 }
2660
2661 /*
2662 * For the 7955/7956 the reference clock frequency must be in the
2663 * range of 20MHz-100MHz. For the 7954 the upper bound is 66.67MHz,
2664 * but this chip is currently not supported.
2665 */
2666 if (hifn_pll_ref[3] != '\0') {
2667 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
2668 if (freq < 20 || freq > 100) {
2669 pr_err("hifn795x: invalid hifn_pll_ref frequency, must"
2670 "be in the range of 20-100");
2671 return -EINVAL;
2672 }
2673 }
2674
2675 err = pci_register_driver(&hifn_pci_driver);
2676 if (err < 0) {
2677 pr_err("Failed to register PCI driver for %s device.\n",
2678 hifn_pci_driver.name);
2679 return -ENODEV;
2680 }
2681
2682 pr_info("Driver for HIFN 795x crypto accelerator chip "
2683 "has been successfully registered.\n");
2684
2685 return 0;
2686 }
2687
2688 static void __exit hifn_fini(void)
2689 {
2690 pci_unregister_driver(&hifn_pci_driver);
2691
2692 pr_info("Driver for HIFN 795x crypto accelerator chip "
2693 "has been successfully unregistered.\n");
2694 }
2695
2696 module_init(hifn_init);
2697 module_exit(hifn_fini);
2698
2699 MODULE_LICENSE("GPL");
2700 MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
2701 MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip.");
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